Method and device for automatically expanding dynamic range of multi-channel receiver and application of method and device

Abstract

The invention relates to the technical field of digital communication, and discloses a method for automatically expanding the dynamic range of a multi-channel receiver, which comprises the following steps of: jointly connecting each receiving channel of the multi-channel receiver with the input end of a detection link through a switch matrix, and connecting the output end of the detection link with an FPGA (Field Programmable Gate Array); the switch matrix is controlled through the FPGA so as to control each receiving channel in a time-sharing manner, so that only one receiving channel is connected with the detection link in the same control time period, and the receiving channel connected with the detection link in the current time period is enabled to be the current receiving channel; and comparing the plurality of sampling data with a preset attenuation threshold and an attenuation release threshold based on a set rule, and according to a comparison result, selecting to carry out extension detection on the current receiving channel or switch the switch matrix to connect the next receiving channel with the detection link. The automatic expansion method designed by the invention can be applied to miniaturized and customized equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of digital communication, and in particular to a method and device for automatically expanding the dynamic range of a multi-channel receiver and applications thereof. Background Art

[0002] Dynamic range is one of the important indicators for measuring the performance of spectrum analyzers, intermediate frequency receivers and other equipment. In order to expand the receiving dynamic range, automatic gain control circuits are often used in spectrum analyzers or receivers. This circuit ensures that the output signal amplitude can be maintained within a smaller range when the input signal amplitude changes greatly.

[0003] In order to make the system converge quickly and respond accurately in steady state, the main functions of the feedback part of the automatic gain control can be realized by FPGA (online programmable gate array). Since FPGA (online programmable gate array) has the characteristics of fast response speed and high digital processing accuracy, it can accurately realize digital gain compensation.

[0004] Usually in a large dynamic range, multi-channel receiver, each channel's receiving link must have a detector and ADC (analog-to-digital conversion) acquisition device, which increases the cost and size of the device and cannot be effectively applied in some multi-channel receivers that require miniaturization and low power consumption. Summary of the invention

[0005] Based on this, the present invention designs a multi-channel dynamic range automatic expansion method, device and application based on FPGA (online programmable gate array), which can be applied to miniaturized and customized equipment.

[0006] The present invention is achieved through the following technical solutions:

[0007] A method for automatically extending the dynamic range of a multi-channel receiver, comprising:

[0008] Connecting the receiving channels of the multi-channel receiver to the input end of a detection link through a switch matrix, and connecting the output end of the detection link to the FPGA;

[0009] Controlling the switch matrix through the FPGA to control each receiving channel in a time-sharing manner so that only one receiving channel is connected to the detection link in the same control period, and making the receiving channel connected to the detection link in the current period the current receiving channel;

[0010] Receiving and processing the intermediate frequency signal from the current receiving channel through the detection link to obtain an AD signal, and sampling the AD signal after preprocessing it through the FPGA to obtain a number of sampled data;

[0011] The plurality of sampled data are compared with a preset attenuation threshold and an attenuation release threshold based on a set rule, and according to the comparison result, it is selected to extend the detection of the current receiving channel or switch the switch matrix so that the next receiving channel is connected to the detection link.

[0012] In some embodiments, the radio frequency signal enters the receiving channel through an antenna, is filtered, amplified, and down-converted into an intermediate frequency signal through the receiving channel, and the intermediate frequency signal enters the detection link through coupling.

[0013] In some embodiments, the switch matrix is ​​N-1 single-pole double-throw switches, N is the number of receiving channels, the static contacts of the single-pole double-throw switches are connected to the receiving channels, the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share one static contact of two adjacent single-pole double-throw switches.

[0014] In some embodiments, the FPGA controls the switch matrix to control the receiving channels connected to the detection link. The specific process is: the FPGA sequentially controls the single-pole double-throw switches through a polling mechanism, so that the receiving channels are sequentially connected to the detection link.

[0015] In some embodiments, the AD signal is pre-processed by the FPGA and then sampled to obtain a number of sampled data. The specific process is:

[0016] The AD signal is firstly digitally filtered by a smoothing filter and the data is smoothed to obtain a first signal;

[0017] The data before Mus of the first signal is removed to obtain a second signal, and then the second signal is continuously sampled to obtain a plurality of sampled data.

[0018] In some embodiments, the setting rules are specifically:

[0019] S1, judging whether all the sampled data are greater than a preset attenuation threshold, if so, jumping to S2, otherwise, jumping to S5;

[0020] S2, determine whether the difference between the two pollings is greater than the anti-oscillation threshold, if so, jump to S3, otherwise, jump to S7;

[0021] S3, controlling the digitally controlled attenuator of the current receiving channel to attenuate the radio frequency signal;

[0022] S4, extending a control period of the current receiving channel, and then returning to S1;

[0023] S5, judging whether all the sampled data are less than the attenuation release threshold, if so, jumping to S6, otherwise, jumping to S7;

[0024] S6, releasing the current receiving channel attenuation, that is, stopping the digitally controlled attenuator from attenuating the radio frequency signal;

[0025] S7, switch to the next receiving channel, and then jump to S1.

[0026] The present invention also discloses a multi-channel receiver dynamic range automatic expansion device, which is used to implement the aforementioned multi-channel receiver dynamic range automatic expansion method, and is characterized by comprising:

[0027] A switch matrix, comprising N-1 single-pole double-throw switches, wherein the static contacts of the single-pole double-throw switches are connected to the receiving channels of the multi-channel receiver, the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share one static contact of two adjacent single-pole double-throw switches, and N is the number of receiving channels of the multi-channel receiver (1);

[0028] The detection link is connected to each of the receiving channels through a switch matrix, and is used to receive the intermediate frequency signal from the receiving channel and convert the intermediate frequency signal into an AD signal, wherein:

[0029] The FPGA is connected to the detection link and preprocesses the received AD signal into sampling data, and compares the sampling data with a preset attenuation threshold and an attenuation release threshold based on a set rule, and selects to extend the detection of the current receiving channel or switch the switch matrix to connect the next receiving channel to the detection link according to the comparison result.

[0030] In some embodiments, the detection link includes a detector and an ADC in sequence along the data transmission direction, the detector is connected to one of the receiving channels in each of the receiving channels at different time periods through the switch matrix, and the ADC is connected to the FPGA.

[0031] In some embodiments, along the data transmission direction, the FPGA includes a smoothing filter, a sampling module and a comparison module in sequence;

[0032] The smoothing filter is connected to the ADC and is used to perform smoothing filtering on the AD signal to obtain a first signal;

[0033] The sampling module is used to remove the data of Mus before the first signal to obtain a second signal and to sample the second signal to obtain a plurality of sampled data;

[0034] The comparison module is used to compare the sampled data with the preset attenuation threshold and attenuation release threshold based on the set rules, and select to extend the detection of the current receiving channel or switch the switch matrix to connect the next receiving channel to the detection link according to the comparison result.

[0035] The present invention also discloses an application of an automatic expansion device, which connects the aforementioned automatic expansion device for dynamic range of a multi-channel receiver with each receiving channel of the multi-channel receiver.

[0036] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0037] The automatic expansion device designed by the present invention can be applied to miniaturized and customized equipment.

[0038] This multi-channel receiver automatic expansion technology can reduce the size of the receiver device, reduce the power consumption of the device, and increase the dynamic range that the device can receive. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0040] Figure 1 It is a structural schematic diagram of a multi-channel receiver dynamic range automatic expansion device according to the present invention;

[0041] Figure 2 A flowchart for preset rules;

[0042] Figure 3 This is the test result of the detector at 50MHz. It is the test result of the chip. A 50MHz signal is used. The intermediate frequency signal of the product is close to this frequency, about 25MHz.

[0043] Marks and corresponding parts names in the attached drawings:

[0044] 1-multi-channel receiver, 2-switch matrix, 3-detection link, 31-detector, 32-ADC, 4-FPGA, 41-smoothing filter, 42-sampling module, 43-comparison module. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0046] This embodiment 1 provides a method for automatically extending the dynamic range of a multi-channel receiver, including:

[0047] Connecting the receiving channels of the multi-channel receiver to the input end of a detection link through a switch matrix, and connecting the output end of the detection link to the FPGA;

[0048] Controlling the switch matrix through the FPGA to control each receiving channel in a time-sharing manner so that only one receiving channel is connected to the detection link in the same control period, and making the receiving channel connected to the detection link in the current period the current receiving channel;

[0049] In some embodiments, the RF signal (-107dbm to -7dbm) enters the receiving channel (receiving link of a multi-channel receiver) through an antenna, is filtered, amplified, and down-converted into an intermediate frequency signal through the receiving channel, and the intermediate frequency signal then enters the detection link through coupling.

[0050] The present invention designs only one detection link, and therefore introduces a channel polling mechanism, which sends the intermediate frequency signals of different receiving channels to the detector on the detection link in a time-sharing manner through an FPGA (online programmable gate array) switching switch matrix; a period of time is occupied on one receiving channel to allow the FPGA (online programmable gate array) to process the data, and then switches to the next receiving channel.

[0051] In some embodiments, Figure 1 As shown, the switch matrix is ​​N-1 single-pole double-throw switches, N is the number of receiving channels, the static contacts of the single-pole double-throw switches are connected to the receiving channels, the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share one static contact of two adjacent single-pole double-throw switches.

[0052] Receiving and processing the intermediate frequency signal from the current receiving channel through the detection link to obtain an AD signal, and sampling the AD signal after preprocessing it through the FPGA to obtain a number of sampled data;

[0053] The plurality of sampled data are compared with a preset attenuation threshold and an attenuation release threshold based on a set rule, and according to the comparison result, it is selected to extend the detection of the current receiving channel or switch the switch matrix so that the next receiving channel is connected to the detection link.

[0054] In some embodiments, the FPGA controls the switch matrix to control the receiving channels connected to the detection link. The specific process is: the FPGA sequentially controls the single-pole double-throw switches through a polling mechanism, so that the receiving channels are sequentially connected to the detection link.

[0055] That is, the order of the receiving channels is set, and the FPGA selects the next receiving channel to be controlled according to the order of the receiving channels.

[0056] In some embodiments, the AD signal is pre-processed by the FPGA and then sampled to obtain a number of sampled data. The specific process is:

[0057] The AD signal is firstly digitally filtered by a smoothing filter and the data is smoothed to obtain a first signal;

[0058] The data before Mus of the first signal is removed to obtain a second signal, and then the second signal is continuously sampled to obtain a plurality of sampled data.

[0059] In some embodiments, Figure 2 As shown, the setting rules are specifically:

[0060] S1, judging whether all the sampled data are greater than a preset attenuation threshold, if so, jumping to S2, otherwise, jumping to S5;

[0061] S2, determine whether the difference between the two pollings is greater than the anti-oscillation threshold, if so, jump to S3, otherwise, jump to S7;

[0062] The specific origin of the difference between two pollings is to obtain a difference by taking the last sampling value of the previous polling of the corresponding channel and the last sampling value of this polling as the difference.

[0063] S3, controlling the digitally controlled attenuator of the current receiving channel to attenuate the radio frequency signal;

[0064] S4, extending a control period of the current receiving channel, and then returning to S1;

[0065] S5, judging whether all the sampled data are less than the attenuation release threshold, if so, jumping to S6, otherwise, jumping to S7;

[0066] S6, releasing the current receiving channel attenuation, that is, stopping the digitally controlled attenuator from attenuating the radio frequency signal;

[0067] The attenuator has 4 gears, which can attenuate the RF signal by 16db\32db\48\64db. Releasing the attenuation means reducing the gear from the high gear to the low gear.

[0068] S7, switch to the next receiving channel, and then jump to S1.

[0069] In this technical solution, the AD signal entering the FPGA (online programmable gate array) is first digitally filtered to smooth the data; the data (sampled data) for a period of time is compared with the preset attenuation threshold and the attenuation release threshold, and all the data (sampled data) during this period exceed the preset attenuation threshold to meet an attenuation condition (condition one); in order to prevent the signal (the signal is slightly lower than the preset attenuation threshold at this time, that is, the signal is slightly lower than the attenuation threshold most of the time, and occasionally exceeds the threshold) from attenuating in the middle of the pulse signal due to a small change near the preset attenuation threshold, an anti-oscillation mechanism is set, and an anti-oscillation threshold ( Figure 2 By comparing the sampling difference between the two pollings, it is determined whether the signal has changed significantly (the previous method is to prevent the signal from attenuating due to small fluctuations, so the signal amplitude change must be relatively large to meet the attenuation condition);

[0070] For example, if a pulse signal is 26ms, and the first 1ms is required to be the time for AGC, the signal amplitude cannot be changed during the rest of the time, and the signal is fluctuating, then the pulse signal will be slightly below the attenuation threshold most of the time, and occasionally only a few sampling values ​​will be above the threshold. If this situation occurs in the next 25ms time period, no attenuation action should be performed.

[0071] If the signal amplitude change exceeds the anti-oscillation threshold and meets another attenuation condition (condition two), the digital controlled attenuator on this channel can be controlled to attenuate the signal; when the sampling data taken for a period of time are all less than the attenuation release threshold, the attenuation is released, otherwise the current state is maintained (the current state is the attenuation state, the attenuation state of the current channel is maintained, and the attenuation gear does not change).

[0072] If the signal is too large, it needs to be attenuated; if the signal is too small, it needs to be released from attenuation, so two thresholds are required.

[0073] When the FPGA (online programmable gate array) is processing a receiving channel, if the signal of this channel is attenuated by one level, the dwell time of this channel is extended to continue to determine whether the attenuated signal of the receiving channel meets the attenuation condition; if there is no attenuation in this receiving channel, it switches to the next receiving channel for detection. In this way, the channel signal amplitude can quickly converge within the specified range.

[0074] A specific implementation case is used to illustrate.

[0075] 1. The multi-channel receiver hardware is designed with 6 receiving channels and a detection link. The detection link uses a detector and ADC (analog-to-digital conversion) acquisition device to send the signal to the FPGA (online programmable gate array) for processing; 5 2-to-1 switches are set to send the 6 coupled signals to the detection link for acquisition respectively, and the switches are controlled by the FPGA (online programmable gate array); through switch switching, channels 1, 2, 3, 4, 5, 6, 1 start to send the signal to the detection link in a time-sharing manner.

[0076] 2. The AD data entering the FPGA (online programmable gate array) first passes through a sliding average filter with a sliding window set to 32 to remove burrs and smooth the data; the detection time of a channel is set to 15us. Since there is overshoot in the signal entering the detection link when switching the switch, the data in the first 10us is unreliable, and the reliable data after 10us is used for subsequent processing; 50 consecutive sampling data are compared with the preset attenuation threshold and attenuation release threshold. When all data exceed the attenuation threshold, one of the conditions for controlling attenuation is met; the other condition is to determine whether the difference between the sampling data of two polls is greater than the anti-oscillation threshold of 3dB to prevent attenuation in the middle of the pulse signal due to small fluctuations in the signal. When both conditions are met, the digital attenuator on this channel can be controlled to attenuate the signal; if 50 consecutive sampling data are less than the attenuation release threshold, the attenuation is released, and in other cases, the current state is maintained unchanged.

[0077] 3. If there is an attenuation action during the detection time of a channel, the detection time of this channel will be extended by 15us and the above process will be repeated; if there is no attenuation action, switch to the next receiving channel for detection.

[0078] Some parameters of the hardware of the present invention are designed as follows:

[0079] Parameter design of detector:

[0080] RF signal input power range: -107dbm ~ -7dbm, receiver gain 73db, theoretically the amplified signal power is -34dbm ~ 66dbm, but because the amplifier's P-1 is 20dbm, the actual output power of the amplifier is -34dbm ~ 20dbm.

[0081] The coupling attenuation of the designed detector is 30db, and the signal power range entering the detector is: -64dbm ~ -10dbm. (IF output power = detector input power + 30db)

[0082] Since the frequency of the intermediate frequency signal is 21.4MHz, the reference detector 50MHz test result diagram is as follows: Figure 3 shown.

[0083] from Figure 3 It can be seen that the linear range of the detector is -55 to 0 dBm, and in the linear region, the detection slope is 20 mv / dB. When the detector input signal power range is -64 dBm to -10 dBm, its output voltage is 0.65 to 1.5 V.

[0084] ADC parameter design:

[0085] The detector output voltage must be within the ADC input voltage range. Since the selected ADC reference voltage is 1V, the detector output voltage needs to be divided. The voltage divider ratio of this design is 1.6, so the detector output voltage becomes 0.41~0.9375V. Since the voltage divider changes the slope, the slope of the detector output is 20 / 1.6=12.5mv / dB.

[0086] The ADC is 14-bit wide, bipolar sampler, and the reference voltage is 1 V. That is, when the input voltage of the ADC is 1 V, the quantized output of the ADC is "01_1111_1111_1111", that is, 2^13-1=8191. At this time, the voltage represented by the LSB of the ADC is 1V / 8191=0.122mv.

[0087] In some embodiments, a multi-channel receiver dynamic range automatic expansion device is also disclosed, which is used to implement the aforementioned multi-channel receiver dynamic range automatic expansion method, including:

[0088] A switch matrix 2, comprising N-1 single-pole double-throw switches, wherein the static contacts of the single-pole double-throw switches are connected to the receiving channels of the multi-channel receiver 1, the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share one static contact of two adjacent single-pole double-throw switches, and N is the number of receiving channels of the multi-channel receiver 1;

[0089] The detection link 3 is connected to each of the receiving channels through the switch matrix 2, and is used to receive the intermediate frequency signal from the receiving channel and convert the intermediate frequency signal into an AD signal, wherein:

[0090] FPGA4 is connected to the detection link 3, and preprocesses the received AD signal into sampling data, and compares the sampling data with the preset attenuation threshold and attenuation release threshold based on the set rules, and selects to extend the detection of the current receiving channel or switch the switch matrix 2 to connect the next receiving channel to the detection link 3 according to the comparison result.

[0091] In some embodiments, the detection link 3 includes a detector 31 and an ADC 32 in sequence along the data transmission direction. The detector 31 is connected to one of the receiving channels in different time periods through the switch matrix 2, and the ADC 32 is connected to the FPGA 4.

[0092] In some embodiments, along the data transmission direction, the FPGA 4 includes a smoothing filter 41, a sampling module 42 and a comparison module 43 in sequence;

[0093] The smoothing filter 41 is connected to the ADC 32 and is used to perform smoothing filtering on the AD signal to obtain a first signal;

[0094] The sampling module 42 is used to remove the data of the first signal Mus to obtain a second signal and to sample the second signal to obtain a plurality of sampled data;

[0095] The comparison module 43 is used to compare the sampled data with the preset attenuation threshold and attenuation release threshold based on the set rules, and select to extend the detection of the current receiving channel or switch the switch matrix 2 to connect the next receiving channel to the detection link 3 according to the comparison result.

[0096] Some embodiments also disclose an application of an automatic expansion device, in which the aforementioned automatic expansion device for dynamic range of a multi-channel receiver is installed in the multi-channel receiver.

[0097] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for automatically extending the dynamic range of a multi-channel receiver, characterized in that: include: Connecting the receiving channels of the multi-channel receiver to the input end of a detection link through a switch matrix, and connecting the output end of the detection link to the FPGA; Controlling the switch matrix through the FPGA to control each receiving channel in a time-sharing manner so that only one receiving channel is connected to the detection link in the same control period, and making the receiving channel connected to the detection link in the current period the current receiving channel; Receiving and processing the intermediate frequency signal from the current receiving channel through the detection link to obtain an AD signal, and sampling the AD signal after preprocessing it through the FPGA to obtain a number of sampled data; The plurality of sampled data are compared with a preset attenuation threshold and an attenuation release threshold based on a set rule, and according to the comparison result, it is selected to extend the detection of the current receiving channel or switch the switch matrix so that the next receiving channel is connected to the detection link.

2. A method for automatically extending the dynamic range of a multi-channel receiver according to claim 1, characterized in that: The radio frequency signal enters the receiving channel through the antenna, is filtered, amplified, and down-converted into an intermediate frequency signal through the receiving channel, and the intermediate frequency signal enters the detection link through coupling.

3. The method for automatically extending the dynamic range of a multi-channel receiver according to claim 1, characterized in that: The switch matrix is ​​N-1 single-pole double-throw switches, N is the number of receiving channels, the static contacts of the single-pole double-throw switches are connected to the receiving channels, the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share a static contact of two adjacent single-pole double-throw switches.

4. A method for automatically extending the dynamic range of a multi-channel receiver according to claim 3, characterized in that: The FPGA controls the switch matrix to control the receiving channels connected to the detection link. The specific process is: the FPGA sequentially controls the single-pole double-throw switches through a polling mechanism, so that the receiving channels are sequentially connected to the detection link.

5. The method for automatically extending the dynamic range of a multi-channel receiver according to claim 1, characterized in that: The AD signal is pre-processed by the FPGA and then sampled to obtain a number of sampled data. The specific process is: The AD signal is firstly digitally filtered by a smoothing filter and the data is smoothed to obtain a first signal; The data before Mus of the first signal is removed to obtain a second signal, and then the second signal is continuously sampled to obtain a plurality of sampled data.

6. The method for automatically extending the dynamic range of a multi-channel receiver according to claim 1, characterized in that: The specific setting rules are: S1, judging whether all the sampled data are greater than a preset attenuation threshold, if so, jumping to S2, otherwise, jumping to S5; S2, determine whether the difference between the two pollings is greater than the anti-oscillation threshold, if so, jump to S3, otherwise, jump to S7; S3, controlling the digitally controlled attenuator of the current receiving channel to attenuate the radio frequency signal; S4, extending a control period of the current receiving channel, and then returning to S1; S5, judging whether all the sampled data are less than the attenuation release threshold, if so, jumping to S6, otherwise, jumping to S7; S6, releasing the current receiving channel attenuation, that is, stopping the digitally controlled attenuator from attenuating the radio frequency signal; S7, switch to the next receiving channel, and then jump to S1.

7. A multi-channel receiver dynamic range automatic expansion device, used to implement a multi-channel receiver dynamic range automatic expansion method according to any one of claims 1 to 6, characterized in that: include: A switch matrix (2) comprises N-1 single-pole double-throw switches, wherein the static contacts of the single-pole double-throw switches are connected to the receiving channels of the multi-channel receiver (1), the moving contacts of the single-pole double-throw switches are commonly connected to the input end of the detection link, and the receiving channels located at non-edge positions share a static contact of two adjacent single-pole double-throw switches, and N is the number of receiving channels of the multi-channel receiver (1); The detection link (3) is connected to each of the receiving channels through the switch matrix (2), and is used to receive the intermediate frequency signal from the receiving channel and convert the intermediate frequency signal into an AD signal, wherein: The FPGA (4) is connected to the detection link (3) and pre-processes the received AD signal into sampling data, and compares the sampling data with a preset attenuation threshold and an attenuation release threshold based on a set rule, and selects, based on the comparison result, to extend the detection of the current receiving channel or switch the switch matrix (2) so that the next receiving channel is connected to the detection link (3).

8. The multi-channel receiver dynamic range automatic expansion device according to claim 7, characterized in that: The detection link (3) comprises a detector (31) and an ADC (32) in sequence along the data transmission direction; the detector (31) is connected to one of the receiving channels in each of the receiving channels at different time periods through the switch matrix (2); and the ADC (32) is connected to the FPGA (4).

9. A method for automatically extending the dynamic range of a multi-channel receiver according to claim 8, characterized in that: Along the data transmission direction, the FPGA (4) comprises a smoothing filter (41), a sampling module (42) and a comparison module (43) in sequence; The smoothing filter (41) is connected to the ADC (32) and is used to perform smoothing filtering on the AD signal to obtain a first signal; The sampling module (42) is used for removing the data of Mus before the first signal to obtain a second signal and sampling the second signal to obtain a plurality of sampled data; The comparison module (43) is used to compare a number of the sampled data with a preset attenuation threshold and an attenuation release threshold based on a set rule, and select, according to the comparison result, to extend the detection of the current receiving channel or switch the switch matrix (2) so that the next receiving channel is connected to the detection link (3).

10. An application of an automatic expansion device, characterized in that: The multi-channel receiver dynamic range automatic expansion device described in any one of claims 7 to 9 is connected to each receiving channel of the multi-channel receiver.

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