Prefix tree construction method, routing entry search method, device and electronic device

Abstract

The present application provides a method for constructing a prefix tree, a method for searching routing entries, a device and an electronic device, and belongs to the field of cloud computing. The method comprises: obtaining the number of layers of the prefix tree and the effective bit range of each layer of the routing according to the mask length of at least one valid routing entry; determining the nodes of each layer of the prefix tree according to the effective bit range of each layer of the routing of the prefix tree and the binary string obtained after mask processing of at least one valid routing entry, wherein the nodes of each layer of the prefix tree include leaf nodes and branch nodes, the leaf nodes correspond to a valid routing entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer; starting from the root node, the nodes corresponding to each valid routing entry are connected layer by layer until the leaf node, and a prefix tree is obtained, wherein the root node corresponds to an empty character or a valid routing entry with a mask length of 0. The present application can reduce the computing resources consumed in the tree building process.

Description

Technical Field

[0001] The present application relates to the field of cloud computing technology, and in particular to a prefix tree construction method, a routing entry search method, a device and an electronic device. Background Art

[0002] In large-scale data centers and multi-tenant environments, it is necessary to support thousands of isolated virtual networks. With the help of network segmentation and isolation technology, combined with virtual network identifiers and destination IP (Internet Protocol) addresses, routing entry lookup for large-scale virtual networks can be achieved. At present, routing entry lookup is mainly based on the LPM (Longest Prefix Match) algorithm, which compares the destination IP address of the data packet with the routing entries supported by the router bit by bit until the routing entry with the longest match to the destination IP address is found. In order to facilitate routing entry lookup based on the LPM algorithm, a prefix tree is usually built based on the routing entries supported by the router. The prefix tree is a tree structure, and the nodes in the prefix tree can represent the string that matches the position of the node.

[0003] When constructing a prefix tree, the related technology constructs a sub-prefix tree step by step according to the mask length of the routing entries supported by the router, in the order of bits from high to low, with 8 bits as a layer. Each level of the sub-prefix tree can include at least one sub-prefix tree, and each sub-prefix tree can include 256 nodes. By storing the node information of each node in each level of the sub-prefix tree, a prefix tree formed by cascading multiple levels of sub-prefix trees is finally obtained.

[0004] However, the related technology needs to establish a multi-level sub-prefix tree, and each level of the sub-prefix tree includes a large number of nodes, resulting in a large consumption of computing resources. Summary of the invention

[0005] The embodiment of the present application provides a method for constructing a prefix tree, a method for searching routing entries, a device and an electronic device. The method only needs to construct a prefix tree, and the number of nodes contained in the constructed prefix tree is small, thereby reducing the consumption of computing resources. The technical solution is as follows:

[0006] In a first aspect, a method for constructing a prefix tree is provided, the method comprising:

[0007] According to the mask length of at least one valid routing entry, the number of layers of the prefix tree and the valid bit range of the routing of each layer are obtained;

[0008] Determine the nodes of each layer of the prefix tree according to the route valid bit range of each layer of the prefix tree and the binary string obtained after the mask operation of the at least one valid route entry, wherein the nodes of each layer of the prefix tree include leaf nodes and branch nodes, the leaf nodes correspond to a valid route entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer;

[0009] Starting from the root node, the nodes corresponding to each valid routing entry are connected layer by layer until the leaf node, to obtain the prefix tree, wherein the root node corresponds to a valid routing entry with a null character or a mask length of 0.

[0010] In a second aspect, a method for searching a routing entry is provided, wherein the method applies the prefix tree constructed in the first aspect, and the method comprises:

[0011] When a target data packet is received, a target address in the target data packet is masked to obtain a target binary string;

[0012] Based on the target binary string and the route valid bit range indicated by each layer of the prefix tree, searching the RAM for a target entry identifier, the target entry identifier being the entry identifier of the valid route entry that has the longest match with the prefix of the target binary string;

[0013] The valid routing entry corresponding to the target entry identifier is determined as the next-hop routing entry of the target address.

[0014] In a third aspect, a prefix tree construction device is provided, the device comprising:

[0015] An acquisition module, used for acquiring the number of layers of the prefix tree and the effective bit range of each layer of the route according to the mask length of at least one effective routing entry;

[0016] A determination module, configured to determine the nodes of each layer of the prefix tree according to the route valid bit range of each layer of the prefix tree and the binary string obtained after the mask operation of the at least one valid route entry, wherein the nodes of each layer of the prefix tree include leaf nodes and branch nodes, wherein the leaf nodes correspond to a valid route entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer;

[0017] The connection module is used to connect the nodes corresponding to each valid routing entry layer by layer starting from the root node until the leaf node to obtain the prefix tree, wherein the root node corresponds to a valid routing entry with a null character or a mask length of 0.

[0018] In a fourth aspect, a routing entry search device is provided, the device applying the prefix tree constructed in the first aspect, the device comprising:

[0019] A mask processing module, configured to perform a mask operation on a target address in a target data packet when a target data packet is received, to obtain a target binary string;

[0020] The search module is further used to search the target entry identifier from the RAM based on the target binary string and the route valid bit range indicated by each layer of the prefix tree, wherein the target entry identifier is the entry identifier of the valid route entry with the longest prefix match with the target binary string;

[0021] The determination module is used to determine the valid routing entry corresponding to the target entry identifier as the next-hop routing entry of the target address.

[0022] In a fifth aspect, an electronic device is provided, comprising a processor and a memory; the memory stores at least one program code; the at least one program code is used to be called and executed by the processor to implement the prefix tree construction method as described in the first aspect, or the routing entry search method as described in the second aspect.

[0023] In a sixth aspect, a computer-readable storage medium is provided, wherein at least one computer program is stored in the computer-readable storage medium, and when the at least one computer program is executed by a processor, the prefix tree construction method described in the first aspect or the routing entry search method described in the second aspect can be implemented.

[0024] In a seventh aspect, a computer program product is provided, the computer program product comprising a computer program, and when the computer program is executed by a processor, the method for constructing a prefix tree described in the first aspect, or the method for searching for routing entries described in the second aspect can be implemented.

[0025] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0026] The present application obtains at least one valid routing entry supported by the router, and based on the mask length of each valid routing entry, obtains the binary string corresponding to each valid routing entry by masking each valid routing entry, and determines the effective bit range of the routing of each layer of the prefix tree to be constructed based on the mask length of each valid routing entry, and then determines the nodes of each layer of the prefix tree according to the effective bit range of the routing of each layer and the binary string corresponding to at least one valid routing entry. The nodes of each layer of the prefix tree include leaf nodes and branch nodes. The leaf nodes correspond to a valid routing entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer. The effective routing entry with a mask length of 0 or a null character is used as the root node, and then starting from the root node, the nodes corresponding to each valid routing entry are connected layer by layer until the leaf node to obtain the prefix tree. Since the number of nodes included is small, the consumption of computing resources in the tree building process is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic diagram of a first-level sub-prefix tree constructed using a related art method;

[0029] Figure 2 It is a schematic diagram of a process of searching for routing entries based on a constructed prefix tree in the related art;

[0030] Figure 3 It is a flowchart of a prefix tree construction method provided in an embodiment of the present application;

[0031] Figure 4 is a schematic diagram of a prefix tree structure constructed in an embodiment of the present application;

[0032] Figure 5 It is a flowchart of storing node information of each node in a prefix tree provided by an embodiment of the present application;

[0033] Figure 6 This is a schematic diagram of implementing node jump using a hash algorithm provided in an embodiment of the present application;

[0034] Figure 7 is a schematic diagram of another prefix tree structure constructed in an embodiment of the present application;

[0035] Figure 8This is another schematic diagram of implementing node jump using a hash algorithm provided in an embodiment of the present application;

[0036] Fig. 9 is a flow chart of a method for searching routing entries provided by an embodiment of the present application;

[0037] Fig.10 It is a schematic diagram of a prefix tree construction device structure provided in an embodiment of the present application;

[0038] Fig.11 is a schematic diagram of a routing entry search device structure provided in an embodiment of the present application;

[0039] Fig.12 A structural block diagram of an electronic device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] It can be understood that the terms "each", "multiple", and "any" used in the embodiments of the present application include two or more, each refers to each of the corresponding multiple, and any refers to any one of the corresponding multiple. For example, the multiple words include 10 words, and each word refers to each of the 10 words, and any word refers to any one of the 10 words.

[0042] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0043] Before executing the embodiments of the present application, the terms involved in the embodiments of the present application are first explained.

[0044] The longest prefix match algorithm is a method for selecting a better path in network routing. It compares the destination address of the data packet with the network prefix of each routing entry supported by the router, and selects the longest prefix match as the path for data packet transmission.

[0045] Each bit of TCAM (Ternary Content Addressable Memory) has 0, 1, and x states, which is used for fuzzy search.

[0046] The prefix bitmap is used to indicate which nodes in the prefix tree contain valid prefixes, and contains the valid prefix information of 255 intermediate nodes in the first-level prefix tree.

[0047] The Child Pointer Bitmap is used to indicate which of the 256 leaf nodes in the last layer of the first-level prefix tree contain child prefix trees.

[0048] The mask is a string of binary numbers that indicates where the network address and host address of an IP address are separated. The length of the mask defines the size of the network address. An easy way to calculate the length of the mask is to count the number of 1s in the mask from left to right. For example, for 255.255.255.0, the first 24 numbers from left to right are 1s, so the mask length is 24 bits. Similarly, for the mask 255.255.0.0, the first 16 numbers from left to right are 1s, so the mask length is 16 bits.

[0049] CIDR (Classless Inter Domain Routing): A routing allocation method. CIDR uses a slash followed by a number to indicate the mask length, such as 192.168.1.1 / 10. The routing table will have the next hop of this routing entry after CIDR.

[0050] Hash algorithm is a compression mapping that converts input of arbitrary length into output of fixed length through a hash algorithm.

[0051] In large-scale data centers and multi-tenant environments, it is necessary to support thousands of isolated virtual networks. With the help of network segmentation and isolation technology, combined with virtual network identifiers and target IP addresses, routing entry lookup for large-scale virtual networks can be achieved. Among them, the virtual network identifier enables the routing device to quickly locate the virtual network, and then combine the target IP address to perform accurate routing lookup in the virtual network. Routing entry lookup is generally based on the longest prefix matching algorithm, which compares the destination address in the current IP data packet with the routing table entries supported by the local router bit by bit, and uses the longest matching routing entry as the next hop.

[0052] As the network speed increases, the frequency of route lookups becomes higher and higher. As the frequency of route lookups increases, the forwarding performance of routing devices decreases and the CPU load increases. For example, when the Ethernet rate is 40 Gbps, if the minimum Ethernet frame is used, the frequency of route lookups per second is as high as 60 million. At 100 Gbps, the frequency of route lookups will increase to 150 million times per second. In order to improve the forwarding performance of routing devices and reduce the CPU load, hardware FPGA (Field Programmable Gate Array) can be used to accelerate the LPM algorithm. When implementing LPM from the hardware architecture level, it is necessary to consider the problems of pipeline design and limited hardware resources. Many algorithms deployed at the software level have great limitations. In addition, the routing table supported by the router locally is not immutable. It will perform update operations such as adding, deleting, and modifying routing entries. When updating routing entries, the related route forwarding will enter a lock period, and data packet forwarding will stop, resulting in forwarding delays and even data packet loss. Therefore, when considering using hardware FPGA to accelerate the LPM algorithm, it is necessary to weigh the three indicators of resource consumption, search speed, and update delay.

[0053] When using hardware FPGA for LPM search, it can be divided into two types, one is based on TCAM search, and the other is based on RAM search. The TCAM-based search method has higher search performance, but compared with RAM, the TCAM-based search method consumes more computing resources and storage resources, and is not suitable for scenarios with tens of thousands of isolated virtual networks and hundreds of thousands of routing entries. In addition, the routing table needs to be stored in TCAM in a specific order. A single routing entry update may cause most of the TCAM content to be rewritten, resulting in a large update delay. The RAM-based search method requires multiple accesses to the memory. Compared with the TCAM method, the computing resources and storage resources are much less consumed, the update delay is smaller, but the search speed is slower. In general, the two methods of using hardware FPGA for LPM search have their own advantages and disadvantages. If you want to take into account the inspection speed, resource consumption and update delay at the same time, you can make up for it by designing a suitable search mechanism and an efficient memory structure. The RAM-based search method has become the mainstream search method due to its low resource consumption and update delay. By combining hash algorithms, prefix trees, Bloom filters, etc., the RAM-based search method has a great advantage.

[0054] Taking the prefix tree as an example, the related technology constructs a prefix tree, obtains the target address from the IP data packet after receiving the IP data packet, and then finds the routing entry with the largest prefix match with the target address by searching the prefix tree, and then sends the data packet to the address indicated by the routing entry. When constructing the prefix tree, the related technology uses 8 bits as units and constructs a multi-level sub-prefix tree in the order of bits from high to low, and the multi-level sub-prefix trees are cascaded to form a prefix tree. The prefix tree has two properties. The first property is that the root node does not contain characters, and each of the remaining nodes contains a node character and a node valid indicator bit. The value of the node valid indicator bit includes 0 or 1. When the value of the node valid indicator bit is 0, it means that the string obtained by connecting the node characters on the entire path from the root node to the node is invalid. The so-called invalid means that the connected string does not match the prefixes of each valid routing entry supported by the router; the second property is: the node characters on the entire path from the root node to a certain node are connected, and the resulting string is the string corresponding to the node, which is used to represent a possible combination of 8-bit binary numbers.

[0055] See also Figure 1 , which shows a schematic diagram of the related art constructing a first-level sub-prefix tree based on the high 8 bits of five valid routing entries, the five valid routing entries include 0.0.0.0 / 0, 255.168.1.1 / 1, 12.168.20.16 / 2, 1.65.20.16 / 12, 255.20.16.1 / 8, wherein the entry identifier of the valid routing entry 0.0.0.0 / 0 is R1, and the corresponding binary string is.; the valid routing entry ... The entry identifier of 8.1.1 / 1 is R2, and the corresponding binary string is 1; the entry identifier of the valid routing entry 12.168.20.16 / 2 is R3, and the corresponding binary string is 00; the entry identifier of the valid routing entry 1.65.20.16 / 12 is R4, and the corresponding binary string is 00000001_0100; the entry identifier of the valid routing entry 255.20.16.1 / 8 is R5, and the corresponding binary string is 11111111. Set the root node to an empty character, the left child node character of each node to 0, and the right child node character to 1. The process of constructing the first-level sub-prefix tree based on the above five valid routing entries is as follows:

[0056] 1. Construct a root node. The node character of the root node is a null character, and the node valid indicator bit is 1 (because the valid routing entry 0.0.0.0 / 0 is a null character, the null character has a corresponding valid routing entry, and its node valid indicator bit is 1).

[0057] 2. Construct the left child node and the right child node for the root node. The left child node and the right child node belong to the nodes of the first layer of the first-level sub-prefix tree, corresponding to the highest bit in the upper 8 bits (i.e., the first bit from left to right). Among them, the node character of the left child node is 0, and the node valid indicator bit is 0 (because there is no 0 in the binary string of the five valid routing entries, the node valid indicator bit is 0); the node character of the right child node is 1, and the node valid indicator bit is 1 (because there is 1 in the binary string of the five valid routing entries, the node valid indicator bit is 1).

[0058] 3. Construct a left child node and a right child node for the left child node of the root node, and construct a left child node and a right child node for the right child node of the root node. The constructed left child node and right child node belong to the nodes of the second layer of the first-level sub-prefix tree, corresponding to the second highest bit in the high 8 bits (i.e., the second bit from the right). Among them, the node character of the left child node constructed for the left child node of the root node is 0, and the node valid indicator bit is 1 (the string obtained by connecting the node characters on the entire path from the root node to the child node is 00. Since 00 exists in the binary string of the five valid routing entries, the node valid indicator bit is 1); the node character of the right child node constructed for the left child node of the root node is 1, and the node valid indicator bit is 0 (the string obtained by connecting the node characters on the entire path from the root node to the child node is 01. Since 01 does not exist in the binary string of the five valid routing entries, the node valid indicator bit is 0). The node character of the left child node constructed for the right child node of the root node is 0, and the node valid indicator bit is 0 (the string obtained by connecting the node characters passing through the entire path from the root node to the child node is 10. Since 10 does not exist in the binary strings of the five valid routing entries, the node valid indicator bit is 0); the node character of the right child node constructed for the right child node of the root node is 1, and the node valid indicator bit is 0 (the string obtained by connecting the node characters passing through the entire path from the root node to the child node is 11. Since 11 does not exist in the binary strings of the five valid routing entries, the node valid indicator bit is 0).

[0059] 4. The third to eighth layers of the first-level sub-prefix tree are constructed in sequence using the above method. The node valid indicator bits of the node characters 00000001 and 11111111 in the eighth layer are 1, and the node valid indicator bits of other node characters are all 0. The tree structure formed by the nodes from the root node to the eighth layer is called the first-level sub-prefix tree.

[0060] After the first-level sub-prefix tree is constructed, the structure of the first sub-prefix tree needs to be stored in RAM. For the convenience of storage, the relevant technology assigns a base address to the root node, and constructs a prefix bitmap based on the node valid indication bit corresponding to each node or sub-node, and then based on the prefix bitmap, accumulates all the high bits before the current node to obtain the offset address of the current node relative to the root node, and then adds the offset address to the base address to obtain the storage address of the current node, and then stores the entry identifier of the valid routing entry corresponding to the node character of the node or sub-node according to the storage address, and the next hop route of the router indicated by the entry identifier. Among them, when the prefix bitmap is constructed, starting from the root node, the node valid indication bit of each node or sub-node is stored in sequence from top to bottom and from left to right, and finally a 255-bit prefix bitmap is obtained. Figure 1 The node valid indicator bit of the root node is 1, the node valid indicator bit of the left child node of the root node is 0, the node valid indicator bit of the right child node of the root node is 1, the node valid indicator bit of the left child node of the left child node of the root node is 1, the node valid indicator bit of the right child node of the left child node of the root node is 0, the node valid indicator bit of the left child node of the right child node of the root node is 0, the node valid indicator bit of the right child node of the right child node of the root node is 1, ..., and so on, until the next child node of the seventh layer, fill in the node valid indicator bits of these nodes or child nodes in the corresponding spaces in turn, and get Figure 1 The prefix bitmap shown. Figure 1 In the prefix bitmap shown, the offset address of the 253th bit is equal to the offset address of the 255th bit + the offset address of the 254th bit. Figure 1 The offset address of the 253rd bit is 1. In addition, the RAM stores the entry identifier of the valid routing entry corresponding to the valid node.

[0061] In addition, analysis of the above five valid routing entries shows that the maximum mask length of the above five routing entries is 12, so it is necessary to build a two-level sub-prefix tree. Figure 1Only the construction process of the first-level sub-prefix tree is shown. The construction process of the second-level sub-prefix tree is similar to that of the first-level sub-prefix tree, and the specific construction process will not be repeated. However, the second-level sub-prefix tree is constructed on the basis of the first-level sub-prefix tree. After the eighth layer of the first-level sub-prefix tree is constructed to obtain 256 high-8-bit binary strings, the relevant technology will also construct a sub-pointer bitmap. The sub-pointer bitmap includes 256 bits, and each bit is used to indicate the validity of a high-8-bit binary string. If a high-8-bit binary string is a high-8-bit binary string corresponding to five valid routing entries, then the high-8-bit binary string is valid, and then the high-8-bit binary string is filled with 1 at the corresponding position of the sub-pointer bitmap; if a high-8-bit binary string is not a high-8-bit binary string corresponding to five valid routing entries, then the high-8-bit binary string is invalid, and then the high-8-bit binary string is filled with 0 at the corresponding position of the sub-pointer bitmap. By adopting this method, a 256-bit sub-pointer bitmap can be finally obtained. See. Figure 1 The high 8-bit binary strings corresponding to the five valid routing entries include 00000001 and 11111111, so the positions corresponding to 00000001 and 11111111 in the sub-pointer bitmap are 1, and the rest of the positions are 0.

[0062] Analyzing the construction process of the first-level sub-prefix tree above, we can see the following points:

[0063] First, the number of valid routing entries with mask length less than 8 determines the valid number of root nodes and nodes at layers 1 to 7, which can be represented by a 255-bit prefix bitmap. The string represented by the valid node is the valid routing entry.

[0064] Second, the number of valid routing entries with mask length greater than 7 determines the valid number of layer 8 nodes, which can be represented by a 256-bit child pointer bitmap. A valid node indicates that this node contains a subtree, that is, a sub-prefix tree of the next level.

[0065] Third, the content stored in RAM of the root node and the 1st to 7th layer nodes is the next hop route, and the content stored in RAM of the eighth layer node is the root node address of the sub-prefix tree.

[0066] Figure 2 The process of performing routing entry lookup based on the constructed prefix tree in the related art is shown in FIG. Figure 2The prefix tree includes 4 levels. The valid routing bits of the first-level sub-prefix tree are [31, 24], the valid routing bits of the second-level sub-prefix tree are [23, 16], the valid routing bits of the third-level sub-prefix tree are [15, 8], and the valid routing bits of the fourth-level sub-prefix tree are [7, 0]. After receiving an IP data packet, the destination address in the IP data packet is matched with each valid routing entry supported by the local router. When matching, the first-level sub-prefix tree is queried every 8 bits starting from the high bit, and the sub-pointer bitmap and prefix bitmap are searched in parallel until the longest match is found at a valid node. The route of the next hop is taken out from the RAM according to the base address and the offset address indicated by the prefix bitmap.

[0067] Assume that the router supports a valid route entry 255.20.16.1 / 25. After masking 255.20.16.1 / 25, the binary string obtained is 11111111_00010100_00010000_0. Among them, the binary string represented by the valid node of the first-level child prefix tree is 11111111, the binary string represented by the valid node of the second-level child prefix tree is 00010100, the binary string represented by the valid node of the third-level child prefix tree is 00010000, and the binary string represented by the valid node of the fourth-level child prefix tree is 0. Based on this prefix tree, if you want to find a matching valid routing entry for the target address 255.20.16.10, you can first perform a mask operation on the target address 255.20.16.10, and the resulting binary string is 11111111_00010100_00010000_00001010. Start by matching the binary string from the first-level child prefix tree to the valid node of the fourth-level child prefix tree (the string represented is 0). At this time, there is no longer match, indicating that the valid routing entry is hit, and then the valid routing entry is used as the next hop. Taking the specific search for the target address 255.20.16.10 as an example, the query process is as follows:

[0068] 1. Get the high 8 bits of the binary string 11111111 of the target address 255.20.16.10, and match the binary string 11111111 at each level of the first-level child prefix tree. The matching strings at levels 1 to 8 are 1, 11, 111, 1111...11111111. Based on the constructed prefix tree, it is found that 1, 11, 111, 1111, ...1111111 (7 1s) are all invalid nodes, that is, the valid bit of the node is 0. According to the child pointer bitmap and prefix bitmap, the only matching string in the valid node is 111111111.

[0069] 2. Since the node with the string 11111111 is an 8th-level node and a valid node, jump to the first-level sub-prefix tree to perform the above search. After searching in the first-level sub-prefix tree, search in the first-level sub-prefix tree and the third-level sub-prefix tree.

[0070] 3. When searching in the fourth-level sub-prefix tree, obtain the lower 8-bit binary string 00001010 of the target address 255.20.16.10, and then perform string matching at each level of the fourth-level sub-prefix tree. The matching strings at levels 1 to 8 are 0 (the first bit of 00001010), 00 (the first 2 bits of 00001010), 000 (the first 3 bits of 00001010), 0000 (the first 4 bits of 00001010), 00001 (the first 5bit), 000010 (the first 6bits of 00001010), 0000101 (the first 7bits of 00001010), 00001010 (the first 8bits of 00001010). According to the child pointer bitmap and prefix bitmap, the only matching string in the valid node is 0. Therefore, it is determined that the routing entry hit by 255.20.16.10 is 255.20.16.1 / 25. The routing entry of the next hop is taken out from the RAM according to the base address of the 4th-level child prefix tree and the offset address indicated by the prefix bitmap.

[0071] Still taking the example of a router supporting a valid route entry 255.20.16.1 / 25, suppose you want to find a matching valid route entry for the target address 255.20.16.128, you can first perform a mask operation on the target address 255.20.16.128, and the resulting binary string is 11111111_00010100_00000001_10000000, and match the binary string from the first-level sub-prefix tree to the fourth-level sub-prefix tree. The fourth-level sub-prefix tree has only one valid node, and the binary string represented is 0, while 255.20.16.128 The lower eight bits of the binary string are 10000000, which does not hit the valid node in the fourth-level sub-prefix tree of the routing rule. At this time, you need to go back from the fourth level to the root node. You find that the root node is not a valid node. Continue to go back to the third level and find that the node hit by the route is the eighth layer. Continue to go back to the second level and the first level and hit the eighth layer as well, but there is no next-hop routing entry in the hit eighth layer. Therefore, it can be determined that the target address 255.20.16.128 does not hit the routing rule (that is, a valid routing entry). At this time, the default routing entry in the root node of the first-level sub-prefix tree can only be used as the next-hop routing entry.

[0072] Furthermore, if you want 255.20.16.128 to hit the routing rule, you need to add a new valid routing entry 255.20.16.11 / 24 in the router. After masking 255.20.16.11 / 24, the binary string obtained is 111111111_00010100_00010000. This valid routing entry will establish a valid node at the root node of the fourth-level sub-prefix tree. When 255.20.16.128 falls back in the fourth-level sub-prefix tree, it will hit the valid routing entry when it returns to the root node, and then use the valid routing entry 255.20.16.11 / 24 as the next hop routing entry.

[0073] Furthermore, since the valid nodes in the prefix tree are stored sequentially in RAM, in order to support the update operations such as adding, deleting, and modifying the valid routing entries, the RAM of the related art needs to reserve RAM space for each level of the sub-prefix tree. When performing an update operation on the valid routing entries in the routing table, it is necessary to rewrite all the storage contents of the nodes after the changed node in RAM to ensure the accuracy of the update operation.

[0074] Compared with the TCAM method, the method of constructing a prefix tree to perform routing entry lookup in the related art has obvious advantages in terms of resource consumption and search speed. However, the prefix tree constructed in the related art still has the following problems:

[0075] Problem 1: Too many nodes

[0076] Since the related technology constructs a multi-level sub-prefix tree based on the mask length of the valid routing entry, and cascades the multi-level sub-prefix trees to form a prefix tree, and each level of the sub-prefix tree includes more nodes, this problem is particularly significant when the mask length of the routing entry is discrete. For example, when there are valid routing entries with a mask length exceeding 23, it is necessary to construct a four-level sub-prefix tree. More importantly, the number of nodes included in the constructed prefix tree is large, but the number of valid nodes corresponding to the valid routing entries is not large, so Figure 1 Taking the constructed first-level sub-prefix tree as an example, there are only 5 valid nodes, but the number of nodes included in the constructed first-level sub-prefix tree reaches hundreds, which seriously wastes computing resources and storage resources. When searching for valid routing entries based on the constructed prefix tree, the search efficiency is low.

[0077] Problem 2: Low RAM storage efficiency

[0078] Since the valid nodes of the prefix tree are stored sequentially in RAM, in order to support the increase of valid routing entries, RAM space needs to be reserved for each level of the sub-prefix tree, resulting in low RAM resource utilization. And when the RAM reserved for a certain level of the sub-prefix tree is consumed, the update of valid routing entries will be restricted.

[0079] Problem 3: Long update delay

[0080] Since the valid nodes of the prefix tree are stored sequentially in the RAM, when a valid routing entry needs to be updated, the subsequent RAM content of a certain node will be rewritten, resulting in excessive update delay.

[0081] In order to solve the above-mentioned problems existing in the related art, the present application provides a method for constructing a prefix tree, which constructs a prefix tree based on a mask level. By constructing a prefix tree, all valid routing entries can be covered, and the constructed prefix tree only includes valid nodes, and does not include invalid nodes, which greatly reduces the number of nodes, saves computing resources and storage resources, and can also improve the search efficiency when searching based on the constructed prefix tree. In addition, the present application adopts a hash algorithm to realize the jump between nodes, and the node information of each node is stored non-sequentially in RAM. There is no need to reserve RAM space for each level of the prefix tree, so as to realize RAM resource pooling scheduling and improve RAM resource utilization. Furthermore, since the node information of each node is not stored sequentially in RAM, when the valid routing entry is updated, it is only necessary to store the node information corresponding to the updated valid routing entry in RAM, and there is no need to pay attention to the storage location.

[0082] In summary, this application provides a mask-level tree construction mechanism with flexible tree construction, efficient memory structure, and low update delay, which overcomes the problems of large number of nodes, low RAM storage efficiency, and large update delay when the related technology constructs a prefix tree and implements the constructed prefix tree as a search tree mechanism in FPGA. The specific solution is reflected in the following three aspects:

[0083] First, based on the mask length range, the mask level is determined, and then a prefix tree is constructed based on the mask level, so that all valid routing entries are established in a prefix tree without the need for multi-level tree sets. The sparser the mask level distribution, the simpler the constructed prefix tree, and the higher the search efficiency when searching based on the prefix tree in the future.

[0084] Secondly, hash calculation is used to realize the jump between nodes, and the node information is stored in RAM in a non-sequential manner, realizing RAM resource pool scheduling. When updating effective routing entries, the pre-stored RAM resources can be shared, realizing an efficient RAM storage structure and improving RAM storage efficiency.

[0085] Thirdly, when valid routing entries are updated, only relevant nodes are updated, and nodes are not updated on a large scale. The update scope is small and the update delay is small. For example, when adding valid routing entries, if the mask length of the newly added valid routing entry already exists, only the mask of the branch node and the storage location of the leaf node related to the newly added valid routing entry are changed. If the mask length of the newly added valid routing entry does not exist, a new layer of nodes needs to be added between the original branch node and the leaf node. When deleting a valid routing entry, only the node information related to the valid routing entry is deleted.

[0086] The present application embodiment provides a method for constructing a prefix tree. Taking an electronic device executing the present application embodiment as an example, the electronic device may be a device with a network routing function, such as a router. Figure 3 , the method flow provided in the embodiment of the present application includes:

[0087] 301. According to the mask length of at least one valid routing entry, obtain the number of layers of the prefix tree and the valid bit range of each layer of the routing.

[0088] For any router, in order to realize the network address lookup function of the router, a prefix tree for route lookup can be constructed for the router based on at least one valid route entry supported by the router. Generally speaking, different routers have different properties and support different valid route entries. In order to distinguish different valid route entries, a different entry identifier can be set for each valid route entry, and the entry identifier is used to uniquely identify a valid route entry in the router. The route entry can be R0, R1, R2, etc. The mask length of each valid route entry is different. According to the mask length rule, the maximum mask length is 32, the minimum mask length is 0, and the mask length of the valid route entry is between 0 and 32. According to the mask length of at least one valid route entry, after masking at least one valid route entry, a binary string corresponding to each valid route entry can be obtained, and the length of these binary strings is between 0 and 32. For example, the router supports nine valid routing entries, namely 0.0.0.0 / 0, 100.64.0.0 / 10, 172.17.112.0 / 20, 172.17.0.0 / 20, 172.17.96.0 / 20, 172.17.208.0 / 20, 192.168.10.0 / 24, 192.168.3.0 / 24, 192.168.1.0 / 24, among which 0.0.0. The entry identifier of 0 / 0 is R0, and its corresponding binary string is a null character. The entry identifier of 100.64.0.0 / 10 is R1, and its corresponding binary string is 0110010001; the entry identifier of 172.17.112.0 / 20 is R2, and its corresponding binary string is 1010110000_0100010111; the entry identifier of 172.17.0.0 / 20 is R3, and its corresponding binary string is The string is 1010110000_0100010000; the entry identifier of 172.17.96.0 / 20 is R4, and its corresponding binary string is 1010110000_0100010110; the entry identifier of 172.17.208.0 / 20 is R5, and its corresponding binary string is 1010110000_0100011101; the entry identifier of 192.168.10.0 / 24 is R6 , and its corresponding binary string is 1100000010_1010000000_1010; the entry identifier of 192.168.3.0 / 24 is R7, and its corresponding binary string is 1100000010_1010000000_0011; the entry identifier of 192.168.1.0 / 24 is R8, and its corresponding binary string is 1100000010_1010000000_0001.

[0089] Among them, the effective bit range of the route of each layer refers to the bit range of the binary characters of the effective route entries intercepted at each layer in order from high to low. When the number of layers of the prefix tree and the effective bit range of the route of each layer are obtained according to the mask length of at least one effective route entry, the number of non-zero mask lengths in at least one effective route entry can be determined as the number of layers of the prefix tree. For example, in the above example, the mask lengths of the nine effective route entries include 0, 10, 20, and 24, then the mask length of length 0 is excluded, and the number of non-zero mask lengths is 3, then the number of layers of the prefix tree is determined to be 3.

[0090] The present application obtains the effective bit range of the route of each layer of the prefix tree according to the mask length of at least one effective route entry, by sorting the mask length of at least one effective route entry in order from small to large, and determining the mask length range between two adjacent layers as the effective bit range of the route of one layer. Specifically, if there is no default route with a mask length of 0 in at least one effective route entry, the default route is placed at the root node, and then the length range between 0 and the minimum mask length is used as the effective range of the route of the first layer, and the minimum prefix length is the node of the first level; the length range between the minimum mask length and the second smallest mask length is used as the effective range of the route of the second layer, and the second smallest prefix length is the node of the second level; and so on, the length range between the second largest mask length and the maximum mask length is used as the effective range of the route of the last layer. If there is a default route with a mask length of 0 in at least one valid route entry, the default route is placed at the root node, and then the length range between 0 and the non-zero minimum mask length is used as the effective range of the first-level route. At this time, the non-zero minimum prefix length is the node of the first level; the length range between the non-zero minimum mask length and the second smallest mask length is used as the effective range of the second-level route. At this time, the second smallest prefix length is the node of the second level; and so on, the length range between the second largest mask length and the maximum mask length is used as the effective range of the last level.

[0091] For example, the router supports nine valid routing entries, namely 0.0.0.0 / 0, 100.64.0.0 / 10, 172.17.112.0 / 20, 172.17.0.0 / 20, 172.17.96.0 / 20, 172.17.208.0 / 20, 192.168.10.0 / 24, 192.168.3.0 / 24, 192.168.1.0 / 24. Sort the mask lengths of the nine valid routing entries from small to large, and you get The sorting results are: 0, 10, 20, 24. Based on the sorting results, 0.0.0.0 / 0 is placed at the root node, and then the length range between 0 and the non-zero minimum mask length 10 [0,9] is determined as the effective routing range of the first layer, the length range between the non-zero minimum mask length 10 and the second smallest mask length 20 [10,19] is determined as the effective routing range of the second layer, and the length range between the second smallest mask length 20 and the maximum mask length 24 [20,23] is determined as the effective routing range of the third layer.

[0092] 302. Determine the node of each layer of the prefix tree according to the binary string obtained after the valid bit range of each layer of the prefix tree and at least one valid routing entry are masked.

[0093] Among them, the nodes of each layer of the prefix tree include leaf nodes and branch nodes, the leaf nodes correspond to a valid routing entry, the branch nodes do not correspond to a valid routing entry, but are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer. Each node of each layer corresponds to a routing valid bit, and the routing valid bit refers to a binary string intercepted from a binary string corresponding to at least one valid routing entry based on the routing valid bit range of each layer. Specifically, according to the routing valid bit range of each layer of the prefix tree and the binary string obtained after the mask operation of at least one valid routing entry, when determining the nodes of each layer of the prefix tree, the following method can be used: according to the routing valid bit range corresponding to each layer, from the binary string obtained after the mask processing of at least one valid routing entry, a binary string within the length range indicated by the routing valid bit range of each layer is intercepted, and at least one binary string is obtained, and a binary string corresponding to each layer is used as a node to obtain the nodes of each layer of the prefix tree. That is, the number of nodes of each layer depends on the type of binary string. There are several binary strings, that is, there are several nodes. In order to facilitate the distinction between nodes of the same layer and different layers, different node identifiers can be set for different nodes, and the node identifier can be expressed in at least one form of numbers, letters, symbols, etc. For example, the node ID 0 may be set for the root node. If the first layer includes three nodes, the node IDs 1, 2, and 3 may be set for the three nodes, respectively.

[0094] Still taking the above example, the router supports binary strings corresponding to nine valid routing entries., 0110010001, 1010110000_0100010111, 1010110000_0100010000, 1010110000_0100010110, 1010110000_0100011101, 1100000010_1010000000_1010, 1100000010_1010000000_0011, 1100000010_1010000000_0001. The valid range of the first-layer route is [0,9]. It is necessary to extract the binary string from the high 1 to high 10 bits from the binary string corresponding to the valid route entry. Except for the default route, the binary string extracted from 0110010001 is 0110010001, the binary string extracted from 1010110000_0100010111, 1010110000_0100010000, 1010110000_0100010110, and 1010110000_0100011101 are all 1010110000, and the binary string extracted from 1100000010_10 The binary strings intercepted from 10000000_1010, 1100000010_1010000000_0011, and 1100000010_1010000000_0001 are all 1100000010, and finally three binary strings are obtained. A node with node identification as ID2 is constructed for the binary string 0110010001, a node with node identification as ID1 is constructed for the binary string 1010110000, and a node with node identification as ID3 is constructed for the binary string 1100000010, and finally the three nodes included in the first layer are obtained.

[0095] The valid range of the second-layer route is [10,19]. It is necessary to extract the binary string from the high 11 bits to the high 20 bits from the binary string corresponding to the valid route entry. Except for the default route and the binary string with a mask length of 10, the binary string extracted from 1010110000_0100010111 is 0100010111, and a node with node ID 4 is constructed for the binary string. The binary string extracted from 1010110000_0100010000 is 0100010000, and a node with node ID 5 is constructed for the binary string. The binary string intercepted from 00010110 is 0100010110, and a node with node identification as ID6 is constructed for the binary string. The binary characters intercepted from 1010110000_0100011101 are 0100011101, and a node with node identification as ID7 is constructed for the binary string. Since the binary strings from the high 1st bit to the high 10th bit of the valid routing entries corresponding to node ID4, node ID5, node ID6 and node ID7 are the same, which are all 1010110000, these nodes are all child nodes of node ID2. In other words, the upper-layer nodes of these nodes are all node ID2. Next, the binary characters from the high 11 bits to the high 20 bits are intercepted from 1100000010_1010000000_1010, 1100000010_1010000000_0011, and 1100000010_1010000000_0001. The intercepted binary strings are all 1010000000. A node with a node ID of ID8 is constructed for the binary string. The binary string from the high 1 bit to the high 10 bits of the valid routing entry corresponding to the node ID8 is 1100000010, so the node is the child node of the node ID3. At this time, it can be determined that the second layer includes five nodes, namely, node ID4, node ID5, node ID6, node ID7, and node ID8, wherein node ID4, node ID5, node ID6, and node ID7 have the same upper layer node, namely, node ID1.

[0096] The valid range of the third-layer route is [20, 23]. It is necessary to extract the binary string from the high 21 bits to the high 24 bits from the binary string corresponding to the valid route entry. Except for the default route and the binary string with a mask length less than 20, the binary string extracted from 1100000010_1010000000_1010 is 1010, and a node with node ID 9 is constructed for the binary string; the binary string extracted from 1100000010_1010000000_0011 is 0011, and a node with node ID 10 is constructed for the binary string; the binary string extracted from 1100000010_1010000000_0001 is 0001, and a node with node ID 11 is constructed for the binary string. At this time, it can be determined that the third layer includes three nodes, namely node ID9, node ID10, and node ID11, wherein node ID9, node ID10, and node ID11 have the same upper layer node, namely node ID8.

[0097] 303. Starting from the root node, connect the nodes corresponding to each valid routing entry layer by layer until the leaf node, and obtain a prefix tree.

[0098] In the embodiment of the present application, the constructed prefix tree has the following properties:

[0099] 1) If the valid routing entries supported by the router include the default route, the root node is the default route with a mask length of 0. If the valid routing entries supported by the router do not include the default route, the root node is empty, that is, the root node corresponds to an empty character or a valid routing entry with a mask length of 0.

[0100] 2) The number of layers of the prefix tree is not fixed. According to the rule that the maximum mask length is 32, the maximum number of layers is 32 layers plus the layer where the root node is located, a total of 33 layers; each layer has two types of nodes:

[0101] The first type is a leaf node, which corresponds to a valid routing entry;

[0102] The second type is a branch node, which does not necessarily correspond to a valid routing entry and is used to jump to a leaf node.

[0103] 3) At the same level, the type of binary number after the mask operation determines the number of branch nodes. The number of valid routing entries contained in this level determines the number of leaf nodes. Each node will be assigned a node identifier.

[0104] Based on the specific properties of the above prefix tree, after determining the nodes of each layer of the prefix tree, starting from the root node, connect the nodes corresponding to each valid routing entry layer by layer until the leaf node, and obtain a prefix tree. The prefix tree can characterize the connection relationship between nodes of different layers, the node identifier of each node, and its corresponding routing valid bit and the entry identifier of the valid routing entry.

[0105] Still taking the above example, see Figure 4 , the router supports the default route with a mask length of 0, then the node ID0 corresponding to the default route R0 is set as the root node, the route valid bit range of the next layer node of node ID0 is [0,9], the next layer nodes of node ID0 are node ID1, node ID2 and node ID3, node ID2 is a leaf node, corresponding to the valid route entry R1. Node ID1 and node ID3 are branch nodes, among which the route valid bit range of the next layer node of node ID1 is [10,19], the next layer nodes of node ID1 are node ID4, node ID5, node ID6 and node ID7, node ID4, node ID5, node ID6 and node ID7 are all leaf nodes, node ID4 corresponds to the valid route entry R2, node ID5 corresponds to the valid route entry R3, node ID6 corresponds to the valid route entry R4, node ID7 corresponds to the valid route entry R5; the route valid bit range of the next layer node of node ID3 is [10,19 】, the next layer node of node ID1 is node ID8, node ID8 is a branch node, the route valid bit range of the next layer node of node ID8 is [20,23], the next layer nodes of node ID8 are node ID9, node ID10 and node ID11, node ID9, node ID10 and node ID11 are all leaf nodes, node ID9 corresponds to valid route entry R6, node ID10 corresponds to valid route entry R7, node ID11 corresponds to valid route entry R8, so far, all valid route entries are represented in the tree structure of the prefix tree, and the prefix tree is constructed.

[0106] The embodiment of the present application is a search mechanism based on RAM. After constructing the prefix tree, the node information of each node in the prefix tree needs to be stored in RAM so that the subsequent router can find the next hop route for the data packet after receiving the data packet carrying the target address. The key to storing the node information of each node in the prefix tree is to determine the storage address of each node, and then store the node information of each node in the prefix tree based on the determined storage address. Figure 5 , which shows the storage process of node information for each node in the prefix tree, the method process includes:

[0107] 501. For any node corresponding to a valid routing entry in the prefix tree, the storage address of the current layer node in the random access memory RAM is determined according to the node identifier of the previous layer node and the routing validity bit of the current layer node.

[0108] Taking any valid routing entry as an example, the storage address of the current layer node in the RAM can be determined based on the node corresponding to the valid routing entry in the prefix tree, according to the node identifier of the upper layer node and the routing valid bit of the current layer node. Specifically, based on the upper and lower layer nodes indicated by the prefix tree, according to the node identifier of the upper layer node and the routing valid bit of the current layer node, when determining the storage address of the current layer node in the random access memory RAM, the node identifier of the upper layer node and the routing valid bit of the current layer node can be spliced ​​to obtain the search information of the upper layer node, and then the search information of the upper layer node is hashed to obtain the storage address of the current layer node. Among them, the storage address of the current node is used to store the node information of the current layer node, and the node information of the current layer node may include the node identifier of the current layer node and the entry identifier of the valid routing entry, etc., or may include the node identifier of the current layer node and the routing valid bit range of the next layer node, etc. Whether the node information of the current layer node is specifically the entry identifier of a valid routing entry or the valid routing bit range of the next layer node depends on the type of the current layer node. If the current layer node is a leaf node, the node information of the current layer node includes the node identifier of the current layer node and the entry identifier of the valid routing entry; if the current layer node is a branch node, the node information of the current layer node includes the node identifier of the current layer node and the valid routing bit range of the next layer node.

[0109] It should be noted that the above description is based on one valid routing entry as an example, and the storage address of each layer of nodes can be determined according to the above method for other valid routing entries. In addition, since there is a same node among the nodes corresponding to at least one valid routing entry, when the storage address of a node is determined based on a valid routing entry, there is no need to determine the storage address of the node based on another valid routing entry.

[0110] See also Figure 6, node ID0 is the root node, node ID1, node ID3 and node ID8 are branch nodes, node ID2, node ID4, node ID5, node ID6, node ID7, node ID9, node ID10 and node ID11 are leaf nodes. The node of the previous layer is node ID0, the node of the current layer is node ID1, the node identifier of the previous layer node is 0, and the routing valid bits of the current layer node are 1010110000. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the search information 0_1010110000 of node ID0. The search information of node ID0 is hashed to obtain the storage address of node ID1. The storage address of node ID1 is used to store the node identifier 1 of node ID1 and the routing valid bit range [10,19] of the next layer node; the node of the previous layer is node ID0, the node of the current layer is node ID2, the node identifier of the previous layer node is 0, and the routing valid bits of the current layer node are 0110010001. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the node The search information of node ID0 is 0_0110010001, and the search information of node ID0 is hashed to obtain the storage address of node ID2. The storage address of node ID2 is used to store the node identifier 2 of node ID2 and the entry identifier R1 of the valid routing entry; the previous layer node is node ID0, the current layer node is node ID3, the node identifier of the previous layer node is 0, and the routing valid bits of the current layer node are 1100000010. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the search information of node ID0 0_1100000010, and the search information of node ID0 is hashed to obtain the storage address of node ID3. The storage address of node ID3 is used to store the node identifier 3 of node ID3 and the routing valid bit range [10,19] of the next layer node.

[0111] The node of the previous layer is node ID1, the node of the current layer is node ID4, the node identifier of the previous layer node is 1, and the routing valid bits of the current layer node are 0100010111. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the search information 1_0100010111 of node ID1. The search information of node ID1 is hashed to obtain the storage address of node ID4. The storage address of node ID4 is used to store the node identifier 4 of node ID4 and the entry identifier R2 of the valid routing entry. ; The node of the previous layer is node ID1, the node of the current layer is node ID5, the node identifier of the previous layer node is 1, and the routing valid bit of the current layer node is 0100010000. The node identifier of the previous layer node is concatenated with the routing valid bit of the current layer node to obtain the search information 1_0100010000 of node ID1. The search information of node ID1 is hashed to obtain the storage address of node ID5. The storage address of node ID5 is used to store the node identifier 5 of node ID5 and the entry identifier R3 of the valid routing entry. ; The node of the previous layer is node ID1, the node of the current layer is node ID6, the node identifier of the previous layer node is 1, and the route valid bit of the current layer node is 0100010110. The node identifier of the previous layer node is concatenated with the route valid bit of the current layer node to obtain the search information 1_0100010110 of node ID1. The search information of node ID1 is hashed to obtain the storage address of node ID6. The storage address of node ID6 is used to store the node identifier 6 of node ID6 and the entry identifier R of the valid route entry. 4; The node of the previous layer is node ID1, the node of the current layer is node ID7, the node identifier of the previous layer node is 1, and the valid routing bit of the current layer node is 010001101. The node identifier of the previous layer node is concatenated with the valid routing bit of the current layer node to obtain the search information 1_010001101 of node ID1. The search information of node ID1 is hashed to obtain the storage address of node ID7. The storage address of node ID7 is used to store the node identifier 7 of node ID7 and the entry identifier R5 of the valid routing entry.

[0112] The previous layer node is node ID3, the current layer node is node ID8, the node identifier of the previous layer node is 3, and the routing valid bits of the current layer node are 1010000000. The node identifier of the previous layer node and the routing valid bits of the current layer node are concatenated to obtain the search information 3_1010000000 of node ID3. The search information of node ID3 is hashed to obtain the storage address of node ID8. The storage address of node ID8 is used to store the node identifier 8 of node ID8 and the routing valid bit range [20,23] of the next layer node.

[0113] The previous layer node is node ID8, the current layer node is node ID9, the node identifier of the previous layer node is 8, and the routing valid bits of the current layer node are 1010. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the search information 8_1010 of node ID8. The search information of node ID8 is hashed to obtain the storage address of node ID8. The storage address of node ID9 is used to store the node identifier 9 of node ID9 and the entry identifier R6 of the valid routing entry; the previous layer node is node ID8, the current layer node is node ID10, the node identifier of the previous layer node is 8, and the routing valid bits of the current layer node are 0011. The node identifier of the previous layer node is concatenated with the routing valid bits of the current layer node to obtain the node ID8. Search information 8_0011, perform hash calculation on the search information of node ID8 to obtain the storage address of node ID8, the storage address of node ID10 is used to store the node identifier 10 of node ID10 and the entry identifier R7 of the valid routing entry; the previous layer node is node ID8, the current layer node is node ID11, the node identifier of the previous layer node is 8, the routing valid bit of the current layer node is 0001, the node identifier of the previous layer node is concatenated with the routing valid bit of the current layer node to obtain the search information 8_0001 of node ID8, perform hash calculation on the search information of node ID8 to obtain the storage address of node ID11, the storage address of node ID11 is used to store the node identifier 11 of node ID11 and the entry identifier R8 of the valid routing entry.

[0114] It should be noted that the hash algorithm is essentially an algorithm that maps more bits to fewer bits. For example, after performing the hash algorithm on each number in 100-200, it is represented by 0-10. The hash algorithm has such a possibility that 101 is calculated by the hash algorithm to become 5, and 150 is calculated by the hash algorithm to become 3. And because the hash algorithm represents more with less, there may be hash conflicts. For example, after processing 151 and 189 with the hash algorithm, the results obtained are both 6. In the prefix tree, the node identifiers of multiple nodes may be processed by the hash algorithm, and the same result is obtained, that is, corresponding to the same node, thereby causing an erroneous query. In order to solve the hash conflict, the search information (key) of the hash algorithm in this application is composed of: node ID_routing valid bit. The routing valid bit is determined according to the routing rules to be supported. After the rules are determined, it will not change, but the node ID can be flexibly configured. It only needs to ensure that the combination of the configured node ID and the routing valid bit is unique after calculation. For example, if the hash calculation results of 1_1001001 and 4_0100101 are the same, then when recreating the node, you can change the node ID configured in 0100101 to 5 to avoid hash conflicts.

[0115] 502. Based on the storage address of each layer of nodes corresponding to at least one valid routing entry, store the node information of each layer of nodes corresponding to at least one valid routing entry into the RAM.

[0116] After determining the storage address of each layer of nodes corresponding to at least one valid routing entry, the node information of each layer of nodes corresponding to at least one valid routing entry is stored in RAM according to the storage address. Since different nodes have different storage addresses, and these storage addresses are obtained by hash calculation and may not be continuous, the node information of the nodes in the embodiment of the present application can be stored in disorder, without the need for sequential storage as in the related art. The storage of node information is more flexible and can realize RAM resource pooling scheduling. When valid routing entries are updated, pre-stored RAM resources can be shared, the memory structure is more efficient, the RAM resource utilization rate is higher, and there is no need to update the content in RAM on a large scale, and the update delay is small.

[0117] In another embodiment of the present application, for a branch node without a leaf node, the branch node can be merged with the next layer node, thereby saving storage resources and improving the subsequent search speed. Still taking any of the above-mentioned valid routing entries as an example, if the number of the next layer nodes of the current layer node is one, and the next layer node is not a leaf node, that is, the current layer node is a branch node, then the current layer node is merged with the next layer node to obtain an updated next layer node, and the routing valid bit range of the updated next layer node is obtained by splicing the routing valid bit range of the current layer node with the routing valid bit range of the next layer node, and then the storage address of the updated next layer node is determined according to the node identifier of the previous layer node and the routing valid bit of the current layer node, and the storage address of the updated next layer node is used to store the node information of the updated next layer node. Figure 3 The prefix tree constructed by the method provided in the embodiment of the present application is observed by Figure 3 From the tree structure shown, we can see that node ID3 is a branch node and node ID3 has no leaf nodes. Then we can merge node ID3 with node ID8 to get updated node ID8. The valid range of the route corresponding to node ID8 before the update is [20, 23], and the valid range of the route corresponding to node ID8 after the update is [10, 23]. After merging node ID3 with node ID8, we can get Figure 7 The tree structure of the prefix tree shown.

[0118] Furthermore, when nodes in the prefix tree are merged, the calculation result of the hash algorithm will change, and the storage address of the updated node will also change. Before merging node ID3 with node ID8, see Figure 6, the previous layer node is node ID0, the current layer node is node ID3, the routing valid bit of the current layer node is 1100000010, the search information of node ID0 is 0_1100000010, the search information of node ID0 is hashed, and the storage address of node ID3 is obtained. The storage address of node ID3 is used to store the node identifier 3 of node ID2 and the routing valid bit range [10,19] of the next layer node. After merging node ID3 with node ID8, see Figure 8 , the previous layer node is node ID0, the current layer node is node ID8, the search information of node ID0 is still 0_1100000010, the search information of node ID0 is hashed, and the storage address of node ID8 is obtained. The storage address of node ID8 is used to store the node identifier 8 of node ID8 and the routing valid bit range [10,23] of the next layer node. Figure 6 Before merging node ID3 with node ID8, when the previous node is node ID8, the valid routing bits of the current node are 1010, 0011 or 0001. After merging node ID3 with node ID8, see Figure 8 , when the node in the previous layer is node ID 8, the valid routing bits of the node in the current layer are 1010000000_1010, 1010000000_0011 or 1010000000_0001.

[0119] The embodiment of the present application provides a RAM-based search mechanism dedicated to hardware acceleration, which builds trees according to the mask hierarchy, solving the problems of large resource consumption, low storage efficiency, and update delays in the construction of related technologies, especially for the scenario where the mask hierarchy of valid routing entries is sparsely distributed, making up for the shortcomings of the RAM-based search mechanism in table lookup efficiency. In addition, a hierarchical compression operation is performed on the basis of the mask hierarchy construction mechanism to further reduce node overhead. In addition, the jump between nodes is completed through hash calculation, and the nodes are not sensitive to the storage order, which can realize RAM resource pooling scheduling.

[0120] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described one by one here.

[0121] The embodiment of the present application provides a method for constructing a prefix tree, which applies the prefix tree constructed in the above embodiment. Taking an electronic device executing the embodiment of the present application as an example, the electronic device may be a device with a network routing function, such as a router. Fig. 9 , the method flow provided in the embodiment of the present application includes:

[0122] 901. When a target data packet is received, a target address in the target data packet is masked to obtain a target binary string.

[0123] When receiving a target data packet, the router can parse the target data packet to obtain the target address of the target data packet, and then mask the target address to obtain the target binary string corresponding to the target address. For example, if the target address is 192.168.1.25, the target address is masked and the target binary string is: 11000000_10101000_00000001_00011001.

[0124] 902. Search the target entry identifier from the RAM based on the target binary string and the route valid bit range indicated by each layer of the prefix tree.

[0125] Specifically, based on the target binary string and the route valid bit range indicated by each layer of the prefix tree, when searching the target entry identifier from the RAM, the following steps are included:

[0126] 9021. According to the route valid bit range indicated by the root node of the prefix tree, extract the first character string within the route valid bit range indicated by the root node from the target binary character string.

[0127] For example, the target binary string corresponding to the target address is: 11000000_10101000_00000001_0001100, and the valid bit range of the route indicated by the root node is [0, 9]. Then, the high 10 binary characters are intercepted from the target binary string, and the first string obtained is 1100000010.

[0128] 9022. Determine a first storage address of the first node according to the node identifier of the root node and the first character string.

[0129] Among them, the first node is the next layer node of the root node. After obtaining the first string, the node identifier of the root node and the first string are concatenated into the search information of the root node, and then the search information is hashed to obtain the first storage address of the first node. For example, the node identifier of the root node is 0, and the first string is 1100000010. The node identifier of the root node and the first string are concatenated to obtain the search information of the root node as 0_1100000010. The search information is hashed to obtain the first storage address of the first node.

[0130] 9023. Obtain first node information corresponding to the first storage address from the RAM.

[0131] Based on the first storage address, first node information corresponding to the first storage address can be obtained from the RAM.

[0132] 9024. If the first node information does not include an entry identifier of a valid routing entry, obtain a valid bit range of the routing of the second node.

[0133] The second node is the node at the next level of the first node. If the first node information does not include the entry identifier of the valid routing entry, it means that the first node is a branch node and has no corresponding valid routing entry. At this time, the valid bit range of the second node's route can be obtained from the first node information, and then further search is required.

[0134] In another possible implementation, if the first node information includes an entry identifier of a valid routing entry, indicating that the first node is a leaf node, corresponding to a valid routing entry, the entry identifier included in the first node information may be determined as the target entry identifier.

[0135] 9025. According to the routing valid bit range of the second node, intercept a second character string within the routing valid bit range indicated by the second node from the target binary character string.

[0136] For example, the target binary string corresponding to the target address is: 11000000_10101000_00000001_0001100, and the valid bit range of the route indicated by the root node is [10, 19]. Then, the binary characters from the high 11 bits to the high 20 bits are intercepted from the target binary string, and the obtained second string is 1010000000.

[0137] 9026. Process the second character string in the same manner as the first character string until the target entry identifier is found in the RAM.

[0138] After obtaining the second string, the node identifier of the first node and the second string can be concatenated into the search information of the first node in the same manner as the first string, and then the search information can be hashed to obtain the second storage address of the second node. The second node information corresponding to the second storage address is obtained from the RAM. If the second node information includes the entry identifier of a valid routing entry, the entry identifier included in the second node information is determined as the target entry identifier. If the second node information does not include the entry identifier of a valid routing entry, the valid bit range of the route of the third node is obtained, and then the calculation is continued until the target entry identifier is found from the RAM. Of course, if the target entry identifier cannot be obtained from the RAM, it will return to the root node. If the root node corresponds to a default route, the default route is used as the next hop routing entry.

[0139] 903. Determine the valid routing entry corresponding to the target entry identifier as the next-hop routing entry of the target address.

[0140] Based on the target entry identifier obtained from the RAM, the valid routing entry corresponding to the target entry identifier can be used as the next hop routing entry of the destination address, and then the target data packet is forwarded to the network device indicated by the next hop routing entry, thereby completing the forwarding of the data packet.

[0141] For the above routing entry search process, the destination address in the received data packet is 192.168.1.25, and the prefix tree built based on the routing entries supported by the router locally is: Figure 6 Taking the prefix tree shown in the figure as an example, the process of searching for the next hop routing entry of the destination address 192.168.1.25 from the routing entries supported by the local router is described in detail. The search process is as follows:

[0142] In the first step, mask the destination address 192.168.1.25 to obtain the binary string 11000000_10101000_00000001_00011001 corresponding to the destination address 192.168.1.25. Then, starting from the root node, according to the route valid bit range [0,9] indicated by the root node, obtain the binary string 1100000010 in the route valid bit range [0,9] from the binary string, and then concatenate the node identifier 0 of the root node with the binary string 1100000010 to obtain the search information 0_1100000010 of the root node.

[0143] The second step is to perform hash calculation on the search information 0_1100000010 of the root node to obtain the storage address of the next node. Based on the storage address, the node information of the next node is obtained from the RAM. The node information includes the node identifier 8, the routing valid bit range [10,23] of the next layer node, and then the routing valid bit range [10,23] of the next layer node is obtained from the binary string 11000000_10101000_00000001_00011001. The binary string from the high 11 bits to the high 24 bits is 10100000000001. The node identifier 8 is concatenated with the route valid bit 10100000000001 to obtain the search information 8_10100000000001. A hash calculation is performed on the search information to obtain the storage address. The node information obtained from the storage address is the node identifier 11 and the entry identifier R8, indicating that R8 is already the longest prefix match. Therefore, the valid routing entry corresponding to R8 is used as the next-hop routing entry.

[0144] Please refer to Fig.10 , which shows a schematic diagram of the structure of a prefix tree construction device provided in an embodiment of the present application. The device can be implemented by software, hardware, or a combination of both, and becomes the whole or part of an electronic device. The device includes:

[0145] The acquisition module 1001 is used to acquire the number of layers of the prefix tree and the effective bit range of each layer of the route according to the mask length of at least one effective routing entry;

[0146] The determination module 1002 is used to determine the nodes of each layer of the prefix tree according to the route valid bit range of each layer of the prefix tree and the binary string obtained after mask processing of the at least one valid routing entry, and the nodes of each layer of the prefix tree include leaf nodes and branch nodes, the leaf nodes correspond to a valid routing entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer;

[0147] The connection module 1003 is used to connect the nodes corresponding to each valid routing entry layer by layer starting from the root node until the leaf node to obtain the prefix tree, wherein the root node corresponds to a valid routing entry with a null character or a mask length of 0.

[0148] In another embodiment of the present application, the acquisition module is used to determine the number of non-zero mask lengths in the at least one valid routing entry as the number of layers of the prefix tree; sort the mask lengths of the at least one valid routing entry in order from small to large, and determine the mask length range between two adjacent layers as the valid bit range of the route of one layer.

[0149] In another embodiment of the present application, a determination module is used to intercept a binary string within the length range indicated by the routing valid bit range of each layer from the binary string obtained after mask processing of the at least one valid routing entry according to the routing valid bit range corresponding to each layer, to obtain at least one binary string; and take a binary string corresponding to each layer as a node to obtain a node of each layer of the prefix tree.

[0150] In another embodiment of the present application, the device further comprises:

[0151] A merging module is used to merge the current layer node with the next layer node if the number of the next layer nodes of the current layer node is one and the next layer node is not a leaf node, so as to obtain an updated next layer node, wherein the routing valid bit range of the updated next layer node is obtained by splicing the routing valid bit range of the current layer node with the routing valid bit range of the next layer node.

[0152] In another embodiment of the present application, each node included in the prefix tree has a different node identifier, and the apparatus further includes:

[0153] The determination module is further used to determine, for a node corresponding to any valid routing entry in the prefix tree, a storage address of the current layer node in a random access memory RAM according to a node identifier of a previous layer node and a routing valid bit of a current layer node, wherein the storage address of the current node is used to store node information of the current layer node, and the node information of the current layer node includes a node identifier of the current layer node, and an entry identifier of the valid routing entry or a routing valid bit range of a next layer node;

[0154] A storage module is used to store the node information of each layer of nodes corresponding to the at least one valid routing entry into the RAM based on the storage address of each layer of nodes corresponding to the at least one valid routing entry.

[0155] The determination module is also used to determine the storage address of the current layer node in the random access memory RAM according to the node identifier of the previous layer node and the route valid bit of the current layer node, including:

[0156] A concatenation module, used for concatenating the node identifier of the upper layer node and the route valid bit of the current layer node to obtain the search information of the upper layer node;

[0157] The calculation module is used to perform hash calculation on the search information of the previous layer node to obtain the storage address of the current layer node.

[0158] Please refer to Fig.11 , which shows a schematic diagram of the structure of a routing entry search device provided in an embodiment of the present application, the prefix tree constructed by the above embodiment of the device, the device can be implemented by software, hardware or a combination of both, and becomes the whole or part of the electronic device, the device includes:

[0159] The acquisition module 1101 is used for performing mask processing on the target address in the target data packet when receiving the target data packet to obtain a target binary string;

[0160] The search module 1102 is further configured to search the RAM for a target entry identifier based on the target binary string and the route valid bit range indicated by each layer of the prefix tree, wherein the target entry identifier is an entry identifier of a valid route entry that has the longest prefix match with the target binary string;

[0161] The determination module 1103 is used to determine the valid routing entry corresponding to the target entry identifier as the next hop routing entry of the target address.

[0162] In another embodiment of the present application, the search module 1102 is used to intercept, from the target binary string, a first string within the routing valid bit range indicated by the root node of the prefix tree; determine, based on the node identifier of the root node and the first string, a first storage address of the first node, the first node being a node in the next layer of the root node; obtain, from the RAM, first node information corresponding to the first storage address; if the first node information does not include an entry identifier of a valid routing entry, obtain a routing valid bit range of a second node, the second node being a node in the next layer of the first node; intercept, from the target binary string, a second string within the routing valid bit range indicated by the second node based on the routing valid bit range of the second node; and process the second string in accordance with the processing method for the first string until the target entry identifier is found from the RAM.

[0163] In another embodiment of the present application, the determination module 1103 is further configured to determine the entry identifier included in the first node information as the target entry identifier if the first node information includes an entry identifier of a valid routing entry.

[0164] Fig.12 The structure block diagram of an electronic device 1200 provided by an exemplary embodiment of the present application is shown. Generally, the electronic device 1200 includes: a processor 1201 and a memory 1202 .

[0165] The processor 1201 can be implemented in at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1201 may also include a main processor and a coprocessor, wherein the main processor is a processor for processing data in an awake state; and the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1201 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1201 may also include an artificial intelligence processor, which is used to process computing operations related to machine learning.

[0166] The memory 1202 may include one or more computer-readable storage media, which may be non-temporary computer-readable storage media, for example, the non-temporary computer-readable storage media may be CD-ROM (Compact Disc Read-Only Memory), ROM, RAM (Random Access Memory), magnetic tape, floppy disk and optical data storage device, etc. The computer-readable storage medium stores at least one computer program, which can implement the above-mentioned prefix tree construction method or routing entry search method when executed.

[0167] Of course, the above electronic device may also include other components, such as input / output interface, communication component, etc. The input / output interface provides an interface between the processor and the peripheral interface module, and the above peripheral interface module may be an output device, an input device, etc. The communication component is configured to facilitate wired or wireless communication between the electronic device and other devices.

[0168] Those skilled in the art will understand that Fig.12 The structure shown in the figure does not constitute a limitation on the electronic device 1200, and may include more or less components than those shown in the figure, or combine certain components, or adopt a different component arrangement.

[0169] An embodiment of the present application provides a computer-readable storage medium, in which at least one computer program is stored. When the at least one computer program is executed by a processor, the above-mentioned prefix tree construction method or routing entry search method can be implemented.

[0170] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it can implement the above-mentioned prefix tree construction method or routing entry search method.

[0171] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0172] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for constructing a prefix tree, characterized in that: The method comprises: Determine the number of non-zero mask lengths in at least one valid routing entry as the number of layers of the prefix tree; Sort the mask lengths of the at least one valid routing entry in ascending order, and determine the mask length range between two adjacent layers as the routing valid bit range of one layer; Determine the nodes of each layer of the prefix tree according to the route valid bit range of each layer of the prefix tree and the binary string obtained after mask processing of the at least one valid route entry, wherein the nodes of each layer of the prefix tree include leaf nodes and branch nodes, the leaf nodes correspond to a valid route entry, and the branch nodes are used to jump to the leaf nodes of the same layer or the branch nodes of the next layer; Starting from the root node, the nodes corresponding to each valid routing entry are connected layer by layer until the leaf node, to obtain the prefix tree, wherein the root node corresponds to a valid routing entry with a null character or a mask length of 0.

2. The method according to claim 1, characterized in that Determining the nodes of each layer of the prefix tree according to the route valid bit range of each layer of the prefix tree and the binary string obtained after the mask operation of the at least one valid route entry includes: According to the route valid bit range corresponding to each layer, from the binary string obtained after the mask processing of the at least one valid route entry, intercept the binary string within the length range indicated by the route valid bit range of each layer to obtain at least one binary string; A binary string corresponding to each layer is taken as a node to obtain the node of each layer of the prefix tree.

3. The method according to claim 1, characterized in that The method further comprises: If the number of next-layer nodes of the current-layer node is one, and the next-layer node is not a leaf node, the current-layer node and the next-layer node are merged to obtain an updated next-layer node, and the routing valid bit range of the updated next-layer node is obtained by concatenating the routing valid bit range of the current-layer node and the routing valid bit range of the next-layer node.

4. The method according to any one of claims 1 to 3, characterized in that Each node included in the prefix tree has a different node identifier, and the method further includes: For any node corresponding to a valid routing entry in the prefix tree, a storage address of the current layer node in a random access memory RAM is determined according to a node identifier of a previous layer node and a routing valid bit of a current layer node, wherein the storage address of the current layer node is used to store node information of the current layer node, wherein the node information of the current layer node includes a node identifier of the current layer node, and an entry identifier of the valid routing entry or a routing valid bit range of a next layer node, wherein the routing valid bit refers to a binary string intercepted from a binary string corresponding to at least one valid routing entry based on a routing valid bit range of each layer; Based on the storage address of each layer of nodes corresponding to the at least one valid routing entry, the node information of each layer of nodes corresponding to the at least one valid routing entry is stored in the RAM.

5. The method according to claim 4, characterized in that Determining the storage address of the current layer node in the random access memory RAM according to the node identifier of the previous layer node and the route valid bit of the current layer node includes: Concatenate the node identifier of the previous layer node and the route valid bit of the current layer node to obtain the search information of the previous layer node; A hash calculation is performed on the search information of the previous layer node to obtain the storage address of the current layer node.

6. A method for searching a routing entry, characterized in that: The method applies the prefix tree constructed according to any one of claims 1 to 5, and the method comprises: When a target data packet is received, a target address in the target data packet is masked to obtain a target binary string; Based on the target binary string and the route valid bit range indicated by each layer of the prefix tree, searching the RAM for a target entry identifier, the target entry identifier being the entry identifier of the valid route entry that has the longest match with the prefix of the target binary string; The valid routing entry corresponding to the target entry identifier is determined as the next-hop routing entry of the target address.

7. The method according to claim 6, characterized in that The step of searching the RAM for a target entry identifier based on the target binary string and the route valid bit range indicated by each layer of the prefix tree comprises: According to the route valid bit range indicated by the root node of the prefix tree, intercepting from the target binary string a first string located within the route valid bit range indicated by the root node; Determine a first storage address of a first node according to the node identifier of the root node and the first character string, where the first node is a node in a next layer of the root node; Obtaining first node information corresponding to the first storage address from the RAM; If the first node information does not include an entry identifier of a valid routing entry, obtaining a routing valid bit range of a second node, where the second node is a node in a next layer of the first node; According to the routing valid bit range of the second node, intercepting a second character string located within the routing valid bit range indicated by the second node from the target binary character string; The second character string is processed in the same manner as the first character string until a target entry identifier is found in the RAM.

8. The method according to claim 7, characterized in that The method further comprises: If the first node information includes an entry identifier of a valid routing entry, the entry identifier included in the first node information is determined as the target entry identifier.

9. An electronic device, characterized in that: It comprises a processor and a memory; the memory stores at least one program code; the at least one program code is used to be called and executed by the processor to implement the prefix tree construction method as described in any one of claims 1 to 5, or the routing entry search method as described in any one of claims 6 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and when the at least one computer program is executed by the processor, it can implement the method for constructing a prefix tree as described in any one of claims 1 to 5, or the method for searching for routing entries as described in any one of claims 6 to 8.

11. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method for constructing a prefix tree as claimed in any one of claims 1 to 5 or the method for searching a routing entry as claimed in any one of claims 6 to 8 can be implemented.

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