Self-adaptive phase LVDS (Low Voltage Differential Signaling) signal decoding system and method

Abstract

The invention discloses a self-adaptive phase LVDS (Low Voltage Differential Signaling) signal decoding system and method, output data of a data processing unit in an LVDS second data channel is detected through a time sequence detection module to judge whether LVDS decoding is correct or not, and the output end of the time sequence detection module is respectively connected to a data mapping module and a clock processing unit; when LVDS decoding is correct, the time sequence detection module outputs an enabling control signal to the data mapping module, and the data mapping module performs Bit bit coding according to data output by the data processing unit in each channel and outputs RGB data; and when LVDS decoding is wrong, the time sequence detection module outputs a control signal to the clock processing unit for adjusting a clock signal and adjusting the position of a data alignment bit. The occurrence position of a time sequence signal after LVDS signal decoding is judged, and the problem of LVDS signal data decoding disorder caused by clock phase deviation is solved through a data and clock shift alignment method.

Description

Technical Field

[0001] The invention relates to the field of video signal transmission decoding, and in particular to a LVDS signal decoding system and method capable of adaptive phase. Background Art

[0002] In the micro-display field, such as the silicon-based OLED display industry, the circuit hardware design space available for the display driver board is extremely limited due to the miniaturization of the display panel, and the encoding and decoding of the signal interface needs to be optimized to reduce the hardware volume and power consumption. The LVDS interface is often used for signal link transmission between signal sources with display resolutions lower than 1080P and display terminals due to its advantages of high-speed transmission, low power consumption, and high anti-interference.

[0003] The traditional method of decoding LVDS signals is to use an LVDS bridge chip to convert the LVDS signal into an RGB signal and then input it into a controller such as an FPGA or SOC for processing. The LVDS decoder used in this solution requires a large circuit board space and is difficult to apply to pilot helmet display systems or consumer wearable device display systems such as VR, which require small circuit system size and low power consumption.

[0004] With the improvement of FPGA device speed, the solution of directly decoding the input LVDS signal by FPGA is adopted. However, in the entire display link system, due to the mismatch of the transmission cables used by the signal source sending end and the display receiving end, or the system is affected by factors such as high and low temperature environment, the LVDS signal will have different phase deviations from the source end to the receiving end. When the FPGA decodes the LVDS signal, the phase deviation will cause the decoding timing signal to be disordered, resulting in disorder in the signal transmission from the signal source end to the display end. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a LVDS signal decoding system and method with adaptive phase, which can adaptively solve the problem of LVDS signal timing decoding disorder caused by phase deviation and improve the anti-interference ability of the decoded signal.

[0006] In order to achieve the above-mentioned object, the technical solution adopted by the present invention is: an adaptive phase LVDS signal decoding system, wherein the LVDS signal includes differential clock signals LVDS CLK_P, LVDS CLK_N and multi-channel differential data signals LVDS DATA_P, LVDSDATA_P / N; the differential clock signals LVDS CLK_P and LVDS CLK_N are input to a clock processing unit for timing signal processing; the multi-channel differential data signals LVDSDATA_P and LVDSDATA_P / N are input to a data processing unit, and the data processing unit recovers the data data[6:0] matched by the corresponding clock phase point under the timing signal and data alignment bit output by the clock processing unit;

[0007] The decoding system includes a timing detection module and a data mapping module; the timing detection module is used to detect the output data of the data processing unit in the second data channel of LVDS to determine whether the LVDS decoding is correct, and the output end of the timing detection module is respectively connected to the data mapping module and the clock processing unit; when the LVDS decoding is correct, the timing detection module outputs an enable control signal to the data mapping module, and the data mapping module performs bit encoding according to the data output by the data processing unit in each channel and outputs RGB data; when the LVDS decoding is wrong, the timing detection module outputs a control signal to the clock processing unit for adjusting the clock signal and adjusting the position of the data alignment bit.

[0008] The clock processing unit also includes a first differential-to-single-ended module, a first delay control module, a clock processor, a first serial-to-parallel module, and a data alignment state machine; the differential clock signals LVDS CLK_P and LVDS CLK_N are input into the first differential-to-single-ended module, and the output of the first differential-to-single-ended module is respectively connected to the first delay control module and the clock processor; the output of the delay control module is connected to the first serial-to-parallel module, the output of the first serial-to-parallel module is connected to the data alignment state machine, and the output of the data alignment state machine is respectively connected to the control end of the first serial-to-parallel module and the control end of the first delay control module and the control end of the data processing unit; the output of the clock processor is connected to the control end of the data processing unit.

[0009] The differential clock signals LVDS CLK_P and LVDS CLK_N are converted into single-ended clock signals through the first differential to single-ended module, and the single-ended clock signals are restored to the pixel clock Receive_Pixe_clk and the 7-fold clock Receive_CLK7 through the clock processor; the single-ended clock signals are delayed-adjusted by the first delay control module and then converted into 7-bit flag data clk_mark through the first serial to parallel module under the control of the data alignment state machine; the data bit alignment state machine receives the control signal of the timing detection module to adjust the output signal of the clock processor and the flag data clk_mark.

[0010] Each channel in the multi-channel differential data signal corresponds to a data processing unit, and the differential data signal of each channel is sent to its corresponding data processing unit, and the data processing unit includes a second differential to single-ended module, a second delay control module, and a second serial to parallel module, wherein: the differential data signals LVDSDATA_P and LVDSDATA_P / N are sent to the second differential to single-ended module, the output end of the second differential to single-ended module is connected to the second delay control module, the output end of the second delay control module is connected to the second serial to parallel module, and the second serial to parallel module outputs data data corresponding to the clock phase point; the control end of the delay control module is connected to the output end of the data alignment state machine; the output ends of the data alignment state machine and the clock processor are both connected to the second serial to parallel module.

[0011] The differential data signals LVDSDATA_P and LVDSDATA_P / N are input into the second serial-to-parallel module after delay control by the second delay control module. The second serial-to-parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine.

[0012] The 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data is selected and input into the timing detection module, wherein the timing detection module includes a row signal timing detection module, a field signal timing detection module, an enable signal timing detection module and a control state machine; the input ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are all input with the data Channel2_Data[6:0]; the output ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are connected to the control state machine, and the output ends of the control state machine are respectively connected to the data mapping module and the data alignment state machine.

[0013] The LVDS signal decoding system capable of adaptive phase is characterized by:

[0014] The row signal timing detection module, field signal timing detection module, and enable signal timing detection module are used to detect the row timing signal, field timing signal, and enable timing signal in the input data Channel2_Data[6:0], and split the input 7-bit data Channel2_Data[6:0] into single-bit data. All single-bit data are simultaneously subjected to row signal timing detection, field signal timing detection, and enable signal timing detection to determine whether the current signal conforms to one of the three timing signals. The control state machine records the detection status of each bit and outputs the corresponding control signal to the data mapping module or the data alignment state machine according to the detection status.

[0015] The control state machine is configured as follows:

[0016] (1) The control state machine obtains the bit positions of the timing signals in all 7 bits, determines whether Bit[2] is a row timing signal, whether Bit[1] is a field timing signal, and whether Bit[0] is an enable timing signal. If all are yes, the control state machine enables the data mapping module to work;

[0017] (2) If any of the two bits is negative, the bit position where the current data enable timing signal appears is recorded, and the difference between the bit position and Bit0 is calculated. The control state machine feeds the difference back to each channel data alignment state machine, and the data alignment state machine shifts the data through the shift register according to the difference to readjust the position of the data alignment bit.

[0018] (3) After the data alignment adjustment is completed, the process returns to step (1) and is executed again until the number of times the data alignment state machine adjusts the data alignment bit exceeds a set threshold and then an adjustment error signal is output;

[0019] (4) If no timing signal is detected in all bit signals, the control state machine is not triggered in the initial state; if only one or two timing signals are detected in the bit position, it is judged that the LVDS video input is wrong.

[0020] A decoding method for an adaptive phase LVDS signal decoding system, the method comprising: detecting and judging the position of a timing signal after LVDS decoding by a timing detection module to judge whether the decoding is correct; if so, the timing detection module outputs an enable control signal to a data mapping module, and the data mapping module outputs RGB data after decoding the LVDS data; if not, the timing detection module outputs a control signal to a clock processing unit to adjust the clock signal and the position of the data alignment bit, thereby achieving alignment through data and clock shifting; the clock processing unit is used to provide a clock signal required for LVDS data decoding.

[0021] The method also includes converting differential clock signals LVDS CLK_P and LVDS CLK_N into single-ended clock signals through a first differential-to-single-ended module, recovering pixel clock Receive_Pixe_clk and generating 7-times clock Receive_CLK7 through a clock processor; the single-ended clock signal is delayed-adjusted by a first delay control module and then converted into 7-bit mark data clk_mark through a first serial-to-parallel module under the control of a data alignment state machine; the data bit alignment state machine receives a control signal from a timing detection module to adjust the output signal of the clock processor and the mark data clk_mark;

[0022] The differential data signals LVDSDATA_P and LVDSDATA_P / N are input into the second serial-to-parallel module after the delay control of the second delay control module. The second serial-to-parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine.

[0023] The data mapping module generates RGB data based on the data of each channel under the control of the timing detection module;

[0024] The timing detection module determines whether the LVDS decoding is correct based on the detection of the 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data; if not, it outputs a control signal to the data alignment state machine to achieve the alignment operation through timing and displacement adjustment; if so, it outputs a trigger signal to the data mapping module, and the data mapping module starts working to output RGB data.

[0025] The advantages of the present invention are: the position of the timing signal after the LVDS signal is decoded is judged by FPGA, and the LVDS signal data decoding disorder caused by the clock phase deviation is solved by the method of data and clock shift alignment, thereby solving the problem of insufficient anti-interference ability of FPGA in decoding signal in LVDS transmission signal system. Each module in the decoding scheme can be implemented by FPGA, and using FPGA to directly decode the LVDS signal saves the circuit board space of the system and reduces the power consumption of the system; this scheme enables FPGA to adapt to the data decoding dislocation problem caused by the transmission link clock phase deviation, improves the anti-interference ability of FPGA in signal interface conversion in complex environments, and improves the stability of the signal transmission system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following is a brief description of the contents expressed in the drawings of the present specification and the marks in the drawings:

[0027] Figure 1 This is a block diagram of the LVDS decoding principle of the present invention;

[0028] Figure 2 This is a principle block diagram of the timing detection module of the present invention;

[0029] Figure 3 A schematic diagram of the mapping relationship between clock and data in the VESA mode of the present invention;

[0030] Figure 4 The mapping relationship between clock and data in the JEIDA mode of the present invention;

[0031] Figure 5 This is a schematic diagram of dividing CLK into bits according to the present invention;

[0032] Figure 6 This is a schematic diagram of LVDS data encoding bit mapping of the present invention;

[0033] Figure 7 It is a schematic diagram of data bit mapping when the clock phase is misaligned according to the present invention. DETAILED DESCRIPTION

[0034] The specific implementation of the present invention will be further explained in detail below by describing the optimal embodiment with reference to the accompanying drawings.

[0035] LVDS signals are widely used in the transmission link interface of display systems. Due to the need for system miniaturization, FPGA is often used to directly decode LVDS signals to reduce hardware wiring space and reduce product power consumption. However, FPGA decoding of LVDS signals has poor anti-interference ability for the entire transmission link. In actual application, due to high and low temperature environments or transmission line problems, phase and data deviations occur, making it impossible for the receiving end to achieve correct data decoding. The present invention proposes a method that can solve the technical solution of LVDS decoding confusion caused by phase deviation problems. The entire decoding system can adapt to phase deviations and improve the stability of the entire signal transmission system. The present invention uses FPGA to determine the position of the timing signal after the LVDS signal is decoded, and solves the LVDS signal data decoding confusion caused by clock phase deviation by aligning data and clock shifts, thereby solving the problem of insufficient anti-interference ability of FPGA decoding signals in LVDS transmission signal systems. The decoding system solution of the present application is described in detail below in conjunction with the accompanying drawings.

[0036] like Figure 1As shown, an adaptive phase LVDS signal decoding system includes a clock processing unit, a data processing unit, a timing detection module and a data mapping module, wherein the clock processing unit, the data processing unit, the timing detection module and the data mapping module are all integrated in the FPGA and implemented by the FPGA. The advantages of the FPGA device in high-speed data processing, small space layout, low power consumption, etc. are used to implement the above-mentioned unit modules, which can greatly save costs and space layout.

[0037] The LVDS signal includes differential clock signals LVDS CLK_P, LVDS CLK_N and multi-channel differential data signals LVDS DATA_P, LVDSDATA_P / N; Figure 1 As shown, it includes differential data of multiple channels. The differential data of each channel corresponds to a clock processing unit and a data processing unit. The clock processing unit and the timing processing unit are one-to-one. The number of channels is generally 4 or 5. The number of data channels is determined by the bit width of the transmitted LVDS video signal. When the video signal bit width is 8 bits, the number of data channels is 4, and when the video signal bit width is 10 bits, the number of data channels is 5.

[0038] The differential clock signals LVDS CLK_P and LVDS CLK_N are input to the clock processing unit for timing signal processing; the multi-channel differential data signals LVDSDATA_P and LVDSDATA_P / N are input to the data processing unit, and the data processing unit recovers the data data[6:0] matching the corresponding clock phase point under the timing signal and data alignment bit output by the clock processing unit;

[0039] The timing detection module is used to detect the output data Channel 2_Data[6:0] of the data processing unit in the second data channel of LVDS to determine whether the LVDS decoding is correct. The output end of the timing detection module is connected to the data mapping module and the clock processing unit respectively. When the LVDS decoding is correct, the timing detection module outputs an enable control signal to the data mapping module. After being enabled, the data mapping module starts working and performs bit encoding according to the data data[6:0] output by the data processing unit in each channel and outputs RGB data. Figure 1 As shown, the data data[6:0] output by the data processing unit of each channel is Channel0_Data...Channeln-1_Data, where n represents the number of channels.

[0040] When an LVDS decoding error occurs, the timing detection module outputs a control signal to the clock processing unit to adjust the clock signal and the position of the data alignment bit. By adjusting the data and clock shift alignment, the LVDS signal data decoding disorder caused by the clock phase deviation is solved, thereby realizing the prepared LVDS decoding.

[0041] In this embodiment, the specific components of the clock processing unit and the data processing unit are as follows: Figure 1 As shown, the clock processing unit also includes a first differential to single-ended module, a first delay control module, a clock processor, a first serial to parallel module, and a data alignment state machine; the differential clock signals LVDS CLK_P and LVDS CLK_N are input into the first differential to single-ended module, and the output ends of the first differential to single-ended module are respectively connected to the first delay control module and the clock processor; the output end of the delay control module is connected to the first serial to parallel module, and the output end of the first serial to parallel module is connected to the data alignment state machine, and the output end of the data alignment state machine is respectively connected to the control end of the first serial to parallel module and the control end of the first delay control module and the control end of the data processing unit; the output end of the clock processor is connected to the control end of the data processing unit. The differential clock signals LVDS CLK_P and LVDS CLK_N are converted into single-ended clock signals through the first differential to single-ended module, and the single-ended clock signals are restored to the pixel clock Receive_Pixe_clk and the 7-fold clock Receive_CLK7 through the clock processor; the single-ended clock signals are delayed-adjusted by the first delay control module and then converted into 7-bit flag data clk_mark through the first serial to parallel module under the control of the data alignment state machine; the data bit alignment state machine receives the control signal of the timing detection module to adjust the output signal of the clock processor and the flag data clk_mark.

[0042] Each channel in the multi-channel differential data signal corresponds to a data processing unit, and the differential data signal of each channel is sent to the corresponding data processing unit. The data processing unit includes a second differential to single-ended module, a second delay control module, and a second serial to parallel module, wherein: the differential data signals LVDSDATA_P and LVDSDATA_P / N are sent to the second differential to single-ended module, the output end of the second differential to single-ended module is connected to the second delay control module, the output end of the second delay control module is connected to the second serial to parallel module, and the second serial to parallel module outputs data data corresponding to the clock phase point; the control end of the delay control module is connected to the output end of the data alignment state machine; the output ends of the data alignment state machine and the clock processor are both connected to the second serial to parallel module. The differential data signals LVDSDATA_P and LVDSDATA_P / N are input to the second serial to parallel module after the delay control of the second delay control module, and the second serial to parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine. The first and second involved in the above-mentioned data processing unit and clock processing unit are for distinguishing two identical modules and do not play a limiting role. They indicate that the data processing unit and the clock processing unit have the same unit module and only play a distinguishing role.

[0043] After the data of each channel is decoded by the data processing unit, it is uniformly sent to the data mapping module to map the corresponding RGB data. However, how to judge whether the data output by each data processing unit is correctly decoded, whether the timing is correct, and whether the position is aligned? Therefore, after the signal is deserialized, the timing signal of the LVDS2 channel is detected by the timing detection module, and the position of the timing signal is used to judge whether the LVDS decoding is wrong. Then, according to the value of the deviation, the data alignment state machine is used to shift and correct the decoded timing signal. The 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data is selected and input into the timing detection module, the timing detection module includes a row signal timing detection module, a field signal timing detection module, an enable signal timing detection module and a control state machine; the input ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are all input with the data Channel2_Data[6:0]; the output ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are connected to the control state machine, and the output ends of the control state machine are respectively connected to the data mapping module and the data alignment state machine.

[0044] The row signal timing detection module, field signal timing detection module, and enable signal timing detection module are used to detect the row timing signal, field timing signal, and enable timing signal in the input data Channel2_Data[6:0], and split the input 7-bit data Channel2_Data[6:0] into single-bit data. All single-bit data are simultaneously subjected to row signal timing detection, field signal timing detection, and enable signal timing detection to determine whether the current signal conforms to one of the three timing signals. The control state machine records the detection status of each bit and outputs the corresponding control signal to the data mapping module or the data alignment state machine according to the detection status.

[0045] The control state machine is used to determine whether the data of the second channel after deserialization is correct, and the control state machine is configured as follows:

[0046] (1) The control state machine obtains the bit positions of the timing signals in all 7 bits, determines whether Bit[2] is a row timing signal, whether Bit[1] is a field timing signal, and whether Bit[0] is an enable timing signal. If all are yes, the control state machine enables the data mapping module to work;

[0047] (2) If any of them is negative, the bit position where the current data enable timing signal appears is recorded, and the difference between the bit position and Bit0 is calculated. The control state machine feeds the difference back to each channel data alignment state machine. The data alignment state machine shifts the data through the shift register according to the difference and readjusts the position of the data alignment bit. Each adjustment is counted and the number of adjustments is recorded.

[0048] (3) After the data alignment adjustment is completed, the process returns to step (1) and executes again until the number of times the data alignment state machine adjusts the data alignment bit exceeds a set threshold, and then outputs an adjustment error signal; in step (2), before each feedback to step (1), it is determined whether the set number threshold is reached. If it is greater than the set number threshold, an error signal is directly output to alarm; if it is not reached, the process feeds back to step (1) for adjustment.

[0049] (4) If no timing signal is detected in all bit signals, the control state machine is not triggered in the initial state; if only one or two timing signals are detected in the bit position, it is judged that the LVDS video input is wrong.

[0050] In the present solution, a decoding method of an adaptive phase LVDS signal decoding system is provided, including: detecting and judging the position of the timing signal after LVDS decoding by a timing detection module to judge whether the decoding is correct; if so, the timing detection module outputs an enable control signal to a data mapping module, and the data mapping module outputs RGB data after decoding the LVDS data; if not, the timing detection module outputs a control signal to a clock processing unit to adjust the clock signal and the position of the data alignment bit, thereby achieving alignment through data and clock shifting; the clock processing unit is used to provide a clock signal required for LVDS data decoding.

[0051] In a preferred embodiment, the differential clock signals LVDS CLK_P and LVDS CLK_N are converted into single-ended clock signals by the first differential-to-single-ended module, and the single-ended clock signals are restored to pixel clock Receive_Pixe_clk and 7-times clock Receive_CLK7 by the clock processor; the single-ended clock signals are delayed-adjusted by the first delay control module and then converted into 7-bit mark data clk_mark by the first serial-to-parallel module under the control of the data alignment state machine; the data bit alignment state machine receives the control signal of the timing detection module to adjust the output signal of the clock processor and the mark data clk_mark;

[0052] The differential data signals LVDSDATA_P and LVDSDATA_P / N are input into the second serial-to-parallel module after the delay control of the second delay control module. The second serial-to-parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine.

[0053] The data mapping module generates RGB data based on the data of each channel under the control of the timing detection module;

[0054] The timing detection module determines whether the LVDS decoding is correct based on the detection of the 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data; if not, it outputs a control signal to the data alignment state machine to achieve the alignment operation through timing and displacement adjustment; if so, it outputs a trigger signal to the data mapping module, and the data mapping module starts working to output RGB data.

[0055] After the signal is deserialized, the timing signal of the LVDS2 channel is detected by the timing detection module, and the position of the timing signal is used to determine whether the LVDS decoding is wrong, and then the data alignment state machine is used to shift and correct the decoded timing signal according to the value of the deviation. The 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data is selected and input into the timing detection module. The timing detection module includes a row signal timing detection module, a field signal timing detection module, an enable signal timing detection module and a control state machine; the input ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are all input with data Channel2_Data[6:0]; the output ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are connected to the control state machine, and the output ends of the control state machine are respectively connected to the data mapping module and the data alignment state machine.

[0056] The row signal timing detection module, field signal timing detection module, and enable signal timing detection module are used to detect the row timing signal, field timing signal, and enable timing signal in the input data Channel2_Data[6:0], and split the input 7-bit data Channel2_Data[6:0] into single-bit data. All single-bit data are simultaneously subjected to row signal timing detection, field signal timing detection, and enable signal timing detection to determine whether the current signal conforms to one of the three timing signals. The control state machine records the detection status of each bit and outputs the corresponding control signal to the data mapping module or the data alignment state machine according to the detection status.

[0057] The control state machine is used to determine whether the data of the second channel after deserialization is correct, and the control state machine is configured as follows:

[0058] (1) The control state machine obtains the bit positions of the timing signals in all 7 bits, determines whether Bit[2] is a row timing signal, whether Bit[1] is a field timing signal, and whether Bit[0] is an enable timing signal. If all are yes, the control state machine enables the data mapping module to work;

[0059] (2) If any of them is negative, the bit position where the current data enable timing signal appears is recorded, and the difference between the bit position and Bit0 is calculated. The control state machine feeds the difference back to each channel data alignment state machine. The data alignment state machine shifts the data through the shift register according to the difference and readjusts the position of the data alignment bit. Each adjustment is counted and the number of adjustments is recorded.

[0060] (3) After the data alignment adjustment is completed, the process returns to step (1) and executes again until the number of times the data alignment state machine adjusts the data alignment bit exceeds a set threshold, and then outputs an adjustment error signal; in step (2), before each feedback to step (1), it is determined whether the set number threshold is reached. If it is greater than the set number threshold, an error signal is directly output to alarm; if it is not reached, the process feeds back to step (1) for adjustment.

[0061] (4) If no timing signal is detected in all bit signals, the control state machine is not triggered in the initial state; if only one or two timing signals are detected in the bit position, it is judged that the LVDS video input is wrong.

[0062] In the solution of this application, FPGA is used to implement the functional modules of LVDS decoding, including:

[0063] 1. FPGA receives LVDS signals through the I / O interface. The LVDS signals include differential clock signals (LVDS CLK_P / N) and 4 or 5-channel differential data signals (LVDSDATA_P / N). The number of data channels is determined by the bit width of the transmitted LVDS video signal. When the video signal bit width is 8 bits, the number of data channels is 4, and when the video signal bit width is 10 bits, the number of data channels is 5.

[0064] 2. The differential clock signal and the differential data signal of channel 1 are converted into a single-ended clock signal and a single-ended data signal through the differential to single-ended module. The clock signal is restored to the pixel clock Receive_Pixe_clk and the 7-fold clock Receive_CLK7 is generated through the clock processor; the single-ended clock signal is delayed and adjusted by the delay control module and converted into a 7-bit bit mark data clk_mark through the serial to parallel module under the control of the data alignment state machine. The data signal is also input into the serial to parallel module after delay control, and the 7-bit data data[6:0] corresponding to the corresponding clock phase point is restored under the control of clk_mark and the data alignment state machine;

[0065] 3. At the same time, the differential clock signal and the remaining channel data signals are converted according to the above step 2; that is, the differential data and differential clock signal of each channel are sent as a group to a pair of data processing units and clock processing units for processing, and then the 7-bit data data[6:0] corresponding to the corresponding clock phase point after deserialization are obtained, which are Channel0_Data...Channeln-1_Data, respectively, where n represents the number of channels.

[0066] 4. LVDS channel 2 data is converted from serial to parallel 7-bit data Channel2_Data[6:0] and input into the timing detection module. The timing detection module splits the input 7-bit data into single-bit data, namely Bit[0]-Bit[6]. 7-bit data

[0067] Channel2_Data[6:0] is input into the timing detection module. The timing detection module splits the input 7-bit data into single-bit data, namely Bit[0]-Bit[6]. The 7-bit data Channel2_Data[6:0] is split in order, where the first bit is Bit[0], the last bit is Bit[6], and so on to get Bit[0]-Bit[6]. All single-bit data are simultaneously subjected to the row signal timing detection (Hsync_detect), field signal timing detection (Vsync_detect), and enable signal timing detection (De_detect) to determine whether the obtained signal meets the characteristics of the above-mentioned row timing signal, field timing signal, and enable signal. The logical results obtained by the three detection programs are output through the OR gate logic, and the control state machine records each bit

[0068] The detection state of the bit or gate logic output; the timing detection module is as follows Figure 2 As shown, the control state machine controls the detection process as follows:

[0069] 1) Obtain the bit positions of the timing signals in all 7 bits, and preliminarily determine whether Bit[2] is a row timing signal, whether Bit[1] is a field timing signal, and whether Bit[0] is an enable timing signal. If the above bits are corresponding timing signals, the control state machine enables the data mapping module to work; Figure 3 and Figure 6 It is known that in VESA timing mode, the relationship between the LVDS encoding bit and the timing signal and data signal. If the clock is not skewed, the data decoded from the LVDS signal corresponds to Bit[2] as the row timing signal, Bit[1] as the field timing signal, and Bit[0] as the enable timing signal.

[0070] 2) If the above bit is not the corresponding timing signal, that is, Bit[2] is not the row timing signal or Bit[1] is not the field timing signal or Bit[0] is not the enable timing signal, then the bit where the current data enable timing signal appears is recorded, and the difference between the bit and the bit0 is calculated. The control state machine feeds the difference back to the data alignment state machine of each channel. The data alignment state machine shifts the data through the shift register according to the difference and readjusts the position of the data alignment bit;

[0071] 3) After the data alignment adjustment is completed, the timing detection module re-detects whether the input data conforms to the bit correspondence relationship described in 1). If not, repeat 2) to make an adjustment. If not, an adjustment error signal is output. If successful, the control state machine enables the data mapping module to work;

[0072] 4) Control state machine abnormal situation processing: If all bit signals do not detect the timing signal, the control state machine will not trigger in the initial state; if only one or two timing signals are detected in the bit position, it is judged that the LVDS video input is wrong;

[0073] 5. After all channels of LVDS video data are converted from serial to parallel data, they are input into the data mapping module. The data mapping module starts working after receiving the control state machine enable signal, and encodes all input data by the number of channels and the sequence. Then, data mapping is performed according to whether the transmitted LVDS video data is in VESA format or JEIDA mode, and RGB data RGB_data[23:0] and RGB timing signal RGB_Timing are output. The timing signal includes line (Hsync), field (Vsync) and data enable signal (DE).

[0074] LVDS uses 1 pair of differential clock signals and 4 or 5 pairs of differential data signals when transmitting video signals. The number of data signal channels is divided into 4 pairs or 5 pairs according to whether the data bit width of the transmitted LVDS video signal is 8 bits or 10 bits. The LVDS transmission video format is divided into VESA or JIEDA mode. The difference between the two modes lies in the different mapping of RGB data bits. Taking 4 pairs of differential data as an example, the data format in VESA mode is as follows Figure 3 , the data format in JEIDA mode is as follows Figure 4 .

[0075] like Figure 3 , 4 As shown in the figure, each differential channel transmits 7 bits of data in one clock cycle. When decoding the LVDS signal, the FPGA first converts the clock and data into single-ended signals through the differential to single-ended module for processing. The converted single-ended clock is used to recover the pixel clock Receive_Pixel_clk of the same frequency and the data receiving recovery clock Receive_clk7 with 7 times the frequency after passing through the clock manager. The transmission ratio of clock to data is 7:1. Using the serial-to-parallel conversion module, i.e., ISERDES, to convert serial data into parallel data requires 7 times the pixel clock frequency.

[0076] The clock signal is converted into 7-bit wide data through the serial-to-parallel conversion module, which is equivalent to dividing the clock cycle of a high and low level into 7 equal parts. Figure 5At this time, the CLK data is represented as 7'b1100011, which is used as the alignment mark of the clock and data. The deserialized data signal in continuous clock cycles is divided by the characteristic value, so that the clock and data transmitted in each clock cycle can be aligned.

[0077] The data mapping module maps the deserialized data of all LVDS data channels into corresponding RGB data according to the LVDS transmission video format. Taking 4 pairs of LVDS data channels as an example, the deserialized signal data has 28 bits, and the data bit encoding is as follows: Figure 6 As shown in the figure, bit16, bit15, and bit14 correspond to the line (HS), field (VS), and data enable signal (DE) of the timing signal respectively. When the control state machine determines that the timing detection module is normal and the decoding is normal, it enables the data mapping module to convert the 28-bit data into the corresponding RGB signal red, green, and blue component data (R_data[7:0], G_data[7:0], and B_data[7:0]) and RGB signal timing signals (DE, Hsync, Vsync).

[0078] In actual application environments, due to the long transmission link of LVDS signals, the impedance mismatch of the transmission medium, or the influence of high and low temperature environments, the clock and data phases may be offset. Figure 7 As shown, the receiving end is unaware of the phase deviation and still decodes the input signal according to the original phase, which will cause the final mapped RGB timing signal and data signal to be disordered, and ultimately cause the display image to be disordered and unable to meet normal use requirements.

[0079] The timing signal only exists in LVDS data channel 2. It is only necessary to perform timing detection on the data after deserialization of LVDS channel 2 to determine whether the LVDS decoding phase is deviated. The 7-bit data after deserialization in channel 2 is bit-encoded, and its bit0 corresponds to the data enable signal (DE), bit1 corresponds to the field signal (VS), and bit2 corresponds to the line signal (HS). The timing detection is to determine whether these 3 bit signals meet the characteristics of their timing signals. If it is detected that the Bit2, Bit1, and Bit1 data are the corresponding data enable signals, the line signal and the field signal indicate that the clock and data are not misaligned, and the input data can be directly output to the data mapping module for mapping. If there is no timing signal or only part of the timing signal exists in the 7 corresponding bits of the detection channel 2, it means that the LVDS signal is wrong when the source is encoded, and the decoded LVDS data can no longer be used. The control state machine reports the LVDS signal input error.

[0080] If it appears Figure 5 The clock phase is misaligned, and the data bits decoded by LVDS are Figure 5Normal mapping Bit14 corresponds to the Vsync signal, Bit15 corresponds to Hsync, Bit16 corresponds to the blue data B5, and the data enable signal appears at the position of Bit20. At this time, the control state machine tells the data alignment state machine to cyclically shift the 7-bit data of the deserialized LVDS channel 2 one bit to the right to achieve correct data mapping. The data alignment device state machine not only performs a shift operation on the LVDS data channel 2, but also performs the same data shift operation on all other channels at the same time to ensure that the data of all channels can be aligned. The state control state machine tells the data alignment state machine to shift the deserialized data according to the detected timing signal and the original offset data amount. After the shift, the output data is tested again to see if it meets the originally set mapping relationship. After this processing, the FPGA decoding can deal with the decoding disorder caused by clock phase deviation.

[0081] Obviously, the specific implementation of the present invention is not limited to the above-mentioned methods. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, they are all within the protection scope of the present invention.

Claims

1. An adaptive phase LVDS signal decoding system, wherein the LVDS signal comprises differential clock signals LVDS CLK_P, LVDS CLK_N and multi-channel differential data signals LVDSDATA_P, LVDSDATA_P / N; the differential clock signals LVDS CLK_P, LVDS CLK_N are input to a clock processing unit for timing signal processing; the multi-channel differential data signals LVDS DATA_P, LVDSDATA_P / N are input to a data processing unit, and the data processing unit recovers data data[6:0] matched by the corresponding clock phase point under the timing signal and data alignment bit output by the clock processing unit; Features: The decoding system includes a timing detection module and a data mapping module; the timing detection module is used to detect the output data of the data processing unit in the second data channel of LVDS to determine whether the LVDS decoding is correct, and the output end of the timing detection module is respectively connected to the data mapping module and the clock processing unit; when the LVDS decoding is correct, the timing detection module outputs an enable control signal to the data mapping module, and the data mapping module performs bit encoding according to the data output by the data processing unit in each channel and outputs RGB data; when the LVDS decoding is wrong, the timing detection module outputs a control signal to the clock processing unit for adjusting the clock signal and adjusting the position of the data alignment bit.

2. The adaptive phase LVDS signal decoding system according to claim 1, characterized in that: The clock processing unit also includes a first differential-to-single-ended module, a first delay control module, a clock processor, a first serial-to-parallel module, and a data alignment state machine; the differential clock signals LVDS CLK_P and LVDS CLK_N are input into the first differential-to-single-ended module, and the output of the first differential-to-single-ended module is respectively connected to the first delay control module and the clock processor; the output of the delay control module is connected to the first serial-to-parallel module, the output of the first serial-to-parallel module is connected to the data alignment state machine, and the output of the data alignment state machine is respectively connected to the control end of the first serial-to-parallel module and the control end of the first delay control module and the control end of the data processing unit; the output of the clock processor is connected to the control end of the data processing unit.

3. The adaptive phase LVDS signal decoding system according to claim 2, characterized in that: The differential clock signals LVDS CLK_P and LVDS CLK_N are converted into single-ended clock signals through the first differential to single-ended module, and the single-ended clock signals are restored to the pixel clock Receive_Pixe_clk and the 7-fold clock Receive_CLK7 through the clock processor; the single-ended clock signals are delayed-adjusted by the first delay control module and then converted into 7-bit flag data clk_mark through the first serial to parallel module under the control of the data alignment state machine; the data bit alignment state machine receives the control signal of the timing detection module to adjust the output signal of the clock processor and the flag data clk_mark.

4. The adaptive phase LVDS signal decoding system according to claim 1, characterized in that: Each channel in the multi-channel differential data signal corresponds to a data processing unit, and the differential data signal of each channel is sent to its corresponding data processing unit, and the data processing unit includes a second differential to single-ended module, a second delay control module, and a second serial to parallel module, wherein: the differential data signals LVDSDATA_P and LVDSDATA_P / N are sent to the second differential to single-ended module, the output end of the second differential to single-ended module is connected to the second delay control module, the output end of the second delay control module is connected to the second serial to parallel module, and the second serial to parallel module outputs data data corresponding to the clock phase point; the control end of the delay control module is connected to the output end of the data alignment state machine; the output ends of the data alignment state machine and the clock processor are both connected to the second serial to parallel module.

5. The adaptive phase LVDS signal decoding system according to claim 4, characterized in that: The differential data signals LVDSDATA_P and LVDSDATA_P / N are input into the second serial-to-parallel module after delay control by the second delay control module. The second serial-to-parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine.

6. The adaptive phase LVDS signal decoding system according to any one of claims 1 to 5, characterized in that: The 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data is selected and input into the timing detection module, wherein the timing detection module includes a row signal timing detection module, a field signal timing detection module, an enable signal timing detection module and a control state machine; the input ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are all input with the data Channel2_Data[6:0]; the output ends of the row signal timing detection module, the field signal timing detection module and the enable signal timing detection module are connected to the control state machine, and the output ends of the control state machine are respectively connected to the data mapping module and the data alignment state machine.

7. The adaptive phase LVDS signal decoding system according to claim 6, characterized in that: The LVDS signal decoding system capable of adaptive phase is characterized by: The row signal timing detection module, field signal timing detection module, and enable signal timing detection module are used to detect the row timing signal, field timing signal, and enable timing signal in the input data Channel2_Data[6:0], and split the input 7-bit data Channel2_Data[6:0] into single-bit data. All single-bit data are simultaneously subjected to row signal timing detection, field signal timing detection, and enable signal timing detection to determine whether the current signal conforms to one of the three timing signals. The control state machine records the detection status of each bit and outputs the corresponding control signal to the data mapping module or the data alignment state machine according to the detection status.

8. The adaptive phase LVDS signal decoding system according to claim 7, characterized in that: The control state machine is configured as follows: (1) The control state machine obtains the bit positions of the timing signals in all 7 bits, determines whether Bit[2] is a row timing signal, whether Bit[1] is a field timing signal, and whether Bit[0] is an enable timing signal. If all are yes, the control state machine enables the data mapping module to work; (2) If any of the two bits is negative, the bit position where the current data enable timing signal appears is recorded, and the difference between the bit position and Bit0 is calculated. The control state machine feeds the difference back to each channel data alignment state machine, and the data alignment state machine shifts the data through the shift register according to the difference to readjust the position of the data alignment bit. (3) After the data alignment adjustment is completed, the process returns to step (1) and is executed again until the number of times the data alignment state machine adjusts the data alignment bit exceeds a set threshold and then an adjustment error signal is output; (4) If no timing signal is detected in all bit signals, the control state machine is not triggered in the initial state; if only one or two timing signals are detected in the bit position, it is judged that the LVDS video input is wrong.

9. A decoding method of an adaptive phase LVDS signal decoding system according to any one of claims 1 to 8, characterized in that: The method comprises: detecting and judging the position where the timing signal after LVDS decoding appears through a timing detection module to judge whether the decoding is correct; if so, the timing detection module outputs an enable control signal to a data mapping module, and the data mapping module outputs RGB data after decoding the LVDS data; if not, the timing detection module outputs a control signal to a clock processing unit to adjust the clock signal and the position of the data alignment bit, thereby achieving alignment through data and clock shifting; the clock processing unit is used to provide a clock signal required for LVDS data decoding.

10. The method for decoding LVDS signals with adaptive phase according to claim 9, characterized in that: The method also includes converting differential clock signals LVDS CLK_P and LVDS CLK_N into single-ended clock signals through a first differential-to-single-ended module, recovering pixel clock Receive_Pixe_clk and generating 7-times clock Receive_CLK7 through a clock processor; the single-ended clock signal is delayed-adjusted by a first delay control module and then converted into 7-bit mark data clk_mark through a first serial-to-parallel module under the control of a data alignment state machine; the data bit alignment state machine receives a control signal from a timing detection module to adjust the output signal of the clock processor and the mark data clk_mark; The differential data signals LVDSDATA_P and LVDSDATA_P / N are input into the second serial-to-parallel module after the delay control of the second delay control module. The second serial-to-parallel control module recovers the 7-bit data data[6:0] corresponding to the corresponding clock phase point under the control of the mark data clk_mark and the data alignment state machine. The data mapping module generates RGB data based on the data of each channel under the control of the timing detection module; The timing detection module determines whether the LVDS decoding is correct based on the detection of the 7-bit data Channel2_Data[6:0] output by the data processing unit corresponding to the second channel in the LVDS multi-channel data; if not, it outputs a control signal to the data alignment state machine to achieve the alignment operation through timing and displacement adjustment; if so, it outputs a trigger signal to the data mapping module, and the data mapping module starts working to output RGB data.

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