High-density vertical stacked DRAM packaging structure and process

Abstract

The present invention belongs to the technical field of packaging structure, and particularly relates to a high-density vertically stacked DRAM packaging structure and process. The packaging structure is formed by vertically stacking DRAM 02 chip to DRAM 04 chip on DRAM 01 chip in sequence, and the front of DRAM 04 chip has a metal bump; the DRAM chip is coated with molding compound to form a molding packaging layer, and a vertical through hole penetrates the packaging structure from the inside, and the molding compound includes finished epoxy resin molding compound, epoxy resin, liquid crystal polymer, beryllium oxide, boron nitride nanotubes, zinc oxide, curing agent, catalyst, antioxidant, flame retardant, and self-repairing agent. The present invention also provides a specific preparation process of the packaging structure. By optimizing the packaging process, packaging structure and packaging materials, the present invention not only simplifies the process flow and reduces the production cost, but also greatly improves the heat dissipation performance and reliability of the packaging structure, meeting the needs of high-performance DRAM packaging.

Description

Technical Field

[0001] The present invention belongs to the technical field of packaging structures, and in particular relates to a high-density vertically stacked DRAM packaging structure and process. Background Art

[0002] In existing high-bandwidth storage, stacked DRAM packaging processes usually use through-silicon via (TSV) and micro-bump technology to build vertical interconnect structures. However, through-silicon via technology and TSV exposure processes are very complex, with low yield and high cost. Therefore, how to introduce a simpler, low-cost and reliable vertical interconnect technology in stacked DRAM packaging has become an urgent problem to be solved in the industry. Summary of the invention

[0003] In view of the deficiencies of the prior art, the present invention provides a solution: a high-density vertically stacked DRAM packaging structure and process.

[0004] (1) A high-density vertically stacked DRAM package structure, comprising a DRAM chip, the DRAM chip comprising a chip body, the chip body comprising a front side and a back side, the front side comprising a circuit surface, the circuit surface being covered with an insulating layer, a redistribution layer being formed on the insulating layer, and the redistribution layer being electrically connected to the circuit surface;

[0005] The DRAM chips include a DRAM 02 chip, the back side of the DRAM 02 chip is vertically stacked on the front side of the DRAM 01 chip, the back side of the DRAM 03 chip is vertically stacked on the front side of the DRAM 02 chip, the back side of the DRAM 04 chip is vertically stacked on the front side of the DRAM 03 chip, and the front side of the DRAM 04 chip has a metal bump;

[0006] The structures of DRAM 01 chip to DRAM 04 chip are the same, and are all coated with molding compound to form a molding packaging layer. The molding compound does not cover the insulating layer and the redistribution layer. The vertical through hole penetrates the high-density vertically stacked DRAM packaging structure from the inside. Specifically, one end of the vertical through hole is connected to the redistribution layer of the DRAM 04 chip, and the other end of the vertical through hole is connected to the redistribution layer of the DRAM 01 chip; a conductive material is deposited in the vertical through hole; the molding compound includes a finished epoxy resin molding compound and a molding material, and the molding material includes at least one of epoxy resin, liquid crystal polymer, beryllium oxide, boron nitride nanotubes, zinc oxide, a curing agent, a catalyst, an antioxidant, a flame retardant, and a self-healing agent.

[0007] Preferably, the curing agent includes an epoxy resin curing agent, the catalyst includes a thermally activated catalyst, the thermally activated catalyst includes benzotriazole, the antioxidant includes butylated hydroxytoluene, the flame retardant includes melamine cyanurate, and the self-healing agent includes thermoplastic polyurethane.

[0008] (II) The manufacturing process of the aforementioned high-density vertically stacked DRAM package structure comprises:

[0009] A separation layer is loaded on a carrier to obtain a temporary carrier, and the back of the wafer is fixed on the temporary carrier to obtain DRAM 01 wafer to DRAM 04 wafer respectively, and the front of the wafer has a circuit surface; a molding compound is used for encapsulation molding to form a molded encapsulation layer on the DRAM 01 wafer to DRAM 04 wafer respectively; the front of the molded encapsulation layer is thinned to expose the circuit that can be connected, and the ground DRAM 01 wafer to DRAM 04 wafer are obtained respectively;

[0010] An insulating layer is deposited on the surface of the ground DRAM 01 wafer ~ DRAM 04 wafer, and a new metal line is made on the insulating layer. The new metal line is connected to the original connectable line to form a rewiring layer, and the DRAM 01 wafer is used as the bottom DRAM; the DRAM 02 wafer ~ DRAM 04 wafer is separated from the separation layer and cut into independent DRAM 02 chips ~ DRAM04 chips;

[0011] The independent DRAM 02 chip is stacked vertically on the bottom DRAM, the independent DRAM 03 chip is stacked vertically on the DRAM 02 chip, and the independent DRAM 04 chip is stacked vertically on the DRAM 03 chip, so as to form a column of stacked chips, and multiple columns of stacked chips are formed on the bottom DRAM; for each column of stacked chips, a vertical through hole is formed in the molded packaging layer of the DRAM 02 chip to the DRAM 04 chip, the vertical through hole penetrates the molded packaging layer, and a conductive material is deposited in the vertical through hole; the front side of each column of stacked chips is rewired, an insulating layer is deposited first, a new metal line is made on the insulating layer, and the new metal line is connected to the original rewiring layer and the deposited conductive material to form a rewiring layer of each column of stacked chips; a metal bump is formed on the rewiring layer of each column of stacked chips;

[0012] The back side of the multi-column stacked chips is separated from the separation layer, and then the metal bumps of the multi-column stacked chips are fixed on a temporary carrier; the multi-column stack is cut into a single-column stack, and the temporary carrier is removed to obtain a high-density vertically stacked DRAM packaging structure.

[0013] Preferably, a vertical through hole is formed in the molded packaging layer of the DRAM 02 chip ~ DRAM 04 chip. When the vertical through hole penetrates the molded packaging layer, it needs to pass through the redistribution layer of the DRAM 02 chip ~ DRAM 04 chip, and the bottom of the vertical through hole is connected to the redistribution layer of the bottom DRAM.

[0014] Preferably, the use parameters of the molding material include the following conditions: condition (1) placing the molding material in a mold for high pressure injection molding; and / or condition (2) performing a primary curing of the molding material at 100-200°C and then heating it to 150-250°C for a secondary curing.

[0015] Preferably, the temporary carrier is a carrier coated with a temporary bonding material, and the temporary bonding material includes at least one of a photothermal conversion release agent, an ultraviolet curing adhesive, and a wafer peeling tape.

[0016] Preferably, when stacked vertically, each layer of chips is bonded together using an adhesive, wherein the adhesive comprises a film-like adhesive.

[0017] (III) A method for preparing the molding compound mentioned in the above content is provided, wherein the molding compound includes a molding material, and the method for preparing the molding material includes:

[0018] Ultrasonic dispersion of epoxy resin and liquid crystal polymer, then adding beryllium oxide and boron nitride nanotubes to disperse evenly, then adding polyvinyl pyrrolidone to shake, gradually adding zinc oxide, stirring evenly, adding or not adding self-healing agent, gradually adding curing agent, then adding or not adding catalyst, stirring evenly, adding antioxidant to obtain molding material.

[0019] (IV) Without adding liquid crystal polymer, a method for preparing the molding compound mentioned in the above content is given, wherein the molding compound includes a molding material, and the method for preparing the molding material includes:

[0020] Beryllium oxide and boron nitride nanotubes are dispersed into epoxy resin by ultrasonic oscillation and mechanical stirring, and then polyvinyl pyrrolidone is added and oscillated, zinc oxide is gradually added, stirred evenly, a self-healing agent is added or not added, a curing agent is gradually added, and then a catalyst is added or not added, stirred evenly, an antioxidant is added to obtain a molding material.

[0021] For the technical solutions (iii) and (iv), further, the molding material is vacuum dried to obtain a solid material, and then the solid material is ball-milled and / or jet-milled to obtain a molding compound.

[0022] Different from the prior art, the advantages and beneficial effects of the present invention are as follows:

[0023] First, simplify the process and reduce costs: The present invention does not require TSV technology, simplifies the packaging process, reduces the complex TSV exposure process and related equipment requirements. The vertical stacking of chips is achieved through "embedded vertical interconnection" technology, which simplifies the manufacturing process and significantly reduces production costs and process complexity.

[0024] Second, improve packaging density: The present invention adopts a high-density vertical stacking structure, allowing multiple DRAM chips to be stacked vertically together to form a multi-column stack. This design achieves higher integration in a limited space, improves packaging density, and can meet the needs of modern high-performance memory. It can reduce the interconnection length, reduce signal delay and power consumption, increase bandwidth, and can be applied to the technical field of device integration and miniaturization.

[0025] Third, the flexible redistribution layer (RDL) technology increases the flexibility of the package design through the two applications of RDL technology, making the I / O contact spacing more flexible, able to accommodate more pins, and improving the signal routing efficiency. This structure expands the chip's connection capabilities with external circuits and enhances the stability and scalability of chip performance.

[0026] Fourth, good heat dissipation performance: As the number of chips stacked increases, the height of the packaging structure also increases. In order to ensure that the heat dissipation does not decrease, and to improve the heat dissipation performance. The present invention makes its own molding material to improve the heat dissipation performance. By optimizing the combination of materials (such as beryllium oxide, boron nitride nanotubes, and zinc oxide), a uniform nanoscale thermal conductive network is formed, which effectively improves the thermal conductivity of the packaging material. The thermal conductivity of this material is higher than that of traditional materials, which can effectively improve the heat dissipation performance of the packaging structure and avoid the accumulation of hot spots under high temperature conditions.

[0027] Fifth, multifunctionality: The use of liquid crystal polymers gives the packaging material the ability to self-regulate. During the heating and cooling process, liquid crystal polymers can form an ordered structure through molecular directional arrangement, enhancing the thermal conductivity and mechanical strength of the material. At the same time, the material can be adaptively adjusted according to temperature changes to ensure that good mechanical properties and thermal conductivity are maintained under different temperature conditions. The introduction of self-healing agents gives the packaging material a self-healing function, which can effectively extend the service life of the packaging structure. Under temperature changes or mechanical stress, the dynamic covalent bonds of the material can break and recombine to repair cracks or damage, significantly improving the durability and reliability of the material. Through the combination of epoxy resin matrix with liquid crystal polymers, antioxidants and flame retardants and other components, the material forms a high-strength, low thermal expansion multifunctional composite structure with good mechanical properties, aging resistance, flame retardancy and other characteristics. This composite material is particularly suitable for use in high temperature and high pressure environments, which improves the reliability and durability of the packaging structure.

[0028] Conclusion: The present invention not only simplifies the process flow and reduces production costs by optimizing the packaging process, optimizing the packaging structure, and optimizing the packaging materials, but also greatly improves the heat dissipation performance and reliability of the packaging structure, meeting the needs of high-performance DRAM packaging.

[0029] A more detailed mechanism is described in detail in the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0031] Figure 1 This is a schematic diagram of the structure in step 1 of the packaging structure preparation process of the present invention;

[0032] Figure 2 It is a structural schematic diagram of step 2 of the packaging structure preparation process of the present invention;

[0033] Figure 3 It is a structural schematic diagram of step 3 of the packaging structure preparation process of the present invention;

[0034] Figure 4 It is a structural schematic diagram of step 4 of the packaging structure preparation process of the present invention;

[0035] Figure 5 It is a structural schematic diagram of step 5 of the packaging structure preparation process of the present invention;

[0036] Figure 6 It is a schematic diagram of the structure in step 6 and step 7 of the packaging structure preparation process of the present invention;

[0037] Figure 7 It is a structural schematic diagram of step 7 of the packaging structure preparation process of the present invention;

[0038] Figure 8 It is a schematic diagram of the structure in step 8 and step 9 of the packaging structure preparation process of the present invention;

[0039] Fig. 9 It is a structural schematic diagram of step 9 of the packaging structure preparation process of the present invention;

[0040] Fig.10 It is a structural schematic diagram of step 10 of the packaging structure preparation process of the present invention;

[0041] Fig.11 It is a structural schematic diagram of step 10 of the packaging structure preparation process of the present invention;

[0042] The markings in the figure are: 1. Carrier; 2. Separation layer; 3. Wafer; 4. Circuit surface; 5. Molded packaging layer; 6. Connectable circuits; 7. Insulation layer; 8. Rewiring layer; 9. Bottom DRAM; 10. Vertical through hole; 11. Metal bump; 12. Temporary carrier; 13. DRAM 02 chip; 14. DRAM 03 chip; 15. DRAM 04 chip; 16. DRAM 01 chip. DETAILED DESCRIPTION

[0043] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0044] Many specific details are disclosed herein to provide a comprehensive and feasible description of embodiments of the present technology. However, those skilled in the art will appreciate that the technology may have additional embodiments and may be practiced without several details of the embodiments described below. For example, some details and conventional techniques / processes of semiconductor devices and / or packaging known in the art are omitted to avoid confusing the present technology. In general, it should be understood that various other devices and systems in addition to those specific embodiments disclosed herein may be within the scope of the present technology.

[0045] In this specification, the use of quantifiers is to better describe the technical solution, but does not exclude the scenario of multiple elements. The purchase method of some materials is provided to help technicians in this field to better implement the technical solution, but does not exclude other reasonable purchase methods. The meaning of "part" in the following is the number of parts by weight.

[0046] 1. Optimizing DRAM (Dynamic Random Access Memory) Packaging Structure

[0047] Technical issues: Through-silicon via technology and TSV exposure processes are very complex, with low yield and high cost. Therefore, how to introduce a simpler, low-cost and reliable vertical interconnection technology in stacked DRAM packaging has become an urgent problem to be solved in the industry.

[0048] Technical means: This application does not use TSV technology to avoid the defects caused by TSV.

[0049] The high-density vertical stacked DRAM package structure has the following steps for the preparation process:

[0050] Step 1: Figure 1As shown, a carrier 1 is selected, and the material of the carrier 1 is glass or silicon carrier or silicon wafer, and the carrier 1 can also be a conventional substrate in the art. A separation layer 2 is loaded on the carrier 1 to obtain a temporary carrier.

[0051] The loading method can be: 1) coating a layer of detachable material (such as a thermosensitive polymer) on the carrier; or 2) pasting a dicing tape on the carrier; or 3) pasting a carrier film on the carrier. Here is the purchase method of dicing tape: ELEGRIP TAPE (dicing tape) of Denka Electric Co., Ltd.

[0052] Step 2: If Figure 2 As shown, the wafer 3 to be processed is fixed face up on a temporary carrier, and DRAM 01 wafer to DRAM 04 wafer are obtained respectively. It should be noted that the wafer face up means that the circuit surface 4 of the wafer faces up, and the circuit surface 4 is defined as the front side of the wafer here, and the back side of the wafer temporarily fixed on the carrier is the back side of the wafer. This definition is for a clearer description of the technical solution of the present application, and the following "front side of the wafer / chip" and "back side of the wafer / chip" also follow this definition and do not violate the basic principles of the art.

[0053] Step 3: If Figure 3 As shown, a molding compound is used for encapsulation molding to form a molded encapsulation layer 5 on each of the DRAM 01 wafer to the DRAM 04 wafer. It should be noted that the molding compound may be an epoxy molding compound (EMC).

[0054] The front side of the molded packaging layer 5 is thinned to the required thickness through a grinding process to expose the connectable circuit 6, and the ground DRAM 01 wafer to DRAM 04 wafer are obtained respectively. It should be noted that the thickness can be adjusted according to actual needs, and the purpose of thinning is to expose the connectable circuit to facilitate the later circuit connection and reconstruction.

[0055] Step 4: Figure 4As shown, based on the RDL technology, an insulating layer 7 is deposited on the surface of the ground DRAM 01 wafer ~ DRAM 04 wafer. The surface here is the front of the wafer. The insulating layer 7 can also be a protective layer and / or a passivation layer and / or a solder mask. The function of the insulating layer 7 is to protect the wafer and avoid energy transfer. The other functions of the insulating layer 7 are well known in the art and will not be described in detail. Then the insulating layer 7 is exposed and developed to define a new wire pattern, and then a new metal line is made using electroplating technology. The new metal line is connected to the original connectable line 6 to achieve line redistribution, forming a rewiring layer 8, and obtaining the rewired DRAM 01 wafer ~ DRAM 04 wafer. It should be noted that the metal of the metal line can be copper, aluminum, electroplated copper, nickel gold, nickel palladium gold, and this metal can also be selected from conventional metal materials in RDL technology. Based on the RDL technology here, the I / O contact spacing is more flexible, and a larger number of pins can be achieved, which improves the flexibility and reliability of the technical solution of this application and reduces costs.

[0056] Step 5: Figure 5 As shown, the DRAM 02 wafer ~ DRAM 04 wafer are separated from the carrier 1 by thermal, chemical or mechanical means, and the separation layer 2 and bonding residues, contaminants and impurities in the process are removed by chemical cleaning (such as IPA solution), and then the DRAM 02 wafer ~ DRAM 04 wafer are cut into independent DRAM 02 chips 13 ~ DRAM 04 chips 15 using precision cutting equipment. It should be noted that the DRAM 01 wafer is not processed in step 5. Figure 5 DRAM 02 chip 13 is illustrated, as are DRAM 03 chip 14 and DRAM 04 chip 15, so this step is illustrated using only one drawing.

[0057] Step 6: Figure 6 As shown, the DRAM 01 wafer to be used is used as the bottom DRAM 01 wafer, that is, as the bottom DRAM 9.

[0058] Step 7: Figure 6 and Figure 7 As shown, the independent DRAM 02 chip 13 is vertically stacked on the bottom DRAM 9, the independent DRAM 03 chip 14 is vertically stacked on the DRAM 02 chip 13, and the independent DRAM 04 chip 15 is vertically stacked on the DRAM 03 chip 14, so as to form a column stack. Multiple columns of stacks can be formed on the bottom DRAM 9, and there can be spaces or channels between the columns, which can be adjusted according to actual needs. It should be noted that in the vertical stacking, each layer of chips is adhered with an adhesive, and the adhesive is an adhesive suitable for use between chips, and can be a film adhesive. The manufacturer models that can be purchased are provided here: LG Chemical, DAF.

[0059] Step 8: Figure 8 As shown, for each column stack, a vertical through hole 10 is formed in the molded package layer 5 of the DRAM 02 chip 13 to the DRAM 04 chip 15 by using laser drilling or mechanical drilling technology. When the vertical through hole 10 penetrates the molded package layer 5, it needs to pass through the redistribution layer 8 of the DRAM 02 chip 13 to the DRAM 04 chip 15. The bottom of the vertical through hole 10 is connected to the redistribution layer 8 of the bottom DRAM 9. There can be multiple vertical through holes 10. In this embodiment, the vertical through holes 10 are symmetrically arranged on both sides of the DRAM 02 chip 13 to the DRAM 04 chip 15. It should be noted that the vertical through holes 10 can connect the bottom DRAM 9 and the lines between the layers of the DRAM 02 chip 13 to the DRAM 04 chip 15.

[0060] Step 9: Continue to refer Figure 8 , using electroplating and / or chemical plating and / or sputtering process, depositing conductive material in vertical through hole 10, ensuring electrical connectivity between bottom DRAM 9 and DRAM 02 chip 13 ~ DRAM 04 chip 15, forming a conductive path. It should be noted that the conductive material can be metal, including copper, gold, silver, aluminum, nickel, electroplated copper metal.

[0061] like Fig. 9 As shown, rewiring is then performed on the front side of each column of stacked chips, that is, the front side of the DRAM 04 chip 15, that is, the rewiring layer 8 of the DRAM 04 chip 15. Similar to step 4, based on the RDL technology, an insulating layer 7 is first deposited, and then the insulating layer 7 is exposed and developed to define a new conductor pattern. Then, a new metal line is made using electroplating technology, and the new metal line is connected to the original rewiring layer 8 and the deposited conductive material to achieve line redistribution, forming a rewiring layer 8 of each column of stacked chips, and obtaining a stacked chip after rewiring. It should be noted that the purpose of performing RDL twice is to expand and optimize the I / O connection and rewire the chip signal to a specified location.

[0062] Continue to refer Fig. 9 Then, a metal bump 11 is formed on the redistribution layer 8 of each column of stacked chips. The metal bump 11 is a solder ball or a C4 bump, and the forming method is a C4 bump method or a solder bump method.

[0063] Step 10: Fig.10As shown, the back side of the multi-column stacked chips is separated from the carrier 1 by heat, chemical or mechanical means, that is, the back side of the DRAM 01 wafer is separated from the carrier 1. Then, the separation layer 2 and the adhesive residues, contaminants and impurities in the process are removed by chemical cleaning (such as IPA solution), and then the multi-column stacked metal bumps 11 are fixed on the temporary carrier 12. It should be noted that the temporary carrier 12 is a conventional carrier suitable for this field, and can also be a conventional carrier coated with a temporary bonding material. The temporary bonding material can be purchased from 3M Company, and the temporary bonding material can be a photothermal conversion release agent, a UV curing adhesive, or a wafer peeling tape.

[0064] like Fig.10 As shown, a precision cutting device is then used to cut the multi-column stack into a single-column stack. When the multi-column stack is cut into a single-column stack, the bottom DRAM 9 is also cut into DRAM 01 chips 16 accordingly.

[0065] like Fig.11 As shown, the temporary carrier 12 is then removed to obtain a high-density vertically stacked DRAM packaging structure.

[0066] It should be noted that if further processing is required according to demand, such as assembly and bonding, the high-density vertically stacked DRAM packaging structure provided in this application can be further improved.

[0067] Furthermore, the mechanism and structure of the high-density vertical stacked DRAM packaging structure of the present application are: using "embedded vertical interconnection" technology to prepare a vertical interconnection structure, in each layer of the structure, a conductive material is embedded to form a vertical interconnection path. This structure not only simplifies the process, but also realizes efficient vertical signal transmission through the vertical stacking structure, and improves the signal transmission efficiency between chips.

[0068] (II) Further optimization of the process

[0069] Technical issue: As the number of chips stacked increases, the height of the package structure will also increase, which may reduce heat dissipation performance.

[0070] Technical means: Improving the thermal conductivity of the packaging material can improve the heat dissipation performance of the packaging structure. Therefore, the molding compound is further improved.

[0071] Example 2

[0072] 1. Different from Example 1, conventional molding plastic is not used, and homemade molding plastic is prepared as follows:

[0073] Step 1: Weigh 50 parts of epoxy resin (Epon™ Resin 828, Hexion) and 20 parts of liquid crystal polymer (Vectra® A950, Celanese), and ultrasonically disperse them at 80°C for 30 minutes. In this environment, the two are mixed evenly without polymer agglomeration to obtain a matrix mixture. It should be noted that ultrasonic dispersion ensures that the liquid crystal polymer is evenly dispersed in the epoxy resin matrix, ensuring the uniform dispersion of the components.

[0074] Step 2: Disperse 5 parts of beryllium oxide (99% purity, Aladdin reagent) and 10 parts of boron nitride nanotubes (99% purity, Guangzhou Hongwu Material Technology Co., Ltd.) into the matrix mixture by ultrasonic oscillation and mechanical stirring, and then add 2 parts of polyvinyl pyrrolidone (98% purity, Yisheng Biological), and continue ultrasonic oscillation for 30 minutes to improve the compatibility of the components with the matrix mixture and ensure uniform distribution to obtain a premixed matrix.

[0075] Step 3: Gradually add 5 parts of zinc oxide (99% purity, Sigma-Aldrich) to the premixed matrix, stirring at 40°C during the addition process to ensure uniform distribution of zinc oxide and prevent agglomeration.

[0076] Then, 5 parts of epoxy resin curing agent (special epoxy curing agent EPICLON, HPC-8000-65T, DIC) and 0.5 parts of thermally activated catalyst (benzotriazole, 99% purity, Sigma-Aldrich) were gradually added and stirred at low speed for 15 minutes to ensure that all components were evenly dispersed.

[0077] Finally, 4.5 parts of an antioxidant (butylated hydroxytoluene, 99% purity, Aladdin reagent) and a flame retardant (melamine cyanurate, Melapur® MC25, BASF) were added, and the temperature was maintained at 40° C. with stirring to obtain a molding material.

[0078] Step 4: Place the molding material in a vacuum drying oven and dry it at a temperature of 60-80°C and a low pressure environment of 100-200 Pa to ensure that the solvent or residual volatiles in the mixture are completely evaporated to obtain a dry solid material.

[0079] Next, the dried solid material is placed in a ball mill with a ball mill speed of 100-200 rpm and a crushing time of 4-6 hours to obtain a coarse crushed material of 5-10 mm. The coarse crushed material is sent to the air flow mill for further refinement. The air flow mill uses high-speed airflow to further crush the particles and automatically separates them according to the different particle qualities. Airflow pressure: set to 0.6-1.0 MPa to ensure that the material is fully dispersed and crushed into uniform particles. Feed rate: control the feed rate to 1-2 kg / h to avoid too much material entering at one time, resulting in a decrease in crushing efficiency. Finally, a homemade molding compound of 50-200 µm is obtained, which is sealed and stored for standby use.

[0080] 2. Application: The self-made molding compound obtained in Example 2 is applied to the preparation process of the high-density vertical stacked DRAM packaging structure in Example 1, which is specifically reflected in step 3: Step 3: Figure 3 As shown, a self-made molding compound is used for encapsulation molding, and a molded encapsulation layer 5 is formed on each of the DRAM 01 wafer to the DRAM 04 wafer. The self-made molding compound is used to replace the conventional epoxy molding compound (EMC), and the method of use adopts the conventional encapsulation molding method in the art. During the use, the self-made molding compound undergoes cross-linking and curing. The remaining steps are the same as those in Example 1, and a high-density vertically stacked DRAM encapsulation structure is obtained.

[0081] 3. It should be noted that the above parts are parts by weight.

[0082] Example 3

[0083] Further provide the use parameters of the homemade film plastic in Example 2:

[0084] During molding: the treated homemade molding material is placed in the mold and a high-pressure injection molding process is adopted with an injection temperature of 80°C and an injection pressure of 100 MPa.

[0085] Then dynamic thermal curing and shape memory molding: a two-step thermal curing process is performed. The first step is to perform initial curing at 150°C for 2 hours to form a preliminary cross-linking network. The second step is to increase the temperature to 180°C for 3 hours to promote the phase change of the liquid crystal polymer and form the final structure. Among them, if the temperature is further increased, the time can be shortened.

[0086] It should be noted that when the above method and parameters are used, the wafer is embedded in the self-made film plastic to form a molded packaging layer 5 .

[0087] 4. New mechanisms and microstructures of homemade film plastics: (1) The molecular arrangement of liquid crystal polymers can be oriented during heating to form a highly ordered molecular structure, which enhances the thermal conductivity and mechanical strength of the material. This process is equivalent to the material being able to adaptively adjust its molecular arrangement during curing to cope with different temperature changes. (2) The mixed matrix of epoxy resin and liquid crystal polymer provides high strength and self-adjustment ability. The dual matrix design, by combining epoxy resin and liquid crystal polymer, combines the characteristics of both, so that the material not only has high toughness and thermal stability, but also can achieve self-adjustment of the matrix structure through external electric field or temperature changes. Through the new self-adjustment mechanism, the molding material can dynamically adjust its mechanical properties and thermal conductivity under different working environments. (3) Through the combination of beryllium oxide, boron nitride nanotubes, zinc oxide and other components, a uniformly distributed nanoscale thermal conductive network is formed. This network structure can quickly transfer heat and effectively reduce the accumulation of hot spots in the packaging structure, thereby improving the overall heat dissipation of the package. In addition, these materials create a fast heat conduction path by filling the gaps in the epoxy resin matrix, thereby achieving higher heat dissipation efficiency. There is also a synergistic effect. Through the synergistic effect of beryllium oxide, boron nitride nanotubes and liquid crystal polymers, the thermal conductivity of the molding material has been significantly improved. (4) Benzotriazole, as a thermally activated catalyst, promotes the cross-linking and curing reaction of epoxy resin at high temperature, while ensuring that the material is stable at a lower temperature. The action of this catalyst makes the material have the characteristics of thermal response, which can be quickly cured in a specific temperature environment, thereby improving the process efficiency. This thermal response property allows the material to be cured and strengthened adaptively according to different temperature environments. (5) Through the combination of epoxy resin matrix with liquid crystal polymer, thermal conductive filler, antioxidant and flame retardant, the material forms a high-strength multifunctional composite structure, which not only has good mechanical properties, but also has anti-aging and flame retardant properties. This multifunctional composite structure is particularly suitable for use in high temperature and high pressure environments, which improves the reliability and durability of the material. (6) The thermal expansion coefficient of the homemade molding material is low, which can reduce the stress caused by thermal expansion during chip packaging and improve the reliability of the packaging structure. (7) This makes the molding material not just a passive packaging material, but also an intelligent material with active regulation capabilities.

[0088] (III) Further optimization of molding materials

[0089] Purpose: To give molding compounds more properties.

[0090] Example 4

[0091] 1. Different from Example 2, step 3 is as follows:

[0092] Step 3: Gradually add 5 parts of zinc oxide (99% purity, Sigma-Aldrich) to the premixed matrix, stirring at 40°C during the addition process to ensure uniform distribution of zinc oxide and prevent agglomeration. Then add 10 parts of self-healing agent (thermoplastic polyurethane, Desmopan®, Covestro) to the mixture and stir at low speed for 15 minutes to ensure uniform dispersion.

[0093] Then, 5 parts of epoxy resin curing agent (special epoxy curing agent EPICLON, HPC-8000-65T, DIC) and 0.5 parts of thermally activated catalyst (benzotriazole, 99% purity, Sigma-Aldrich) were gradually added and stirred at low speed for 15 minutes to ensure that all components were evenly dispersed.

[0094] Finally, 4.5 parts of an antioxidant (butylated hydroxytoluene, 99% purity, Aladdin reagent) and a flame retardant (melamine cyanurate, Melapur® MC25, BASF) were added, and the temperature was maintained at 40° C. with stirring to obtain a molding material.

[0095] The remaining steps are the same as those in Example 2.

[0096] 2. Introduce self-healing agents to give the material self-healing capabilities and extend the service life of the packaging structure, especially in response to mechanical stress and cracks. When external forces or temperature changes, dynamic covalent bonds can break and recombine after the environment recovers, thereby repairing cracks or damaged areas. Since these reversible bonds can be broken and formed multiple times, the material can self-repair multiple times, improving durability. Thermally activated catalysts can cooperate with self-healing agents to improve self-healing efficiency.

[0097] (IV) Testing

[0098] For the specific composition and purchase method of the materials in Case 1 to Case 4, please refer to Example 2 and Example 4.

[0099] Test whether homemade molding compounds can improve heat dissipation.

[0100] Case 1:

[0101] Step 1: Weigh 50 parts of epoxy resin and 20 parts of liquid crystal polymer, and ultrasonically disperse them at 80° C. for 30 minutes. In this environment, the two are mixed evenly without polymer agglomeration, to obtain a matrix mixture.

[0102] Step 2: Disperse 5 parts of beryllium oxide and 10 parts of boron nitride nanotubes into the matrix mixture by ultrasonic oscillation and mechanical stirring, then add 2 parts of polyvinyl pyrrolidone, and continue ultrasonic oscillation for 30 minutes to obtain a premixed matrix.

[0103] Step 3: Gradually add 5 parts of zinc oxide to the premixed matrix, and stir at 40°C during the addition process. Then gradually add 5 parts of epoxy resin curing agent and 0.5 parts of thermally activated catalyst, and stir at a low speed for 15 minutes. Finally, add 4.5 parts of antioxidant and flame retardant, and stir at 40°C to obtain a molding material.

[0104] Case 2: No liquid crystal polymer is added.

[0105] Step 1: Disperse 5 parts of beryllium oxide and 10 parts of boron nitride nanotubes into 50 parts of epoxy resin by ultrasonic oscillation and mechanical stirring, then add 2 parts of polyvinyl pyrrolidone, and continue ultrasonic oscillation for 30 minutes to obtain a premixed matrix.

[0106] Step 2: Gradually add 5 parts of zinc oxide to the premixed matrix, and stir at 40°C during the addition process. Then gradually add 5 parts of epoxy resin curing agent and 0.5 parts of thermally activated catalyst, and stir at a low speed for 15 minutes. Finally, add 4.5 parts of antioxidant and flame retardant, and stir at 40°C to obtain a molding material.

[0107] Case 3: No thermally activated catalyst is added.

[0108] Step 1: Weigh 50 parts of epoxy resin and 20 parts of liquid crystal polymer, and ultrasonically disperse them at 80° C. for 30 minutes. In this environment, the two are mixed evenly without polymer agglomeration, to obtain a matrix mixture.

[0109] Step 2: Disperse 5 parts of beryllium oxide and 10 parts of boron nitride nanotubes into the matrix mixture by ultrasonic oscillation and mechanical stirring, then add 2 parts of polyvinyl pyrrolidone, and continue ultrasonic oscillation for 30 minutes to obtain a premixed matrix.

[0110] Step 3: Gradually add 5 parts of zinc oxide to the premixed matrix, and stir at 40°C during the addition process. Then gradually add 5 parts of epoxy resin curing agent and stir at a low speed for 10 minutes. Finally, add 4.5 parts of antioxidant and flame retardant, and stir at 40°C to obtain a molding material.

[0111] Case 4: Adding self-healing agent.

[0112] Step 1: Weigh 50 parts of epoxy resin and 20 parts of liquid crystal polymer, and ultrasonically disperse them at 80° C. for 30 minutes. In this environment, the two are mixed evenly without polymer agglomeration, to obtain a matrix mixture.

[0113] Step 2: Disperse 5 parts of beryllium oxide and 10 parts of boron nitride nanotubes into the matrix mixture by ultrasonic oscillation and mechanical stirring, then add 2 parts of polyvinyl pyrrolidone, and continue ultrasonic oscillation for 30 minutes to obtain a premixed matrix.

[0114] Step 3: Gradually add 5 parts of zinc oxide to the premixed matrix, stirring at 40°C during the addition process. Then add 10 parts of self-healing agent to the mixture and stir at low speed for 15 minutes. Then gradually add 5 parts of epoxy resin curing agent and 0.5 parts of thermally activated catalyst and stir at low speed for 15 minutes. Finally, add 4.5 parts of antioxidant and flame retardant, keep the temperature at 40°C and stir to obtain molding material.

[0115] Prepare samples from Case 1 to Case 4 and test the thermal conductivity:

[0116] Case 1, Case 3, and Case 4 were injection molded using a transfer molding machine at an injection temperature of 80°C and an injection pressure of 100 MPa. The initial curing was then performed at 150°C for 2 hours, and then the temperature was raised to 180°C for 3 hours to obtain the sample.

[0117] In case 2, a transfer molding machine was used to obtain a sample by injection molding at an injection temperature of 80°C and an injection pressure of 100 MPa.

[0118] The specifications of the samples are: diameter: 10 mm, thickness: 2 mm.

[0119] Then use the laser flash thermal conductivity tester (LFA 447) to place the sample on the sample holder of the test instrument to ensure good contact between the sample and the test probe. Set the test temperature (25℃, 50℃ and 100℃) and allow the sample to equilibrate at the test temperature for 30 minutes. The laser pulse irradiates the bottom of the sample, and the heat generated by the laser irradiation is conducted inside the sample, and the temperature change on the top of the sample is detected by the infrared sensor above.

[0120] The instrument calculates the thermal diffusivity of the sample based on the temperature response curve. Repeat this process to measure the thermal conductivity of each sample, test 3 times, and take the average thermal conductivity to ensure the data is reliable.

[0121] Heat dissipation performance evaluation: Heat dissipation performance is analyzed based on thermal conductivity. The higher the thermal conductivity, the more effectively the material can dissipate heat.

[0122] Table 1

[0123]

[0124] The test results are shown in Table 1. This shows that after adding liquid crystal polymer / thermally activated catalyst / self-healing agent, the thermal conductivity of the material is significantly improved, and the synergistic effect of each component further enhances the thermal conductivity and stability of the material. Among them, in case 4, the thermal conductivity performance is the best when the self-healing agent is added, especially at 100°C. Specific analysis:

[0125] Case 1 (with liquid crystal polymer): As the temperature rises, the thermal conductivity further improves. Due to the synergistic effect of liquid crystal polymer and other components, the thermal conductivity path is well established.

[0126] Case 2 (without LCP): Due to the lack of the thermal conductivity enhancement effect of LCP, the thermal conductivity is low. Nevertheless, the addition of other components still makes its thermal conductivity close to 8 W / m·K.

[0127] Case 3 (without using thermally activated catalyst): Due to the lack of thermally activated catalyst, the thermal conductivity path of this material is slightly insufficient, but the overall performance is still good, reaching 8.4 W / m·K at 100°C.

[0128] Case 4 (addition of self-healing agent): The addition of self-healing agent enhances the structural stability of the material, and its thermal conductivity is even better at high temperatures, reaching 8.9 W / m·K at 100°C.

[0129] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0130] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A process for preparing a high-density vertically stacked DRAM package structure, characterized in that: include: A separation layer (2) is loaded on a carrier (1) to obtain a temporary carrier, and the back of a wafer (3) is fixed on the temporary carrier to obtain DRAM 01 wafer to DRAM 04 wafer, respectively, and the front of the wafer (3) has a circuit surface (4); a molding compound is used for encapsulation molding to form a molded encapsulation layer (5) on the DRAM 01 wafer to the DRAM 04 wafer respectively; the front of the molded encapsulation layer (5) is thinned to expose a circuit (6) that can be connected, and the ground DRAM 01 wafer to the DRAM 04 wafer are respectively obtained; An insulating layer (7) is deposited on the surface of the ground DRAM 01 wafer to the DRAM 04 wafer, and a new metal line is made on the insulating layer (7). The new metal line is connected to the original connectable line (6) to form a redistribution layer (8), and the DRAM 01 wafer is used as the bottom DRAM (9); the DRAM 02 wafer to the DRAM 04 wafer are separated from the separation layer (2) and cut into independent DRAM 02 chips (13) to DRAM 04 chips (15); An independent DRAM 02 chip (13) is vertically stacked on the bottom DRAM (9), an independent DRAM 03 chip (14) is vertically stacked on the DRAM 02 chip (13), and an independent DRAM 04 chip (15) is vertically stacked on the DRAM 03 chip (14), so as to form a column of stacked chips, and multiple columns of stacked chips are formed on the bottom DRAM (9); for each column of stacked chips, a vertical through hole (10) is formed in the molded packaging layer (5) of the DRAM 02 chip (13) to the DRAM 04 chip (15), the vertical through hole (10) penetrates the molded packaging layer (5), and a conductive material is deposited in the vertical through hole (10); Rewiring the front side of each column of stacked chips, first depositing an insulating layer (7), making a new metal line on the insulating layer (7), connecting the new metal line to the original rewiring layer (8) and the deposited conductive material, and forming a rewiring layer (8) of each column of stacked chips; forming a metal bump (11) on the rewiring layer (8) of each column of stacked chips; The back side of the multi-column stacked chips is separated from the separation layer (2), and then the metal bumps (11) of the multi-column stacked chips are fixed on a temporary carrier (12); the multi-column stack is cut into a single-column stack, and the temporary carrier (12) is removed to obtain a high-density vertically stacked DRAM packaging structure.

2. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: A vertical through hole (10) is formed in the molded packaging layer (5) of the DRAM02 chip (13) to the DRAM04 chip (15). When the vertical through hole (10) penetrates the molded packaging layer (5), it needs to pass through the redistribution layer (8) of the DRAM02 chip (13) to the DRAM04 chip (15). The bottom of the vertical through hole (10) is connected to the redistribution layer (8) of the bottom DRAM (9).

3. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: The molding compound includes a molding material, and the preparation method of the molding material includes: Ultrasonic dispersion of epoxy resin and liquid crystal polymer, then adding beryllium oxide and boron nitride nanotubes to disperse evenly, then adding polyvinyl pyrrolidone to shake, gradually adding zinc oxide, stirring evenly, adding or not adding self-healing agent, gradually adding curing agent, then adding or not adding catalyst, stirring evenly, adding antioxidant to obtain molding material.

4. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: The molding compound includes a molding material, and the preparation method of the molding material includes: Beryllium oxide and boron nitride nanotubes are dispersed into epoxy resin by ultrasonic oscillation and mechanical stirring, and then polyvinyl pyrrolidone is added and oscillated, zinc oxide is gradually added, stirred evenly, a self-healing agent is added or not added, a curing agent is gradually added, and then a catalyst is added or not added, stirred evenly, an antioxidant is added to obtain a molding material.

5. The process for preparing a high-density vertically stacked DRAM package structure according to claim 3 or 4, characterized in that: The molding material is vacuum dried to obtain a solid material, and then the solid material is ball-milled and / or jet-milled to obtain a molding compound.

6. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: The use parameters of the molding material include the following conditions: Condition 1: placing the molding material in a mold for high pressure injection molding; and / or Condition 2: performing a primary curing of the molding material at 100-200°C and then heating it to 150-250°C for a secondary curing.

7. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: The temporary carrier (12) is a carrier coated with a temporary bonding material, wherein the temporary bonding material comprises at least one of a photothermal conversion type release agent, an ultraviolet curing adhesive, and a wafer peeling tape.

8. The process for preparing a high-density vertically stacked DRAM package structure according to claim 1, wherein: When stacked vertically, each layer of chips is bonded together using an adhesive, including a film adhesive.

9. A high-density vertically stacked DRAM package structure, characterized in that: The high-density vertically stacked DRAM package structure is prepared by the preparation process of the high-density vertically stacked DRAM package structure according to claim 1, The packaging structure comprises a DRAM chip, the DRAM chip comprises a chip body, the chip body comprises a front side and a back side, the front side comprises a circuit surface (4), an insulating layer (7) is covered on the circuit surface (4), a redistribution layer (8) is formed on the insulating layer (7), and the redistribution layer (8) and the circuit surface (4) are electrically connected; The DRAM chip includes a DRAM 02 chip (13), the back side of the DRAM 02 chip (13) is vertically stacked on the front side of the DRAM 01 chip (16), the back side of the DRAM 03 chip (14) is vertically stacked on the front side of the DRAM 02 chip (13), the back side of the DRAM 04 chip (15) is vertically stacked on the front side of the DRAM 03 chip (14), and the front side of the DRAM 04 chip (15) has a metal bump (11); The structures of the DRAM 01 chip (16) to the DRAM 04 chip (15) are the same, and are all coated with a molding compound to form a molding packaging layer (5). The molding compound does not coat an insulating layer (7) and a redistribution layer (8). A vertical through hole (10) penetrates the high-density vertically stacked DRAM packaging structure from the inside, and specifically, one end of the vertical through hole (10) is connected to the redistribution layer (8) of the DRAM 04 chip (15), and the other end of the vertical through hole (10) is connected to the redistribution layer (8) of the DRAM 01 chip (16); a conductive material is deposited in the vertical through hole (10); the molding compound includes a finished epoxy resin molding compound and a molding material, and the molding material includes at least one of epoxy resin, liquid crystal polymer, beryllium oxide, boron nitride nanotubes, zinc oxide, a curing agent, a catalyst, an antioxidant, a flame retardant, and a self-healing agent.

10. The high-density vertically stacked DRAM package structure according to claim 9, wherein: The curing agent includes an epoxy resin curing agent, the catalyst includes a thermally activated catalyst, the thermally activated catalyst includes benzotriazole, the antioxidant includes butylated hydroxytoluene, the flame retardant includes melamine cyanurate, and the self-healing agent includes thermoplastic polyurethane.

Images