Thin film transistor, method of manufacturing same, and display device including same

Abstract

A thin film transistor, a method of manufacturing the same, and a display device including the same are provided. The thin film transistor includes a light shielding layer, an active layer on the light shielding layer, a gate spaced apart from the active layer and overlapping at least a portion of the active layer, and an inner bridge electrically connecting the light shielding layer and the gate insulated from the active layer, wherein the inner bridge overlaps the gate and penetrates the active layer in a direction from the gate to the light shielding layer. In addition, one embodiment of the present disclosure provides a display device including a thin film transistor.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor, a method for manufacturing the thin film transistor, and a display device including the thin film transistor. In more detail, embodiments of the present disclosure relate to a thin film transistor including an inner bridge connecting a gate and a light shielding layer through a channel region, a method for manufacturing the thin film transistor, and a display device including the thin film transistor. Background Art

[0002] Since a thin film transistor can be manufactured on a glass or plastic substrate, the thin film transistor has been widely used as a switching element or a driving element in, for example, a liquid crystal display device or an organic light emitting device.

[0003] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors (in which amorphous silicon is used as the active layer), polycrystalline silicon thin film transistors (in which polycrystalline silicon is used as the active layer), and oxide semiconductor thin film transistors (in which oxide semiconductor is used as the active layer).

[0004] Among them, the oxide semiconductor thin film transistor (oxide semiconductor TFT) has high mobility and can have a large resistance change depending on the oxygen content, which has the advantage that the desired performance can be easily obtained. In addition, the manufacturing cost of the oxide semiconductor thin film transistor is low because the oxide constituting the active layer can be formed at a relatively low temperature in the manufacturing process of the oxide semiconductor thin film transistor. Due to the nature of the oxide, the oxide semiconductor is transparent, so the oxide semiconductor thin film transistor is conducive to the realization of a transparent display device. Summary of the invention

[0005] The electrical properties of an oxide semiconductor may vary depending on light. Therefore, in order to ensure the driving stability of a thin film transistor including an oxide semiconductor, a light shielding layer for blocking light incident on the oxide semiconductor may be provided in the thin film transistor. However, when a light shielding layer is provided in a thin film transistor, the area of ​​the thin film transistor may increase due to reasons such as the area of ​​the light shielding layer itself and the area for forming a contact hole.

[0006] In addition, light is blocked in the frame portion, but in the case of a transparent display device, light irradiated in an oblique direction may be incident on the frame portion. Therefore, in the case of a transparent display device, a light shielding layer needs to be provided to protect the thin film transistor provided in the frame portion.

[0007] Since such a thin film transistor requiring a light shielding layer is provided in a display device, research is being conducted to improve the efficiency of providing the light shielding layer and to drive the thin film transistor using the light shielding layer.

[0008] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to improve the arrangement efficiency of a light shielding layer in a thin film transistor having the light shielding layer.

[0009] Another object of the present disclosure is to provide a structure that can effectively connect a light shielding layer and other devices in a thin film transistor having the light shielding layer.

[0010] Another object of the present disclosure is to improve driving efficiency of a thin film transistor by using a light shielding layer.

[0011] To this end, an embodiment of the present disclosure provides a thin film transistor including an inner bridge penetrating a channel region and connecting a gate and a light shielding layer.

[0012] Another embodiment of the present disclosure provides a method for manufacturing a thin film transistor having the above structure.

[0013] Still another embodiment of the present disclosure provides a display device including the thin film transistor having the above structure.

[0014] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor, which includes a light shielding layer; an active layer on the light shielding layer; a gate spaced from the active layer and overlapping with at least a portion of the active layer; and an internal bridge electrically connecting the gate and the light shielding layer, wherein the active layer includes a channel portion overlapping with the gate; a first connecting portion, which is in contact with one side of the channel portion, and the first connecting portion does not overlap with the gate; and a second connecting portion, which is spaced from the first connecting portion and in contact with the other side of the channel portion, and the second connecting portion does not overlap with the gate, wherein the light shielding layer overlaps with at least the entire channel portion, and the internal bridge overlaps with the gate and the internal bridge penetrates the active layer in a direction from the gate to the light shielding layer.

[0015] The thin film transistor may further include a buffer layer between the light shielding layer and the active layer and a gate insulating layer between the active layer and the gate, wherein the inner bridge is insulated from the active layer and penetrates the gate insulating layer and the buffer layer.

[0016] The inner bridge may contact the gate and the light shielding layer.

[0017] The internal bridge can be integrated with the gate.

[0018] The active hole may be disposed in a region whose boundary is defined by the active layer and the active layer is not disposed in the active hole, wherein at least a portion of the active hole overlaps the gate and the internal bridge is disposed in the active hole in a plan view.

[0019] The active hole as a whole may overlap the gate.

[0020] A portion of the active hole may not overlap with the gate.

[0021] The active hole may include a first active hole and a second active hole spaced apart from each other, and at least a portion of the first active hole and at least a portion of the second active hole may overlap the gate.

[0022] The inner bridge may include a first inner bridge disposed in the first active hole and a second inner bridge disposed in the second active hole.

[0023] The first active hole and the second active hole may be disposed to be spaced apart from each other in a direction perpendicular to a direction connecting the first connection portion and the second connection portion.

[0024] The first active hole and the second active hole may be disposed to be spaced apart from each other in a direction connecting the first connection portion and the second connection portion.

[0025] In a plan view, a portion of the active hole may protrude from the gate in a direction connecting the first connection portion and the second connection portion.

[0026] In a plan view, the active hole may protrude on both sides of the gate.

[0027] The thin film transistor may further include a first conductive pattern on the first connection portion and a second conductive pattern on the second connection portion, wherein the first conductive pattern and the second conductive pattern do not overlap the gate.

[0028] Each of the first conductive pattern and the second conductive pattern may not overlap the gate.

[0029] Each of the first and second conductive patterns may be spaced apart from the gate in a plan view.

[0030] The active layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0031] The thin film transistor may further include an external bridge that does not penetrate the active layer and is disposed outside a region defined by the active layer, wherein the external bridge may overlap the gate and electrically connect the gate and the light shielding layer.

[0032] The external bridge may be insulated from the active layer.

[0033] Another exemplary embodiment of the present disclosure provides a display device including a substrate and the above-mentioned thin film transistor.

[0034] The display device may further include a gate driver disposed on the substrate, wherein the gate driver may include a thin film transistor.

[0035] The display device may further include a pixel driving circuit disposed on the substrate, wherein the pixel driving circuit may include a thin film transistor.

[0036] According to other aspects of the present disclosure, the above and other purposes can be achieved by providing a method for manufacturing a thin film transistor, the method comprising the following steps: forming a light shielding layer on a substrate; forming a buffer layer on the light shielding layer; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer; and forming a gate on the gate insulating layer. Forming the active layer includes forming an active hole by selectively removing a portion of the active layer, the active hole is arranged in a region whose boundary is defined by the active layer, forming the gate insulating layer includes forming a through hole penetrating the gate insulating layer and the buffer layer, the through hole passes through the active hole, and forming the gate includes forming an internal bridge arranged in the through hole.

[0037] The inner bridge may be in contact with the gate and the light shielding layer.

[0038] Technical effects of the present disclosure

[0039] According to one embodiment of the present disclosure, the light shielding layer and the gate are connected by an internal bridge arranged inside the active layer or an external bridge arranged outside the active layer, thereby providing the same effect as a thin film transistor with a double gate structure. As a result, the thin film transistor according to an embodiment of the present disclosure can have excellent current characteristics and excellent driving characteristics.

[0040] Since the inner bridge is arranged in the active hole formed in the active layer to electrically connect the gate and the light shielding layer, no additional contact hole is required to connect the gate and the light shielding layer. As a result, the space utilization of the thin film transistor is increased, and a thin film transistor with a double gate structure can be implemented in a narrow area.

[0041] In addition, since the inner bridge or the outer bridge can apply an electric field to the channel portion of the active layer, the current characteristics of the channel portion can be improved.

[0042] The display device according to the embodiment of the present disclosure includes the above-described thin film transistor and thus can exhibit excellent response speed and excellent display quality.

[0043] In addition to the above-mentioned effects, other features and advantages of the present disclosure are described below or may be clearly understood from the description by those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present application, illustrate embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure. The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0045] Figure 1A is a plan view of a thin film transistor according to an embodiment of the present disclosure.

[0046] Figure 1B is along Figure 1A A cross-sectional view taken along line Ia-Ia'.

[0047] Figure 1C is along Figure 1A A cross-sectional view taken along line Ib-Ib'.

[0048] Figure 2A and Figure 2B Each of them is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0049] Figure 3A and Figure 3B Each of them is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0050] Figure 4A is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0051] Figure 4B is along Figure 4A A cross-sectional view taken along line IVa-IVa'.

[0052] Figure 4C is along Figure 4A A cross-sectional view taken along line IVb-IVb'.

[0053] Figure 5A and Figure 5B Each of them is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0054] Figure 6 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0055] Fig. 7A is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0056] Figure 7B is along Fig. 7A A cross-sectional view taken along line VIIa-VIIa'.

[0057] Figure 7C is along Fig. 7A A cross-sectional view taken along line VIIb-VIIb'.

[0058] Figure 8 is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0059] Fig. 9 is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0060] Fig. 10Ais a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0061] Fig. 10B is along Fig. 10A A cross-sectional view taken along line Xa-Xa'.

[0062] Fig. 10C is along Fig. 10A A cross-sectional view taken along line Xb-Xb'.

[0063] Fig.11 is a cross-sectional view of a thin film transistor according to another embodiment of the present disclosure.

[0064] Fig. 12A is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0065] Fig. 12B is along Fig. 12A A cross-sectional view taken along line XIIa-XIIa'.

[0066] Fig. 12C is along Fig. 12A A cross-sectional view taken along line XIIb-XIIb'.

[0067] Fig.12D is along Fig. 12A A cross-sectional view taken along line XIIc-XIIc'.

[0068] Fig.13A is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0069] Fig. 13B is along Fig.13A A cross-sectional view taken along line XIII-XIII'.

[0070] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D Each of them is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0071] Fig.15 is a plan view of a thin film transistor according to another embodiment of the present disclosure.

[0072] FIG. 16A to FIG. 16F is a schematic diagram of a method for manufacturing a thin film transistor according to another embodiment of the present disclosure.

[0073] Fig.17 is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0074] Fig.18 is a schematic diagram of a shift register.

[0075] Fig.19 yes Fig.18 A circuit diagram of an embodiment of a shift register having stages arranged therein.

[0076] Fig. 20 yes Fig.17 Circuit diagram of a pixel.

[0077] Fig.21 is a circuit diagram of a pixel of a display device according to another embodiment of the present disclosure.

[0078] Fig. 22 is a circuit diagram of a pixel of a display device according to another embodiment of the present disclosure.

[0079] Fig.23 is a circuit diagram of a pixel of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] The advantages and features of the present disclosure and methods for implementing the same will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully explain the present disclosure to those skilled in the art.

[0081] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and therefore, the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals represent the same elements. In the following description, when it is determined that the detailed description of the related known functions or configurations unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0082] In the case where “including,” “having,” and “comprising” described in the present specification are used, another part may be added unless “only” is used. Terms in the singular form may include plural forms unless mentioned otherwise.

[0083] When constructing an element, the element is interpreted as including an error range although there is no explicit description.

[0084] When describing a positional relationship, for example, when the positional relationship is described as "on," "over," "under," and "beside," one or more parts may be set between two other parts unless "only" or "directly" is used.

[0085] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to easily describe the relationship of one or more elements to another or more elements as shown in the figures. It should be understood that these terms are intended to include different orientations of the device in addition to the orientations shown in the figures. For example, if the device shown in the figures is inverted, a device described as being disposed "below" or "below" another device may be disposed "above" the other device. Thus, the exemplary term "below or below" may include both "below or below" and "above" orientations. Similarly, the exemplary terms "above..." or "on..." may include both "above" and "below or below" orientations.

[0086] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0087] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to separate one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0088] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0089] The features of the various embodiments of the present disclosure may be partially or entirely connected or combined with each other, and may interoperate with each other differently and be driven technically, as those skilled in the art can fully understand. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0090] In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.

[0091] In the embodiments of the present disclosure, for ease of description, the source and the drain are distinguished from each other. However, the source and the drain can be used interchangeably. The source can be a drain, and the drain can be a source. In addition, the source in any one embodiment of the present disclosure can be a drain in another embodiment of the present disclosure, and the drain in any one embodiment of the present disclosure can be a source in another embodiment of the present disclosure.

[0092] In some embodiments of the present disclosure, for ease of description, the source connection portion and the source are distinguished, and the drain connection portion and the drain are distinguished, but the embodiments of the present disclosure are not limited thereto. The source connection portion may be the source, and the drain connection portion may be the drain. In addition, the source connection portion may be the drain, and the drain region may be the source.

[0093] Figure 1A is a plan view of a thin film transistor according to an embodiment of the present disclosure, Figure 1B is along Figure 1A A cross-sectional view taken along line Ia-Ia', Figure 1C is along Figure 1A A cross-sectional view taken along line Ib-Ib'.

[0094] The thin film transistor 100 according to an embodiment of the present disclosure includes a light shielding layer 111, an active layer 130 on the light shielding layer 111, a gate 150 spaced apart from the active layer 130 and overlapping at least a portion of the active layer 130, and an inner bridge (BR) electrically connecting the gate 150 and the light shielding layer 111. The inner bridge (BR) is insulated from the active layer 130.

[0095] Reference Figure 1B and Figure 1C , the thin film transistor 100 according to the embodiment of the present disclosure may be disposed on a substrate 110 .

[0096] Glass or plastic may be used as the substrate 110. Transparent plastic having flexibility, such as polyimide, may be used as the plastic of the substrate 110. When polyimide is used as the substrate 110, heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high-temperature deposition process on the substrate 110.

[0097] The light shielding layer 111 is disposed on the substrate 110. The light shielding layer 111 blocks light incident from the outside and protects the active layer 130. The light shielding layer 111 may be made of a material having a light blocking property.

[0098] In addition, according to an embodiment of the present disclosure, the light shielding layer 111 has conductivity. The light shielding layer 111 according to an embodiment of the present disclosure may include a metal layer. The light shielding layer 111 may be made of one or more metal layers.

[0099] For example, the light shielding layer 111 may include at least one of aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The light shielding layer 111 may have a single layer structure or a multilayer structure including at least two conductive layers having different physical or electrical properties.

[0100] The buffer layer 120 may be disposed on the light shielding layer 111. The buffer layer 120 has electrical insulation properties. The buffer layer 120 may include, for example, at least one of silicon oxide, silicon nitride, and a metal-based oxide. The buffer layer 120 may block oxygen (O2) or moisture (H2O) to protect the active layer 130. In addition, the buffer layer 120 may make the surface of the upper portion of the substrate 110 uniform.

[0101] Reference Figure 1B and Figure 1C , the active layer 130 is disposed on the buffer layer 120 .

[0102] The active layer 130 may include a semiconductor material. According to one embodiment of the present disclosure, the active layer 130 may include an oxide semiconductor material.

[0103] According to one embodiment of the present disclosure, the active layer 130 may include at least one of an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on ITZO (InSnZnO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on FIZO (FeInZnO), an oxide semiconductor material based on ZnO, an oxide semiconductor material based on SIZO (SiInZnO), and an oxide semiconductor material based on ZnON (Zn-Oxynitride). However, one embodiment of the present disclosure is not limited thereto, and the active layer 130 may be formed of other oxide semiconductor materials known in the art.

[0104] According to one embodiment of the present disclosure, the active layer 130 includes a channel portion 130 n , a first connection portion 130 a , and a second connection portion 130 b .

[0105] The channel portion 130n overlaps the gate electrode 150. The channel portion 130n serves as a channel of the thin film transistor 100.

[0106] According to one embodiment of the present disclosure, the light shielding layer 111 may overlap at least the entire channel portion 130n. As a result, the light shielding layer 111 may effectively protect the channel portion 130n. Figure 1A, based on a plan view, the light shielding layer 111 overlaps the entire channel portion 130n, and the area of ​​the light shielding layer 111 is greater than the area of ​​the channel portion 130n. According to one embodiment of the present disclosure, the light shielding layer 111 may overlap the entire active layer 130, and the area of ​​the light shielding layer 111 may be greater than the area of ​​the active layer 130.

[0107] The first connection portion 130a contacts one side (or first side FS) of the channel portion 130n and does not overlap the gate 150. The second connection portion 130b is spaced apart from the first connection portion 130a and contacts the other side (or second side SS) of the channel portion 130n and does not overlap the gate 150. The first connection portion 130a and the second connection portion 130b may be referred to as "connection portions".

[0108] The first connection portion 130a and the second connection portion 130b may be formed by selective conduction of the active layer 130. The first connection portion 130a and the second connection portion 130b are also referred to as "conductive portions."

[0109] According to one embodiment of the present disclosure, the process of imparting conductivity to a portion of the oxide semiconductor layer is called conductive. In addition, the method of imparting conductivity to a specific selected area of ​​the oxide semiconductor layer is called selective conductive. Through selective conductive, the portion to which conductivity is imparted is conductive, and the portion to which conductivity is not imparted is not conductive. According to one embodiment of the present disclosure, the conductive portion may have properties similar to those of a metal or a conductor.

[0110] Figure 1A , Figure 1B and Figure 1C The illustrated first connection portion 130 a and the second connection portion 130 b are portions having conductivity through selective conduction.

[0111] According to one embodiment of the present disclosure, selective conductivity can be achieved by doping with a dopant or by plasma treatment.

[0112] For example, the selective conductivity of the active layer 130 may be achieved by selective dopant doping or selective dopant implantation using the gate 150 or photoresist as a mask. The dopant may include, for example, at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0113] When selectively conducting the active layer 130 by dopant doping, the dopant doped region of the active layer 130 is selectively conducted to become the first connection portion 130a or the second connection portion 130b. The region of the active layer 130 not doped with the dopant is not conducted and may become the channel portion 130n.

[0114] Alternatively, the selective conduction of the active layer 130 may be achieved by plasma treatment applied in the process of patterning the gate insulating layer 140. For example, plasma may be used in the process of patterning the gate insulating layer 140, and a portion of the active layer 130 in contact with the plasma is selectively conducted to become the first connection portion 130a or the second connection portion 130b of the active layer 130. A portion of the active layer 130 that is protected by the gate insulating layer 140 and the gate 150 and does not contact the plasma is not conducted and may become the channel portion 130n.

[0115] According to one embodiment of the present disclosure, the first connection portion 130a of the active layer 130 may be a source region, and the second connection portion 130b may be a drain region. However, one embodiment of the present disclosure is not limited thereto, and the first connection portion 130a may be a drain region, and the second connection portion 130b may be a source region.

[0116] Figure 1B and Figure 1C A configuration is shown in which the active layer 130 is composed of one layer, but one embodiment of the present disclosure is not limited thereto. The active layer 130 may have a single layer structure or a multi-layer structure.

[0117] Reference Figure 1A and Figure 1B , wherein the active hole PN where the active layer 130 is not provided is provided in a region whose boundary is defined by the active layer 130. Figure 1A and Figure 1B , the edge of the active hole PN may be defined by the active layer 130. According to one embodiment of the present disclosure, the active hole PN is disposed in a region defined by the active layer 130 in a plan view. According to one embodiment of the present disclosure, the active hole PN may be formed by patterning and removing a portion of the active layer 130.

[0118] Reference Figure 1A and Figure 1B , an active hole PN is formed in a region of the active layer 130 and is surrounded by the active layer 130. The active hole PN may be a region formed by removing a portion of the active layer 130. When referring to the plan view and the cross-sectional view, the active hole PN is a hole formed in the active layer 130 by removing a portion of the active layer 130, and thus according to an embodiment of the present disclosure, the hole formed in the active layer 130 is referred to as an "active hole".

[0119] According to one embodiment of the present disclosure, at least a portion of the active hole PN may overlap with the gate 150. Figure 1A and Figure 1B , the entire active hole PN may overlap with the gate 150 .

[0120] The gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel portion 130n.

[0121] The gate insulating layer 140 has insulating properties. The gate insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0122] Reference Figure 1B and Figure 1C , the gate insulating layer 140 may have a patterned structure. However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layer 140 may not be patterned or may be disposed on the entire surface above the substrate 110 (see Figure 2A and Figure 2B ).

[0123] The gate 150 is disposed on the gate insulating layer 140. The gate 150 overlaps the channel portion 130n of the active layer 130.

[0124] The gate 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate 150 may have a multilayer structure including at least two conductive layers, each having different physical properties. For example, the gate 150 may include at least one of molybdenum (Mo) and titanium (Ti).

[0125] According to one embodiment of the present disclosure, the gate insulating layer 140 may be patterned by etching using the gate 150 as a mask, and in this process, the active layer 130 may be selectively conductive to form the first connection portion 130a and the second connection portion 130b. In detail, according to one embodiment of the present disclosure, a region of the active layer 130 overlapping the gate 150 is not conductive and becomes a channel portion 130n having semiconductor characteristics, and a region of the active layer 130 not overlapping the gate 150 is conductive to become the first connection portion 130a and the second connection portion 130b.

[0126] According to one embodiment of the present disclosure, the thin film transistor 100 includes an inner bridge BR. The inner bridge BR is insulated from the active layer 130 and electrically connects the gate 150 and the light shielding layer 111.

[0127] Reference Figure 1A and Figure 1B , the inner bridge BR overlaps the gate electrode 150 and penetrates the active layer 130 in a direction from the gate electrode 150 to the light shielding layer 111. In this structure, the inner bridge BR does not contact the active layer 130 and is insulated from the active layer 130.

[0128] According to one embodiment of the present disclosure, Figure 1A and Figure 1B As shown, the inner bridge BR may penetrate the gate insulating layer 140 and the buffer layer 120 .

[0129] Reference Figure 1B , the inner bridge BR is disposed in the through hole H formed in the gate insulating layer 140 and the buffer layer 120. The inner bridge BR connects the gate 150 and the light shielding layer 111 to each other through the through hole H formed in the gate insulating layer 140 and the buffer layer 120. The inner bridge BR may contact the gate insulating layer 140 and the buffer layer 120.

[0130] The inner bridge BR is disposed in a region overlapping the gate electrode 150 in a plan view. According to one embodiment of the present disclosure, the inner bridge BR may contact the gate electrode 150 and the light shielding layer 111.

[0131] According to one embodiment of the present disclosure, the inner bridge BR may be integrally formed with the gate 150. The inner bridge BR may be made of the same material as the gate 150, and may be formed together with the gate 150 when the gate 150 is formed.

[0132] In addition, refer to Figure 1A and Figure 1B In a plan view, the inner bridge BR is disposed in the active hole PN. The inner bridge BR penetrates the active hole PN. In a plan view, the inner bridge BR is disposed in the through hole H formed in the active hole PN.

[0133] The light shielding layer 111 overlaps the channel portion 130n of the active layer 130, and the light shielding layer 111 is electrically connected to the gate 150 through the internal bridge BR, whereby the light shielding layer 111 can be used as the gate of the thin film transistor 100. The gate 150 and the light shielding layer 111 can be used as a double gate on both sides of the channel portion 130n. As a result, the thin film transistor 100 according to one embodiment of the present disclosure can have the same effect as having a double gate structure.

[0134] The thin film transistor 100 according to one embodiment of the present disclosure may have excellent current characteristics and excellent driving characteristics due to the effect of the gates disposed on both sides of the channel portion 130 n .

[0135] In addition, since the inner bridge BR is disposed in the active hole PN formed in the active layer 130 and electrically connects the gate 150 and the light shielding layer 111, no additional contact hole is required to connect the gate 150 and the light shielding layer 111. In detail, the gate 150 and the light shielding layer 111 can be connected to each other, thereby exhibiting a double gate effect even without a contact hole formed outside the active layer 130. As a result, the space utilization of the thin film transistor 100 is increased, and the thin film transistor 100 having a double gate structure can be formed in a narrow area.

[0136] The diameter of the inner bridge (BR) and the diameter of the active hole (PN) may vary according to the performance of etching equipment, the performance and resolution of exposure equipment, and the like.

[0137] Since the inner bridge BR in the active hole PN region must be insulated from the active layer 130, the diameter of the active hole PN is designed to be larger than the diameter of the inner bridge BR. In order to stably surround the inner bridge BR in a plan view and stably insulate the inner bridge BR, the diameter of the active hole PN can be designed to be at least 4 μm larger than the diameter of the inner bridge BR. Alternatively, the diameter of the active hole (PN) can be designed to be at least 2 μm larger than the diameter of the inner bridge BR.

[0138] Considering performance and resolution of exposure equipment, the inner bridge BR may have a diameter of 1 μm or more, and may have a diameter of 2 μm or more. Considering the width of the active layer 130 and the size of the channel portion 130 n, the inner bridge BR may have a diameter of 2 μm to 4.5 μm.

[0139] Reference Figure 1B and Figure 1C , an interlayer insulating film 160 may be disposed on the gate electrode 150. The interlayer insulating film 160 may be made of an organic or inorganic insulating material. The interlayer insulating film 160 may have a multi-layer structure including an organic layer and an inorganic layer.

[0140] According to an embodiment of the present disclosure, the thin film transistor 100 may include a source electrode 171 and a drain electrode 172 disposed on the interlayer insulating film 160. The positions of the source electrode 171 and the drain electrode 172 may be changed. However, an embodiment of the present disclosure is not limited thereto, and the first connection portion 130a and the second connection portion 130b may be used as a source electrode and a drain electrode, respectively.

[0141] Reference Figure 1A , Figure 1B and Figure 1C The source electrode 171 and the drain electrode 172 may be connected to the active layer 130 through the contact holes CH1 and CH2, respectively. In detail, the source electrode 171 may contact the first connection portion 130a through the contact hole CH1. The drain electrode 172 may be spaced apart from the source electrode 171 and may contact the second connection portion 130b through the contact hole CH2.

[0142] Figure 2A and Figure 2B Each of them is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present disclosure. Figure 2A Corresponding to the Figure 1A A cross-sectional view taken along line Ia-Ia', and Figure 2B Corresponding to the Figure 1A A cross-sectional view taken along line Ib-Ib'.

[0143] Figure 2A and Figure 2B The thin film transistor 200 includes an unpatterned gate insulating layer 140. Figure 1B and Figure 1C The embodiments shown are different. Figure 2A and 2B The gate insulating layer 140 may not be patterned.

[0144] When the gate insulating layer 140 is not patterned, the active layer 130 may be selectively made conductive by selective ion doping, selective hydrogen implantation, or selective ultraviolet irradiation, so that the first connection portion 130 a and the second connection portion 130 b may be formed.

[0145] Contact holes CH1 and CH2 may be formed in the gate insulating layer 140. In addition, a through hole H may be formed in the gate insulating layer 140 and the buffer layer 120, and a bridge BR may be disposed in the through hole H.

[0146] Figure 3A and Figure 3B Each of them is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present disclosure. Figure 3A Corresponding to the Figure 1A A cross-sectional view taken along line Ia-Ia', and Figure 3B Corresponding to the Figure 1A A cross-sectional view taken along line Ib-Ib'.

[0147] According to another embodiment of the present disclosure, the active layer 130 of the thin film transistor 300 may have a multi-layer structure. Figure 3A and Figure 3B , the active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131 .

[0148] The first oxide semiconductor layer 131 may support the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 may be referred to as a "supporting layer". The channel may be mainly formed in the second oxide semiconductor layer 132. Therefore, the second oxide semiconductor layer 132 may be referred to as a "channel layer". However, the embodiments of the present disclosure are not limited thereto, and the channel may also be formed in the first oxide semiconductor layer 131. In addition, the channel may be mainly formed in the first oxide semiconductor layer 131.

[0149] The active layer 130 is composed of a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 , and is also referred to as having a double-layer structure.

[0150] Although not shown, the active layer 130 may have a three-layer or more structure. For example, the active layer 130 may include a first oxide semiconductor layer 131, a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131, and a third oxide semiconductor layer on the second oxide semiconductor layer 132. However, another embodiment of the present disclosure is not limited thereto, and the active layer 130 may further include another semiconductor layer.

[0151] Figure 4A is a plan view of a thin film transistor 400 according to another embodiment of the present disclosure, Figure 4B is along Figure 4A IVa-IVa' cross-sectional view, Figure 4C is along Figure 4A A cross-sectional view taken along line IVb-IVb'.

[0152] Figure 4A , Figure 4B and Figure 4C The thin film transistor 400 may include a first conductive pattern 175 on the first connection portion 130 a and a second conductive pattern 176 on the second connection portion 130 b .

[0153] According to another embodiment of the present disclosure, the first conductive pattern 175 and the second conductive pattern 176 may have conductivity. The first conductive pattern 175 may be disposed in contact with the first connection portion 130a, and the second conductive pattern 176 may be disposed in contact with the second connection portion 130b.

[0154] For example, the first conductive pattern 175 and the second conductive pattern 176 may include a metal. In more detail, the first conductive pattern 175 and the second conductive pattern 176 are respectively formed of aluminum (Al), titanium (Ti), molybdenum (Mo), calcium (Ca), barium (Ba), copper (Cu), etc. The first conductive pattern 175 and the second conductive pattern 176 may have a reducing property.

[0155] In addition, the first conductive pattern 175 and the second conductive pattern 176 may include a transparent conductive oxide (TCO). For example, each of the first conductive pattern 175 and the second conductive pattern 176 may include at least one of an ITO (InSnO)-based transparent conductive oxide (TCO), an IGZO (InGaZnO)-based transparent conductive oxide (TCO), an IGO (InGaO)-based transparent conductive oxide (TCO), an IGZTO (InGaZnSnO)-based transparent conductive oxide (TCO), an IZO (InZnO)-based transparent conductive oxide (TCO), and an ITZO (InSnZnO)-based transparent conductive oxide (TCO).

[0156] Reference Figure 4A , Figure 4B and Figure 4C , each of the first conductive pattern 175 and the second conductive pattern 176 does not overlap with the gate 150. For example, the first conductive pattern 175 and the second conductive pattern 176 may be disposed to be spaced apart from the gate 150 in a plan view.

[0157] The first connection portion 130 a may include a first portion 130 a 1 overlapping the first conductive pattern 175 and a second portion 130 a 2 not overlapping the first conductive pattern 175 .

[0158] The first portion 130a1 of the first connection portion 130a overlapping the first conductive pattern 175 is protected by the first conductive pattern 175 and may not be conductive. In detail, in the process of selectively conductively converting the active layer 130, the first conductive pattern 175 acts as a mask for the first portion 130a1 of the first connection portion 130a, and thus the first portion 130a1 may maintain semiconductor characteristics without being conductive. The first portion 130a1 of the first connection portion 130a may contact the first conductive pattern 175.

[0159] The second portion 130a2 of the first connection portion 130a not overlapping the first conductive pattern 175 may be conductive. In detail, in the process of selectively conductive ...

[0160] The second connection portion 130 b may include a first portion 130 b 1 overlapping the second conductive pattern 176 and a second portion 130 b 2 not overlapping the second conductive pattern 176 .

[0161] The first portion 130b1 of the second connection portion 130b overlapping the second conductive pattern 176 is protected by the second conductive pattern 176 and may not be conductive. In detail, in the process of selectively conductively converting the active layer 130, the second conductive pattern 176 acts as a mask for the first portion 130b1 of the second connection portion 130b, and thus the first portion 130b1 may maintain semiconductor characteristics without being conductive. The first portion 130b1 of the second connection portion 130b may contact the second conductive pattern 176.

[0162] The second portion 130b2 of the second connection portion 130b not overlapping the second conductive pattern 176 may be conductive. In detail, in the process of selectively conductive ...

[0163] When the first portion 130a1 of the first connection portion 130a and the first portion 130b1 of the second connection portion 130b contact the reducing metal, the first portion 130a1 of the first connection portion 130a and the first portion 130b1 of the second connection portion 130b may be reduced, respectively, so that the conductivity of the first portion 130a1 of the first connection portion 130a and the first portion 130b1 of the second connection portion 130b may be improved.

[0164] When the first portion 130a1 of the first connection portion 130a and the first portion 130b1 of the second connection portion 130b contact the first conductive pattern 175 and the second conductive pattern 176 including the metal layer, respectively, the contact portion can be reduced and oxygen vacancies can appear in the contact portion. Therefore, the conductivity can be improved at the first portions 130a1 and 130b1 to produce the same effect as the conductivity. As a result, the conductivity of the first portion 130a1 of the first connection portion 130a and the first portion 130b1 of the second connection portion 130b can be improved.

[0165] According to another embodiment of the present disclosure, the source electrode 171 and the drain electrode 172 may be disposed on the same layer as the gate electrode 150. In detail, Figure 4B and Figure 4C As shown, the source 171 and the drain 172 may be disposed on the gate insulating layer 140 , similar to disposing the gate 150 on the gate insulating layer 140 .

[0166] According to another embodiment of the present disclosure, the source electrode 171 may contact the first conductive pattern 175 , and the drain electrode 172 may contact the second conductive pattern 176 .

[0167] Figure 5A and Figure 5BEach of them is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present disclosure. Figure 5A Corresponding to the Figure 4A IVa-IVa' cross-sectional view, Figure 5B Corresponding to the Figure 4A A cross-sectional view taken along line IVb-IVb'.

[0168] Figure 5A and Figure 5B The thin film transistor 500 includes an unpatterned gate insulating layer 140. When the gate insulating layer 140 is not patterned, the active layer 130 may be selectively conductive by selective ion doping, selective hydrogen implantation, or selective ultraviolet irradiation, so that the first connection portion 130a and the second connection portion 130b may be formed. In addition, contact holes CH1 and CH2 may be formed in the gate insulating layer 140.

[0169] Figure 6 is a plan view of a thin film transistor 600 according to another embodiment of the present disclosure. Figure 6 , the active hole PN may include two or more regions spaced apart from each other.

[0170] According to another embodiment of the present disclosure, the active hole PN may include a first active hole PN1 and a second active hole PN2 spaced apart from each other. At least a portion of the first active hole PN1 and at least a portion of the second active hole PN2 may overlap the gate 150 .

[0171] Reference Figure 6 , the inner bridge BR may include two or more bridges. According to another embodiment of the present disclosure, the inner bridge BR includes a first inner bridge BR1 disposed in the first active hole PN1 and a second inner bridge BR2 disposed in the second active hole PN2. The first inner bridge BR1 and the second inner bridge BR2 each overlap the gate 150. The first inner bridge BR1 and the second inner bridge BR2 may each be disposed in a region overlapping the gate 150.

[0172] In a plan view, the first inner bridge BR1 is disposed in the first active hole PN1. The first inner bridge BR1 penetrates the first active hole PN1.

[0173] In a plan view, the second inner bridge BR2 is disposed in the second active hole PN2. The second inner bridge BR2 penetrates the second active hole PN2.

[0174] Reference Figure 6, the first active holes PN1 and the second active holes PN2 are aligned to be spaced apart from each other in a direction DR2 perpendicular to the direction DR1 connecting the first connection portion 130a and the second connection portion 130b. However, another embodiment of the present disclosure is not limited thereto, and the first active holes PN1 and the second active holes PN2 may be aligned to be spaced apart from each other in the direction DR1 connecting the first connection portion 130a and the second connection portion 130b.

[0175] Although not shown in the drawings, the first active hole PN1 and the second active hole PN2 may be aligned to be spaced apart from each other in a direction inclined at a predetermined angle to a direction DR1 connecting the first connection portion 130 a and the second connection portion 130 b .

[0176] The thin film transistor 600 may have three or more active holes PN and three or more internal bridges BR for stable electrical connection between the gate 150 and the light shielding layer 111. For example, the thin film transistor 600 may have 3 to 10 active holes PN and 3 to 10 internal bridges BR.

[0177] The sizes of the inner bridge BR and the active hole PN may vary according to the performance and resolution of the exposure equipment. If the size of the inner bridge BR is reduced, the number of the inner bridge BR may be increased to ensure a stable electrical connection between the gate 150 and the light shielding layer 111.

[0178] Fig. 7A is a plan view of a thin film transistor 700 according to another embodiment of the present disclosure, Figure 7B is along Fig. 7A VIIa-VIIa' is a cross-sectional view taken from Figure 7C is along Fig. 7A A cross-sectional view taken along VIIb-VIIb'.

[0179] Reference Fig. 7A and Figure 7B , active holes PN1, PN2, PN3, and PN4 are formed, and a portion of each of the active holes PN1, PN2, PN3, or PN4 may protrude from the gate 150 in a direction DR1 connecting the first connection portion 130a and the second connection portion 130b in a plan view.

[0180] In detail, the first and third active holes PN1 and PN3 protrude from the gate 150 in a plan view and protrude toward the first connection portion 130a, respectively. The second and fourth active holes PN2 and PN4 protrude from the gate 150 in a plan view and protrude toward the second connection portion 130b, respectively.

[0181] like Fig. 7A and Figure 7BAs shown, in a plan view, the active holes PN1 , PN2 , PN3 , and PN4 may protrude on both sides of the gate 150 .

[0182] Reference Fig. 7A and Figure 7B , the first active hole PN1, the second active hole PN2, the third active hole PN3, and the fourth active hole PN4 are spaced apart from each other.

[0183] The first active hole PN1 and the second active hole PN2 are disposed to be spaced apart from each other along the direction DR1 connecting the first connection portion 130a and the second connection portion 130b. In addition, the first active hole (PN1) and the third active hole (PN3) are disposed to be spaced apart from each other along the direction DR2 perpendicular to the direction DR1 connecting the first connection portion 130a and the second connection portion 130b.

[0184] The third active hole PN3 and the fourth active hole PN4 are disposed to be spaced apart from each other along the direction DR1 connecting the first connection portion 130a and the second connection portion 130b. In addition, the second active hole PN2 and the fourth active hole PN4 are disposed to be spaced apart from each other along the direction DR2 perpendicular to the direction DR1 connecting the first connection portion 130a and the second connection portion 130b.

[0185] At least a portion of the first active hole PN1 may overlap the gate 150. Fig. 7A , a portion of the first active hole PN1 does not overlap with the gate 150 .

[0186] In plan view, the first inner bridge BR1 is disposed in the first active hole PN1. In detail, in plan view, the first inner bridge BR1 is disposed in a region of the first active hole PN1 overlapping the gate 150. The first inner bridge BR1 penetrates the first active hole PN1 in a region overlapping the gate 150.

[0187] The first inner bridge BR1 is disposed in a through hole H1 penetrating the gate insulating layer 140 and the buffer layer 120 , and electrically connects the gate 150 and the light shielding layer 111 .

[0188] At least a portion of the second active hole PN2 may overlap the gate 150. Fig. 7A , a portion of the second active hole PN2 does not overlap with the gate 150 .

[0189] In plan view, the second inner bridge BR2 is disposed in the second active hole PN2. In detail, in plan view, the second inner bridge BR2 is disposed in a region of the second active hole PN2 overlapping the gate 150. The second inner bridge BR2 penetrates the second active hole PN2 in a region overlapping the gate 150.

[0190] The second inner bridge BR2 is disposed in the through hole H2 penetrating the gate insulating layer 140 and the buffer layer 120 , and electrically connects the gate 150 and the light shielding layer 111 .

[0191] At least a portion of the third active hole PN3 may overlap the gate 150. Fig. 7A , a portion of the third active hole PN3 does not overlap with the gate 150 .

[0192] The third inner bridge BR3 is disposed in the third active hole PN3 in a plan view. In detail, in a plan view, the third inner bridge BR3 is disposed in a region of the third active hole PN3 overlapping the gate 150. The third inner bridge BR3 penetrates the third active hole PN3 in a region overlapping the gate 150.

[0193] The third inner bridge BR3 may be disposed in a through hole penetrating the gate insulating layer 140 and the buffer layer 120 , and electrically connect the gate 150 and the light shielding layer 111 .

[0194] At least a portion of the fourth active hole PN4 may overlap the gate 150. Fig. 7A , a portion of the fourth active hole PN4 does not overlap with the gate 150 .

[0195] In plan view, the fourth inner bridge BR4 is disposed in the fourth active hole PN4. In detail, in plan view, the fourth inner bridge BR4 is disposed in a region of the fourth active hole PN4 overlapping the gate 150. The fourth inner bridge BR4 penetrates the fourth active hole PN4 in a region overlapping the gate 150.

[0196] The fourth inner bridge BR4 may be disposed in a through hole penetrating the gate insulating layer 140 and the buffer layer 120 , and electrically connect the gate 150 and the light shielding layer 111 .

[0197] The first inner bridge BR1 , the second inner bridge BR2 , the third inner bridge BR3 , and the fourth inner bridge BR4 are disposed to be spaced apart from each other and penetrate the gate insulating layer 140 and the buffer layer 120 , respectively.

[0198] According to another embodiment of the present disclosure, a gate voltage is applied to the light shielding layer 111 through a plurality of inner bridges BR1, BR2, BR3, and BR4. Therefore, the thin film transistor 700 may have a dual gate structure. In addition, since the gate voltage is applied to the plurality of inner bridges BR1, BR2, BR3, and BR4, the plurality of inner bridges BR1, BR2, BR3, and BR4 may also apply an electric field to the channel portion 130n. As a result, the current characteristics of the thin film transistor 700 may be improved in the channel portion 130n of the thin film transistor 700.

[0199] In a thin film transistor 700 according to another embodiment of the present disclosure, since an electric field is applied to the channel portion 130n through the gate 150, the light shielding layer 111 and the plurality of internal bridges BR1, BR2, BR3 and BR4, the current characteristics of the channel portion 130n are improved, so that the thin film transistor 700 can have excellent driving characteristics.

[0200] According to one embodiment of the present disclosure, the distance between the two ends of the channel portion 130n along the direction DR1 connecting the first connection portion 130a and the second connection portion 130b is defined as the length of the channel portion. The distance between the two ends of the channel portion 130n along the direction DR2 perpendicular to the direction DR1 connecting the first connection portion 130a and the second connection portion 130b is defined as the width of the channel portion.

[0201] When the channel portion 130n has a large width, the interface between the channel portion 130n and the conductive portion is large. Therefore, when the conductive portion 130a and the second connecting portion 130b are formed, the diffusion of the conductive portion toward the channel portion 130n may be significant. If the diffusion of the conductive portion toward the channel portion 130n is large, the threshold voltage (Vth) of the thin film transistor 700 may change in the negative (-) direction, and the driving stability of the thin film transistor 700 may be reduced.

[0202] On the other hand, when the channel portion 130n has a small width, the interface between the channel portion 130n and the conductive portion is small. Therefore, when the conductive portion 130a and the second connection portion 130b are formed, diffusion of the conductive portion toward the channel portion 130n can be suppressed.

[0203] According to another embodiment of the present disclosure, Fig. 7A As shown, the first active hole PN1 and the third active hole PN3 are formed in the boundary between the channel portion 130n and the first connection portion 130a. As a result, the interface between the first connection portion 130a and the channel portion 130n is reduced, and the diffusion of the conductive part from the first connection portion 130a as the conductive part to the channel portion 130n can be suppressed.

[0204] In addition, if Fig. 7A As shown, the second active hole PN2 and the fourth active hole PN4 are formed in the boundary between the channel portion 130n and the second connection portion 130b. As a result, the interface between the second connection portion 130b and the channel portion 130n is reduced, and the diffusion of the conductive part from the second connection portion 130b as the conductive part to the channel portion 130n can be suppressed.

[0205] As a result, fluctuation or change in the threshold voltage (Vth) of the thin film transistor 700 can be suppressed, and driving stability of the thin film transistor 700 can be improved.

[0206] Furthermore, when the total width of the channel portion 130 n is small, the total amount of carriers passing through the channel portion 130 n of the thin film transistor 700 decreases, and the on-current characteristics of the thin film transistor 700 may deteriorate.

[0207] According to another embodiment of the present disclosure, the plurality of active holes PN1, PN2, PN3, and PN4 have the effect of dividing one channel portion 130n into a plurality of channels having a smaller channel width. As a result, even if the channel portion 130n has a large width, diffusion or penetration of the conductive ions into the channel portion 130n can be suppressed, and the total width of the channel portion 130n can be kept large, so that the total amount of carriers passing through 130n is not substantially reduced. As a result, according to another embodiment of the present disclosure, the thin film transistor 700 can have excellent on-current characteristics while suppressing diffusion or penetration of the conductive ions into the channel portion 130n.

[0208] Figure 8 is a cross-sectional view of a thin film transistor 800 according to another embodiment of the present disclosure.

[0209] Figure 8 Corresponding to the Fig. 7A A cross-sectional view taken along line VIIa-VIIa' in FIG. Figure 8 The thin film transistor 800 includes an unpatterned gate insulating layer 140. Figure 7B and 7C Unlike the embodiment shown in , the gate insulating layer 140 may not be patterned. Figure 8 as shown in .

[0210] Fig. 9 is a cross-sectional view of a thin film transistor 900 according to another embodiment of the present disclosure. Fig. 9 Corresponding to the Fig. 7A A cross-sectional view taken along line VIIa-VIIa' in FIG.

[0211] According to another embodiment of the present disclosure, the active layer 130 of the thin film transistor 900 may have a multi-layer structure. Fig. 9 , the active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 on the first oxide semiconductor layer 131. Although not shown in the drawings, the active layer 130 may have a structure of three or more layers.

[0212] Fig. 10A is a plan view of a thin film transistor 1000 according to another embodiment of the present disclosure, Fig. 10B is along Fig. 10A The cross-sectional view taken along Xa-Xa' is Fig. 10C is along Fig. 10A Cross-sectional view taken along line Xb-Xb'.

[0213] Reference Fig. 10A , Fig. 10B and Fig. 10C , a thin film transistor 1000 according to another embodiment of the present disclosure includes a first conductive pattern 175 on a first connection portion 130 a and a second conductive pattern 176 on a second connection portion 130 b .

[0214] According to another embodiment of the present disclosure, the first conductive pattern 175 and the second conductive pattern 176 may have conductivity. The first conductive pattern 175 may be disposed to contact the first connection portion 130a, and the second conductive pattern 176 may be disposed to contact the second connection portion 130b. The conductive patterns 175 and 176 are not disposed in the active holes PN1, PN2, PN3, and PN4 where the active layer 130 is not disposed.

[0215] Since the first conductive pattern 175 and the second conductive pattern 176 have been described, detailed descriptions of the first conductive pattern 175 and the second conductive pattern 176 will be omitted hereinafter to avoid redundancy.

[0216] The first connection portion 130 a may include a first portion 130 a 1 overlapping the first conductive pattern 175 and a second portion 130 a 2 not overlapping the first conductive pattern 175 .

[0217] A first portion 130a1 of the first connection portion 130a overlapping the first conductive pattern 175 is protected by the first conductive pattern 175 and may not be conductive. A second portion 130a2 of the first connection portion 130a not overlapping the first conductive pattern 175 may be conductive.

[0218] The second connection portion 130 b may include a first portion 130 b 1 overlapping the second conductive pattern 176 and a second portion 130 b 2 not overlapping the second conductive pattern 176 .

[0219] A first portion 130b1 of the second connection portion 130b overlapping the second conductive pattern 176 is protected by the second conductive pattern 176 and may not be conductive. A second portion 130b2 of the second connection portion 130b not overlapping the second conductive pattern 176 may be conductive.

[0220] According to another embodiment of the present disclosure, the source electrode 171 and the drain electrode 172 may be disposed on the same layer as the gate electrode 150. Fig. 10B and Fig. 10C , the source electrode 171 and the drain electrode 172 may be disposed on the gate insulating layer 140 .

[0221] Fig.11 is a cross-sectional view of a thin film transistor 1100 according to another embodiment of the present disclosure.

[0222] Fig.11 Corresponds to Fig. 10A A cross-sectional view taken along Xa-Xa'. Fig.11 The thin film transistor 1100 includes an unpatterned gate insulating layer 140 .

[0223] Fig. 12A is a plan view of a thin film transistor 1200 according to another embodiment of the present disclosure, Fig. 12B is along Fig. 12A A cross-sectional view taken along line XIIa-XIIa', Fig. 12C is along Fig. 12A A cross-sectional view taken along line XIIb-XIIb' of Fig.12D is along Fig. 12A A cross-sectional view taken along line XIIc-XIIc'.

[0224] The thin film transistor 1200 according to another embodiment of the present disclosure includes a first active hole PN1 and a second active hole PN2 spaced apart from each other. In a plan view, the first active hole PN1 and the second active hole PN2 may protrude at both sides of the gate 150, respectively.

[0225] Reference Fig. 12A , the length of the first active hole PN1 and the length of the second active hole PN2 in the direction DR1 connecting the first connection portion 130a and the second connection portion 130b are longer than the length of the gate 150 in the direction DR1 connecting the first connection portion 130a and the second connection portion 130b.

[0226] Reference Fig. 12A , the first inner bridge BR1 is disposed in the first active hole PN1 , and the second inner bridge BR2 is disposed in the second active hole PN2 . The first inner bridge BR1 and the second inner bridge BR2 may each be disposed in a region overlapping the gate 150 .

[0227] The first inner bridge BR1 is disposed in the through hole H1 penetrating the gate insulating layer 140 and the buffer layer 120, and electrically connects the gate 150 and the light shielding layer 111. In addition, the second inner bridge BR2 is disposed in the through hole H2 penetrating the gate insulating layer 140 and the buffer layer 120, and electrically connects the gate 150 and the light shielding layer 111.

[0228] Reference Fig. 12C, the region of the channel portion 130n disposed between the first inner bridge BR1 and the second inner bridge (BR2) has a structure surrounded by the gate 150, the light shielding layer 111, the first inner bridge BR1, and the second inner bridge BR2. As a result, the electrical characteristics of the channel portion 130n can be improved in the region between the first inner bridge BR1 and the second inner bridge BR2. Therefore, the current characteristics of the entire channel portion 130n are improved, and the thin film transistor 1200 can have excellent driving or operating characteristics.

[0229] Fig.13A is a plan view of a thin film transistor 1300 according to another embodiment of the present disclosure, and Fig. 13B is along Fig.13A A cross-sectional view taken along line XIII-XIII'.

[0230] and Fig. 12A Compared to the thin film transistor 1200 shown, Fig.13A The illustrated thin film transistor 1300 further includes external bridges BR21 and BR22. In a plan view, the external bridges BR21 and BR22 are disposed outside a region defined by the active layer 130.

[0231] Reference Fig.13A , a thin film transistor 1300 according to another embodiment of the present disclosure includes external bridges BR21, BR22 that do not penetrate the active layer 130 and are disposed outside a region defined by the active layer 130. The external bridges BR21, BR22 overlap the gate 150 and electrically connect the gate 150 and the light shielding layer 111.

[0232] In detail, the external bridge may include a first external bridge BR21 and a second external bridge BR22. The first external bridge BR21 is disposed in a through hole H3 penetrating the gate insulating layer 140 and the buffer layer 120, and electrically connects the gate 150 and the light shielding layer 111. The second external bridge BR22 is disposed in a through hole H4 penetrating the gate insulating layer 140 and the buffer layer 120, and electrically connects the gate 150 and the light shielding layer 111.

[0233] The external bridges BR21 and BR22 are insulated from the active layer 130 .

[0234] Reference Fig. 13B , the four sides of the channel portion 130n are surrounded by the gate 150, the light shielding layer 111, the first outer bridge BR21, the first inner bridge BR1, the second inner bridge BR2, and the second outer bridge BR22. As a result, when the gate voltage is applied, the electric field effect applied to the channel portion 130n increases, and the electrical characteristics of the channel portion 130n can be improved. Therefore, the current characteristics of the entire channel portion 130n are improved, and the thin film transistor 1300 can have excellent driving or operating characteristics.

[0235] Fig.14A , Fig. 14B , Fig. 14C and 14D 1401 , 1402 , 1403 , and 1404 are plan views respectively of thin film transistors according to another embodiment of the present disclosure.

[0236] Fig.14A The thin film transistor 1401 shown includes a first external bridge BR21, a second external bridge BR22, a first internal bridge BR1, a second internal bridge BR2, a third internal bridge BR3 and a fourth internal bridge BR4.

[0237] Fig. 14B The illustrated thin film transistor 1402 has a structure in which the width of the channel portion 130n is smaller than the width of the first connection portion 130a and the width of the second connection portion 130b.

[0238] Reference Fig. 14B , a portion of the channel portion 130n at an edge in the width direction of the channel portion 130n is removed along the length direction of the channel portion 130n, which is a direction connecting the first connection portion 130a and the second connection portion 130b, so that the width of the channel portion 130n is reduced. The first outer bridge BR21 and the second outer bridge BR22 may be provided in the region where the channel portion 130n has been removed.

[0239] Fig. 14C The thin film transistor 1403 shown has a structure in which the first inner bridge BR1 and the second inner bridge BR2 are disposed offset on one side of the channel portion 130n in the width direction. Fig. 14C The first inner bridge BR1 and the second inner bridge BR2 are offset and disposed on one side of the channel portion 130n.

[0240] when Fig. 14C When the thin film transistor 1403 shown is turned on, in the region where the first inner bridge BR1 and the second inner bridge BR2 are provided, the current increase rate of the channel portion 130n is relatively fast, but due to the narrow width, the charge amount is relatively small. On the other hand, in the region where the first inner bridge BR1 and the second inner bridge BR2 are not provided, the current increase rate of the channel portion 130n is relatively slow, but due to the wide width, the charge amount is large. Due to the deviation of the current increase rate and the charge amount in the channel portion 130n, the slope of the current graph of the thin film transistor 1403 may increase in the threshold voltage portion. The thin film transistor 1403 having these characteristics can have a large s factor (threshold swing).

[0241] Fig.14D The illustrated thin film transistor 1404 includes a first internal bridge BR1 disposed diagonally along the width direction of the channel portion 130n.

[0242] In the above, various configurations and shapes of the inner bridges BR1, BR2, BR3 and BR4 and the outer bridges BR21 and BR22 have been described as examples with reference to the accompanying drawings, but the embodiments of the present disclosure are not limited thereto. The inner bridges BR1, BR2, BR3 and BR4 and the outer bridges BR21 and BR22 may be configured in various structures different from those shown in the accompanying drawings.

[0243] Fig.15 is a plan view of a thin film transistor 1500 according to another embodiment of the present disclosure. Fig.15 The thin film transistor 1500 shown has Fig. 12A The structure of the thin film transistor 1200 is similar to that shown in FIG. Fig.15 The thin film transistor 1500 shown is Fig. 12A The illustrated thin film transistor 1200 includes a greater number of active holes PN and internal bridges BR.

[0244] Fig.15 The thin film transistor 1500 including four active holes PN and four internal bridges BR is shown. However, another embodiment of the present disclosure is not limited thereto, and the thin film transistor may include a greater number of active holes PN and internal bridges BR.

[0245] In the following, reference will be made to FIG. 16A to FIG. 16F A method of manufacturing a thin film transistor according to another embodiment of the present disclosure is described.

[0246] FIG. 16A to FIG. 16F is a schematic diagram of a method of manufacturing a thin film transistor 1500 according to another embodiment of the present disclosure.

[0247] FIG. 16A to FIG. 16F shows the direction corresponding to Fig.15 Cross-sectional views taken along lines XVa-XVa' and XVb-XVb'.

[0248] According to another embodiment of the present disclosure, a method for manufacturing a thin film transistor 1500 includes forming a light shielding layer 111 on a substrate 110, forming a buffer layer 120 on the light shielding layer 111, forming an active layer 130 on the buffer layer 120, forming a gate insulating layer 140 on the active layer 130, and forming a gate 150 on the gate insulating layer 140.

[0249] First, refer to Fig.16A , a light shielding layer 111 is formed on the substrate 110, and a buffer layer 120 is formed on the light shielding layer 111. In addition, an active material layer 130m is formed on the buffer layer 120. Fig.16A , a conductive material layer 175m may be formed on the active material layer 130m.

[0250] Next, refer to Fig. 16B, the active material layer 130 m is patterned to form the active layer 130 . At this time, the conductive material layer 175 m is patterned to form the first conductive pattern 175 and the second conductive pattern 176 .

[0251] The active material layer 130m and the conductive material layer 175m may be patterned by the same process, for example, by selective patterning using a half-tone mask, thereby forming the active layer 130, the first conductive pattern 175, and the second conductive pattern 176.

[0252] The first conductive pattern 175 and the second conductive pattern 176 are disposed on the active layer 130. The entire conductive material layer 175m on the channel portion 130n of the active layer 130 may be removed. As a result, the first conductive pattern 175 or the second conductive pattern 176 may not be disposed on the channel portion 130n of the active layer 130.

[0253] In addition, in the step of forming the active layer 130, a portion of the active layer 130 is selectively removed to form an active hole PN. In more detail, during the formation of the active layer 130, a portion of the active material layer 130m disposed in a region whose edge is defined by the active layer 130 may be removed, so that the active hole PN may be formed.

[0254] Reference Fig.15 and Fig. 16B , the active hole PN is disposed in a region whose edge is defined by the active layer 130 .

[0255] Next, refer to Fig. 16C , a gate insulating layer 140 is formed on the active layer 130. The gate insulating layer 140 has an insulating property. The gate insulating layer 140 may be made of a dielectric material.

[0256] In the step of forming the gate insulating layer 140, a through hole H penetrating the gate insulating layer 140 and the buffer layer 120 is formed. The through hole H penetrates the active hole PN formed in a region whose edge is defined by the active layer 130. An upper portion of the light shielding layer 111 is partially exposed by the through hole H. In more detail, a portion of the light shielding layer 111 may be exposed from the buffer layer 120 and the gate insulating layer 140 through the through hole H.

[0257] In addition, in the step of forming the gate insulating layer 140, contact holes CH1 and CH2 may be formed in the gate insulating layer 140. The upper portion of the active layer 130 is partially exposed by the contact holes CH1 and CH2. In more detail, a portion of the first conductive pattern 175 disposed on the active layer 130 is exposed from the gate insulating layer 140 through the first contact hole CH1, and a portion of the second conductive pattern 176 disposed on the active layer 130 may be exposed from the gate insulating layer 140 through the second contact hole CH2.

[0258] Reference Fig.16D , a gate 150 is formed on the gate insulating layer 140 .

[0259] When forming the gate 150 , the inner bridge BR may be formed. According to another embodiment of the present disclosure, forming the gate 150 may include forming the inner bridge BR.

[0260] The inner bridge BR is disposed in the through hole H. The inner bridge BR may be formed by disposing a gate electrode 150 forming material in the through hole H. The inner bridge BR contacts the gate electrode 150 and the light shielding layer 111 .

[0261] The inner bridge BR may be made of the same material as the gate 150 , and may be manufactured through the same process as the gate 150 .

[0262] Reference Fig.16D , the source electrode 171 and the drain electrode 172 may also be formed on the gate insulating layer 140. According to another embodiment of the present disclosure, the source electrode 171 and the drain electrode 172 may be disposed on the same layer as the gate electrode 150.

[0263] According to another embodiment of the present disclosure, the source electrode 171 and the drain electrode 172 may be made of the same material as the gate electrode 150 , and may be made through the same process as the gate electrode 150 .

[0264] Reference Fig.16E , selectively etching the gate insulating layer 140. For example, the gate insulating layer 140 may be selectively etched by an etching process using the gate 150, the source 171, and the drain 172 as a mask. Portions of the gate insulating layer 140 that are not protected by the gate 150, the source 171, and the drain 172 are removed by etching.

[0265] In the process of selectively etching the gate insulating layer 140 , the active layer 130 may be selectively conductive.

[0266] During the selective etching process of the gate insulating layer 140 , a region of the active layer 130 overlapping the gate 150 , the first conductive pattern 175 , and the second conductive pattern 176 is protected by the gate 150 , the first conductive pattern 175 , and the second conductive pattern 176 and is not conductively made.

[0267] A region of the active layer 130 not protected by the gate 150, the first conductive pattern 175, and the second conductive pattern 176 may be conductive during the selective etching process of the gate insulating layer 140. As a result, the second portion 130a2 of the first connection portion 130a and the second portion 130b2 of the second connection portion 130b may be conductive.

[0268] Next, refer to Fig.16F , an interlayer insulating film 180 is disposed on the gate electrode 150, the source electrode 171, and the drain electrode 172. As a result, a thin film transistor 1500 according to another embodiment of the present disclosure may be completed.

[0269] Hereinafter, a display device according to another embodiment of the present disclosure will be described. The display device according to another embodiment of the present disclosure includes a substrate 110 and thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, 1500 disposed on the substrate 110.

[0270] Fig.17 is a schematic diagram of a display device 1600 according to another embodiment of the present disclosure.

[0271] like Fig.17 As shown, a display device 1600 according to another embodiment of the present disclosure includes a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0272] The gate lines GL and the data lines DL are disposed on the display panel 310 , and the pixels P are disposed in the crossing regions of the gate lines GL and the data lines DL. An image is displayed in the display panel 310 by driving the pixels P.

[0273] The controller 340 controls the gate driver 320 and the data driver 330 .

[0274] The controller 340 uses a signal provided from an external system (not shown) to generate a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. In addition, the controller 340 samples the input image data input from the external system, realigns it, and provides the realigned digital image data (RGB) to the data driver 330.

[0275] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst and a gate clock GCLK. In addition, the gate control signal GCS may include a control signal for controlling a shift register.

[0276] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0277] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0278] According to one embodiment of the present disclosure, the gate driver 320 may be disposed on the substrate 110 . The gate driver 320 may include a shift register 350 .

[0279] The shift register 350 sequentially supplies a gate pulse to the gate line GL within one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching element (thin film transistor) provided in the pixel P.

[0280] In addition, the shift register 350 provides a gate-off signal capable of turning off the switching element to the gate line GL during the remaining period of one frame in which the gate pulse is not supplied. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal (SS or Scan).

[0281] According to one embodiment of the present disclosure, the gate driver 320 may be mounted on the display panel 310. As such, a structure in which the gate driver 320 is directly mounted on the display panel 310 is referred to as a gate-in-panel (GIP) structure.

[0282] The gate driver 320 may include a plurality of thin film transistors. The plurality of thin film transistors included in the gate driver 320 may be disposed in the shift register 350 .

[0283] According to another embodiment of the present disclosure, the gate driver 320 may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, 1500). The thin film transistor provided in the gate driver 320 may have the same structure as at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, 1500.

[0284] Fig.18 is a schematic diagram of the shift register 350 . Fig.19 yes Fig.18 A circuit diagram of an embodiment of a shift register 350 is provided in stage 351 .

[0285] Reference Fig.18 , the shift register 350 may include a number g of stages 351 (ST1 to STg).

[0286] The shift register 350 transmits one scan signal SS to the pixel P connected to one gate line GL through one gate line GL. Each stage 351 may be connected to one gate line GL. When n gate lines (GL) are formed in the display panel 310, the shift register 350 may include g stages 351 (ST1 to STg) and may generate g scan signals (SS1 to SSg).

[0287] In general, each stage 351 outputs the gate pulse GP once per frame, and the gate pulse GP is sequentially output from each stage 351 .

[0288] like Fig.19 As shown, each stage 351 that sequentially outputs a strobe pulse GP includes a pull-up transistor Pu, a pull-down transistor Pd, a start transistor Tst, a reset transistor Trs, and an inverter I. The above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, 1500 can be applied to the pull-up transistor Pu, the pull-down transistor Pd, the start transistor Tst, and the reset transistor Trs, respectively.

[0289] The pull-up transistor Pu is turned on or off according to the logic state of the Q node, and when turned on, it receives the clock signal CLK and outputs a gate pulse GP [Vout (SS)]. The pull-down transistor Pd is connected between the pull-up transistor Pu and the cut-off voltage VSS1, and is cut off when the pull-up transistor Pu is turned on, and is turned on when the pull-up transistor Pu is turned off, and outputs a gate cut-off signal Goff.

[0290] Thus, the output Vout of the stage 351 includes the gate pulse GP and the gate-off signal Goff. The gate pulse GP may have a high-level voltage, and the gate-off signal Goff may have a low-level voltage.

[0291] In response to a previous output PRE from a previous stage, the start transistor Tst charges the Q node with a high level voltage VD. When the stage 351 is the first stage ST1, the start signal Vst is provided instead of the previous output PRE.

[0292] In response to the rear output NXT from the next stage, the reset transistor Trs discharges the Q node to the low potential voltage VSS as a reset voltage. When the stage 351 is the last stage STg, the reset pulse Rest is provided instead of the rear output NXT.

[0293] When the Q node is high, the control signal input to the gate terminal of the reset transistor Trs is normally maintained in a low state.

[0294] When a high level signal is input to the Q node, the pull-up transistor Pu is turned on and the gate pulse GP is output. At this time, the reset transistor Trs must be turned off so that the low potential voltage VSS is not supplied to the reset transistor Trs.

[0295] When the strobe pulse GP is output, a high-level control signal is input to the gate terminal of the reset transistor Trs, the reset transistor Trs is turned on, and the pull-up transistor Pu is turned off. As a result, the strobe pulse GP is not output through the pull-up transistor Pu.

[0296] When the inverter 1 performs such a function, the inverter 1 performs a function of transmitting a Qb node control signal for generating a gate-off signal Goff to the pull-down transistor Pd through the Qb node.

[0297] Due to the turn-on voltage capable of turning on the switching element of each pixel P connected to the gate line GL, the data voltage is output to the data line DL in each horizontal period. During the remaining periods except for one horizontal period in one frame, a gate-off signal (Goff) that keeps the switching element in an off state is usually output to the gate line GL.

[0298] To this end, the inverter 1 transmits the Qb node control signal to the pull-down transistor Pd through the Qb node during the remaining period except for one horizontal period in one frame.

[0299] By the Qb node control signal supplied from the inverter I, the pull-down transistor Pd is turned on, and the gate-off signal Goff is output to the gate line GL.

[0300] Fig. 20 yes Fig.17 Circuit diagram of pixel P.

[0301] Fig. 20 The circuit diagram of FIG. 1 is an equivalent circuit diagram of a pixel P of the display device 1600 including an organic light emitting diode OLED as a display element 710. The pixel P includes the display element 710 and a pixel driving circuit PDC driving the display element 710.

[0302] According to another embodiment of the present disclosure, a display device 1600 includes a pixel driving circuit PDC disposed on a substrate 110. The pixel driving circuit PDC may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, 1500.

[0303] Reference Fig. 20 The pixel driving circuit PDC includes a first thin film transistor TR1 and a second thin film transistor TR2. As at least one of the first thin film transistor TR1 and the second thin film transistor TR2, at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, and 1500 can be used.

[0304] According to another embodiment of the present disclosure, the first thin film transistor TR1 is a driving transistor, and the second thin film transistor TR2 is a switching transistor.

[0305] The second thin film transistor TR2 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

[0306] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the second thin film transistor TR2 controls application of the data voltage Vdata.

[0307] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display element 710 .

[0308] When the second thin film transistor TR2 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied from the data line DL is supplied to the gate electrode of the first thin film transistor TR1 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the first thin film transistor TR1.

[0309] The amount of current supplied to the organic light emitting diode OLED as the display element 710 through the first thin film transistor TR1 is controlled according to the data voltage Vdata, thereby controlling grayscale light emitted from the display element 710 .

[0310] According to another embodiment of the present disclosure, the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the substrate 110 .

[0311] Fig.21 is a circuit diagram of a pixel P of a display device 1700 according to another embodiment of the present disclosure.

[0312] Fig.21 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0313] Fig.21 The pixel P of the illustrated display device 1700 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0314] In the pixel P, signal lines DL, GL, PL, RL, and SCL that supply signals to the pixel driving circuit PDC are provided.

[0315] A data voltage Vdata is supplied to the data line DL, a scan signal SS is supplied to the gate line GL, a driving voltage Vdd for driving pixels is supplied to the driving power line PL, a reference voltage Vref is supplied to the reference line RL, and a sensing control signal SCS is supplied to the sensing control line SCL.

[0316] The pixel driving circuit PDC, for example, includes a second thin film transistor TR2 (switching transistor) connected to the gate line GL and the data line DL, a first thin film transistor TR1 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the second thin film transistor TR2, and a third thin film transistor TR3 (reference transistor) for sensing the characteristics of the first thin film transistor TR1.

[0317] The storage capacitor C1 is located between the gate electrode of the first thin film transistor TR1 and the display element 710 .

[0318] The second thin film transistor TR2 is turned on by the scan signal SS supplied to the gate line GL, and transfers the data voltage Vdata supplied to the data line DL to the gate electrode of the first thin film transistor TR1.

[0319] The third thin film transistor TR3 is connected to the first node n1 between the first thin film transistor TR1 and the display element 710 and the reference line RL, and is turned on or off by the sensing control signal SCS, and senses characteristics of the first thin film transistor TR1 as a driving transistor during a sensing period.

[0320] The second node n2 connected to the gate electrode of the first thin film transistor TR1 is connected to the second thin film transistor TR2. The storage capacitor C1 is formed between the second node n2 and the first node n1.

[0321] When the second thin film transistor TR2 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the first thin film transistor TR1. The data voltage Vdata is charged in the first capacitor C1 formed between the gate electrode and the source electrode of the first thin film transistor TR1.

[0322] When the first thin film transistor TR1 is turned on, current is supplied to the display element 710 through the first thin film transistor TR1 by the driving voltage Vdd driving the pixel, and light is emitted from the display element 710 .

[0323] Fig. 22 is a circuit diagram of a pixel of a display device 1800 according to another embodiment of the present disclosure.

[0324] Fig. 22 The pixel P of the illustrated display device 1800 includes an organic light emitting diode OLED as a display element 710 and a pixel driving circuit PDC driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0325] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0326] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL that supply signals to the pixel driving circuit PDC are provided.

[0327] and Fig.21 Compared with the pixel P, Fig. 22 The pixel P further includes a light emitting control line EL. A light emitting control signal EM is supplied to the light emitting control line EL.

[0328] In addition, Fig.21 Compared with the pixel driving circuit PDC, Fig. 22 The pixel driving circuit PDC further includes a fourth thin film transistor TR4 which is a light emission control transistor for controlling the light emission timing of the first thin film transistor TR1.

[0329] The storage capacitor C1 is located between the gate electrode of the first thin film transistor TR1 and the display element 710 .

[0330] The second thin film transistor TR2 is turned on by the scan signal SS supplied to the gate line GL, and transfers the data voltage Vdata supplied to the data line DL to the gate electrode of the first thin film transistor TR1.

[0331] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and senses characteristics of the first thin film transistor TR1 as a driving transistor during a sensing period.

[0332] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the first thin film transistor TR1 or blocks the driving voltage Vdd according to the light emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the first thin film transistor TR1, thereby emitting light from the display element 710.

[0333] The pixel driving circuit PDC according to another embodiment of the present disclosure may be formed in various structures different from the above-mentioned structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0334] Fig.23 is a circuit diagram of a pixel of a display device 1900 according to another embodiment of the present disclosure.

[0335] Fig.23 The pixel P of the illustrated display device 1900 includes a pixel driving circuit PDC and a liquid crystal capacitor C1c connected to the pixel driving circuit PDC. The liquid crystal capacitor C1c corresponds to a display element. Fig.23 The display device 1900 is a liquid crystal display device.

[0336] The pixel driving circuit PDC includes a thin film transistor TR connected to the gate line GL and the data line DL, a pixel electrode 371 connected to the thin film transistor TR, a common electrode 372 opposite to the pixel electrode 371, and a storage capacitor Cst connected between the thin film transistor TR and the common electrode 372. A liquid crystal capacitor C1c is connected between the thin film transistor TR and the common electrode 372 in parallel with the storage capacitor Cst.

[0337] The liquid crystal capacitor (Clc) charges the voltage difference between the data voltage Vdata supplied to the pixel electrode 371 through the thin film transistor (TR) and the common voltage Vcom supplied to the common electrode 372, and drives the liquid crystal according to the charged voltage to control the light transmission amount. The storage capacitor Cst keeps the voltage charged in the liquid crystal capacitor Clc stable.

[0338] A display device 1900 according to another embodiment of the present disclosure may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1401, 1402, 1403, 1405, and 1500.

[0339] The present disclosure described above is not limited to the above-mentioned embodiments and drawings, and it is well known to those skilled in the art that various substitutions, modifications, and changes are possible within the scope of the technical details of the present disclosure.

[0340] CROSS-REFERENCE TO RELATED APPLICATIONS

[0341] This application claims the benefit of and priority to Korean Patent Application No. 10-2023-0093880, filed on Jul. 19, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A thin film transistor, comprising: Light shielding layer; an active layer on the light shielding layer; a gate spaced apart from the active layer and overlapping at least a portion of the active layer; as well as an inner bridge electrically connecting the gate and the light shielding layer; Wherein, the active layer comprises: a channel portion overlapping the gate; a first connection portion, the first connection portion contacting one side of the channel portion, the first connection portion not overlapping the gate; and a second connection portion, the second connection portion being spaced apart from the first connection portion and contacting the other side of the channel portion, the second connection portion not overlapping the gate, wherein the light shielding layer overlaps at least the entire channel portion, and The inner bridge overlaps the gate electrode and penetrates the active layer in a direction from the gate electrode to the light shielding layer.

2. The thin film transistor according to claim 1, further comprising: a buffer layer between the light shielding layer and the active layer; as well as a gate insulating layer between the active layer and the gate, The inner bridge is insulated from the active layer and penetrates the gate insulating layer and the buffer layer.

3. The thin film transistor according to claim 1, in, The inner bridge contacts the gate and the light shielding layer.

4. The thin film transistor according to claim 1, in, The inner bridge is integrated with the gate.

5. The thin film transistor according to claim 1, in, The active hole is arranged in a region whose boundaries are defined by the active layer, wherein at least a portion of the active hole overlaps with the gate, and In a plan view, the inner bridge is disposed in the active hole.

6. The thin film transistor according to claim 5, in, The active hole overlaps with the gate as a whole.

7. The thin film transistor according to claim 5, in, A portion of the active hole does not overlap the gate.

8. The thin film transistor according to claim 5, in, The active holes include a first active hole and a second active hole spaced apart from each other, and At least a portion of the first active hole overlaps the gate, and at least a portion of the second active hole overlaps the gate.

9. The thin film transistor according to claim 8, wherein: The inner bridge comprises: a first inner bridge disposed in the first active hole; and A second inner bridge is disposed in the second active hole.

10. The thin film transistor according to claim 9, in, The first active hole and the second active hole are disposed to be spaced apart from each other in a direction perpendicular to a direction connecting the first connection portion and the second connection portion.

11. The thin film transistor according to claim 9, in, The first active hole and the second active hole are disposed to be spaced apart from each other in a direction connecting the first connection portion and the second connection portion.

12. The thin film transistor according to claim 5, in, In a plan view, a portion of the active hole protrudes from the gate in a direction connecting the first connection portion and the second connection portion.

13. The thin film transistor according to claim 12, in, In a plan view, the active hole protrudes at both sides of the gate.

14. The thin film transistor according to claim 1, further comprising: a first conductive pattern on the first connecting portion; as well as a second conductive pattern on the second connecting portion, The first conductive pattern does not overlap with the gate, and the second conductive pattern does not overlap with the gate.

15. The thin film transistor according to claim 1, further comprising: an external bridge which does not penetrate the active layer and is disposed outside a region defined by the active layer, The external bridge overlaps the gate and electrically connects the gate and the light shielding layer.

16. A display device, comprising: substrate; as well as The thin film transistor according to any one of claims 1 to 15, wherein the thin film transistor is provided on the substrate.

17. The display device according to claim 16, further comprising: A gate driver is provided on the substrate, Wherein, the gate driver includes the thin film transistor.

18. The display device according to claim 16, further comprising: A pixel driving circuit is provided on the substrate, Wherein, the pixel driving circuit includes the thin film transistor.

19. A method for manufacturing a thin film transistor, the method comprising the following steps: forming a light shielding layer on a substrate; forming a buffer layer on the light shielding layer; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer; as well as forming a gate on the gate insulating layer, The step of forming the active layer includes: forming an active hole by selectively removing a portion of the active layer, The active hole is arranged in a region whose boundary is defined by the active layer, The step of forming the gate insulating layer includes: forming a through hole penetrating the gate insulating layer and the buffer layer, The through hole passes through the active hole, and The step of forming the gate includes forming an inner bridge disposed in the through hole.

20. The manufacturing method according to claim 19, in, The inner bridge contacts the gate electrode and the light shielding layer.

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