Field effect transistor and method of manufacturing the same, memory, electronic device

Abstract

The application provides a field effect transistor and a preparation method thereof, a memory and an electronic device. The field effect transistor comprises a gate, an insulating layer, a conductive channel layer arranged in sequence, and a source and a drain arranged at intervals on a side surface of the conductive channel layer away from the insulating layer. The conductive channel layer comprises a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material. In the application, the conductive channel layer comprises the two-dimensional material, and the hydrazine hydrate enters the two-dimensional material, thereby increasing the number of charge trapping centers, promoting the movement of electrons, enhancing the electrical hysteresis characteristic, expanding the electrical hysteresis window, improving the storage performance of the field effect transistor, reducing the preparation cost of the field effect transistor, and being beneficial to enhancing the data reliability and anti-interference capability of the memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of field effect transistors, in particular to a field effect transistor and a preparation method thereof, a memory, and an electronic device. BACKGROUND

[0002] With the increasing demand for miniaturization and high performance of electronic devices, the requirements for memories are becoming higher and higher, and the performance of field effect transistors determines the storage performance of memories. At present, two-dimensional materials are expected to become the next generation of field effect transistor materials due to their unique bipolar characteristics. In the prior art, two-dimensional material field effect transistors have problems such as complex preparation process, high cost, small hysteresis window, poor storage performance, and are difficult to be produced and applied on a large scale. Therefore, a field effect transistor with good electrical hysteresis characteristics, excellent storage performance, simple preparation process, and low cost is needed. SUMMARY

[0003] In view of this, the present application provides a field effect transistor and a preparation method thereof, a memory, and an electronic device. The structure of the field effect transistor includes hydrazine hydrate modified two-dimensional material, which reduces interface defects, increases the number of charge trapping centers, strengthens electron flow, enhances electrical hysteresis characteristics, expands the electrical hysteresis window, improves the storage performance of the field effect transistor, and is beneficial to improving the data reliability and anti-interference ability of the memory. At the same time, the preparation method of the field effect transistor is simple and has low preparation cost, which is beneficial to the industrialized production of the field effect transistor.

[0004] In a first aspect, the present application provides a field effect transistor, which includes a gate, an insulating layer, a conductive channel layer arranged in sequence, and a source and a drain arranged at intervals on a side surface of the conductive channel layer away from the insulating layer. The conductive channel layer includes two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material.

[0005] Optionally, the hydrazine hydrate is uniformly dispersed in the conductive channel layer.

[0006] Optionally, part of the hydrazine hydrate exists in the internal structure of the two-dimensional material.

[0007] Optionally, the thickness of the conductive channel layer is 5-10 nm.

[0008] Optionally, the field effect transistor further includes a hydrazine hydrate layer arranged on the conductive channel layer between the source and the drain.

[0009] Optionally, the two-dimensional material includes a transition metal chalcogenide.

[0010] Optionally, the transition metal chalcogen compound has a chemical formula of MX2, wherein M represents a transition metal element, M includes one or more of Ti, V, Ta, Mo, W, Re, and X represents a chalcogen atom, X is S, Se, or Te.

[0011] Optionally, a material of the gate includes one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium, and tin, and a material of the insulating layer includes one or more of silicon dioxide, silicon nitride, and aluminum oxide.

[0012] Optionally, a material of the source includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt, and a material of the drain includes one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt.

[0013] Optionally, the electrochemical hysteresis window of the field effect transistor is greater than or equal to 65v.

[0014] The field effect transistor provided by the present application includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material in the conductive channel layer of the field effect transistor, the number of charge trapping centers and the electron concentration are improved, the electrical hysteresis characteristics of the two-dimensional material are enhanced, the electrical hysteresis window is improved, and the storage performance of the field effect transistor is improved.

[0015] In a second aspect, the present application provides a preparation method of a field effect transistor, comprising:

[0016] forming a gate on one side surface of an insulating layer, forming a two-dimensional material layer, a source, and a drain on a side surface of the insulating layer away from the gate, to obtain a field effect transistor to be modified;

[0017] placing the field effect transistor to be modified in a hydrazine hydrate atmosphere for a first time to obtain the field effect transistor.

[0018] Optionally, the first time is 30s-15min.

[0019] The preparation method of the field effect transistor provided by the present application is novel, has low preparation cost, and simple preparation process, the electrical hysteresis characteristics of the prepared field effect transistor are excellent, the electrical hysteresis window is large, and the storage performance is good.

[0020] In a third aspect, the present application provides a memory, which includes the field effect transistor of the first aspect or the field effect transistor prepared by the preparation method of the second aspect.

[0021] The memory provided by the present application has excellent comprehensive performance, excellent storage performance, high stability, and high reliability.

[0022] In a fourth aspect, the present application provides an electronic device comprising the memory of the third aspect.

[0023] The electronic device provided by the present application has low production cost, high running speed and high stability. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. The specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0025] Figure 1 A cross-sectional structure schematic diagram of a field effect transistor provided by an embodiment of the present application is shown in the figure.

[0026] Figure 2 A cross-sectional structure schematic diagram of a field effect transistor provided by another embodiment of the present application is shown in the figure.

[0027] Figure 3 A preparation flow schematic diagram of a field effect transistor provided by an embodiment of the present application is shown in the figure.

[0028] Figure 4 An Electron Energy Loss Spectroscopy (EELS) diagram of a field effect transistor provided by Embodiment 1 of the present application is shown in the figure.

[0029] Figure 5 A Raman spectrum diagram of a conductive channel layer cross section in a field effect transistor provided by Embodiment 1 of the present application is shown in the figure.

[0030] Figure 6 A cycle characteristic curve diagram of a field effect transistor provided by Embodiment 1 of the present application is shown in the figure.

[0031] Figure 7 A transfer characteristic curve of a field effect transistor of Embodiments 1-4 and Comparative Example 1 of the present application.

[0032] EXPLANATION OF DRAWINGS

[0033] 100 - field effect transistor; 10 - gate; 20 - insulating layer; 30 - conductive channel layer; 41 - source; 42 - drain; 50 - hydrazine hydrate layer. DETAILED DESCRIPTION

[0034] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0035] With the continuous miniaturization and high performance demand of electronic devices, the performance requirements of field effect transistors are getting higher and higher. Field effect transistor is a kind of semiconductor device that uses the electric field effect of control input circuit to control the current of output circuit. Because two-dimensional material has bipolarity, it can realize the transmission of electrons and holes at the same time, and is expected to become the next generation of field effect transistor material. However, in the prior art, two-dimensional material cannot be doped by ion implantation and other simple operations to obtain pure p-type or n-type field effect transistor to realize storage function. Usually, two-dimensional material needs to be combined with floating gate storage structure or ferroelectric storage structure to obtain field effect transistor with excellent storage performance. Among them, floating gate memory realizes the storage and release of electric charge by constructing floating gate structure on two-dimensional material and using tunneling effect, but it needs precise multi-layer structure, including floating gate, charge tunnel layer and control gate, etc., and the prepared storage structure is complex, the preparation process steps are numerous, and the process cost and time cost are greatly increased. Ferroelectric memory relies on the spontaneous polarization characteristics of special ferroelectric material to realize data storage and erasure under the action of external electric field, and can also obtain a storage device with large electrical hysteresis loop after being combined with two-dimensional material; and the ferroelectric memory may degrade after high temperature or long time use, and the preparation and integration process of the storage device is strict, which further increases the manufacturing difficulty and cost. Therefore, a field effect transistor with low preparation cost, simple process, large electrical hysteresis window and excellent storage performance is needed.

[0036] Please refer to Figure 1 , Figure 1A cross-sectional structure schematic diagram of a field effect transistor provided in an embodiment of the present application, the field effect transistor 100 includes a gate electrode 10, an insulating layer 20, a conductive channel layer 30, and a source electrode 41 and a drain electrode 42 which are arranged at intervals on a side surface of the conductive channel layer 30 away from the insulating layer 20, and the conductive channel layer 30 includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material. In the present application, the transmission of carriers in the conductive channel layer is realized by applying an external voltage on the gate electrode, the source electrode and the drain electrode, and the directional movement of electrons is promoted to realize data storage and erasure; in addition, the hydrazine hydrate is dispersed in the two-dimensional material layer, the hydrazine hydrate molecules are introduced into the structure of the two-dimensional material, the interface defects are reduced, a large number of charge trapping centers are formed in the two-dimensional material, the number and efficiency of captured and released charges can be increased, the electrical hysteresis characteristics of the field effect transistor are enhanced, a larger electrical hysteresis window is realized, excellent data access and reading performance is achieved, the anti-interference ability and data reliability of the memory are enhanced; at the same time, the hydrazine hydrate is a strong polar compound, which can make the bipolarity of the two-dimensional material change to electron (n-type) doping induction on the premise of not reacting with the two-dimensional material, increase the electron concentration of the conductive channel layer, increase the current, improve the on-off ratio of the device, improve the control ability of the gate voltage on the channel, and is conducive to improving the storage performance of the field effect transistor. In addition, the structure of the field effect transistor in the present application is simple, and special materials are not required, which reduces the preparation cost of the memory and is conducive to the wide application of the memory. The electrical hysteresis window of the field effect transistor provided in the present application is large, the data storage and erasure efficiency is high, and the storage performance and data stability of the memory are improved.

[0037] In an embodiment of the present application, the conductive channel layer 30 includes a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material, the hydrazine hydrate fully enters the two-dimensional material, causes the crystal structure of the two-dimensional material to change, causes the bond length to become longer, thereby introducing a large number of charge trapping centers, increasing the number of captured and released charges in the conductive channel layer, and promoting the movement of electrons in the conductive channel layer, thereby being conducive to improving the storage performance of the memory; the strong polarity of the hydrazine hydrate causes the two-dimensional material to gradually change from the bipolar transport characteristics dominated by p-type to n-type, thereby increasing the electron concentration in the conductive channel layer and being conducive to improving the electrical hysteresis window of the field effect transistor. Specifically, the two-dimensional material can include but is not limited to a transition metal chalcogenide, for example, the chemical formula of the transition metal chalcogenide is MX2, wherein M represents a transition metal element, M can include but is not limited to one or more of Ti, V, Ta, Mo, W, Re, X represents a chalcogen element atom, and X can be but not limited to S, Se or Te, etc. In an embodiment of the present application, the conductive channel layer includes MoTe2, and after the hydrazine hydrate enters the two-dimensional material, the bond length of the Mo-Te bond of MoTe2 is increased from to the bond length of the Te-Te bond is increased from to

[0038] In an embodiment of the present application, the thickness of the conductive channel layer 30 is 5-10 nm, and the suitable thickness of the conductive channel layer 30 can increase the electrical hysteresis window of the field effect transistor, and improve the storage and reading efficiency of data. Specifically, the thickness of the conductive channel layer 30 can be, but is not limited to, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, etc. In an embodiment of the present application, the thickness of the conductive channel layer 30 can be 5-8 nm. In another embodiment of the present application, the thickness of the conductive channel layer 30 can be 7-10 nm.

[0039] Please refer to Figure 2 , the conductive channel layer 30 between the source 41 and the drain 42 also includes a hydrazine hydrate layer 50, which can increase the number of charge trapping centers of the conductive channel layer, realize stable capture and release of charges, and is beneficial to improve the electrical hysteresis window of the field effect transistor.

[0040] In an embodiment of the present application, the field effect transistor includes the source 41 and the drain 42 arranged on the surface of the conductive channel layer 30 away from the insulating layer 20, the source 41 controls the inflow of carriers, and the carriers are discharged from the drain 42 to realize the storage function of the field effect transistor. Specifically, the material of the source 41 can include one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, but is not limited to. The material of the drain 42 can include one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel and cobalt, but is not limited to. The thickness of the source 41 can be, but is not limited to, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. The thickness of the drain 42 can be, but is not limited to, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. In an embodiment of the present application, a 10 nm thick palladium metal can be used as the source 41. In another embodiment of the present application, a 50 nm thick metal can be used as the drain 42. In some embodiments, an external voltage (drain voltage V d , source voltage V s ) is applied to the source 41 and the drain 42, the source voltage is grounded, and the drain is used as the external voltage.

[0041] In an embodiment of the present application, the source 41 and / or the drain 42 can be composed of a metal conductive layer and a metal compound layer, wherein the metal conductive layer is connected to an applied voltage, and the metal compound layer is located between the conductive channel layer and the metal conductive layer, which is conducive to improving the electron flow speed in the conductive channel layer and reducing the preparation cost of the field effect transistor. Specifically, the material of the metal conductive layer can include, but is not limited to, one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt; and the material of the metal compound layer can include, but is not limited to, one or more of metal oxides, metal nitrides, and alloys.

[0042] In an embodiment of the present application, the source 41 and / or the drain 42 can be composed of a metal conductive layer and a metal compound layer, wherein the metal conductive layer is connected to an applied voltage, and the metal compound layer is located between the conductive channel layer and the metal conductive layer, which is conducive to improving the electron flow speed in the conductive channel layer and reducing the preparation cost of the field effect transistor. Specifically, the material of the metal conductive layer can include, but is not limited to, one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt; and the material of the metal compound layer can include, but is not limited to, one or more of metal oxides, metal nitrides, and alloys.

[0043] In an embodiment of the present application, the gate 10 can be connected to an applied voltage to enable the carriers to enter the conductive channel layer 30, thereby realizing the reading, writing, and erasing of data. The insulating layer 20 can prevent the interface reaction and mutual diffusion between the gate 10 and the conductive channel layer 30, which is conducive to improving the structural stability of the field effect transistor. Specifically, the material of the gate 10 can include, but is not limited to, one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium, and tin; and the material of the insulating layer 20 can include, but is not limited to, one or more of silicon dioxide, silicon nitride, and aluminum oxide. In an embodiment of the present application, the insulating layer 20 can be silicon dioxide, and the gate 10 can be silicon, and the insulating layer and the gate constitute the substrate of the field effect transistor. In some embodiments, an applied voltage (gate voltage V g ) is applied to the gate 10.

[0044] In an embodiment of the present application, the thickness of the insulating layer 20 is 10 nm-350 nm, and a suitable thickness of the insulating layer 20 can improve the structural stability of the field effect transistor. Specifically, the thickness of the insulating layer 20 can be, but is not limited to, 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, or 350 nm, etc. In an embodiment of the present application, the thickness of the insulating layer 20 can be 10 nm-250 nm. In another embodiment of the present application, the thickness of the insulating layer 20 can be 200 nm-350 nm.

[0045] In an embodiment of the present application, the electrical hysteresis window of the field effect transistor is greater than or equal to 65 V. The electrical hysteresis window refers to the voltage gap of the field effect transistor in programming and erasing operations. The larger the electrical hysteresis window, the more conducive to improving the storage and reading ability of the field effect transistor, improving the access and reading efficiency, enhancing the anti-interference ability and data reliability of the field effect transistor. Specifically, the electrical hysteresis window of the field effect transistor can be, but is not limited to, greater than or equal to 65 V, greater than or equal to 66 V, greater than or equal to 68 V, greater than or equal to 70 V, greater than or equal to 72 V, or greater than or equal to 75 V, etc. In an embodiment of the present application, the electrical hysteresis window of the field effect transistor can be greater than or equal to 68 V. In some embodiments, the transfer characteristic curve test can be performed on the field effect transistor, and the read, write, and erase voltages are selected according to the transfer curve, and a cycle test of erase, write, read, and write is performed to obtain the cycle characteristics, thereby obtaining the electrical hysteresis window range of the field effect transistor.

[0046] The present application provides a preparation method of a field effect transistor, comprising:

[0047] S101: forming a gate electrode on one side surface of an insulating layer, and forming a two-dimensional material layer, a source electrode, and a drain electrode on the side surface of the insulating layer away from the gate electrode to obtain a field effect transistor to be modified;

[0048] S102: placing the field effect transistor to be modified in a hydrazine hydrate atmosphere for a first time to obtain a field effect transistor. The preparation method of the field effect transistor provided by the present application is novel, the preparation process is simple, the preparation cost is low, the field effect transistor prepared has good electrical hysteresis characteristics, a large programming and erasing window, and improved data storage and reading efficiency of the field effect transistor. In the present application, hydrazine hydrate molecules are introduced into the two-dimensional material to form a large number of charge trapping centers in the two-dimensional material, which can increase the number of trapped and released charges, enhance the electrical hysteresis characteristics of the field effect transistor, achieve a large electrical hysteresis window, achieve excellent data access and reading performance, and enhance the anti-interference ability and data reliability of the memory. Hydrazine hydrate is relatively inexpensive, which reduces the preparation cost of the field effect transistor and improves the economy and feasibility of the memory.

[0049] Please refer to Figure 3 , Figure 3 The preparation process of the field effect transistor provided in an embodiment of the present application is shown in the schematic diagram. The two-dimensional material is arranged on the surface of the insulating layer to form a two-dimensional material layer, which is conducive to realizing charge storage and improving the structural stability of the field effect transistor. In an embodiment of the present application, the mechanical exfoliation two-dimensional material (MoTe2) nanosheet is transferred to the surface of the cleaned silicon insulating layer by using an optical microscope and a transfer stage to form a two-dimensional material layer.

[0050] In an embodiment of the present application, the source electrode and the drain electrode are arranged on the surface of the two-dimensional material layer after the two-dimensional material is arranged on the surface of the insulating layer. In an embodiment of the present application, the photoresist is arranged on the surface of the two-dimensional material layer, and after electron beam lithography and cleaning, the exposed area and the area covered by the photoresist are formed on the surface of the two-dimensional material layer. After electron beam evaporation, the source electrode and the drain electrode are arranged on the surface of the exposed area. After removing the photoresist covering the remaining area, the field effect transistor to be modified is obtained.

[0051] In the present application, the field effect transistor to be modified is placed in hydrazine hydrate vapor for a first time. The hydrazine hydrate vapor modifies the field effect transistor to be modified to form a conductive channel layer within the first time. The hydrazine hydrate is dispersed in the two-dimensional material and forms a hydrazine hydrate layer on the surface of the two-dimensional material layer between the source electrode and the drain electrode to obtain the field effect transistor.

[0052] In an embodiment of the present application, the first time is 30s-15min, which is conducive to inserting the hydrazine hydrate into the two-dimensional material, modifying the conductive channel layer, and improving the storage performance of the field effect transistor. Specifically, the first modification time can be but is not limited to 30s, 1min, 2min, 5min, 8min, 10min, 12min, 14min or 15min, etc. In an embodiment of the present application, 0.5ml of hydrazine hydrate is placed in a flask and heated to 70℃. The field effect transistor to be modified is hung in the flask by a support, and the hydrazine hydrate vapor is used for modification for 10min to obtain the field effect transistor.

[0053] The present application also provides a memory, which comprises the field effect transistor of any one of the above embodiments or the field effect transistor prepared by the preparation method of any one of the above embodiments. In the present application, the field effect transistor is modified by hydrazine hydrate to form a hydrazine hydrate modification layer on the surface of the conductive channel layer, introduce hydrazine hydrate into the two-dimensional material, improve the storage performance of the field effect transistor, and further improve the programming and erasing window of the memory. This is conducive to improving the data storage and reading efficiency of the memory device and improving the operation speed of the electronic equipment.

[0054] In an embodiment of the present application, the metal electrode and the insulating layer in the field effect transistor are externally applied with a voltage, which can cause the directional movement of the electrons in the conductive channel layer, thereby having the data storage and erasing functions, and obtaining a memory with excellent storage performance. In an embodiment of the present application, one field effect transistor can be a memory device.

[0055] In an embodiment of the present application, the memory can be divided into random access memory and read-only memory according to the working mode. The random access memory is a memory that reads and writes data at a high speed in a random manner at the same speed for any address (the writing speed and the reading speed can be different); the content in the read-only memory can only be read in a random manner and cannot be written, and once the information is written into the memory, it is fixed and cannot be changed, and even if the power is off, the content will not be lost. The field effect transistor provided in the present application can be applied to the preparation of the above-mentioned memory, and the storage capacity of the above-mentioned memory can be improved.

[0056] The present application also provides an electronic device comprising the memory of any one of the above-mentioned embodiments. The electronic device can be, for example, a mobile phone, a tablet computer, a notebook computer, a wearable device (watch, bracelet), a digital camera, etc. The memory provided in the present application has low preparation cost and good storage performance, which is conducive to improving the running speed of the electronic device and the wide application of the electronic device, for example: the electronic device can be applied in data centers, network communication, consumer electronics, automotive electronics, industrial electronics, etc. In an embodiment of the present application, the electronic device can be a computer, which comprises three core hardware: a central processing unit, a memory and a hard disk, wherein the central processing unit is responsible for operation, the hard disk is responsible for storage, and the memory is a bridge between the central processing unit and the hard disk, which is used for temporarily storing the operation data in the central processing unit. The memory and the hard disk comprise the memory of any one of the above-mentioned embodiments, which can realize the fast reading and writing and long-term storage of data, and improve the running speed of the computer.

[0057] The effects of the technical solutions of the present application will be further described below through specific examples.

[0058] Embodiment 1

[0059] The bulk two-dimensional material (5 nm MoTe2 nanosheet) is transferred to the cleaned insulating layer (300 nm SiO2) by using the blue tape and the mechanical peeling method, the gate electrode (Si) is arranged on the side away from the two-dimensional material layer, the photoresist is coated on the surface of the two-dimensional material layer, the electron beam lithography and electron beam evaporation are performed to obtain the source electrode (palladium (Pd, 10 nm)) and the drain electrode (gold (Au, 50 nm)), and the photoresist is removed to obtain the field effect transistor to be modified;

[0060] In a 250 mL flask, 0.5 mL of hydrazine hydrate was added, the flask was heated to 70°C to obtain hydrazine hydrate vapor, and the field effect transistor to be modified was vertically placed at the bottle opening and kept in the hydrazine hydrate gas for a first time (10 min) to obtain the field effect transistor.

[0061] Figure 4 The Electron Energy Loss Spectroscopy (EELS) spectrum of the field effect transistor provided in Example 1 of the present application is provided. According to Figure 4 It can be seen that the N element in the hydrazine hydrate molecule is distributed in the two-dimensional material of the conductive channel layer, that is, the hydrazine hydrate molecule can enter the two-dimensional material. Figure 5 The Raman spectrum of the field effect transistor provided in Example 1 of the present application is provided. According to Figure 5 It can be seen that the two-dimensional material MoTe2 does not change before and after the modification of hydrazine hydrate, and there is no obvious difference in the Raman spectrum peak position of the two-dimensional material before and after the modification, which proves that the two-dimensional material MoTe2 does not change substantially, and the hydrazine hydrate does not react with the two-dimensional material. Figure 6 The cycle characteristic curve of the field effect transistor provided in Example 1 of the present application is provided: (a) is the linear graph of the transfer characteristic curve of the field effect transistor; (b) is the logarithmic graph of the transfer characteristic curve of the field effect transistor; (c) is the cycle current change graph of a single field effect transistor; (d) is the cycle current change graph of multiple field effect transistors; (e) is a schematic diagram of the data retention capability of the field effect transistor; (f) is a schematic diagram of the data retention capability of the field effect transistor, wherein (a) (b) show that the hysteresis window of the field effect transistor is 65 V; (c) (d) describe the erase and write tests under single cycle and 256 cycles, and the data shows that the resistance switching ratio of the device is 10 3 , and the data remains stable within 256 cycles. (e) (f) describes the data retention capability of the field effect transistor, and the data retention time can reach 60 minutes.

[0062] Example 2

[0063] The difference from Example 1 is that the first time is 5 min.

[0064] Example 3

[0065] The difference from Example 1 is that the first time is 2 min.

[0066] Example 4

[0067] The difference from Example 1 is that the first time is 0.5 min.

[0068] Comparative Example 1

[0069] The difference from Example 1 is that no hydrazine hydrate modification is performed.

[0070] Performance detection

[0071] The field effect transistors prepared in the above Examples 1-4 and Comparative Example 1 are subjected to electrical hysteresis characteristic curve testing. The testing process is as follows: according to the transfer curve, the read (Vg=0V), write (Vg=60V), and erase (Vg=-60V) voltages are selected, and a cycle of erase, write, read, and write is tested to obtain the cycle characteristics. The results are shown in Table 1. Figure 7 Figure 7 The transfer characteristic curve of the field effect transistor of Example 1-4 and Comparative Example 1 of the present application is shown in Figure 1.

[0072] The field effect transistors prepared in the above Examples 1 and Comparative Example 1 are subjected to synchrotron radiation X-ray absorption spectroscopy (XAFS). The results are shown in Table 1.

[0073] Table 1: Performance test results

[0074]

[0075] As can be seen from Examples 1-4 and Comparative Example 1, after the hydrazine hydrate modification, the hydrazine hydrate enters the two-dimensional material, changes the bond length of the two-dimensional material, increases the number of charge trapping centers, and significantly increases the hysteresis window. The N-terminal current (Vg=60V) increases from 6x10 -6 A to 1.5x10 -5 A, which increases the electron concentration in the transistor. The larger hysteresis window is beneficial to improve the storage and reading ability of the device. As can be seen from Examples 1-4, with the increase of the hydrazine hydrate modification time, the field effect transistor gradually changes from a bipolar transport characteristic mainly of p-type to n-type, and the N-terminal current gradually increases, indicating that the hydrazine molecule can induce n-type doping of the transistor to a certain extent, resulting in an increasing trend of the hysteresis window of the field effect transistor, which is beneficial to improve the storage performance of the field effect transistor.

[0076] The above describes the preferred embodiments of the present application, but should not be construed as limiting the scope of the present application. It should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which are also considered within the scope of protection of the present application.​

Claims

1. A field effect transistor, characterized by The field effect transistor comprises a gate, an insulating layer, and a conductive channel layer arranged in sequence, a source and a drain arranged at a side surface of the conductive channel layer away from the insulating layer, and a hydrazine hydrate layer arranged on the conductive channel layer between the source and the drain, wherein the conductive channel layer comprises a two-dimensional material and hydrazine hydrate dispersed in the two-dimensional material, and the two-dimensional material comprises a transition metal chalcogenide compound. The preparation of the field effect transistor comprises forming a gate at a side surface of an insulating layer, forming a two-dimensional material layer, a source, and a drain at a side surface of the insulating layer away from the gate to obtain a field effect transistor to be modified, and placing the field effect transistor to be modified in a hydrazine hydrate atmosphere for a first time to obtain the field effect transistor.

2. The field effect transistor of claim 1, wherein The hydrazine hydrate is uniformly dispersed in the conductive channel layer.

3. The field-effect transistor as described in claim 1, characterized in that, The thickness of the conductive channel layer is 5-10 nm.

4. The field-effect transistor as described in claim 1, characterized in that, The chemical formula of the transition metal chalcogenide compound is MX2, wherein M represents a transition metal element, M comprises one or more of Ti, V, Ta, Mo, W, Re, and X represents a chalcogen element atom, X is S, Se, or Te. The material of the gate comprises one or more of elemental silicon, molybdenum silicide, tungsten silicide, aluminum, copper, chromium, nickel, molybdenum, tungsten, titanium, indium, and tin, and the material of the insulating layer comprises one or more of silicon dioxide, silicon nitride, and aluminum oxide. The material of the source comprises one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt, and the material of the drain comprises one or more of iridium, rhodium, ruthenium, platinum, gold, silver, palladium, nickel, and cobalt.

5. The field-effect transistor as claimed in claim 1, characterized in that, The electrical hysteresis window of the field effect transistor is greater than or equal to 65 V.

6. The field-effect transistor as claimed in claim 1, characterized in that, The first time is 30 s-15 min.

7. A memory, comprising: The memory comprises the field effect transistor of any one of claims 1-6.

8. An electronic device, comprising: The electronic device comprises the memory of claim 7.

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