Driving backboard, display panel and tiled display device
By designing a specific layout of the wiring layer in the drive backplane, electrostatic discharge is prioritized, which solves the problem of product yield reduction caused by electrostatic discharge, improves production yield and reduces costs.
Patent Information
- Application Number
- CN202310907539.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-21
- Publication Date
- 2025-01-24
AI Technical Summary
In the process of producing miniaturized LED array structures, electrostatic discharge (ESD) leads to a decrease in product yield and increases costs.
A driving backplane is designed, including a substrate substrate, a pixel driving circuit and a wiring layer. The distance between the outermost edge of the wiring layer and the same-side edge of the base substrate is smaller than the distance between the outermost edge of the pixel driving circuit and the same-side edge of the base substrate, so that ESD is preferentially derived during the production process.
By giving priority to exporting ESD, the production yield of the drive backplane is improved and the cost is reduced.
Smart Images
Figure CN119364971A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a display panel and a spliced display device. Background Art
[0002] Sub-millimeter light emitting diode (Mini LED) or micro light emitting diode (Micro LED) is a miniaturized LED array structure, which has the advantages of ultra-high contrast, wide color gamut, low power consumption, and splicing, and is widely used.
[0003] For production, yield is the main factor affecting cost. The high incidence of electrostatic discharge (ESD) during the production process directly leads to a decrease in product yield, which in turn leads to an increase in cost. Summary of the invention
[0004] The present disclosure provides a driving backplane, a display panel and a spliced display device, and the specific scheme is as follows:
[0005] The present disclosure provides a driving backplane, which includes:
[0006] substrate substrate;
[0007] A pixel driving circuit located on the substrate;
[0008] A wiring layer located on a side of the pixel driving circuit away from the substrate, the wiring layer comprising a pattern of potential wiring and binding electrodes, the binding electrodes being used to bind the micro light emitting diodes;
[0009] Wherein, the distance between the outermost edge of the wiring layer and the edge of the substrate on the same side is smaller than the distance between the outermost edge of the pixel driving circuit and the edge of the substrate on the same side.
[0010] Optionally, in the embodiment of the present disclosure, the driving backplane also includes a switching electrode located between the potential wiring and the base substrate and electrically connected to the potential wiring and the pixel driving circuit respectively, and the orthographic projection of the potential wiring on the base substrate and the orthographic projection of the switching electrode on the base substrate are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.
[0011] Optionally, in an embodiment of the present disclosure, the potential routing includes an outermost edge routing and a middle routing located in a middle area, and the line width of the edge routing is smaller than the line width of the middle routing.
[0012] Optionally, in an embodiment of the present disclosure, the binding electrode located at the outermost edge of the wiring layer is arranged flush with the edge wiring on the same side.
[0013] Optionally, in an embodiment of the present disclosure, the substrate is divided into a plurality of light zones arranged in an array, two adjacent light zones in the plurality of light zones are arranged at an equal distance, and each of the light zones is configured to be electrically connected to a corresponding micro-LED through the potential routing and the binding electrode in the corresponding area.
[0014] Optionally, in an embodiment of the present disclosure, along a direction away from the substrate, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer and a first source-drain electrode layer arranged in sequence; the driving backplane includes an insulating layer and a second source-drain electrode layer arranged in sequence on the side of the first source-drain electrode layer away from the substrate; the transfer electrode is located in the first source-drain electrode layer, and the potential routing and the binding electrode are located in the second source-drain electrode layer.
[0015] Optionally, in an embodiment of the present disclosure, the edge routing is intermittently arranged along the extension direction of the outermost edge of the wiring layer to form a plurality of intermittent portions, and each of the intermittent portions is electrically connected via a transfer electrode formed by the first source-drain electrode layer.
[0016] Optionally, in the embodiment of the present disclosure, the orthographic projection of the outermost edge of the pixel driving circuit on the base substrate is overlapped with the orthographic projection of the same side edge of the first source-drain electrode layer on the base substrate.
[0017] Optionally, in the embodiment of the present disclosure, the distance between the outermost edge of the wiring layer and the same side edge of the substrate is in the range of 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit and the same side edge of the substrate is in the range of 180 μm to 220 μm.
[0018] Accordingly, an embodiment of the present disclosure provides a display panel, comprising:
[0019] A driving backplane as described in any one of the above items, and a plurality of micro light emitting diodes bound to the driving backplane.
[0020] Accordingly, an embodiment of the present disclosure provides a spliced display device, comprising:
[0021] A plurality of display panels as described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A schematic diagram of a top view structure of a driving backplane in the related art;
[0023] Figure 2 A schematic diagram of a top view structure of a driving backplane provided in an embodiment of the present disclosure;
[0024] Figure 3 For along Figure 2 A schematic diagram of one of the cross-sectional structures in the direction indicated by MM;
[0025] Figure 4 For along Figure 2 A schematic diagram of one of the cross-sectional structures in the direction indicated by MM;
[0026] Figure 5 A schematic diagram of a top view of a configuration of potential wiring and transfer wiring in a driver backplane provided in an embodiment of the present disclosure;
[0027] Figure 6 A schematic diagram of a top view structure of a potential routing in a driving backplane provided in an embodiment of the present disclosure;
[0028] Figure 7 A schematic diagram of a top view structure of a driving backplane provided in an embodiment of the present disclosure;
[0029] Figure 8 For along Figure 2 A schematic diagram of one of the cross-sectional structures in the direction indicated by MM;
[0030] Fig. 9 A schematic diagram of a top view structure of an edge routing in a driving backplane provided in an embodiment of the present disclosure;
[0031] Fig.10 for Figure 2 The pattern of the first gate layer in the middle region Q;
[0032] Fig.11 for Figure 2 Pattern of the active layer in the middle region Q;
[0033] Fig.12 for Figure 2 The pattern of the second gate layer in the middle region Q;
[0034] Fig.13 for Figure 2 The pattern of the first source-drain electrode layer in the middle region Q;
[0035] Fig.14 for Figure 2 The pattern of the second source-drain electrode layer in the middle region Q;
[0036] Fig.15 for Figure 2 The pattern after the relevant conductive layers are superimposed in the middle region Q;
[0037] Fig.16 A schematic diagram of a structure of a display panel provided in an embodiment of the present disclosure;
[0038] Fig.17 A schematic diagram of a structure of a spliced display device provided in an embodiment of the present disclosure;
[0039] Fig.18 A schematic diagram of a partial top view of the structure of two display panels spliced together;
[0040] Fig.19 for Fig.18 A simplified top view structural diagram of a single display panel before part of the pixel driving circuit is moved inward;
[0041] Fig. 20 for Fig.18 A simplified top view schematic diagram of the structure after part of the pixel driving circuit in a single display panel is moved inward. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.
[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0044] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.
[0045] In the related technology, the production process is often used to manufacture Figure 1 The driving backplane shown in the figure, where 01 represents the setting area of the pixel circuit, 02 represents the setting area of the top conductive layer, and 03 represents the backplane. The pixel circuit is closer to the edge of the driving backplane than the top conductive layer (such as the Cu layer) coupled thereto. In the production process of the driving backplane, the edge of the backplane is the location where ESD is most likely to occur; when ESD occurs at the edge of the backplane during the process, since the backplane is not connected to any signal, the pixel circuit is divided into multiple independent units by its corresponding multiple thin film transistors (TFT), blocking the discharge path of the charge; ESD will damage the pixel circuit and cause defects.
[0046] In view of this, the embodiments of the present disclosure provide a driving backplane, a display panel and a spliced display device for effectively exporting ESD and improving the backplane yield.
[0047] Combination Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of a top view of a driving backplane provided in an embodiment of the present disclosure. Figure 3 For along Figure 2 A schematic diagram of a cross-sectional structure in the direction indicated by MM in FIG. Specifically, the drive backplane includes:
[0048] Base substrate 10;
[0049] A pixel driving circuit 20 located on the base substrate 10;
[0050] A wiring layer 30 located on a side of the pixel driving circuit 20 away from the base substrate 10, the wiring layer 30 includes a pattern of potential wiring 31 and binding electrodes 32, and the binding electrodes 32 are used to bind the micro light emitting diodes;
[0051] The distance between the outermost edge of the wiring layer 30 and the same side edge of the base substrate 10 is smaller than the distance between the outermost edge of the pixel driving circuit 20 and the same side edge of the base substrate 10 .
[0052] In the specific implementation process, the driving backplane includes a substrate 10, a pixel driving circuit 20 and a wiring layer 30. Exemplarily, the substrate 10 can be a rigid substrate, such as a glass substrate, a silicon-based substrate, etc.; it can also be a flexible substrate, such as a polyimide (PI) substrate. Of course, the specific material of the substrate 10 can also be set according to the actual application needs, which is not limited here. Moreover, the pixel driving circuit 20 is arranged on the substrate 10, and the wiring layer 30 is located on the side of the pixel driving circuit 20 away from the substrate 10, wherein the wiring layer 30 includes a pattern of a potential wiring 31 and a binding electrode 32. Exemplarily, the potential wiring 31 and the binding electrode 32 are made of a conductive layer of the same layer and the same material. Exemplarily, the potential wiring 31 can be a power wiring of a constant potential, such as a high potential wiring, a low potential wiring, etc. In practical applications, the binding electrode 32 is used to bind the micro-light-emitting diode, and accordingly, the pixel driving circuit 20 is used to drive the light emission and display of the micro-light-emitting diode. Exemplarily, the micro-LED can be Mini LED or Micro LED, which is not limited here. In practical applications, the specific number and arrangement of the micro-LEDs can be set according to actual needs, which is not limited here.
[0053] In addition, the distance between the outermost edge of the wiring layer 30 and the same side edge of the base substrate 10 is smaller than the distance between the outermost edge of the pixel driving circuit 20 and the same side edge of the base substrate 10. Figure 2 As shown, a represents the distance between the outermost edge of the wiring layer 30 and the edge of the same side of the base substrate 10, and b represents the distance between the outermost edge of the pixel driving circuit 20 and the edge of the same side of the base substrate 10, and a<b. In this way, in the production process, even if ESD is generated at the outermost edge of the driving backplane, the ESD can be preferentially guided out through the wiring layer 30, thereby avoiding the accumulation of ESD at the pixel driving circuit 20 and improving the production yield of the driving backplane.
[0054] In the embodiment of the present disclosure, the driving backplane also includes a switching electrode 40 located between the potential wiring 31 and the base substrate 10 and electrically connected to the potential wiring 31 and the pixel driving circuit 20 respectively. The orthographic projection of the potential wiring 31 on the base substrate 10 and the orthographic projection of the switching electrode 40 on the base substrate 10 are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.
[0055] In the specific implementation process, Figure 4 For along Figure 2One of the cross-sectional structural schematic diagrams in the direction shown in MM, the driving backplane also includes a switching electrode 40 located between the potential wiring 31 and the base substrate 10, and electrically connected to the potential wiring 31 and the pixel driving circuit 20 respectively. In this way, the potential wiring 31 and the pixel driving circuit 20 are effectively electrically connected through the switching electrode 40, thereby ensuring the driving control of the micro-light-emitting diode by the pixel driving circuit 20. Moreover, the positive projection of the potential wiring 31 on the base substrate 10 and the positive projection of the switching electrode 40 on the base substrate 10 are arranged in a mesh structure, and accordingly, the mesh structure is configured as an electrostatic protection unit, through which static electricity can be effectively derived. In this way, the same signals can be connected to form a corresponding mesh structure, and the mesh structure has a lower resistance and is easier to derive static electricity, thereby improving the electrostatic protection capability of the driving backplane. Figure 5 Taking the exemplary embodiment shown in the figure as an example, the potential trace 31 is extended in a direction parallel to the outermost edge of the substrate 10, such as Figure 5 As shown by the arrow X in the middle, the transfer electrode 40 is extended in a direction perpendicular to the outermost edge of the base substrate 10. Figure 5 As shown by arrow Y in the middle.
[0056] In the embodiment of the present disclosure, the potential wiring 31 includes an outermost edge wiring 311 and a middle wiring 312 located in the middle area, and the line width of the edge wiring 311 is smaller than the line width of the middle wiring 312 .
[0057] In the specific implementation process, Figure 6 The figure shows a schematic diagram of a top view of a potential wiring 31, wherein the potential wiring 31 includes an edge wiring 311 located at the outermost edge and a middle wiring 312 located in the middle area, wherein the line width of the edge wiring 311 is smaller than the line width of the middle wiring 312. In this way, under the premise of the same arrangement of the micro-LEDs, the edge wiring 311 occupies less edge space, providing the possibility for subsequent seamless splicing. Figure 6 In the exemplary embodiment shown, the line width of edge line 311 is c, and the line width of middle line 312 is d, where c<d. It should be noted that in actual applications, the maximum line width of edge line 311 may still be smaller than the line width of middle line 312.
[0058] In the embodiment of the present disclosure, the binding electrode 32 located at the outermost edge of the wiring layer 30 is arranged flush with the edge trace 311 on the same side.
[0059] In the specific implementation process, Figure 6As shown, the binding electrode 32 located at the outermost edge of the wiring layer 30 is arranged flush with the edge trace 311 on the same side. In this way, under the premise of the same arrangement of the micro-LEDs, the space occupied by the edge trace 311 can be effectively reduced. Accordingly, the edge trace 311 occupies less edge space, thereby providing the possibility for subsequent seamless splicing.
[0060] In the embodiment of the present disclosure, the base substrate 10 is divided into a plurality of light zones 50 arranged in an array, and two adjacent light zones 50 among the plurality of light zones 50 are arranged at an equal distance, and each of the light zones 50 is configured to be electrically connected to the corresponding micro-light-emitting diode through the potential wiring 31 and the binding electrode 32 of the corresponding area.
[0061] In the specific implementation process, Figure 7 The diagram shows a schematic diagram of a top view of a driving backplane. Specifically, the substrate 10 is divided into a plurality of lamp areas 50 arranged in an array, and two adjacent lamp areas 50 in the plurality of lamp areas 50 are arranged at equal distances. It should be noted that the "equal distance" mentioned here can be "approximately" equal distances or "approximately" equal distances, which are not limited here. Moreover, each lamp area 50 is configured to be electrically connected to the corresponding micro-light-emitting diode through the potential wiring 31 and the binding electrode 32 of the corresponding area. Since in the embodiment of the present disclosure, the outermost edge of the pixel driving circuit 20 is further away from the same side edge of the substrate 10 than the outermost edge of the wiring layer 30, the space occupied by the pixel driving circuit 20 at the edge of the driving backplane is effectively reduced; especially when the edge space is reduced and the line width of the edge wiring 311 is further reduced, even if the driving backplane is spliced with another driving backplane designed based on the concept of the present disclosure, the distance between the two lamp areas 50 at the outermost edges of the two driving backplanes can still be ensured to be equal to the distance between the two adjacent lamp areas 50 in a single driving backplane, thereby ensuring display uniformity. The specific number of the plurality of light zones 50 can be set according to actual application requirements and is not limited here.
[0062] In the embodiment of the present disclosure, Figure 8 As shown, along the direction away from the base substrate 10, the conductive layer 21 of the pixel driving circuit 20 includes a first gate layer 211, an active layer 212, a second gate layer 213 and a first source-drain electrode layer 214 arranged in sequence; the driving backplane includes an insulating layer 60 and a second source-drain electrode layer 70 arranged in sequence on the side of the first source-drain electrode layer 214 away from the base substrate 10; the transfer electrode 40 is located in the first source-drain electrode layer 214, and the potential wiring 31 and the binding electrode 32 are located in the second source-drain electrode layer 70.
[0063] In the specific implementation process, Figure 8As shown, the driving backplane also includes a buffer layer 80 disposed between the first gate layer 211 and the active layer 212, a gate insulating layer 90 disposed between the active layer 212 and the second gate layer 213; an interlayer insulating layer 91 disposed between the second gate layer 213 and the first source-drain electrode layer 214; an insulating layer 60 disposed between the first source-drain electrode layer 214 and the second source-drain electrode layer 70 includes a first flat layer 61 and a first passivation layer 62 disposed sequentially away from the base substrate 10; and a second passivation layer 63, a second flat layer, and a third passivation layer 65 disposed sequentially away from the base substrate 10 on the second source-drain electrode layer 70. Of course, for the driving backplane provided in the embodiment of the present disclosure, in addition to the above-mentioned related film layers, other film layer structures can also be provided according to actual application needs, which are not limited here.
[0064] Moreover, the transfer electrode 40 is located in the first source-drain electrode layer 214, and the potential wiring 31 and the binding electrode 32 are located in the second source-drain electrode layer 70. Accordingly, the first source-drain electrode layer 214 can be used to prepare the pattern of the transfer electrode 40 in the same layer and material, and the second source-drain electrode layer 70 can be used to prepare the pattern of the potential wiring 31 and the pattern of the binding electrode 32 in the same layer and material, thereby simplifying the manufacturing process and reducing the manufacturing cost.
[0065] In the embodiment of the present disclosure, the edge routing 311 is intermittently arranged along the extension direction of the outermost edge of the wiring layer 30 to form a plurality of intermittent portions 310 , and each of the intermittent portions 310 is electrically connected via a transfer electrode 40 formed by the first source-drain electrode layer 214 .
[0066] In the specific implementation process, combined with Fig. 9 As shown, along the extension direction of the outermost edge of the wiring layer 30, as shown by the arrow X in the figure, the edge wiring 311 is discontinuously arranged to form a plurality of discontinuous portions 310, and each discontinuous portion 310 is electrically connected through the transfer electrode 40 formed by the first source-drain electrode layer 214. In this way, while reducing the occupancy rate of the edge space by the edge wiring 311, the signal transmission performance of the driving backplane is guaranteed.
[0067] In one exemplary embodiment, the orthographic projection of the outermost edge of the pixel driving circuit 20 on the base substrate 10 overlaps with the orthographic projection of the same side edge of the first source-drain electrode layer 214 on the base substrate 10. In other words, the outermost edge of the first source-drain electrode layer 214 is the outermost edge on the same side of the pixel driving circuit 20.
[0068] In order to clearly illustrate the inventive concept of the present disclosure, a corresponding explanation is given in conjunction with a specific layout. Figures 10 to 15 As shown, Fig.10 for Figure 2 The pattern of the first gate layer 211 in the middle region Q, Fig.11 for Figure 2 The pattern of the active layer 212 in the middle region Q, Fig.12 for Figure 2 The pattern of the second gate layer 213 in the middle region Q, Fig.13 for Figure 2 The pattern of the first source-drain electrode layer 214 in the middle region Q, Fig.14 for Figure 2 The pattern of the second source-drain electrode layer 70 in the middle region Q, Fig.15 for Figure 2 The pattern after the relevant conductive layers 21 are superimposed in the middle region Q. It should be noted that, in one exemplary embodiment, Figures 10 to 13 The structure in the dotted box actually corresponds to the smallest repeating unit of the pixel driving circuit 20, which is set corresponding to two sub-pixels. Accordingly, area Q is actually set corresponding to 2*12 sub-pixels. If each pixel includes 3 sub-pixels including red sub-pixels, green sub-pixels and blue sub-pixels, it is set corresponding to 2*4 pixels. In the actual manufacturing process, the pixel driving circuit 20 corresponding to 2*12 sub-pixels can be used as the basic inward shift unit, and the center of the pixel driving circuit 20 corresponding to the 24 sub-pixels can be used as the reference for inward shift. The center position remains unchanged before and after the inward shift. In this way, the space occupied by the driving backplane at the edge is reduced, which provides the possibility for subsequent splicing while taking into account the electrostatic protection capability. Among them, along Fig.15 The schematic diagram of the cross-sectional structure in the direction indicated by NN can be as follows Figure 8 As shown, the introduction of the relevant structural membrane layers refers to the description of the aforementioned relevant parts and will not be repeated here.
[0069] In the embodiment of the present disclosure, the distance between the outermost edge of the wiring layer 30 and the edge on the same side of the substrate 10 is in the range of 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the substrate 10 is in the range of 180 μm to 220 μm. Exemplarily, the distance between the outermost edge of the wiring layer 30 and the edge on the same side of the substrate 10 is 159 μm, and the distance between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the substrate 10 is 200 μm. Of course, the specific distance value between the outermost edge of the wiring layer 30 and the edge on the same side of the substrate 10, and the specific distance value between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the substrate 10 can also be set according to actual application needs, and are not limited here.
[0070] Based on the same public concept, Fig.16As shown, the embodiment of the present disclosure further provides a display panel, which includes a driving backplane 100 as described in any of the above items, and a plurality of micro-light emitting diodes 200 bound to the driving backplane 100. The plurality of micro-light emitting diodes 200 can be set according to actual application needs, which is not limited here. The principle of solving the problem by the display panel is similar to that of the aforementioned driving backplane 100, so the implementation of the display panel can refer to the implementation of the aforementioned driving backplane 100, and the repeated parts will not be repeated.
[0071] In the specific implementation process, the display panel provided by the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display panel should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations of the present invention.
[0072] Based on the same public concept, Fig.17 As shown, the embodiment of the present disclosure further provides a spliced display device, which includes a plurality of display panels 1000 as described above. The principle of solving the problem by the spliced display device is similar to that of the aforementioned driving backplane 100, so the implementation of the spliced display device can refer to the implementation of the aforementioned driving backplane 100, and the repeated parts will not be repeated.
[0073] It should be noted that the inventors have found in actual research that in order to achieve a narrow frame design for a single driver backplane, or even seamless splicing between driver backplanes, the design space at the edge of the driver backplane is often smaller than that within the surface. However, during the production process, there will be cutting paths and grinding lines at the edge of the driver backplane. Once there are any circuits under them, there will be risks of film breakage, short circuits, and reliability.
[0074] In one exemplary embodiment, two drive backplanes are used as an example. Fig.18 As shown, the circular structure represents a single micro-LED. In order to ensure that the distance between the two micro-LEDs located at the edge of the two spliced drive backplanes is consistent with the set distance within the surface of a single drive backplane (i.e., d1=d2), while leaving space for cutting paths and grinding lines, the space left for pixel drive circuits and potential wiring will be relatively reduced. In the embodiment of the present disclosure, the gaps between the pixel drive circuits corresponding to multiple sub-pixels can be merged to free up more space at the edge of the drive backplane. Moreover, in the embodiment of the present disclosure, the outermost edge of the pixel drive circuit is farther away from the same side edge of the substrate than the edge of the wiring layer, which is equivalent to the pixel drive circuit moving into the surface of the single drive backplane. As shown in FIG. Fig.19 and Fig. 20 As shown, Fig.19The figure shows a simplified top view of the structure before the inward movement. Fig. 20 The simplified schematic diagram of the top view of the structure after the inward shift is shown, and the dotted box A and the dotted box B represent the edge space; in one of the exemplary embodiments, taking the pixel driving circuit corresponding to 2*12 sub-pixels as the basic unit as an example, the edge space is small before the inward shift, and it is easy to damage the circuit in the production process, reducing the production yield; the edge space after the inward shift is effectively improved compared with that before the inward shift. In the disclosed embodiment, although the edge space is still relatively small and the line width of the edge routing is smaller than that of the middle routing, the inward shift of the pixel driving circuit makes the outermost edge of the wiring layer closer to the same side edge of the substrate, and the wiring layer can cover the pixel driving circuit to a certain extent, so that ESD can be effectively derived through the wiring layer, thereby improving the production yield.
[0075] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.
[0076] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.
Claims
1. A driving backplane, wherein: include: substrate substrate; A pixel driving circuit located on the substrate; A wiring layer located on a side of the pixel driving circuit away from the substrate, the wiring layer comprising a pattern of potential wiring and binding electrodes, the binding electrodes being used to bind the micro light emitting diodes; Wherein, the distance between the outermost edge of the wiring layer and the edge of the substrate on the same side is smaller than the distance between the outermost edge of the pixel driving circuit and the edge of the substrate on the same side.
2. The driving backplane according to claim 1, wherein: It also includes a switching electrode located between the potential wiring and the base substrate and electrically connected to the potential wiring and the pixel driving circuit respectively. The orthographic projection of the potential wiring on the base substrate and the orthographic projection of the switching electrode on the base substrate are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.
3. The driving backplane according to claim 2, wherein: The potential wiring includes an outermost edge wiring and a middle wiring located in a middle area, and the line width of the edge wiring is smaller than the line width of the middle wiring.
4. The driving backplane according to claim 3, wherein: The binding electrode located at the outermost edge of the wiring layer is arranged flush with the edge wiring on the same side.
5. The driving backplane according to any one of claims 1 to 4, wherein: The base substrate is divided into a plurality of lamp areas arranged in an array, wherein two adjacent lamp areas in the plurality of lamp areas are arranged at equal distances, and each of the lamp areas is configured to be electrically connected to a corresponding micro-LED through the potential wiring and the binding electrode in the corresponding area.
6. The driving backplane according to claim 5, wherein: Along the direction away from the base substrate, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer and a first source-drain electrode layer arranged in sequence; the driving backplane includes an insulating layer and a second source-drain electrode layer arranged in sequence on the side of the first source-drain electrode layer away from the base substrate; the transfer electrode is located in the first source-drain electrode layer, and the potential routing and the binding electrode are located in the second source-drain electrode layer.
7. The driving backplane according to claim 6, wherein: Along the extension direction of the outermost edge of the wiring layer, the edge routing is discontinuously arranged to form a plurality of discontinuous portions, and each of the discontinuous portions is electrically connected via a transfer electrode formed by the first source-drain electrode layer.
8. The driving backplane according to claim 7, wherein: The orthographic projection of the outermost edge of the pixel driving circuit on the base substrate is overlapped with the orthographic projection of the same side edge of the first source-drain electrode layer on the base substrate.
9. The driving backplane according to any one of claims 1 to 8, wherein: The distance between the outermost edge of the wiring layer and the same side edge of the base substrate ranges from 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit and the same side edge of the base substrate ranges from 180 μm to 220 μm.
10. A display panel, wherein: include: A driving backplane as described in any one of claims 1 to 9, and a plurality of micro light emitting diodes bound to the driving backplane.
11. A spliced display device, wherein: include: A plurality of display panels as claimed in claim 10.