Display device

Abstract

A display device having an aperture ratio, providing high resolution and improved light emission quality, and including: a substrate; a first driving thin film transistor (TFT) and a first storage capacitor for emitting light of a first color and on the substrate; a data wiring unit including a first data line, a second data line, and a third data line on a first side of the first storage capacitor, extending in a first direction, and spaced apart from each other by a predetermined distance in a second direction crossing the first direction; a driving voltage line located on a second side of the first storage capacitor and extending in the first direction; and a first pixel electrode electrically connected to the first driving TFT.

Description

[0001] This application is a divisional application of the patent application with application number 201910958321.5 and title “Display Device” filed on October 10, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] Korean Patent Application No. 10-2018-0120609, entitled “Display Apparatus”, filed on October 10, 2018 in the Korean Intellectual Property Office is hereby incorporated by reference in its entirety. Technical Field

[0004] One or more embodiments relate to a display device. Background Art

[0005] An organic light-emitting display device generally includes a thin film transistor (TFT) and an organic light-emitting device on a substrate. The organic light-emitting device emits light by itself. Such an organic light-emitting display device is used in display units of various sizes, such as for small products such as mobile phones, or for large products such as televisions.

[0006] There is a demand for display devices with high resolution. However, in display devices according to the related art, the aperture ratio is reduced by pixel arrangement, and as the resolution of the display device increases, the light emission quality decreases due to an increase in the load applied to the wiring. Summary of the invention

[0007] According to one or more embodiments, a display device includes: a substrate; a first driving thin film transistor (TFT) and a first storage capacitor for emitting light of a first color and located on the substrate; a data wiring unit including a first data line, a second data line, and a third data line located on a first side of the first storage capacitor, extending along a first direction and spaced apart from each other by a predetermined distance along a second direction intersecting the first direction; a driving voltage line located on a second side of the first storage capacitor and extending along the first direction; and a first pixel electrode electrically connected to the first driving TFT.

[0008] On a plane, the first pixel electrode may have a short axis in the first direction and a long axis in the second direction.

[0009] The first pixel electrode may overlap the data wiring unit.

[0010] The first pixel electrode may overlap the first data line, the second data line, and the third data line.

[0011] The display device may further include a first switching TFT for emitting light of a first color and connected to the first data line.

[0012] The display device may further include a common voltage line located at a second side of the first storage capacitor, spaced apart from the driving voltage line by a predetermined distance, and extending in the first direction.

[0013] The display device may further include a first conductive layer under the common voltage line and connected to the common voltage line via the contact hole.

[0014] The display device may further include a second conductive layer located under the driving voltage line and connected to the driving voltage line via the contact hole.

[0015] The first conductive layer and the second conductive layer may include the same material.

[0016] The display device may further include an initialization voltage line located between the driving voltage line and the common voltage line and extending along the first direction.

[0017] The display device may further include: a second driving TFT for emitting light having a second color, a second storage capacitor, and a second pixel electrode electrically connected to the second driving TFT; and a third driving TFT for emitting light having a third color, a third storage capacitor, and a third pixel electrode electrically connected to the third driving TFT, wherein, on a plane, the second storage capacitor and the third storage capacitor are located between the data wiring unit and the driving voltage line.

[0018] The driving voltage line may supply the same driving voltage to the first driving TFT, the second driving TFT, and the third driving TFT.

[0019] Each of the second pixel electrode and the third pixel electrode may have a short axis in the first direction and a long axis in a second direction crossing the first direction, and extend in the second direction.

[0020] The display device may further include a scan line and a sensing line extending in the second direction, wherein the scan line does not overlap the first pixel electrode.

[0021] The display device may further include: a first extension line extending from the scan line in a first direction; and a first switching TFT including a first switching semiconductor layer for emitting light of a first color, a second switching TFT including a second switching semiconductor layer for emitting light of a second color, and a third switching TFT including a third switching semiconductor layer for emitting light of a third color, wherein at least a portion of the first extension line overlaps with the first switching semiconductor layer, the second switching semiconductor layer and the third switching semiconductor layer.

[0022] The display device may further include: a second extension line extending from the sensing line in the first direction; and a first sensing TFT including a first sensing semiconductor layer for emitting light of a first color, a second sensing TFT including a second sensing semiconductor layer for emitting light of a second color, and a third sensing TFT including a third sensing semiconductor layer for emitting light of a third color, wherein at least a portion of the second extension line overlaps with the first sensing semiconductor layer, the second sensing semiconductor layer, and the third sensing semiconductor layer.

[0023] The display device may further include an insulating layer, the insulating layer including: a first opening covering an edge of the first pixel electrode and exposing a central portion of the first pixel electrode, a second opening covering an edge of the second pixel electrode and exposing a central portion of the second pixel electrode, and a third opening covering an edge of the third pixel electrode and exposing a central portion of the third pixel electrode, wherein a width of the insulating layer between the first opening and the second opening in the first direction is the same as a width of the insulating layer between the second opening and the third opening in the first direction.

[0024] The display device may further include: an intermediate layer including a first color emission layer located on the first pixel electrode; a counter electrode located on the intermediate layer; and an auxiliary electrode located on a first side or a second side of the first pixel electrode and electrically connected to a common voltage line, wherein the auxiliary electrode is electrically connected to the counter electrode.

[0025] The insulating layer may further include a first hole exposing a central portion of the auxiliary electrode, and the intermediate layer may further include a second hole exposing at least a portion of the auxiliary electrode via the first hole, and the auxiliary electrode may be electrically connected to the counter electrode via the first and second holes.

[0026] According to one or more embodiments, a display device includes a pixel unit, the pixel unit including a first pixel for emitting light of a first color, a second pixel for emitting light of a second color, and a third pixel for emitting light of a third color. The pixel unit may further include a storage unit, the storage unit including: a first storage capacitor for emitting light of the first color, a second storage capacitor for emitting light of the second color, and a third storage capacitor for emitting light of the third color. The data wiring unit may be located at a first side of the storage unit, extending along a first direction, and including a first data line for transmitting a data signal to the first pixel, a second data line for transmitting a data signal to the second pixel, and a third data line for transmitting a data signal to the third pixel. The driving voltage line may be located at a second side of the storage unit, extending along the first direction, and supplying a driving voltage to the first pixel, the second pixel, and the third pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0028] Figure 1 A display device according to an embodiment is shown;

[0029] Figure 2 An equivalent circuit diagram of one pixel of a display device according to an embodiment is shown;

[0030] Figure 3 An equivalent circuit diagram of a pixel of a display device according to another embodiment is shown;

[0031] Figure 4 Shown include Figure 3 A layout diagram of a pixel unit of a pixel circuit;

[0032] Figures 5 to 8 Shows Figure 4 A layout diagram of a pixel circuit according to components of each layer;

[0033] Fig. 9 A cross-sectional view showing a stacked structure of a pixel of a display device according to an embodiment; and

[0034] Fig.10 A layout diagram of a pixel unit including a pixel circuit of a display device according to another embodiment is shown. DETAILED DESCRIPTION

[0035] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The effects and features of the present disclosure and the ways to achieve them will become apparent by referring to the embodiments that will be described in detail later with reference to the drawings. However, the present disclosure is not limited to the following embodiments, but can be embodied in various forms.

[0036] Hereinafter, embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and detailed descriptions thereof will be omitted.

[0037] It should be understood that although the terms "first", "second", etc. may be used to describe various components herein, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] It should also be understood that the terms "including" and / or "comprising" used herein indicate the presence of the features or components, but do not exclude the presence or addition of one or more other features or components. It should be understood that when a layer, region or component is referred to as being "formed on another layer, region or component", it can be directly or indirectly formed on the other layer, region or component. That is, for example, there may be intermediate layers, regions or components.

[0039] For convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for convenience of explanation, the following embodiments are not limited thereto.

[0040] The x-axis, y-axis and z-axis are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other but intersect each other. In addition, when two elements overlap each other, this means that the two constituent elements overlap each other along the z-axis direction, for example, in a direction perpendicular to the top of the substrate.

[0041] When an embodiment may be implemented differently, the specific process sequence may be performed differently from the sequence described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the sequence described. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Expressions such as "at least one" when located after a list of elements modify the entire list of elements rather than modifying a single element in the list.

[0042] Figure 1 is a plan view of a display device according to an embodiment. Figure 1 , the display device includes a substrate 100. The substrate 100 has a display area DA and a peripheral area PA outside the display area DA.

[0043] A pixel unit PXU including a plurality of display devices such as an organic light emitting device (OLED) may be arranged in a display area DA of a substrate 100. Each of the pixel units PXU may include at least one pixel PX. Each of the pixel units PXU according to the current embodiment includes a plurality of pixels PX1, PX2, and PX3. Each of the plurality of pixels PX1, PX2, and PX3 may emit light having different colors. For example, a first pixel PX1 may emit light of a first color, a second pixel PX2 may emit light of a second color, and a third pixel PX3 may emit light of a third color. In this case, the first color may be red, the second color may be green, and the third color may be blue. According to an embodiment, any three colors that may be combined to produce white light may be used. Moreover, in the current embodiment, a plurality of pixels PX1, PX2, and PX3 of the pixel unit PXU may be arranged in strips. In other embodiments, a plurality of pixels PX1, PX2, and PX3 of the pixel unit PXU may also be arranged in other ways (e.g., honeycomb).

[0044] Various wirings for transmitting electrical signals to be applied to the display area DA may be located in the peripheral area PA of the substrate 100. Hereinafter, for convenience, a display device including an OLED as a display element will be described, but the arrangements herein may be applicable to other types of display devices.

[0045] Figure 2 and Figure 3 is an equivalent circuit of one pixel of the display device according to the embodiment.

[0046] See also Figure 2 , the pixel PX includes a pixel circuit PC and a display device connected to the pixel circuit PC. Figure 2 The pixel PX is one of the plurality of pixels PX1, PX2, and PX3. Figure 2 In FIG. 1 , an OLED is shown as a display device. The pixel circuit PC may include a first thin film transistor (TFT) T1, a second TFT T2, and a storage capacitor Cst. Figure 2 In the pixel circuit PC, the first TFT T1 and the second TFT T2 are of P type, but may be of N type.

[0047] The first TFT T1 is a driving TFT connected to the driving voltage line PL and the storage capacitor Cst. The first TFT T1 may control a driving current I flowing from the driving voltage line PL through the OLED corresponding to a voltage value stored in the storage capacitor Cst. d . Since the driving current I d , the OLED may emit light having a predetermined brightness. The common voltage ELVSS may be supplied to a counter electrode, such as a cathode, of the OLED.

[0048] The second TFT T2 is a switching TFT connected to the scan line SL and the data line DL. The second TFT T2 may transfer a data voltage input from the data line DL to the first TFT T1 according to a switching voltage input from the scan line SL to the gate electrode of the second TFT T2. The storage capacitor Cst is connected to the second TFT T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transferred from the second TFT T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0049] exist Figure 2 In the embodiment, the pixel circuit PC includes two TFTs and one storage capacitor. In some embodiments, the number of TFTs and the number of storage capacitors may be changed in various ways according to the design of the pixel circuit PC.

[0050] In another embodiment, see Figure 3 , Figure 3 The pixel circuit PC may include a first TFT T1, a second TFT T2, a third TFT T3 and a storage capacitor Cst. Figure 3 In the pixel circuit PC, the first TFT T1, the second TFT T2, and the third TFT T3 are of N-type, but may be of P-type.

[0051] and Figure 2 Similarly, the first TFT T1 is a driving TFT, the second TFT T2 is a switching TFT, and Figure 3 The pixel circuit PC may further include: a compensation circuit including a third TFT T3. The compensation circuit is added to compensate for a threshold voltage of the driving TFT, and may include one or more TFTs.

[0052] The third TFT T3 is a sensing TFT and includes a gate electrode connected to the sensing line SSL, a first connection electrode (i.e., a source electrode connected to the reference line RL), and a second connection electrode (i.e., a drain electrode connected to the OLED). The third TFT T3 operates to supply an initialization voltage (or a sensing voltage) transmitted via the reference line RL to the sensing node of the first TFT T1 or to sense a voltage or current of the sensing node of the first TFT T1 or the reference line RL.

[0053] Depending on the configuration of the external compensation algorithm (or compensation circuit), the operation time of the third TFT T3 may be equal to, similar to, or different from the operation time of the second TFT T2. That is, as in the present embodiment, the second TFT T2 may have a gate electrode connected to the scan line SL, and the third TFT T3 may have a gate electrode connected to the sensing line SSL. In another embodiment, the scan line SL connected to the gate electrode of the second TFT T2 and the sensing line SSL connected to the gate electrode of the third TFT T3 may be connected to each other so as to be shared.

[0054] Hereinafter, a pixel PX of a display device according to an embodiment will be described. Figure 3 The case of the pixel circuit PC. Figure 4 Yes Figure 3 Layout diagram of the pixel unit PXU of the pixel circuit PC. Figures 5 to 8 It is stacked along the stacking direction (z-axis direction or third direction) Figure 4 A layout diagram of components of a pixel circuit, and Fig. 9 is a cross-sectional view of a stacked structure of a pixel of a display device according to an embodiment. Figure 4 The detailed structure of the pixel unit PXU shown in FIG. Figures 5 to 9 to describe.

[0055] Figures 5 to 8 Each of the figures shows the arrangement of wiring, electrodes, and semiconductor layers formed in the same layer. The insulating layer may be located Figures 5 to 8 For example, the gate insulating layer (see Fig. 9 103) Insert in Figure 5 The layers and Figure 6 between the layers, and the interlayer insulation layer (see Fig. 9 105) is located in Figure 6 The layers and Figure 7 between the layers and planarize the insulating layer (see Fig. 9 107) is located in Figure 7 The layers and Figure 8 Insulating layer used to define the emission area of ​​the pixel (see Fig. 9 109) is located in Figure 8 On the layer shown in . Figures 5 to 8 The layers shown in the drawings may be electrically connected to each other through contact holes defined in at least a portion of the above-mentioned insulating layer.

[0056] See also Figure 4, the pixel unit PXU includes a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a storage capacitor and one or more TFTs. In the present embodiment, the first pixel PX1 may include: a first driving TFT T11 including a first driving semiconductor layer ACT11, a first driving gate electrode G11, and a first driving connection electrode A11; a first switching TFT T12 including a first switching semiconductor layer ACT12, a first switching gate electrode G12, and a first switching connection electrode A12; and a first sensing TFT T13 including a first sensing semiconductor layer ACT13, a first sensing gate electrode G13, and a first sensing connection electrode A13.

[0057] The second pixel PX2 may include: a second driving TFT T21 including a second driving semiconductor layer ACT21, a second driving gate electrode G21, and a second driving connection electrode A21; a second switching TFT T22 including a second switching semiconductor layer ACT22, a second switching gate electrode G22, and a second switching connection electrode A22; and a second sensing TFT T23 including a second sensing semiconductor layer ACT23, a second sensing gate electrode G23, and a second sensing connection electrode A23.

[0058] The third pixel PX3 may include: a third driving TFT T31 including a third driving semiconductor layer ACT31, a third driving gate electrode G31, and a third driving connection electrode A31; a third switching TFT T32 including a third switching semiconductor layer ACT32, a third switching gate electrode G32, and a third switching connection electrode A32; and a third sensing TFT T33 including a third sensing semiconductor layer ACT33, a third sensing gate electrode G33, and a third sensing connection electrode A33. The "connection electrode" may be a source electrode or a drain electrode.

[0059] The pixel unit PXU includes a data wiring unit 150 extending in a column direction (y direction or first direction) and applying a data signal, a common voltage ELVSS, an initialization voltage, and a driving voltage ELVDD, respectively, a common voltage line 131, an initialization voltage line 133, and a driving voltage line 135. The initialization voltage line 133 may be connected to the third TFT T3 and may operate as a reference line RL (see Figure 3 The pixel unit PXU includes a scan line 121 and a sense line 123 crossing the data wiring unit 150, applying a scan signal and a sense signal respectively, and extending in a row direction (x direction or second direction).

[0060] In the current embodiment, the data wiring unit 150 includes a first data line 151 for supplying a data signal to the first pixel PX1, a second data line 152 for supplying a data signal to the second pixel PX2, and a third data line 153 for supplying a data signal to the third pixel PX3. The data wiring unit 150 may be located at a first side of the pixel unit PXU. The driving voltage line 135 is not provided separately in each pixel, but may be a single wiring that simultaneously applies the driving voltage ELVDD to the first pixel PX1, the second pixel PX2, and the third pixel PX3. Therefore, space may be used more efficiently to provide high resolution.

[0061] The pixel PX includes a TFT (see Figure 3 T1 to T3 of the TFTs, a storage capacitor Cst, and an OLED electrically connected to the TFTs and the storage capacitor Cst (see Fig. 9 300). Hereinafter, for convenience, a description thereof will be provided according to a stacking order along a stacking direction (z direction or a third direction).

[0062] See also Figure 4 , Figure 5 and Fig. 9 , a first pixel circuit PC1 of a first pixel PX1 includes a first driving TFT T11, a first switching TFT T12, and a first sensing TFT T13; a second pixel circuit PC2 of a second pixel PX2 includes a second driving TFT T21, a second switching TFT T22, and a second sensing TFT T23; and a third pixel circuit PC3 of a third pixel PX3 includes a third driving TFT T31, a third switching TFT T32, and a third sensing TFT T33. Semiconductor layers ACT11, ACT12, ACT13, ACT21, ACT22, ACT23, ACT31, ACT32, and ACT33 (hereinafter, referred to as ACTS) of the first driving TFT T11, the second driving TFT T21, and the third driving TFT T31, the first switching TFT T12, the second switching TFT T22, and the third switching TFT T32, and the first sensing TFT T13, the second sensing TFT T23, and the third sensing TFT T33 are arranged on the same layer.

[0063] The semiconductor layer ACTS is located on a buffer layer 101 on a substrate 100. The substrate 100 may be formed of a glass material, a metal material, or a plastic material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide. The buffer layer 101 may be made of, for example, silicon oxide (SiO x ) and / or an oxide layer such as silicon nitride (SiN x )'s nitride layer, etc. are formed.

[0064] The semiconductor layer ACTS may include polycrystalline silicon. Alternatively, the semiconductor layer ACTS may include amorphous silicon or a GIZO layer [(In 2 O 3 ) a (Ga 2 O 3 ) b (ZnO) c

[0063] (wherein a, b, and c are real numbers satisfying the conditions a≥0, b≥0, c>0, respectively) an oxide semiconductor layer, etc. Hereinafter, for convenience, the semiconductor layer ACTS including polycrystalline silicon will be described.

[0065] The semiconductor layer ACTS may include a channel region having a source region and a drain region on both sides of the channel region. In an example, the source region and the drain region may be doped with impurities, such as N-type impurities or P-type impurities. The source region and the drain region may be a source electrode and a drain electrode, respectively, and may be connected to Figure 7 layer.

[0066] The first driving semiconductor layer ACT11 may include a first driving channel region CA11 and a first driving source region SA11 and a first driving drain region DA11 on both sides of the first driving channel region CA11. The first switching semiconductor layer ACT12 may include a first switching channel region CA12 and a first switching source region SA12 and a first switching drain region DA12 on both sides of the first switching channel region CA12. The first sensing semiconductor layer ACT13 may include a first sensing channel region CA13 and a first sensing source region SA13 and a first sensing drain region DA13 on both sides of the first sensing channel region CA13.

[0067] The second driving semiconductor layer ACT21 may include a second driving channel region CA21 and a second driving source region SA21 and a second driving drain region DA21 on both sides of the second driving channel region CA21. The second switching semiconductor layer ACT22 may include a second switching channel region CA22 and a second switching source region SA22 and a second switching drain region DA22 on both sides of the second switching channel region CA22. The second sensing semiconductor layer ACT23 may include a second sensing channel region CA23 and a second sensing source region SA23 and a second sensing drain region DA23 on both sides of the second sensing channel region CA23.

[0068] The third driving semiconductor layer ACT31 may include a third driving channel region CA31 and a third driving source region SA31 and a third driving drain region DA31 on both sides of the third driving channel region CA31. The third switching semiconductor layer ACT32 may include a third switching channel region CA32 and a third switching source region SA32 and a third switching drain region DA32 on both sides of the third switching channel region CA32. The third sensing semiconductor layer ACT33 may include a third sensing channel region CA33 and a third sensing source region SA33 and a third sensing drain region DA33 on both sides of the third sensing channel region CA33.

[0069] Including metal shielding (see Fig. 9 The shielding layer 217 may be located below the semiconductor layer ACTS, for example, between the substrate 100 and the semiconductor layer ACTS. The shielding layer 217 is used to block light incident on the substrate 100 in the top emission display device. The buffer layer 101 may be located between the semiconductor layer ACTS and the shielding layer 217.

[0070] The gate insulating layer 103 may be located on the semiconductor layer ACTS. The gate insulating layer 103 may include an inorganic material, such as an oxide and a nitride. For example, the gate insulating layer 103 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 )wait.

[0071] See also Figure 4 , Figure 6 and Fig. 9 , the scan line 121, the sensing line 123, the first lower electrode layer 141, the second lower electrode layer 142, and the third lower electrode layer 143, and the first conductive layer 125 and the second conductive layer 127 are located on the gate insulating layer 103. The scan line 121, the sensing line 123, the first lower electrode layer 141, the second lower electrode layer 142, and the third lower electrode layer 143, and the first conductive layer 125 and the second conductive layer 127 may include the same material. For example, the scan line 121, the sensing line 123, the first lower electrode layer 141, the second lower electrode layer 142, and the third lower electrode layer 143, and the first conductive layer 125 and the second conductive layer 127 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single layer or a multi-layer structure.

[0072] Portions or protruding portions of the scan line 121 , the sensing line 123 , the first lower electrode layer 141 , the second lower electrode layer 142 , and the third lower electrode layer 143 may correspond to gate electrodes of the TFTs T11 to T33 .

[0073] Specifically, the scan line 121 extends in the row direction (x direction or the second direction), and the first extension line 122 extending from the scan line 121 in the column direction (y direction or the first direction) is located at a first side of the scan line 121. At least a portion of the first extension line 122 may overlap with the first switching semiconductor layer ACT12, the second switching semiconductor layer ACT22, and the third switching semiconductor layer ACT32. The portion of the first extension line 122 overlapping with the first switch channel region CA12 corresponds to the first switch gate electrode G12, the portion of the first extension line 122 overlapping with the second switch channel region CA22 corresponds to the second switch gate electrode G22, and the portion of the first extension line 122 overlapping with the third switch channel region CA32 corresponds to the third switch gate electrode G32.

[0074] The sensing line 123 extends in the row direction (x direction or second direction), and the second extension line 124 extending from the sensing line 123 in the column direction (y direction or first direction) is located at one side of the sensing line 123. At least a portion of the second extension line 124 may overlap with the first sensing semiconductor layer ACT13, the second sensing semiconductor layer ACT23, and the third sensing semiconductor layer ACT33. The portion of the second extension line 124 overlapping with the first sensing channel region CA13 corresponds to the first sensing gate electrode G13, and the portion of the second extension line 124 overlapping with the second sensing channel region CA23 corresponds to the second sensing gate electrode G23, and the portion of the second extension line 124 overlapping with the third sensing channel region CA33 corresponds to the third sensing gate electrode G33.

[0075] In this way, the first switch gate electrode G12, the second switch gate electrode G22, and the third switch gate electrode G32 are formed by the first extension line 122, and the first sensing gate electrode G13, the second sensing gate electrode G23, and the third sensing gate electrode G33 are formed by the second extension line 124, so that the space can be reduced compared with the case where the gate electrodes are formed by different wirings. Therefore, a pixel suitable for high resolution can be realized.

[0076] The first lower electrode layer 141, the second lower electrode layer 142, and the third lower electrode layer 143 may be located between the first extension line 122 and the second extension line 124 along the row direction (x direction or second direction). The portion of the first lower electrode layer 141 overlapping with the first driving channel region CA11 corresponds to the first driving gate electrode G11. The portion of the second lower electrode layer 142 overlapping with the second driving channel region CA21 corresponds to the second driving gate electrode G21. The portion of the third lower electrode layer 143 overlapping with the third driving channel region CA31 corresponds to the third driving gate electrode G31.

[0077] The first lower electrode layer 141 is a driving gate electrode and is also used as a lower storage plate of the first storage capacitor Cst1. The second lower electrode layer 142 is a driving gate electrode and is also used as a lower storage plate of the second storage capacitor Cst2. The third lower electrode layer 143 is a driving gate electrode and is also used as a lower storage plate of the third storage capacitor Cst3.

[0078] The first conductive layer 125 and the second conductive layer 127 may be respectively connected to the conductive layer 125 and the conductive layer 127 to be described later. Figure 7 The common voltage line 131 and the driving voltage line 135 are in contact with each other, so that a phenomenon called power supply voltage drop (IR drop) in a large area display device can be alleviated.

[0079] The interlayer insulating layer 105 is located on the scan line 121, the sensing line 123, the first lower electrode layer 141, the second lower electrode layer 142 and the third lower electrode layer 143, and the first conductive layer 125 and the second conductive layer 127. The interlayer insulating layer 105 may include an inorganic material including oxide or nitride. For example, the interlayer insulating layer 105 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO 2 ) etc. The interlayer insulating layer 105 may include a layer formed of the above-mentioned inorganic insulating material and a layer formed of the above-mentioned organic insulating material.

[0080] See also Figure 4 , Figure 7 and Fig. 9, the common voltage line 131, the initialization voltage line 133, the driving voltage line 135, the data wiring unit 150, and the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 are located on the interlayer insulating layer 105. The common voltage line 131, the initialization voltage line 133, the driving voltage line 135, the data wiring unit 150, and the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 may include the same material. For example, the common voltage line 131, the initialization voltage line 133, the driving voltage line 135, the data wiring unit 150, and the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 may include Mo, Al, Cu, Ti, etc., and may have a single-layer or multi-layer structure. In an example, the common voltage line 131 , the initialization voltage line 133 , the driving voltage line 135 , the data wiring unit 150 , and the first, second, and third upper electrode layers 161 , 162 , and 163 may have a multi-layer structure of Ti / Al / Ti.

[0081] The common voltage line 131, the initialization voltage line 133, the driving voltage line 135, and the data wiring unit 150 are positioned to extend in the column direction (y direction or first direction). The data wiring unit 150 may be located at a first side of the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163, for example, spaced apart from the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 in the +x direction, and the common voltage line 131, the initialization voltage line 133, and the driving voltage line 135 may be located at a second side of the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163, for example, spaced apart from the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 in the -x direction. In other words, the first upper electrode layer 161 , the second upper electrode layer 162 , and the third upper electrode layer 163 may be located between the data wiring unit 150 and the common voltage line 131 , the initialization voltage line 133 , and the driving voltage line 135 along the x-direction.

[0082] The common voltage line 131 is connected to the first conductive layer 125 via a contact hole 131b passing through the interlayer insulating layer 105. The driving voltage line 135 is connected to the second conductive layer 127 via a contact hole 135b passing through the interlayer insulating layer 105. In this way, the common voltage line 131 and the driving voltage line 135 have a double-layer structure, so that the IR drop phenomenon in a large-area display device can be reduced.

[0083] The initialization voltage line 133 is connected to a source region or a drain region of each of the first, second, and third sensing semiconductor layers ACT13 , ACT23 , and ACT33 via a contact hole 133 a passing through the interlayer insulating layer 105 and the gate insulating layer 103 .

[0084] The driving voltage line 135 is connected to a source region or a drain region of each of the first, second, and third driving semiconductor layers ACT11 , ACT21 , and ACT31 via a contact hole 135 a passing through the interlayer insulating layer 105 and the gate insulating layer 103 .

[0085] The first upper electrode layer 161 is connected to the source region or drain region of the first driving semiconductor layer ACT11 via a contact hole 161a passing through the interlayer insulating layer 105 and the gate insulating layer 103, and is connected to the source region or drain region of the first sensing semiconductor layer ACT13 via a contact hole 161b. The second upper electrode layer 162 is connected to the source region or drain region of the second driving semiconductor layer ACT21 via a contact hole 162a passing through the interlayer insulating layer 105 and the gate insulating layer 103, and is connected to the source region or drain region of the second sensing semiconductor layer ACT23 via a contact hole 162b. The third upper electrode layer 163 is connected to the source region or drain region of the third driving semiconductor layer ACT31 via a contact hole 163a passing through the interlayer insulating layer 105 and the gate insulating layer 103, and is connected to the source region or drain region of the third sensing semiconductor layer ACT33 via a contact hole 163b.

[0086] The first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 are source electrodes or drain electrodes of the first drive TFT T11, the second drive TFT T21, and the third drive TFT T31, and are also used as upper storage plates of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3. Figure 6 The first lower electrode layer 141, the second lower electrode layer 142 and the third lower electrode layer 143 overlap with the first upper electrode layer 161, the second upper electrode layer 162 and the third upper electrode layer 163, respectively, so that the first storage capacitor Cst1, the second storage capacitor Cst2 and the third storage capacitor Cst3 can be formed.

[0087] The data wiring unit 150 extends along the column direction (y direction or first direction) and is connected to the source region or drain region of each of the first switching semiconductor layer ACT12, the second switching semiconductor layer ACT22 and the third switching semiconductor layer ACT32 via a contact hole 150a passing through the interlayer insulating layer 105 and the gate insulating layer 103.

[0088] The data wiring unit 150 includes a first data line 151, a second data line 152, and a third data line 153. The first data line 151, the second data line 152, and the third data line 153 may be spaced apart from each other by a predetermined distance W in a row direction (x direction or second direction). For example, in a 65-inch display device, the distance W between the first data line 151, the second data line 152, and the third data line 153 may be about 2 μm to about 4 μm, but may be implemented differently according to the size of the display device and the number of pixels.

[0089] In the present embodiment, the data wiring unit 150 is located at a first side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, and the driving voltage line 135 is located at a second side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3. Because the first data line 151, the second data line 152, and the third data line 153 are biased toward one side of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3, space utilization can be maximized compared to the case where the first data line 151, the second data line 152, and the third data line 153 are located between pixels.

[0090] The planarization insulating layer 107 is located on the common voltage line 131, the initialization voltage line 133, the driving voltage line 135, the data wiring unit 150, and the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163. The planarization insulating layer 107 may include an organic material such as acrylic resin, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), and the like.

[0091] See also Figure 4 , Figure 8 and Fig. 9 , the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B are located on the planarization insulating layer 107. The first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B are connected to the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163 via the contact hole 320a defined in the planarization insulating layer 107. The first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may be connected to the first upper electrode layer 161, the second upper electrode layer 162, and the third upper electrode layer 163, and may be connected to the source electrode or the drain electrode of the first drive TFT T11, the second drive TFT T21, and the third drive TFT T31.

[0092] Each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may extend in the row direction (x direction or the second direction). That is, on a plane, each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may be provided to have a short axis in the column direction (y direction or the first direction) and a long axis in the row direction (x direction or the second direction).

[0093] Each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may overlap with the data wiring unit 150. That is, each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may overlap with the first data line 151, the second data line 152, and the third data line 153 at the same time. In the present embodiment, each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B overlaps with the first data line 151, the second data line 152, and the third data line 153 at the same time. However, in another embodiment, at least one of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may overlap with the first data line 151, the second data line 152, and the third data line 153 at the same time.

[0094] At least a portion of each of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B overlaps with the driving voltage line 135. Therefore, the capacitance C OLED (See Figure 3 ), so that the amount of voltage change stored in the storage capacitor Cst can be minimized to achieve a stable pixel circuit.

[0095] Meanwhile, the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B are positioned so as not to overlap with the scan line 121. Figure 4 In the embodiment, since the first pixel electrode 320R does not overlap the scan line 121, an increase in a load caused by a capacitance between the first pixel electrode 320R and the scan line 121 can be minimized.

[0096] The first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may be reflective electrodes. For example, the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B may include a reflective layer formed of silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a reflective layer formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO).

[0097] The insulating layer for defining the emission regions EM1, EM2 and EM3 (see Fig. 9 The insulating layer 109 is located on the first pixel electrode 320R, the second pixel electrode 320G and the third pixel electrode 320B. The insulating layer 109 includes a plurality of openings OP1, OP2 and OP3 for defining emission regions EM1, EM2 and EM3, and each of the emission regions EM1, EM2 and EM3 is defined by the first opening OP1, the second opening OP2 and the third opening OP3. For example, the insulating layer 109 may include one or more organic insulating materials, such as polyimide, polyamide, acrylic resin, BCB and phenolic resin, etc.

[0098] See also Figure 8 , the width L1 of the insulating layer 109 between the first opening OP1 and the second opening OP2 in the column direction (y direction or first direction) may be the same as the width L2 of the insulating layer 109 between the second opening OP2 and the third opening OP3 in the column direction (y direction or first direction). In this way, the width of the insulating layer 109 is the same in each pixel, so that the problem of color mixing in the light leakage phenomenon can be effectively solved by the insulating layer 109.

[0099] Fig. 9 1 shows a cross-sectional view of one pixel. The cross-sectional structures of the plurality of pixels PX1, PX2 and PX3 are similar to each other. Therefore, as an example, Fig. 9 A first pixel PX1 is shown.

[0100] See also Fig. 9 , the intermediate layer 310 is located on the first pixel electrode 320R exposed by the insulating layer 109. The intermediate layer 310 may include an emission layer 312. The emission layer 312 may include an organic material including a fluorescent or phosphorescent material that emits red light, green light, blue light, or white light. The intermediate layer 310 may include a small molecular weight organic material, a polymer organic material, and the like.

[0101] Functional layers 311 and 313 , such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL), may optionally be further located under / on the emission layer 312 .

[0102] The counter electrode 330 may be a light-transmitting electrode. For example, the counter electrode 330 may be a transparent or semi-transparent electrode and may be formed of a metal thin film having a low work function including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, and In 2 O 3 etc., can be further located on the metal film.

[0103] Return to see Figure 8 and Fig. 9 The auxiliary electrode 340 is located at the second side of the first pixel electrode 320R, the second pixel electrode 320G, and the third pixel electrode 320B. The auxiliary electrode 340 may be electrically connected to the common voltage line 131 in a downward direction via a contact hole 340a defined in the planarization insulating layer 107, and may be electrically connected to the counter electrode 330 in an upward direction via a contact hole H.

[0104] The contact hole H includes a first hole H1 passing through the insulating layer 109 and a second hole H2 passing through the functional layers 311 and 313 of the intermediate layer 310. For example, the first hole H1 may be formed simultaneously with an opening for exposing each of the pixel electrodes 320R, 320G, and 320B, and the second hole H2 may be formed by laser drilling. When the functional layers 311 and 313 are formed on the entire surface of the substrate 100 similarly to the counter electrode 330, the functional layers 311 and 313 on the auxiliary electrode 340 must be removed so that the auxiliary electrode 340 and the counter electrode 330 can contact each other. Therefore, the second hole H2 may be formed by irradiating the laser onto the functional layers 311 and 313 so that the auxiliary electrode 340 and the counter electrode 330 can be electrically connected to each other.

[0105] The auxiliary electrode 340 may be connected to the counter electrode 330 via a first hole H1 passing through the insulating layer 109 and a second hole H2 passing through the functional layers 311 and 313 except the emission layer 312 in the intermediate layer 310. By the auxiliary electrode 340, an IR drop phenomenon in a large area display device may be alleviated.

[0106] Fig.10 FIG. 1 is a layout diagram of a pixel circuit of a pixel unit PXU′ of a display device according to another embodiment. Fig.10The present embodiment is different from the above-mentioned embodiment in the arrangement of the plurality of pixels PX1', PX2' and PX3', specifically, the arrangement of the first pixel electrode 320R, the second pixel electrode 320G and the third pixel electrode 320B. Fig.10 In the embodiment of the present invention, the first pixel electrode 320R, the second pixel electrode 320G and the third pixel electrode 320B extend along the column direction (y direction or the first direction). The configuration of the layers below the first pixel electrode 320R, the second pixel electrode 320G and the third pixel electrode 320B may be the same as that of the above embodiment.

[0107] This article mainly describes a display device. However, the embodiment is not limited thereto. For example, a method for manufacturing a display device also belongs to the scope of the embodiment.

[0108] As described above, according to the embodiment, a display device by which an aperture ratio can be easily obtained at a high resolution and light emission quality can be improved can be realized.

[0109] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as of the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: substrate; A first capacitor is arranged on the substrate; a first data line arranged at a first side of the first capacitor in a plan view and extending along a first direction; a second data line spaced apart from the first data line along a second direction crossing the first direction; a third data line spaced apart from each of the first data line and the second data line along the second direction; a driving voltage line, arranged on a second side of the first capacitor in the plan view, the driving voltage line being electrically connected to the first capacitor and extending along the first direction; a scanning line extending along the second direction; a first line extending from the scan line in the first direction; as well as a first switching TFT including a first switching semiconductor layer for emitting light having a first color; a second switching TFT including a second switching semiconductor layer for emitting light having a second color; and a third switching TFT including a third switching semiconductor layer for emitting light having a third color, At least a portion of the first line overlaps with the first switching semiconductor layer, the second switching semiconductor layer, and the third switching semiconductor layer. 2 . The display device according to claim 1 , the driving voltage line is spaced apart from the first capacitor in the plan view. 3 . The display device according to claim 1 , further comprising a first driving TFT and a first pixel electrode electrically connected to the first driving TFT.

4. The display device according to claim 3, wherein: The first pixel electrode overlaps the first data line, the second data line, and the third data line.

5. The display device according to claim 3, wherein: The first switch TFT is connected to the first data line. 6 . The display device of claim 3 , further comprising a common voltage line disposed at the second side of the first capacitor, the common voltage line being spaced apart from the driving voltage line in the second direction and extending in the first direction.

7. The display device according to claim 6, wherein: The common voltage line is spaced apart from the first capacitor in the plan view.

8. The display device according to claim 6, further comprising a first conductive layer located below the common voltage line, wherein: The common voltage line is connected to the first conductive layer via a contact hole.

9. The display device according to claim 8, further comprising a second conductive layer located below the driving voltage line, wherein: The driving voltage line is connected to the second conductive layer via a contact hole.

10. The display device according to claim 9, wherein: The first conductive layer and the second conductive layer include the same material.

11. The display device according to claim 6, further comprising: an intermediate layer, located on the first pixel electrode, comprising a first color emission layer; a counter electrode, located on the intermediate layer; as well as an auxiliary electrode, located at the first side or the second side of the first pixel electrode and electrically connected to the common voltage line, Wherein, the auxiliary electrode is electrically connected to the counter electrode.

12. A display device, comprising: substrate; A first driving TFT and a first capacitor are arranged on the substrate; a driving voltage line, arranged on a first side of the first capacitor in a plan view, the driving voltage line being electrically connected to the first capacitor and extending in a first direction; a common voltage line spaced apart from the driving voltage line along a second direction crossing the first direction and extending along the first direction; a first pixel electrode electrically connected to the first driving TFT; an intermediate layer, located on the first pixel electrode, comprising a first color emission layer; a counter electrode, located on the intermediate layer and electrically connected to the common voltage line; as well as a scan line extending in the second direction; a first line extending from the scan line in the first direction; as well as a first switching TFT including a first switching semiconductor layer for emitting light having a first color; a second switching TFT including a second switching semiconductor layer for emitting light having a second color; and a third switching TFT including a third switching semiconductor layer for emitting light having a third color, At least a portion of the first line overlaps with the first switching semiconductor layer, the second switching semiconductor layer, and the third switching semiconductor layer.

13. The display device according to claim 12, wherein: The common voltage line is spaced apart from the first capacitor in the plan view.

14. The display device according to claim 12, further comprising: a first data line, arranged on a second side of the first capacitor in the plan view and extending along the first direction; a second data line spaced apart from the first data line along the second direction; a third data line spaced apart from each of the first data line and the second data line along the second direction, Wherein, the first pixel electrode overlaps with the first data line, the second data line and the third data line.

15. The display device according to claim 14, wherein: The first switch TFT is connected to the first data line.

16. The display device according to claim 14, wherein: The driving voltage line is spaced apart from the first capacitor in the plan view.

17. The display device according to claim 14, further comprising: A second driving TFT, a second capacitor, and a second pixel electrode electrically connected to the second driving TFT arranged on the substrate; as well as a third driving TFT disposed on the substrate, a third capacitor, and a third pixel electrode electrically connected to the third driving TFT, Wherein, in the plan view, the second capacitor and the third capacitor are arranged between the first to third data lines and the driving voltage line.

18. The display device according to claim 17, wherein: The driving voltage line supplies the same driving voltage to each of the first driving TFT, the second driving TFT, and the third driving TFT.

19. The display device according to claim 12, further comprising: an auxiliary electrode, located at the first side or the second side of the first pixel electrode and electrically connected to the common voltage line, Wherein, the auxiliary electrode is electrically connected to the counter electrode.

20. The display device according to claim 19, wherein: The auxiliary electrode overlaps the common voltage line in the plan view.

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