Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, the array substrate is provided with a peripheral area and a display area which are adjacently arranged, and the array substrate comprises a substrate; the plurality of touch electrode block arrays are arranged on the substrate and located in the display area; the plurality of scanning lines are arranged on the substrate in rows; the plurality of data lines are arranged on the substrate in columns, and the plurality of scanning lines and the plurality of data lines are crossed to limit a plurality of pixel units arranged in an array; the shielding metal layer is arranged on the substrate and is different from the scanning lines, the shielding metal layer comprises a plurality of shielding blocks and a plurality of signal lines, and the signal lines are arranged in rows; wherein a disconnection interval is arranged between any two adjacent rows of touch electrode blocks, the signal lines comprise first compensation scanning lines and second compensation scanning lines, the first compensation scanning lines correspond to and are adjacent to the first scanning lines and are connected to the second scanning lines, and the second compensation scanning lines correspond to and are adjacent to the second scanning lines. The second compensation scanning line corresponds to and is adjacent to the second scanning line and is connected to the first scanning line.

Description

Technical Field

[0001] The present invention relates to the field of display panel design, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of science and technology, display devices are widely used in many electronic products, such as mobile phones, tablet computers, watches, cars, etc. Taking a thin film transistor liquid crystal display (TFT LCD) as an example, in order to realize the embedded touch function, the common electrode layer is reused as a touch electrode layer. Specifically, the touch electrode layer includes a plurality of touch electrode blocks arranged in an array in the display area, and there is a disconnection interval between any two adjacent rows of touch electrode blocks. Each touch electrode block corresponds to a plurality of pixel units arranged in an array. In the display stage, the plurality of pixel units share the same touch electrode block as a common electrode. Each row of pixel units is connected to a scan line. During display, the plurality of scan lines sequentially send control signals to the corresponding row of pixel units, and the common electrode receives a common potential signal. Among the plurality of pixel units corresponding to the touch electrode block, except for the first and last rows of pixel units, each row of pixel units can offset the influence of the control signal of the pixel units in the previous row on the common electrode by the control signal of the pixel units in the previous row, and the first and last rows of pixel units cannot offset the influence of the control signal on the common electrode, thus generating horizontal stripes at the junction of the touch electrode blocks. Summary of the invention

[0003] In order to solve the above problem, the present invention provides an array substrate having a peripheral area and a display area arranged adjacent to each other, the array substrate comprising:

[0004] substrate;

[0005] A touch electrode layer, comprising a plurality of touch electrode blocks, wherein the plurality of touch electrode blocks are arranged in an array on the substrate and located in the display area;

[0006] A plurality of scanning lines are arranged in rows on the substrate;

[0007] A plurality of data lines are arranged in rows on the substrate, the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel units arranged in an array, each pixel unit comprising a thin film transistor; and

[0008] A shielding metal layer is disposed on the substrate and is in a different layer from the plurality of scanning lines. The shielding metal layer includes a plurality of shielding blocks and a plurality of signal lines. The plurality of signal lines are arranged in rows. Each shielding block is correspondingly disposed under each thin film transistor and is not connected to the plurality of signal lines.

[0009] There is a disconnection gap between any two adjacent rows of touch electrode blocks, wherein the touch electrode blocks in the first row are located above the disconnection gap, and the touch electrode blocks in the second row are located below the disconnection gap. Among the scan lines corresponding to the touch electrode blocks in the first row, the scan line closest to the disconnection gap is the first scan line, and among the scan lines corresponding to the touch electrode blocks in the second row, the scan line closest to the disconnection gap is the second scan line.

[0010] The plurality of signal lines include a first compensation scan line and a second compensation scan line, wherein the first compensation scan line corresponds to and is adjacent to the first scan line and is connected to the second scan line, and the second compensation scan line corresponds to and is adjacent to the second scan line and is connected to the first scan line.

[0011] In one embodiment of the array substrate of the present invention, the array substrate further includes a gate driving circuit, a first connection structure and a second connection structure located in the peripheral area, the gate driving circuit is connected to the first scan line and the second compensation scan line via the first connection structure, and the gate driving circuit is connected to the second scan line and the first compensation scan line via the second connection structure.

[0012] In one embodiment of the array substrate of the present invention, the first scan line is located in a first metal layer, the first metal layer is located above the shielding metal layer, the first connection structure electrically connects the first scan line, the second compensation scan line and a connecting part of the gate drive circuit, the connecting part is located in a second metal layer, and the second metal layer is located above the first metal layer.

[0013] In an embodiment of the array substrate of the present invention, the second scan line is located in the first metal layer, and the second connection structure electrically connects the second scan line, the first compensation scan line and a connection portion of the gate driving circuit.

[0014] In an embodiment of the array substrate of the present invention, the first connection structure and the second connection structure include transparent conductive layers.

[0015] In one embodiment of the array substrate of the present invention, the first compensation scan line and the second compensation scan line include a first part and a second part that are connected to each other, the first part of the first compensation scan line extends along the row direction and is arranged adjacent to the first scan line, the first part of the second compensation scan line extends along the row direction and is arranged adjacent to the second scan line, the second parts of the first compensation scan line and the second compensation scan line extend along the column direction, the first parts of the first compensation scan line and the second compensation scan line have a first line width d1, and the second parts of the first compensation scan line and the second compensation scan line have a second line width d2, wherein d1<d2.

[0016] In one embodiment of the array substrate of the present invention, the relationship between the first line width d1 and the second line width d2 is: 1.5*d1 <d2<2.5*d1。

[0017] In an embodiment of the array substrate of the present invention, the first compensation scan line and the first scan line do not overlap in the projection direction of the substrate; the second compensation scan line and the second scan line do not overlap in the projection direction of the substrate.

[0018] In one embodiment of the array substrate of the present invention, in the column direction, the first compensation scan line and the first scan line have a first spacing, the shielding block has a first width, and the first spacing is greater than or equal to the first width; or, in the column direction, the line width of the first compensation scan line is not greater than the line width of the first scan line.

[0019] In one embodiment of the array substrate of the present invention, in the column direction, the second compensation scan line and the second scan line have a second spacing, and the second spacing is greater than or equal to the first width; or, in the column direction, the line width of the second compensation scan line is not greater than the line width of the second scan line.

[0020] The present invention also discloses a display panel, comprising:

[0021] An array substrate as described in any one of the above; and

[0022] A color filter substrate, comprising a black matrix layer and a color resist layer, wherein the black matrix layer comprises a plurality of hollow regions arranged in an array, and the color resist layer is located in the plurality of hollow regions;

[0023] The black matrix layer has a first projection range on the array substrate, and projections of the first compensation scanning line and the second compensation scanning line on the color filter substrate are located within the first projection range.

[0024] The present invention further discloses a display device, comprising a backlight module and a display panel, wherein the display panel comprises the array substrate as described in any one of the above items.

[0025] The array substrate, display panel and display device disclosed in the present invention respectively set the first compensation scanning line and the second compensation scanning line for the first row of touch electrode blocks and the second row of touch electrode blocks with disconnected intervals by using a shielding metal layer, so that the first row and the last row of pixel units in each row of touch electrode blocks can offset the influence on the common electrode through the control signals of the second compensation scanning line and the first compensation scanning line, thereby solving the problem of horizontal stripes generated at the junction of the touch electrode blocks.

[0026] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of an array substrate according to an embodiment of the present invention is shown.

[0028] Figure 2 A schematic diagram of the connection structure of the compensation scanning lines of the array substrate according to an embodiment of the present invention is shown.

[0029] Figure 3 A schematic diagram of a cross-sectional structure of an array substrate in one embodiment of the present invention is shown.

[0030] Figure 4 FIG. 4 is a schematic diagram showing a signal timing sequence of a touch electrode block in an embodiment of the present invention.

[0031] Figure 5 A schematic diagram of a display panel according to an embodiment of the present invention is shown.

[0032] Figure 6 A schematic diagram of a display device according to an embodiment of the present invention is shown.

[0033] Wherein, the reference numerals are:

[0034] 10…Array substrate

[0035] 101…Substrate

[0036] 102…Gate drive circuit

[0037] 1021…Connection part

[0038] 103...Pixel unit

[0039] 104 ... first connection structure

[0040] 105…Second connection structure

[0041] 111…first compensation scanning line

[0042] 1111, 1121…Part 1

[0043] 1112, 1122…Part 2

[0044] 112…Second compensation scanning line

[0045] 204a, 204b, 204c, 205a, 205b, 205c...holes

[0046] 11…Touch electrode layer

[0047] 12…Shielding the metal layer

[0048] 13…First metal layer

[0049] 14… Second metal layer

[0050] 15…Transparent conductive layer

[0051] 121…Shielding Block

[0052] TP, TP1, TP2, TP3…Touch electrode block

[0053] AA…Display area

[0054] BA…Nearby Area

[0055] GL…Scan Line

[0056] DL…Data line

[0057] 20…Color filter substrate

[0058] 21…Black matrix layer

[0059] 22…Hollowout area

[0060] 23…Color resist layer

[0061] 24…Second substrate

[0062] 100…Display Panel

[0063] 200…Backlight module

[0064] 1000…Display device DETAILED DESCRIPTION

[0065] The following specific embodiments and accompanying drawings are used to illustrate the embodiments disclosed in the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. However, the contents disclosed below are not intended to limit the scope of protection of the present invention. Without departing from the spirit of the present invention, those skilled in the art can implement the present invention with other different embodiments based on different viewpoints and applications.

[0066] For the sake of clarity, the drawings of the present invention are simplified schematic diagrams to illustrate the basic structure of the present invention. Therefore, the structures shown in the drawings of the present invention are not drawn according to the shape and size ratio of the actual implementation. For example, the size of a specific component is exaggerated for the convenience of explanation.

[0067] In addition, it should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or intermediate components may also exist. In contrast, when a component is referred to as being "directly on" or "directly connected to" another component, there are no intermediate components. As used herein, "connected" can refer to physical and / or electrical connections. Furthermore, "electrically connected" or "coupled" can mean the presence of other components between two components.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as understood by a person of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0069] In addition, it should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, parts, regions, layers and / or parts, these components, parts, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer or part from another component, part, region, layer or part. Therefore, the "first component", "component", "region", "layer" or "part" discussed below may be referred to as a second component, part, region, layer or part without departing from the teachings of this article.

[0070] It should be understood that references in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., mean that the embodiment being described may include certain features, structures, or characteristics, but does not necessarily include these certain features, structures, or characteristics. In addition, such expressions do not refer to the same embodiment. Further, when a certain feature, structure, or characteristic is described in conjunction with an embodiment, it is indicated that it is within the knowledge of those skilled in the art to combine such feature, structure, or characteristic into other embodiments, whether or not it is explicitly described.

[0071] Certain words are used in the specification and subsequent claims to refer to specific modules, components or parts. It should be understood by those of ordinary skill in the art that technical users or manufacturers may refer to the same module, component or part by different nouns or terms. This specification and subsequent claims do not use differences in names as a way to distinguish modules, components or parts, but use differences in the functions of modules, components or parts as the criteria for distinction. "Including" and "including" mentioned throughout the specification and subsequent claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the word "connect" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.

[0072] Furthermore, in the following specification and claims, reference will be made to a number of terms which shall be defined as having the following meanings. The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

[0073] In order to solve the problem that when implementing the embedded touch function, there is a disconnection interval between any two adjacent rows of touch electrode blocks TP, so that among the multiple pixel units corresponding to the touch electrode blocks TP, the first and last rows of pixel units cannot offset the influence of the control signal on the common electrode, thereby generating horizontal stripes at the intersection of the touch electrode blocks TP, please refer to Figure 1 , Figure 1 A schematic diagram of an array substrate in an embodiment of the present invention is shown. The present invention proposes an array substrate 10 having a peripheral area BA and a display area AA arranged adjacent to each other. The array substrate 10 comprises: a substrate 101, a touch electrode layer 11, a plurality of scan lines GL, a plurality of data lines DL and a shielding metal layer 12. The touch electrode layer 11 comprises a plurality of touch electrode blocks TP, and the plurality of touch electrode blocks TP are arranged in an array on the substrate 101 and located in the display area AA. The touch electrode layer 11 is reused as a common electrode and a touch function in the display stage and the touch sensing stage. A plurality of scan lines GL are arranged in rows on the substrate 101, and a plurality of data lines DL are arranged in columns on the substrate 101. The plurality of scan lines and the plurality of data lines DL cross to define a plurality of pixel units 103 arranged in an array, and each pixel unit 103 comprises a thin film transistor (not shown). In one embodiment, the gate of the thin film transistor is electrically connected to the corresponding scan line, the signal of the scan line controls the thin film transistor to turn on or off, the data line DL is electrically connected to the drain of the thin film transistor, and the source of the thin film transistor is connected to the pixel electrode of the pixel unit 103. When the thin film transistor is turned on, an electric field is formed by the voltage difference between the common electrode and the pixel electrode to twist the liquid crystal for display. This is common knowledge in the art and will not be elaborated here.

[0074] In one embodiment, the scan line GL 1(1) To GL 1(m) The scanning line GL electrically connects the first row of pixel units corresponding to the first row of touch electrode blocks TP to the mth row of pixel units, wherein the aforementioned row of pixel units includes the row of pixel units corresponding to each touch electrode block TP in the row of touch electrode blocks TP; n(1) To GL n(m) The first row of pixel units corresponding to the nth row of touch electrode blocks TP are electrically connected to the mth row of pixel units. Each scan line is responsible for controlling the opening or closing of the thin film transistors in the pixel units in the row.

[0075] In the present invention, the shielding metal layer 12 is disposed on the substrate 101 and is not in the same layer as the plurality of scan lines GL. The shielding metal layer 12 includes a plurality of shielding blocks 121 and a plurality of signal lines. The plurality of signal lines are arranged in rows. Each shielding block 121 is correspondingly disposed below each thin film transistor and is not connected to the plurality of signal lines. Further, there is a disconnection interval between any two adjacent rows of touch electrode blocks TP, wherein the first row of touch electrode blocks TP is defined as the upper side of the disconnection interval, and the second row of touch electrode blocks TP is defined as the lower side of the disconnection interval. The scan line closest to the disconnection interval among the scan lines corresponding to the first row of touch electrode blocks TP is defined as the first scan line, and the scan line closest to the disconnection interval among the scan lines corresponding to the second row of touch electrode blocks TP is defined as the second scan line; wherein the plurality of signal lines include a first compensation scan line 111 and a second compensation scan line 112. The first compensation scan line 111 is disposed corresponding to and adjacent to the first scan line and is connected to the second scan line, and the second compensation scan line 112 is disposed corresponding to and adjacent to the second scan line and is connected to the first scan line.

[0076] See also Figure 4 , Figure 4 FIG. 4 is a schematic diagram showing a signal timing sequence of a touch electrode block in an embodiment of the present invention. Figure 4 FIG. 1 schematically shows a signal timing diagram of three touch electrode blocks TP1, TP2, and TP3 (TP1 corresponds to the first row of touch electrode blocks in the touch electrode block array, and the rest correspond to the same) of the array substrate 10 after the above implementation. In the first row of touch electrode blocks TP1, the first scan line GL 1(m) The signal timing of the first compensation scan line 111 is indicated by a dotted line. 1(m) The corresponding first compensation scan line 111 signal is the second scan line GL of the second row of touch electrode blocks TP2. 2(1) In the second row of touch electrode blocks TP2, adjacent to the second scan line GL 2(1) The signal timing of the second compensation scan line 112 is indicated by a dotted line. 2(1)The corresponding second compensation scan line 112 signal is the first scan line GL of the first row of touch electrode blocks TP1. 1(m) The scanning signals of the multiple scanning lines are sent in sequence from the first row to the last row. In this embodiment, there is no overlapping area between the signals of each level. When the first scanning line GL 1(m) When the signal is turned off, the second scan line GL 2(1) The signal is turned on, then the first scan line GL of the first row of touch electrode blocks TP1 1(m) The falling edge of the signal is connected to the first compensation scan line 111 signal (ie, the second scan line GL of the second row of touch electrode blocks TP2). 2(1) The rising edge of the second scanning line GL of the touch electrode block TP2 of the second row corresponds to the rising edge of the second scanning line GL of the touch electrode block TP2 of the second row, thereby canceling the influence on the common electrode (corresponding to the touch electrode block TP1 of the first row). 2(1) The rising edge of the signal is connected to the second compensation scan line 112 signal (ie, the first scan line GL of the first row of touch electrode blocks TP1). 1(m) Similarly, for the next row of touch electrode blocks TP3 to the last row of touch electrode blocks of the second row of touch electrode blocks TP2, the design of the first row of touch electrode blocks TP1 and the second row of touch electrode blocks TP2 can be similar, and corresponding first compensation scan lines 111 and second compensation scan lines 112 are set at each disconnection interval, which cooperate with the first scan line 111 on the upper side of the disconnection interval and the second scan line 112 on the lower side to offset the influence of the scan signal on the common electrode, thereby eliminating the horizontal stripes generated at the junction of the touch electrode blocks.

[0077] In the present invention, the first compensation scan line 111, the second compensation scan line 112 and the plurality of shielding blocks 121 are jointly arranged in the shielding metal layer. The plurality of shielding blocks 121 protect the thin film transistors to ensure their electrical performance. The first compensation scan line 111 and the second compensation scan line 112 are not in the same layer as the scan lines and the data lines. While eliminating the horizontal stripes generated at the junction of the touch electrode blocks, the shielding metal layer is fully utilized without adjusting the position and line width of the scan lines and the data lines, which does not affect the transmittance of each pixel unit, thereby ensuring the display quality.

[0078] See also Figure 2 , Figure 2A schematic diagram of the connection structure of the compensation scan line of the array substrate in one embodiment of the present invention is shown. In one embodiment, the array substrate 10 further includes a gate driving circuit 102, a first connection structure 104, and a second connection structure 105 located in the peripheral area BA. The gate driving circuit 102 is connected to the first scan line and the second compensation scan line 112 via the first connection structure 104, and the gate driving circuit 102 is connected to the second scan line and the first compensation scan line 111 via the second connection structure 105. Since the gate driving circuit 102 is electrically connected to the first scan line and the second compensation scan line 112 in the peripheral area BA via the first connection structure 104, and is electrically connected to the second scan line and the first compensation scan line 111 in the peripheral area BA via the second connection structure 105, each connection structure is connected across different layers, and the signal emitted by the gate driving circuit 102 in the peripheral area BA can reduce the impact on the display area AA elements through the layer transfer connection. Please refer to Figure 3 , Figure 3 A schematic diagram of the cross-sectional layer structure of an array substrate in one embodiment of the present invention is depicted. In one embodiment, in the cross-sectional hierarchical structure of the array substrate 10, from bottom to top, there are a shielding metal layer 12, a first metal layer 13, a second metal layer 14 and a transparent conductive layer, that is, the first metal layer 13 is located on the shielding metal layer 12, and the second metal layer 14 is located on the first metal layer 13. In actual operation, an insulating layer is provided between each metal layer. In one embodiment, the first scan line is located in the first metal layer 13, and the first connection structure 104 electrically connects the first scan line, the second compensation scan line 112 and a corresponding connection portion 1021 of the gate drive circuit 102 (such as the output end of a first-stage shift register), and this corresponding connection portion 1021 is located in the second metal layer 14. In one embodiment, the second scan line is located in the first metal layer 13, and the second connection structure 105 electrically connects the second scan line, the first compensation scan line 111 and a corresponding connection part 1021 of the gate driving circuit 102 (such as the output end of another stage shift register), and this corresponding connection part 1021 is located in the second metal layer 14.

[0079] In the present invention, in addition to the multiple shielding blocks 121, the shielding metal layer 12 is also provided with compensation scanning lines connected to the corresponding scanning lines, and the scanning lines (located in the first metal layer 13) are connected to the corresponding output ends (located in the second metal layer 14) of the gate driving circuit 102 by the connecting structure 104 before accessing the display area AA. The connection between each compensation scanning line (located in the shielding metal layer 12) and the corresponding scanning line is located near the output end of the gate driving circuit 102 (such as by drilling holes in the insulating layer to directly connect each compensation scanning line to each output end, which will be explained later), without the need for a new mask, and will not affect the component design in the display area AA.

[0080] In one embodiment, if Figure 2 and Figure 3As shown, the first connection structure 104 includes a transparent conductive layer 15 and a hole. The connection portion 1021 of the gate driving circuit 102 located in the second metal layer 14 is connected to the transparent conductive layer 15 through the hole 204a (specifically, the conductive material located in the hole, such as a transparent conductive material, and the following hole description is similar to it), the second compensation scanning line 112 located in the shielding metal layer 12 is connected to the transparent conductive layer 15 through the hole 204b, and the first scanning line located in the first metal layer 13 is connected to the transparent conductive layer 15 through the hole 204c; in one embodiment In the embodiment, the second connection structure 105 may also include a transparent conductive layer 15 and a hole. The transparent conductive layers of the first connection structure 104 and the second connection structure 105 may be arranged in the same layer and are not connected. The connection part 1021 of the gate driving circuit 102 located in the second metal layer 14 is connected to the transparent conductive layer 15 through the hole 205a. The first compensation scanning line 111 located in the shielding metal layer 12 is connected to the transparent conductive layer 15 through the hole 205b. The second scanning line located in the first metal layer 13 is connected to the transparent conductive layer 15 through the hole 205c. The connection part 1021 of the gate driving circuit 102, the second compensation scanning line 112, and the first scanning line are connected through the transparent conductive layer, and the connection part 1021 of the gate driving circuit 102, the first compensation scanning line 111, and the second scanning line are connected through the transparent conductive layer. The layers are transferred to the first metal layer 13 in the peripheral area BA and then enter the display area AA, so that the connection of each compensation scanning line will not affect the arrangement of the components in the display area AA, and the manufacturing difficulty is low.

[0081] In one embodiment, the first compensation scan line 111 includes a connected first portion 1111 and a second portion 1112, and the second compensation scan line 112 includes a connected first portion 1121 and a second portion 1122. The first portion 1111 of the first compensation scan line 111 extends in the row direction and is disposed adjacent to the first scan line. The first portion 1121 of the second compensation scan line 112 extends in the row direction and is disposed adjacent to the second scan line. The second portions 1112 and 1122 of the first compensation scan line 111 and the second compensation scan line 112 extend in the column direction. In one embodiment, the first portions 1111 and 1121 of the first compensation scan line 111 and the second compensation scan line 112 have a first line width d1, and the second portions 1112 and 1122 of the first compensation scan line 111 and the second compensation scan line 112 have a second line width d2, where d1 < d2. The compensation scan lines are disposed on the light-shielding metal layer and can be disposed at the scan lines that need to be compensated across the disconnection interval, without affecting the normal line widths and position designs of the respective scan lines and data lines. Further, the line width of the first portion of the compensation scan line located within the display area AA is controlled to avoid the influence of each compensation scan line on the aperture ratio of each pixel unit. At the same time, the line width of the compensation scan line located within the peripheral area BA is set to be relatively wide, which can reduce the resistance value of this part of the circuit and ensure the signal transmission quality on each compensation scan line.

[0082] In one embodiment, the relationship between the first line width d1 and the second line width d2 is: 1.5*d1 < d2 < 2.5*d1. Since the first line width d1 is smaller than the second line width d2, the projected area of the first portion of the compensation scan line on the substrate 101 can be reduced, avoiding the influence on the aperture ratio of each pixel unit. When the ratio is 1.5*d1 < d2 < 2.5*d1, while avoiding the influence on the aperture ratio, the resistance value of each compensation scan line can be effectively controlled, ensuring the signal transmission quality and better compensating the first scan line and the second scan line, that is, offsetting the influence of the scan line signal on the common electrode.

[0083] In one embodiment, the first compensation scan line 111 does not overlap with the first scan line in the projection direction of the substrate 101; the second compensation scan line 112 does not overlap with the second scan line in the projection direction of the substrate 101. Further, in one embodiment, in the column direction, the first compensation scan line 111 has a first spacing with the first scan line, the shielding block 121 has a first width, the first spacing is greater than or equal to the first width, and the second compensation scan line 112 has a second spacing with the second scan line, the second spacing is greater than or equal to the first width. In this embodiment, the compensation scan line is arranged in a different layer from the scan line, the data line, etc., and does not overlap but has a spacing in the projection direction of the substrate 101, so that each compensation scan line has a sufficient distance from the scan line, the data line, the thin film transistor and other components, so as to avoid the signal on each compensation scan line from affecting other lines (such as the first scan line, the second scan line, the switch of each pixel unit, etc.) due to the close distance (such as electrical coupling), so that each component can work normally and ensure the display quality.

[0084] In one embodiment, in the column direction, the first compensation scan line 111 is closer to the opening area of ​​the corresponding pixel unit than the first scan line, and the second compensation scan line 112 is closer to the opening area of ​​the corresponding pixel unit than the second scan line. The line width of the first compensation scan line 111 is not greater than the line width of the first scan line, and the line width of the second compensation scan line 112 is not greater than the line width of the second scan line. In this way, the influence of the first compensation scan line 111 and the second compensation scan line 112 on the opening area of ​​the pixel unit can be avoided, and at the same time, the line width of the second part of the first compensation scan line 111 and the second compensation scan line 112 is set to control the resistance of the entire first compensation scan line 111 and the first compensation scan line 112 to ensure the signal transmission quality.

[0085] See also Figure 5 , Figure 5 A schematic diagram of a display panel in an embodiment of the present invention is shown. The present invention further discloses a display panel 100, comprising the aforementioned array substrate 10 and a color filter substrate 20, wherein the color filter substrate 20 comprises a second substrate 24, a black matrix layer 21 and a color resist layer 23, wherein the black matrix layer 21 comprises a plurality of hollow regions 22 arranged in an array, and the color resist layer 23 is located in the plurality of hollow regions 22; wherein the black matrix layer 21 has a first projection range on the array substrate 10, and the projections of the first compensation scanning line 111 and the second compensation scanning line 112 on the color filter substrate 20 are located within the first projection range, thereby avoiding the influence of the first compensation scanning line 111 and the second compensation scanning line 112 on the opening region of the pixel unit, thereby ensuring the display quality.

[0086] See also Figure 6 , Figure 6The present invention further discloses a display device 1000 , which includes a backlight module 200 and a display panel 100 . The display panel 100 includes the array substrate 10 .

[0087] The array substrate, display panel and display device disclosed in the present invention respectively set the first compensation scanning line and the second compensation scanning line for the first row of touch electrode blocks and the second row of touch electrode blocks with disconnected intervals by using a shielding metal layer, so that the first row and the last row of pixel units in each row of touch electrode blocks can offset the influence on the common electrode through the control signals of the second compensation scanning line and the first compensation scanning line, thereby solving the problem of horizontal stripes generated at the junction of the touch electrode blocks, and will not affect the normal setting of each scanning line and each data line, and the manufacturing difficulty is low.

[0088] The above disclosed contents are only preferred feasible embodiments of the present invention, and do not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the specification and drawings of the present invention fall within the scope of the patent application of the present invention.

Claims

1. An array substrate having a peripheral area and a display area arranged adjacent to each other, characterized in that: The array substrate comprises: substrate; A touch electrode layer, comprising a plurality of touch electrode blocks, wherein the plurality of touch electrode blocks are arranged in an array on the substrate and located in the display area; A plurality of scanning lines are arranged in rows on the substrate; A plurality of data lines are arranged in rows on the substrate, the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel units arranged in an array, each pixel unit comprising a thin film transistor; and A shielding metal layer is disposed on the substrate and is in a different layer from the plurality of scanning lines. The shielding metal layer includes a plurality of shielding blocks and a plurality of signal lines. The plurality of signal lines are arranged in rows. Each shielding block is correspondingly disposed under each thin film transistor and is not connected to the plurality of signal lines. There is a disconnection gap between any two adjacent rows of touch electrode blocks, wherein the touch electrode blocks in the first row are located above the disconnection gap, and the touch electrode blocks in the second row are located below the disconnection gap. Among the scan lines corresponding to the touch electrode blocks in the first row, the scan line closest to the disconnection gap is the first scan line, and among the scan lines corresponding to the touch electrode blocks in the second row, the scan line closest to the disconnection gap is the second scan line. The plurality of signal lines include a first compensation scan line and a second compensation scan line, wherein the first compensation scan line corresponds to and is adjacent to the first scan line and is connected to the second scan line, and the second compensation scan line corresponds to and is adjacent to the second scan line and is connected to the first scan line.

2. The array substrate according to claim 1, characterized in that: The array substrate also includes a gate driving circuit, a first connection structure and a second connection structure located in the peripheral area, the gate driving circuit is connected to the first scan line and the second compensation scan line via the first connection structure, and the gate driving circuit is connected to the second scan line and the first compensation scan line via the second connection structure.

3. The array substrate according to claim 2, characterized in that: The first scan line is located in a first metal layer, the first metal layer is located above the shielding metal layer, the first connection structure electrically connects the first scan line, the second compensation scan line and a connecting part of the gate drive circuit, the connecting part is located in a second metal layer, and the second metal layer is located above the first metal layer.

4. The array substrate according to claim 3, characterized in that: The second scan line is located in the first metal layer, and the second connection structure electrically connects the second scan line, the first compensation scan line and a connection portion of the gate driving circuit.

5. The array substrate according to claim 2, characterized in that: The first connection structure and the second connection structure include a transparent conductive layer.

6. The array substrate according to claim 1, characterized in that: The first compensation scan line and the second compensation scan line include a first portion and a second portion that are connected to each other. The first portion of the first compensation scan line extends along a row direction and is disposed adjacent to the first scan line. The first portion of the second compensation scan line extends along a row direction and is disposed adjacent to the second scan line. The second portions of the first compensation scan line and the second compensation scan line extend along a column direction. The first portions of the first compensation scan line and the second compensation scan line have a first line width d1, and the second portions of the first compensation scan line and the second compensation scan line have a second line width d2, wherein d1<d2.

7. The array substrate according to claim 6, characterized in that: The relationship between the first line width d1 and the second line width d2 is: 1.5*d1 <d2<2.5*d1。 8. The array substrate according to any one of claims 1 to 7, characterized in that: The first compensation scanning line does not overlap with the first scanning line in the projection direction of the substrate; the second compensation scanning line does not overlap with the second scanning line in the projection direction of the substrate.

9. The array substrate according to claim 8, characterized in that: In the column direction, the first compensation scanning line and the first scanning line have a first spacing, the shielding block has a first width, and the first spacing is greater than or equal to the first width; Alternatively, in the column direction, the line width of the first compensation scan line is not greater than the line width of the first scan line.

10. The array substrate according to claim 9, characterized in that: In the column direction, the second compensation scan line and the second scan line have a second spacing, and the second spacing is greater than or equal to the first width; or, in the column direction, the line width of the second compensation scan line is not greater than the line width of the second scan line.

11. A display panel, characterized in that Include, The array substrate according to any one of claims 1 to 10; as well as A color filter substrate, comprising a black matrix layer and a color resist layer, wherein the black matrix layer comprises a plurality of hollow regions arranged in an array, and the color resist layer is located in the plurality of hollow regions; The black matrix layer has a first projection range on the array substrate, and projections of the first compensation scanning line and the second compensation scanning line on the color filter substrate are located within the first projection range.

12. A display device comprising a backlight module and a display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 10.

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