Shutdown control circuit, display driver and display device

Abstract

The utility model discloses a shutdown control circuit, a display driver and a display device, and the shutdown control circuit comprises a control unit which is connected with a grounding end; the voltage output unit is connected with the control unit, the voltage output unit comprises a plurality of transistors, and source ends or drain ends of the transistors are connected with data lines or scanning lines in the display panel in a one-to-one correspondence manner; wherein the control end of the control unit is connected with the first output end of the source electrode driving circuit so as to receive a second control signal or a third control signal, and the control end of the voltage output unit is connected with the second output end of the source electrode driving circuit so as to receive a first control signal. According to the power-off control circuit, the display driver and the display device, the charges in the display panel are released to the grounding end through the transistor in the power-off control circuit after power-off, the function of rapid discharging after power-off is achieved, and the problems of power-off ghost shadow and splash screen are solved.

Description

Technical Field

[0001] The utility model relates to the technical field of display, and in particular to a shutdown control circuit, a display driver and a display device. Background Art

[0002] The liquid crystal display device mainly includes a display panel and a circuit board that provides various signals for the display panel. The display panel includes a display driver and a pixel array. The display driver includes at least a source drive circuit and a gate drive circuit. The pixel array is composed of a plurality of pixel units defined by a plurality of scan lines and a plurality of data lines. Generally speaking, the pixel unit is mainly composed of a thin film transistor, a storage capacitor and a liquid crystal unit. The output end of the gate drive circuit is coupled to a plurality of scan lines, and is used to turn on or off a plurality of thin film transistors connected to the corresponding scan lines. The source drive circuit is connected to a plurality of data lines. When a plurality of thin film transistors are turned on, a grayscale display voltage is provided to the corresponding pixel unit, so that a signal is stored in each pixel unit to display an image. Since the liquid crystal display accumulates charge in the storage capacitor when displaying an image, when the display panel of the liquid crystal display is turned off, the accumulated charge will slowly disappear in the pixel unit. The charge remaining in the pixel causes the liquid crystal display device to display the image at the last shutdown when it is turned on next time. In severe cases, the liquid crystal will be polarized, thereby causing an afterimage problem.

[0003] In order to solve the above problems, the prior art turns on the thin film transistors of all pixel units by triggering the XON (Output ALL-ON Control, signal forced high) function when the display device is turned off, so as to forcibly neutralize and release the charge in the pixel unit quickly. However, it is found through actual measurements that in the continuous 3-second power on and off experiment of the display device, even if the Xon function is turned on, the problems of screen flickering and shutdown afterimage are still prone to occur after 30 experiments; but if the power on and off time is extended from 3 seconds to 10 seconds, the screen flickering and shutdown afterimage phenomena disappear. Research on this phenomenon has found that when the power is turned off, the in-plane charge is released to the driver chip through the source line (data line). Since the source line is an output line, not a ground line, when the discharge time of the clock signal CLK in the display device is too long, the release path of the in-plane charge and its slow release speed become the main causes of screen flickering and shutdown afterimage. Utility Model Content

[0004] In view of the above problems, the purpose of the utility model is to provide a shutdown control circuit, a display driver and a display device. The charge in the display panel is released to the ground terminal through the transistor in the shutdown control circuit after shutdown, thereby realizing the function of rapid discharge after shutdown and reducing the shutdown afterimage and screen flickering problems.

[0005] According to one aspect of the utility model, a shutdown control circuit is provided, which is used to release the residual charge in the display panel after the display panel is shut down, the display panel includes m scan lines and n data lines, m and n are non-zero natural numbers, and the shutdown control circuit includes: a control unit connected to the ground terminal; a voltage output unit connected to the control unit, the voltage output unit includes a plurality of transistors, the source or drain of the transistor is connected one-to-one with the data line or the scan line in the display panel; wherein the control end of the control unit is connected to the first output end of the source driving circuit to receive the second control signal or the third control signal, and the control end of the voltage output unit is connected to the second output end of the source driving circuit to receive the first control signal.

[0006] Optionally, the control unit includes: a first control transistor, the second end of the first control transistor is connected to the ground end, and the control end receives the second control signal; a second control transistor, the second end of the second control transistor is connected to the ground end, and the control end receives the second control signal; a third control transistor, the second end of the third control transistor is connected to the ground end, and the control end receives the second control signal.

[0007] Optionally, the voltage output unit includes: first to n-th transistors, the first ends of the first to n-th transistors are connected to n data lines one by one in sequence, and the control end receives the first control signal; the first to n-th transistors are grouped into groups of three, the second end of the first transistor in each group is connected to the first end of the first control transistor, the second end of the second transistor in each group is connected to the first end of the second control transistor, and the third transistor in each group is connected to the first end of the third control transistor.

[0008] Optionally, the control unit includes: a fourth control transistor, a second end of the fourth control transistor is connected to the ground end, and the control end receives the second control signal; a fifth control transistor, a second end of the fifth control transistor is connected to the ground end, and the control end receives the second control signal.

[0009] Optionally, the voltage output unit includes: first to n-th transistors, the first ends of the first to n-th transistors are connected to n data lines one by one in sequence, and the control end receives the first control signal; the first to n-th transistors are divided into an odd group and an even group, the first ends of the transistors in the odd group are connected to the corresponding odd-numbered data lines, and the second ends are connected to the first end of the third control transistor; the first ends of the transistors in the even group are connected to the corresponding even-numbered data lines, and the second ends are connected to the first end of the fourth control transistor.

[0010] Optionally, the control unit includes: a fourth control transistor, a second end of the fourth control transistor is connected to the ground end, and the control end receives the third control signal; a fifth control transistor, a second end of the fifth control transistor is connected to the ground end, and the control end receives the third control signal.

[0011] Optionally, the voltage output unit includes: first to m-th transistors, the first ends of the first to m-th transistors are connected to m scan lines in sequence in a one-to-one correspondence, and the control end receives the first control signal; the first to m-th transistors are divided into an odd group and an even group, the first ends of the transistors in the odd group are connected to the corresponding odd-numbered scan lines, and the second ends are connected to the first end of the third control transistor; the first ends of the transistors in the even group are connected to the corresponding even-numbered scan lines, and the second ends are connected to the first end of the fourth control transistor.

[0012] Optionally, the first control signal and the second control signal simultaneously control the control unit and the voltage output unit to be turned on; or after the first control signal controls the voltage output unit to be turned on for a predetermined time, the third control signal controls the control unit to be turned on.

[0013] According to another aspect of the present invention, a display driver is provided, comprising a source driving circuit, a gate driving circuit, a timing control circuit and the above-mentioned shutdown control circuit, wherein the shutdown control circuit is connected to the source driving circuit, a ground terminal and a scan line or a data line to release residual charge in a display panel to the ground terminal via the scan line or the data line.

[0014] According to another aspect of the present invention, a display device is provided, comprising a system mainboard, a display panel and the above-mentioned display driver, wherein a shutdown control circuit in the display driver is connected to a ground terminal of the system mainboard.

[0015] In the shutdown control circuit, display driver and display device provided by the utility model, the shutdown control circuit includes a control unit and a voltage output unit connected to the control unit, the voltage output unit includes a plurality of transistors, one of the source and drain ends of the plurality of transistors is connected to the data line or the gate line in a one-to-one correspondence, and the other of the source and drain ends is connected to the control unit, and the control unit is also connected to the ground pin of the system mainboard, so that after the display device is shut down, the shutdown control circuit turns on the control unit and the voltage output unit according to the first control signal and the second control signal (or the third control signal), so that the residual charge in the display panel reaches the ground terminal via the data line (or the gate line) and the shutdown control circuit, and the charge is released more thoroughly, which not only realizes rapid discharge, but also reduces the shutdown afterimage and screen flickering problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram showing the structure of a display device according to a first embodiment of the utility model is shown;

[0018] Figure 2 A circuit structure diagram of a shutdown control circuit in a display device according to a first embodiment of the utility model is shown;

[0019] Figure 3 A schematic structural diagram of a display device according to a second embodiment of the utility model is shown;

[0020] Figure 4 A circuit structure diagram of a shutdown control circuit in a display device according to a second embodiment of the utility model is shown;

[0021] Figure 5 A schematic structural diagram of a display device according to a third embodiment of the present utility model is shown;

[0022] Figure 6 A circuit structure diagram of a shutdown control circuit in a display device according to a third embodiment of the utility model is shown;

[0023] Figure 7 shows a waveform diagram of the shutdown stage according to the first embodiment and the second embodiment of the utility model;

[0024] Figure 8 A waveform diagram of the shutdown stage according to the third embodiment of the utility model is shown. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] The specific implementation of the utility model is further described in detail below in conjunction with the drawings and embodiments.

[0027] Figure 1 A schematic diagram showing the structure of a display device according to a first embodiment of the utility model is shown; Figure 2 The circuit structure diagram of the shutdown control circuit in the display device according to the first embodiment of the utility model is shown.

[0028] refer to Figure 1The display device 10 of the present application includes a display panel 100 , a display driver 200 , and a system mainboard 300 . The system mainboard 300 is connected to the display driver 200 , and the display driver 200 is connected to the display panel 100 .

[0029] Specifically, the display panel 100 includes a plurality of pixel units 110, m scan lines 120 and n data lines 130, where m and n are non-zero natural numbers. Each pixel unit 110 includes a thin film transistor T, a liquid crystal capacitor C LC and a storage capacitor C ST In the display panel 100, the gates of the thin film transistors T in the pixel units 110 in the same row are connected to the corresponding primary gate driving unit in the gate driving circuit 210 through the same scanning line 120; the sources or drains of the thin film transistors T in the pixel units 110 in the same column are connected to the source driving circuit 220 through the same data line 130.

[0030] The display driver 200 includes a gate driving circuit 210, a source driving circuit 220, a timing control circuit 230 and a shutdown control circuit 240. The timing control circuit 230 is connected to the gate driving circuit 210 and the source driving circuit 220, and is used to provide a clock signal CLK to the gate driving circuit 210 and the source driving circuit 220. The gate driving circuit 210 in the display driver 200 includes m cascaded gate driving units, each of which is connected to a scan line 120. The gate driving circuit 210 selects each pixel unit 110 in the display panel 100 row by row through the multiple scan lines 120; the source driving circuit 220 applies a grayscale voltage to each pixel unit 110 through n data lines 130, so that the display panel 100 presents an image. The shutdown control circuit 240 is connected to the source driving circuit 220, and is used to receive the first control signal Cell_ADD and the second control signal Xon_ADD, and after the display panel 100 is shut down, the residual charge in the display panel 100 is released to the ground terminal via the data line and the shutdown control circuit 240 according to the first control signal Cell_ADD and the second control signal Xon_ADD, thereby achieving the purpose of rapid discharge.

[0031] The system mainboard 300 is used to send instructions to the timing control circuit 230 in the display driver 200 through a protocol (eg, an I2C protocol), so that the timing control circuit 230 generates a clock signal with a suitable frequency.

[0032] In this embodiment, the first control signal Cell_ADD and the second control signal Xon_ADD are respectively from the display driver 200 or the source driving circuit 220 of the display driver 200. Specifically, on the packaged chip, the first control signal Cell_ADD and the second control signal Xon_ADD are respectively from the output pin CGOUT of the display driver 200 or the source driving circuit 220 of the display driver 200. In this embodiment, for the convenience of description, the first control signal Cell_ADD and the second control signal Xon_ADD are both shown as coming from the source driving circuit 220.

[0033] In this embodiment, the first control signal Cell_ADD and the second control signal Xon_ADD are both signals related to the shutdown signal of the display panel 100. For example, when the first control signal Cell_ADD and the second control signal Xon_ADD are at a low level, the display panel 100 works normally, but when the display panel 100 receives the shutdown signal, the first control signal Cell_ADD and the second control signal Xon_ADD change from a low level to a high level.

[0034] Further, refer to Figure 2 The shutdown control circuit 240 includes a control unit 241 and a voltage output unit 242. The control end of the control unit 241 is connected to the first output end of the source driving circuit 220 to receive the second control signal Xon_ADD, the first end is connected to the voltage output unit 242, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the voltage output unit 242 is connected to the second output end of the source driving circuit 220 to receive the first control signal Cell_ADD, the first end is connected to the data line, and the second end is connected to the first end of the control unit 241.

[0035] Specifically, the control unit 241 includes a first control transistor TR, a second control transistor TG, and a third control transistor TB, and the voltage output unit 242 includes a first transistor T1 to an nth transistor Tn. Specifically, the control end of the first control transistor TR receives the second control signal Xon_ADD, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the second control transistor TG is connected to the control end of the first control transistor TR to receive the second control signal Xon_ADD, and the second end is connected to the second end of the first control transistor TR to be connected to the ground terminal GND of the system mainboard 300; the control end of the third control transistor TB is connected to the control end of the first control transistor TR to receive the second control signal Xon_ADD, and the second end is connected to the second end of the first control transistor TR to be connected to the ground terminal GND of the system mainboard 300. Among the first transistor T1 to the nth transistor Tn, three consecutive transistors are grouped together, for example, the first transistor T1 to the third transistor T3 are grouped together, and the fourth transistor T4 to the sixth transistor T6 are grouped together. In each group, for example, taking the group where the first transistor T1 to the third transistor T3 are located as an example, the first end of the first transistor T1 is connected to the first data line 130, the second end is connected to the first end of the first control transistor TR, and the control end receives the first control signal Cell_ADD; the first end of the second transistor T2 is connected to the second data line 130, the second end is connected to the first end of the second control transistor TG, and the control end receives the first control signal Cell_ADD; the first end of the third transistor T3 is connected to the third data line 130, the second end is connected to the first end of the third control transistor TB, and the control end receives the first control signal Cell_ADD. Similarly, in the fourth transistor T4 to the sixth transistor T6 of the next group, the first end thereof is connected to the fourth data line to the sixth data line in sequence, the second end thereof is connected to the first end of the first control transistor TR to the third control transistor TB in sequence, and the connection mode of the seventh transistor T7 to the nth transistor Tn is analogous, so that each data line has a transistor connected to it, and these transistors are connected to one of the first control transistor TR to the third control transistor TB.

[0036] In this embodiment, the n data lines are repeatedly arranged in the order of red (R), green (G), and blue (B), for example, that is, the first data line 130 is connected to the R pixel unit 110, the second data line 130 is connected to the G pixel unit 110, the third data line 130 is connected to the B pixel unit 110, the fourth data line 130 is connected to the R pixel unit 110, the fifth data line 130 is connected to the G pixel unit 110, etc. Since the first transistor T1 to the nth transistor Tn are sequentially connected to the corresponding first to nth data lines 130, the transistor connected to the first control transistor TR among the first transistor T1 to the nth transistor in the shutdown control circuit 240 is also connected to the corresponding red data line, the transistor connected to the second control transistor TG is also connected to the corresponding green data line, and the transistor connected to the third control transistor TB is also connected to the corresponding blue data line.

[0037] Further, refer to Figure 7 In the normal display stage, the first control signal Cell_ADD and the second control signal Xon_ADD are both at low levels, and all transistors in the shutdown control circuit 240 are in the off state. When the display panel 100 is shut down, the first control signal Cell_ADD and the second control signal Xon_ADD change from low level to high level according to the change of the power supply voltage VCC (from high voltage to low voltage), and all transistors in the shutdown control circuit 240 are turned on. The residual current in the display panel 100 reaches the ground terminal GND via the data line and the transistors in the shutdown control circuit 240, thereby realizing the rapid release of residual charge and reducing the screen flickering and shutdown afterimage phenomenon of the display panel.

[0038] In addition, according to the connection method of multiple transistors in the shutdown control circuit 240 in the present application, the shutdown control circuit 240 can also be used to test the pixel unit in the display panel. In the test phase, by connecting the test voltage from the first control transistor TR to the second end of the third transistor TB, setting the first control signal Cell_ADD to a high level, for example, and the second control signal Xon_ADD to a low level, for example, the pixel unit in the display panel 100 can be lit for testing.

[0039] Figure 3 A schematic structural diagram of a display device according to a second embodiment of the utility model is shown;

[0040] Figure 4 The circuit structure diagram of the shutdown control circuit in the display device according to the second embodiment of the utility model is shown.

[0041] like Figure 3 and Figure 4As shown, the similarities between the semiconductor device of the second embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figure 1 to Figure 2 The difference is that, compared with the first embodiment, the control transistors in the shutdown control circuit 240 in the second embodiment include two.

[0042] Specifically, refer to Figure 3 and Figure 4 The shutdown control circuit 240 includes a control unit 241 and a voltage output unit 242. The control end of the control unit 241 is connected to the first output end of the source driving circuit 220 to receive the second control signal Xon_ADD, the first end is connected to the voltage output unit 242, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the voltage output unit 242 is connected to the second output end of the source driving circuit 220 to receive the first control signal Cell_ADD, the first end is connected to the data line, and the second end is connected to the first end of the control unit 241.

[0043] Specifically, the control unit 241 includes a fourth control transistor Todd and a fifth control transistor Teven, and the voltage output unit 242 includes a first transistor T1 to an nth transistor Tn. Specifically, the control end of the fourth control transistor Todd receives the second control signal Xon_ADD, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the fifth control transistor Teven is connected to the control end of the fourth control transistor Todd to receive the second control signal Xon_ADD, and the second end is connected to the second end of the fourth control transistor Todd to be connected to the ground terminal GND of the system mainboard 300. The first transistor T1 to the nth transistor Tn are divided into two groups according to odd numbers and even numbers, for example, the first transistor T1, the third transistor T3, the fifth transistor T5, etc. are an odd group, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, etc. are an even group. In the odd-numbered array, for example, taking the first transistor T1 as an example, the first end of the first transistor T1 is connected to the first data line 130, the second end is connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD; the first end of the third transistor T3 is connected to the third data line 130, the second end is connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD. The first ends of the transistors in other odd-numbered arrays are also connected to the corresponding odd-numbered data lines, and the second ends are connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD. Similarly, in the second transistor T2, the fourth transistor T4, etc. in the even-numbered array, the first end thereof is sequentially connected to the second data line, the fourth data line, and other even-numbered data lines, and the second end is sequentially connected to the first end of the fifth control transistor Teven, and the control end receives the first control signal Cell_ADD, so that each data line has a transistor corresponding to it according to odd and even numbers, and these transistors are connected to one of the fourth control transistor Todd and the fifth control transistor Teven.

[0044] Further, refer to Figure 7 In the normal display stage, the first control signal Cell_ADD and the second control signal Xon_ADD are both at low levels, and all transistors in the shutdown control circuit 240 are in the off state. When the display panel 100 is shut down, the first control signal Cell_ADD and the second control signal Xon_ADD change from low level to high level according to the change of the power supply voltage VCC (from high voltage to low voltage), and all transistors in the shutdown control circuit 240 are turned on. The residual current in the display panel 100 reaches the ground terminal GND via the data line and the transistors in the shutdown control circuit 240, thereby realizing the rapid release of residual charge and reducing the screen flickering and shutdown afterimage phenomenon of the display panel.

[0045] Compared with the first embodiment, one control transistor is reduced in the second embodiment, so that the area of ​​the shutdown control circuit can be reduced accordingly.

[0046] Figure 5 A schematic structural diagram of a display device according to a third embodiment of the present utility model is shown;

[0047] Figure 6 The circuit structure diagram of the shutdown control circuit in the display device according to the third embodiment of the utility model is shown.

[0048] like Figure 5 and Figure 6 As shown, the similarities between the semiconductor device of the third embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figure 1 to Figure 2 The difference is that, compared with the first and second embodiments, the shutdown control circuit 240 in the third embodiment releases the charge through the scan line.

[0049] Specifically, refer to Figure 5 and Figure 6 The shutdown control circuit 240 includes a control unit 241 and a voltage output unit 242. The control end of the control unit 241 is connected to the first output end of the source driving circuit 220 to receive the third control signal Xon_ADD_gate, the first end is connected to the voltage output unit 242, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the voltage output unit 242 is connected to the second output end of the source driving circuit 220 to receive the first control signal Cell_ADD, the first end is connected to the scan line, and the second end is connected to the first end of the control unit 241.

[0050] Specifically, the control unit 241 includes a fourth control transistor Todd and a fifth control transistor Teven, and the voltage output unit 242 includes a first transistor T1 to an m-th transistor Tm. Specifically, the control end of the fourth control transistor Todd receives the third control signal Xon_ADD_gate, and the second end is connected to the ground terminal GND of the system mainboard 300; the control end of the fifth control transistor Teven is connected to the control end of the fourth control transistor Todd to receive the third control signal Xon_ADD_gate, and the second end is connected to the second end of the fourth control transistor Todd to be connected to the ground terminal GND of the system mainboard 300. The first transistor T1 to the m-th transistor Tm are divided into two groups according to odd numbers and even numbers, for example, the first transistor T1, the third transistor T3, the fifth transistor T5, etc. are an odd group, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, etc. are an even group. In the odd array, for example, taking the first transistor T1 as an example, the first end of the first transistor T1 is connected to the first scan line 120, the second end is connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD; the first end of the third transistor T3 is connected to the third scan line 120, the second end is connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD. The first ends of the transistors in other odd arrays are also connected to the corresponding odd scan lines, and the second ends are connected to the first end of the fourth control transistor Todd, and the control end receives the first control signal Cell_ADD. Similarly, in the second transistor T2, the fourth transistor T4, etc. in the even array, the first end thereof is sequentially connected to the second scan line, the fourth scan line, and other even scan lines, and the second end is sequentially connected to the first end of the fifth control transistor Teven, and the control end receives the first control signal Cell_ADD, so that each scan line has a transistor corresponding to it according to odd and even, and these transistors are connected to one of the fourth control transistor Todd and the fifth control transistor Teven.

[0051] Further, refer to Figure 8In the normal display stage, the first control signal Cell_ADD and the third control signal Xon_ADD_gate are both at low levels, and all transistors in the shutdown control circuit 240 are in the off state. When the display panel 100 is shut down, the first control signal Cell_ADD first changes from a low level to a high level according to the change of the power supply voltage VCC (from a high voltage to a low voltage), and the first transistor T1 to the mth transistor Tm in the shutdown control circuit 240 are all turned on. After a predetermined time, the third control signal Xon_ADD_gate changes from a low level to a high level, and the fourth control transistor Todd and the fifth control transistor Teven are turned on, so that the residual current in the display panel 100 reaches the ground terminal GND via the scan line and the transistors in the shutdown control circuit 240, thereby realizing the rapid release of residual charge and reducing the flickering screen and shutdown afterimage phenomenon of the display panel. In addition, referring to Figure 8 The third control signal Xon_ADD_gate is used for discharging the source driving circuit during the period of time when the third control signal Xon_ADD_gate becomes a high level later than the first control signal Cell_ADD. That is, in the third embodiment, after the display panel is turned off, the third control signal Xon_ADD_gate needs to become a high level only after the source driving circuit has completed discharging, so as to release the residual charge in the display panel.

[0052] In the shutdown control circuit, display driver and display device provided by the utility model, the shutdown control circuit includes multiple transistors, one of the source and drain ends of the transistor is connected to the data line or the gate line, and the other of the source and drain ends is connected to the ground pin of the system motherboard, so that after the display device is shut down, the shutdown control circuit is turned on according to the first control signal and the second control signal, so that the residual charge in the display panel reaches the ground end via the data line and the shutdown control circuit, and the charge is released more thoroughly, which not only realizes rapid discharge but also reduces the shutdown afterimage and screen flickering problems.

[0053] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A shutdown control circuit, used for releasing residual charge in a display panel after the display panel is shut down, wherein the display panel comprises m scan lines and n data lines, where m and n are non-zero natural numbers, and wherein: The shutdown control circuit comprises: A control unit connected to the ground terminal; a voltage output unit connected to the control unit, the voltage output unit comprising a plurality of transistors, source terminals or drain terminals of the transistors being connected one-to-one with data lines or scan lines in the display panel; Among them, the control end of the control unit is connected to the first output end of the source driving circuit to receive the second control signal or the third control signal, and the control end of the voltage output unit is connected to the second output end of the source driving circuit to receive the first control signal.

2. The shutdown control circuit according to claim 1, characterized in that: The control unit comprises: a first control transistor, wherein a second terminal of the first control transistor is connected to the ground terminal, and a control terminal receives the second control signal; a second control transistor, wherein a second terminal of the second control transistor is connected to the ground terminal, and a control terminal receives the second control signal; A third control transistor, wherein the second terminal of the third control transistor is connected to the ground terminal, and the control terminal receives the second control signal.

3. The shutdown control circuit according to claim 2, characterized in that: The voltage output unit comprises: first transistor to n-th transistor, wherein the first ends of the first transistor to n-th transistor are sequentially connected to n data lines in a one-to-one correspondence, and the control ends receive the first control signal; The first to nth transistors form a group of three each, the second end of the first transistor in each group is connected to the first end of the first control transistor, the second end of the second transistor in each group is connected to the first end of the second control transistor, and the second end of the third transistor in each group is connected to the first end of the third control transistor.

4. The shutdown control circuit according to claim 1, characterized in that: The control unit comprises: a fourth control transistor, wherein a second terminal of the fourth control transistor is connected to the ground terminal, and a control terminal receives the second control signal; A fifth control transistor, wherein the second terminal of the fifth control transistor is connected to the ground terminal, and the control terminal receives the second control signal.

5. The shutdown control circuit according to claim 4, characterized in that: The voltage output unit comprises: first transistor to n-th transistor, wherein the first ends of the first transistor to n-th transistor are sequentially connected to n data lines in a one-to-one correspondence, and the control ends receive the first control signal; The first to nth transistors are divided into an odd group and an even group, the first ends of the transistors in the odd group are connected to the corresponding odd-numbered data lines, and the second ends are connected to the first end of the fourth control transistor; the first ends of the transistors in the even group are connected to the corresponding even-numbered data lines, and the second ends are connected to the first end of the fifth control transistor.

6. The shutdown control circuit according to claim 1, characterized in that: The control unit comprises: a fourth control transistor, wherein a second terminal of the fourth control transistor is connected to the ground terminal, and a control terminal receives the third control signal; A fifth control transistor, wherein the second terminal of the fifth control transistor is connected to the ground terminal, and the control terminal receives the third control signal.

7. The shutdown control circuit according to claim 6, characterized in that: The voltage output unit comprises: first transistor to m-th transistor, wherein first ends of the first transistor to m-th transistor are sequentially connected to m scan lines in a one-to-one correspondence, and control ends receive the first control signal; The first transistor to the mth transistor are divided into an odd group and an even group, the first end of the transistor in the odd group is connected to the corresponding odd-numbered scan line, and the second end is connected to the first end of the fourth control transistor; the first end of the transistor in the even group is connected to the corresponding even-numbered scan line, and the second end is connected to the first end of the fifth control transistor.

8. The shutdown control circuit according to claim 1, characterized in that: The first control signal and the second control signal simultaneously control the control unit and the voltage output unit to be turned on; or After the first control signal controls the voltage output unit to be turned on for a predetermined time, the third control signal controls the control unit to be turned on.

9. A display driver, comprising a source driving circuit, a gate driving circuit, a timing control circuit and a shutdown control circuit as claimed in any one of claims 1 to 8, The shutdown control circuit is connected to the source driving circuit, the ground terminal and the scan line or the data line to release the residual charge in the display panel to the ground terminal via the scan line or the data line.

10. A display device comprising a system mainboard, a display panel and the display driver according to claim 9, wherein: The shutdown control circuit in the display driver is connected to the ground terminal of the system mainboard.

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