Method for sending indicator light signal, storage medium, integrated hard disk and computer program product

Abstract

The embodiments of the present application provide a method for sending an indicator light signal, a storage medium, an integrated hard disk and a computer program product, which are applied to an integrated hard disk. The integrated hard disk includes: a main board, a backplane, and a hard disk interface card. The transmission channel of the virtual pin interface of the central processing unit on the main board has been expanded to N through a channel expansion component. The N transmission channels are connected one-to-one with the N first connectors on the main board, including: sending N enable signals to the first type pins of the N first connectors respectively, so as to forward the N enable signals to a logic control device through the first type pins of the N second connectors connected one-to-one with the N first connectors; sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a method for sending an indicator light signal, a storage medium, an integrated hard disk, and a computer program product. Background Art

[0002] In the design of modern computing systems, indicator lights serve as a key visual feedback method for hardware status and fault diagnosis, helping technicians quickly determine the operating status of the system, identify potential hardware failures, and perform necessary maintenance operations. However, the existing lighting control logic is often closely bound to a specific type of central processing unit (CPU), which means that when the CPU model or version changes, the original lighting control logic may no longer be applicable, requiring developers to redesign the lighting control logic based on the changed CPU.

[0003] Regarding the related art, when the CPU type changes, the lighting control logic needs to be redesigned, resulting in high design costs and other problems, and no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide a method for sending an indicator light signal, a storage medium, an integrated hard disk, and a computer program product, so as to at least solve the problem in the related art that when the CPU type changes, the lighting control logic needs to be redesigned, resulting in high design costs.

[0005] According to an embodiment of the present application, a method for sending an indicator light signal is provided, which is applied to an integrated hard disk, wherein the integrated hard disk comprises: a mainboard, and a backplane connected to the mainboard, wherein a transmission channel of a virtual pin interface of a central processing unit on the mainboard has been expanded to N through a channel expansion component, and the N transmission channels are connected to N first connectors on the mainboard in a one-to-one correspondence, comprising: sending N enable signals to first-class pins of the N first connectors respectively, so as to forward the N enable signals to a logic control device through first-class pins of N second connectors connected to the N first connectors in a one-to-one correspondence, wherein the second The connector and the logic control device are both arranged on the backplane; the N indicator light signals are respectively sent to the second type pins of the N first connectors through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0006] In an exemplary embodiment, before sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, the method also includes: when the central processing unit is connected to the backplane through the hard disk interface card, the N enable signals are forwarded to the logic control device through the first type pins of the N second connectors and the first type pins of N third connectors, wherein the N third connectors are arranged on the hard disk interface card, the first type pins of the N third connectors have been set as ground pins, and the hard disk interface card is connected to both the mainboard and the backplane; when the first type pins of the N third connectors have been set as ground pins, the hard disk interface card is prohibited from adjusting the level status of the N received enable signals.

[0007] In an exemplary embodiment, before the N enable signals are forwarded to the logic control device through the first type pins of the N second connectors and the first type pins of the N third connectors, the method also includes: forwarding the N indicator light signals and the N enable signals to the same fourth connector through the N first connectors, wherein the fourth connector, the N third connectors and the controller are all arranged on the hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; forwarding the N indicator light signals and the N enable signals to the controller through the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is used to forward the N indicator light signals and the N enable signals to the N third connectors.

[0008] In an exemplary embodiment, after forwarding the N indicator light signals and the N enable signals to the controller through the fourth connector and the first interface bus, the method further includes: forwarding the N indicator light signals to the N third connectors through the controller and N second interface buses, so as to forward the N indicator light signals to the logic control device through the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0009] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method also includes: when the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is in an open state, controlling the enable signal corresponding to the fourth interface bus to be the first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or when the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is in a closed state, controlling the enable signal corresponding to the fifth interface bus to be the second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

[0010] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method also includes: obtaining the first device address of the hard disk interface card and determining the second device addresses of N target hard disks corresponding to N third interface buses; and setting the second device address to the first device address through a write operation.

[0011] In an exemplary embodiment, the second device address is set to the first device address through a write operation, including: determining a target position where a first character that is inconsistent with the first device address is located; obtaining a second character corresponding to the target position from the first device address; and modifying the first character at the target position in the second device address to the second character, so as to modify the second device address to be consistent with the first device address.

[0012] In an exemplary embodiment, after forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: in the event that a first target hard disk among the N target hard disks fails, receiving an interrupt request issued by the first target hard disk through the second connector corresponding to the first target hard disk through the sixth interface bus corresponding to the first target hard disk, wherein the N target hard disks are arranged on the backplane; generating an interrupt instruction according to the interrupt request, and sending the interrupt instruction to the second type pin of the first connector corresponding to the sixth interface bus through the sixth interface bus, so as to send the interrupt instruction to the logic control device through the second type pin of the second connector corresponding to the sixth interface bus, so as to shut down the first target hard disk.

[0013] In an exemplary embodiment, after turning off the first target hard disk, the method further includes: when the difference between the time when the first target hard disk is turned off and the current time is greater than a preset time, sending a startup instruction to the logic control device through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

[0014] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method further includes: sending a target address through an integrated circuit interconnect bus to determine a target IO expander that communicates with the central processing unit from a plurality of IO expanders, wherein the plurality of IO expanders are connected to the central processing unit; sending a register address to the target IO expander to determine a target register that controls the N enable signals, wherein the target register exists in an internal storage space of the target IO expander; writing 0 at a target position of the target register to control the first enable signal to be a low level, and writing 1 at the target position to control the second enable signal to be a high level.

[0015] In an exemplary embodiment, after forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: when the first enable signal exists among the N enable signals, lighting up the indicator light corresponding to the first enable signal through the logic control device; and when the second enable signal exists among the N enable signals, turning off the indicator light corresponding to the second enable signal through the logic control device.

[0016] According to another embodiment of the present application, an integrated hard disk is provided, comprising: a mainboard, on which a central processing unit and N first connectors are provided, the transmission channels of the virtual pin interface of the central processing unit have been expanded to N through a channel expansion component, and the N transmission channels are connected to the N first connectors on the mainboard in a one-to-one correspondence; a backplane, on which N second connectors and a logic control device are provided; wherein the central processing unit is used to send N enable signals to the first type pins of the N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of the N second connectors connected to the N first connectors in a one-to-one correspondence. A control device, wherein the N second connectors and the logic control device are arranged on a backplane; and the N indicator light signals are respectively sent to the second type pins of the N first connectors through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0017] The integrated hard disk also includes: a hard disk interface card connected to both the main board and the backplane, and the central processing unit, which is used to forward the N enable signals to the logic control device through the fourth connector, the first type pins of the N second connectors, and the first type pins of the N third connectors when the central processing unit is connected to the backplane through the hard disk interface card, wherein the N third connectors are arranged on the hard disk interface card, and the first type pins of the N third connectors are set as ground pins; when the first type pins of the N third connectors are set as ground pins, the hard disk interface card is prohibited from adjusting the level status of the N received enable signals.

[0018] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0019] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0020] Through the present application, N enable signals are respectively sent out through the first type pins of the N first connectors on the mainboard, through the first type pins of the N second connectors on the backplane, and finally reach the logic control device on the backplane, wherein the second connector is connected to the first connector one-to-one. N indicator light signals are sent to the second type pins of the N first connectors through N transmission channels, and then these indicator light signals are forwarded to the logic control device on the backplane via the second type pins of the N second connectors. When the first enable signal is at a low level, the logic controller parses the indicator light signal corresponding to the first enable signal, and when the second enable signal is at a high level, the logic control device shields the indicator light signal corresponding to the second enable signal. Therefore, the problem in the related art that when the CPU type changes, the lighting control logic needs to be redesigned, resulting in high design costs, etc. can be solved. This greatly enhances the compatibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a hardware structure block diagram of a method for sending an indicator light signal according to an embodiment of the present application;

[0022] Figure 2 is a flow chart of a method for sending an indicator light signal according to an embodiment of the present application;

[0023] Figure 3 is a first schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application;

[0024] Figure 4 is a second schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application;

[0025] Figure 5 is a third schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application;

[0026] Figure 6 is a fourth schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application;

[0027] Figure 7 It is a structural block diagram of an integrated hard disk according to a method for sending indicator light signals according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The method embodiments provided in the embodiments of the present application can be executed in an integrated hard disk or a similar computing device. Taking running on an integrated hard disk as an example, Figure 1 1 is a hardware structure block diagram of a method for sending an indicator light signal according to an embodiment of the present application. Figure 1 As shown, the integrated hard disk may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor or a programmable logic device) and a memory 104 for storing data, wherein the above-mentioned integrated hard disk may also include a transmission device 106 for communication functions and an input and output device 108. A person skilled in the art will understand that Figure 1 The structure shown is only for illustration and does not limit the structure of the integrated hard disk. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for sending the indicator light signal in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the method for sending the above-mentioned indicator light signal. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the integrated hard disk via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the integrated hard disk. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] In this embodiment, a method for sending an indicator light signal is provided, which is applied to the above-mentioned integrated hard disk. Figure 2 is a flow chart of a method for sending an indicator light signal according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0034] Step S202, sending N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of N second connectors connected to the N first connectors in a one-to-one correspondence, wherein the second connectors and the logic control device are both arranged on the backplane;

[0035] Among them, the N enable signals and the N first connectors are in a one-to-one correspondence, and each first connector has a first-class pin. That is, the N enable signals are respectively sent to the first-class pins that exist in the N first connectors. Then the N enable signals are sent to the first-class pins of the N second connectors through the first-class pins. It should be clarified that the N second connectors connected one-to-one by the N first connectors in this embodiment can be understood as, assuming that there are two first connectors, namely the first connector A and the first connector B, the first-class pin of the first connector A corresponds to the first-class pin connected to the second connector A', the second-class pin of the first connector A corresponds to the second-class pin connected to the second connector A', the first-class pin of the first connector B corresponds to the first-class pin connected to the second connector B', and the second-class pin of the first connector B corresponds to the second-class pin connected to the second connector B'.

[0036] Step S204, sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0037] Among them, there is a one-to-one correspondence between the N transmission channels and the N first connectors, and each first connector has a second type of pin. That is, the N indicator light signals are respectively sent to the second type of pins existing in the N first connectors through the N transmission channels. Then, the N indicator light signals are sent to the second type of pins of the N second connectors through the second type of pins.

[0038] Through the above steps, N enable signals are respectively sent to the first type pins of N first connectors, so that the N enable signals are forwarded to the logic control device through the first type pins of N second connectors connected one-to-one with the N first connectors, wherein the second connector and the logic control device are both arranged on the backplane; N indicator light signals are respectively sent to the second type pins of the N first connectors through the N transmission channels, so that the N indicator light signals are forwarded to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal in the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal in the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1. Therefore, the problem that the lighting control logic needs to be redesigned when the CPU type changes, resulting in high design costs, etc. in the related art can be solved, thereby greatly enhancing the compatibility of the system.

[0039] In an exemplary embodiment, before sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, the method also includes: when the central processing unit is connected to the backplane through the hard disk interface card, the N enable signals are forwarded to the logic control device through the first type pins of the N second connectors and the first type pins of N third connectors, wherein the N third connectors are arranged on the hard disk interface card, the first type pins of the N third connectors have been set as ground pins, and the hard disk interface card is connected to both the mainboard and the backplane; when the first type pins of the N third connectors have been set as ground pins, the hard disk interface card is prohibited from adjusting the level status of the N received enable signals.

[0040] In the scenario where the CPU establishes a connection with the backplane through the hard disk interface card, N enable signals are first sent from the CPU, passing through the N first connectors on the motherboard, and then through the first type pins of the N third connectors on the hard disk interface card, and finally reaching the first type pins of the N second connectors on the backplane, so that the enable signals can be forwarded to the logic control device (Complex Programmable Logic Device, referred to as CPLD) on the backplane. It should be clear that the first type pins of the N third connectors in this embodiment are pre-set to ground (GND) pins to ensure that during the forwarding process of the N enable signals, the level state of the above N enable signals will not be modified by any device on the hard disk interface card. Therefore, no matter whether the original state of the enable signal is high or low, it can remain unchanged through the hard disk interface card and directly reach the logic control device on the backplane. When the enable signal is at a low level, the logic control device starts to parse the corresponding indicator light signal; and the high level enable signal instructs the logic control device to shield the corresponding indicator light signal, that is, no lighting operation is performed.

[0041] By setting the first type pin of the third connector in the hard disk interface card as the ground pin, the enable signal level state is prevented from being changed during the transmission process, and the stable forwarding of the enable signal is achieved. This design not only simplifies the lighting control logic, but also reduces the complexity of hardware design and maintenance.

[0042] In an exemplary embodiment, before the N enable signals are forwarded to the logic control device through the first type pins of the N second connectors and the first type pins of the N third connectors, the method also includes: forwarding the N indicator light signals and the N enable signals to the same fourth connector through the N first connectors, wherein the fourth connector, the N third connectors and the controller are all arranged on the hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; forwarding the N indicator light signals and the N enable signals to the controller through the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is used to forward the N indicator light signals and the N enable signals to the N third connectors.

[0043] As attached Figure 6 As shown in FIG. 1 , the N indicator light signals and the N enable signals sent from the CPU are received by the N first connectors on the motherboard. Then, the N indicator light signals and the N enable signals are uniformly forwarded to the fourth connector (equivalent to the attached Figure 6 The fourth connector is responsible for receiving all signals forwarded from the first connector and also for transmitting signals through the first interface bus (equivalent to the attached Figure 6 The controller receives the N indicator light signals and N enable signals from the fourth connector through the first interface bus, and transmits them to the controller through the second interface bus (equivalent to the PCIe of the attached card). Figure 6 The PCIe (connecting the Controller and the MCIO connector) on the Tri-mode card further forwards the N indicator signals and the N enable signals to the third connector.

[0044] It should be clarified that the second interface bus corresponds one-to-one with the third interface bus on the motherboard. Assuming that there are two third interface buses on the motherboard, namely PCIE_PEx_[0:7] and PCIE_PEx_[8:15], there are also two corresponding second interface buses PCIE_PEx_[0:7] and PCIE_PEx_[8:15] on the Tri-mode card (equivalent to the hard disk interface card in this embodiment) to ensure that there is no confusion when the N indicator light signals and N enable signals are transmitted to the third connector through the second interface bus.

[0045] In this embodiment, the Tri-mode card efficiently and accurately forwards N indicator light signals and N enable signals from the CPU through a fourth connector, ensuring that these indicator light signals and enable signals can stably reach the N third connectors on the hard disk interface card and are further correctly processed and applied.

[0046] In an exemplary embodiment, after forwarding the N indicator light signals and the N enable signals to the controller through the fourth connector and the first interface bus, the method further includes: forwarding the N indicator light signals to the N third connectors through the controller and N second interface buses, so as to forward the N indicator light signals to the logic control device through the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0047] As attached Figure 6 As shown, when N indicator lights arrive at the third connector (equivalent to the attached Figure 6 When the N indicator light signals are connected to the MCIO connector on the Tri-mode card, the N indicator light signals are transferred to the second type pins (A8 / A9) of the second connector (MCIO connector on the backplane) through the second type pins (B8 / B9) of the third connector, and then these signals are stably transmitted to the corresponding second type pins of the N second connectors on the backplane through cable connection. Finally, the N indicator light signals are forwarded to the logic control device (i.e., CPLD) through the second connector, and the logic control device parses and processes them to control the display status of the LED indicator lights on the backplane.

[0048] In this embodiment, by forwarding N indicator light signals to the same controller, and then transmitting them to N third connectors through N second interface buses, and forwarding the N indicator light signals to the logic control device through the second type pin of the third connector and the second type pin of the second connector, the complex signal path and hardware matching requirements in the traditional design are avoided, thereby reducing the design cost and maintenance difficulty.

[0049] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method also includes: when the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is in an open state, controlling the enable signal corresponding to the fourth interface bus to be the first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or when the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is in a closed state, controlling the enable signal corresponding to the fifth interface bus to be the second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

[0050] Optionally, assuming that the VMD (virtual machine device queue) state corresponding to 3 interface buses (i.e., the fourth interface bus) among the N third interface buses is in an open state, the enable signal corresponding to the 3 interface buses is controlled to be a first enable signal (i.e., an enable signal in a low-level state). Assuming that the VMD state corresponding to 5 interface buses (i.e., the fifth interface bus) among the N third interface buses is in a closed state, the enable signal corresponding to the 5 interface buses is controlled to be a second enable signal (i.e., an enable signal in a high-level state).

[0051] It should be clear that the addresses of the N third interface buses are consistent with the addresses of the N second interface buses, which means that during the transmission of the enable signal, a mapping relationship is formed between the N third interface buses and the N second interface buses, ensuring that the enable signal is accurately transmitted between the CPU and the backplane.

[0052] In this embodiment, by monitoring and responding to the status of VMD, the high and low levels of the enable signal are intelligently adjusted, and the lighting and extinguishing of the indicator light signal are controlled according to the high and low levels of the enable signal, thereby avoiding incorrect lighting when the VMD is in the off state and improving the accuracy of the indication signal.

[0053] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method also includes: obtaining the first device address of the hard disk interface card and determining the second device addresses of N target hard disks corresponding to N third interface buses; and setting the second device address to the first device address through a write operation.

[0054] Optionally, the VPP slave device address (i.e., the second device address) of all PCIe Ports (i.e., the third interface bus) is set to be consistent with the slave device address (i.e., the first device address) of the Tri-mode card. For example, the VPP slave device address of the PCIe Port and the slave device address of the Tri-mode card are both set to 0x40. Specifically, the VPP_CH1 channel address corresponding to PCIE_PEx_[0:7] is set to 0xE0, and the VPP slave device address is 0x40. The VPP_CH2 channel address corresponding to PCIE_PEx_[8:15] is set to 0xE0, and the VPP slave device address can also be 0x40. The purpose of this is that although the devices under each PCIe Port share the same VPP slave device address (0x40), due to the different channel addresses, the CPU can still accurately control the lighting behavior of each target device.

[0055] This design strategy not only simplifies the hardware link, but also improves the system's compatibility with different device configurations, making the lighting control logic consistent between the CPU direct-connected backplane and the Tri-mode card direct-connected backplane without the need for additional hardware or software adjustments.

[0056] In an exemplary embodiment, the second device address is set to the first device address through a write operation, including: determining a target position where a first character that is inconsistent with the first device address is located; obtaining a second character corresponding to the target position from the first device address; and modifying the first character at the target position in the second device address to the second character, so as to modify the second device address to be consistent with the first device address.

[0057] Optionally, check whether the second device address is exactly the same as the first device address. If they are inconsistent, determine the position of the first different character in the two addresses, that is, the target position. For example, if the first device address is "0x12345678" and the second device address is "0x1234567A", then the different character is "A" and the target position is the last bit of the address. Extract the character at the target position from the first device address, that is, in the above example, the extracted character is "8". Next, modify the different character at the target position in the second device address, which is "A" in the example, to the character "8" obtained from the first device address to ensure that the second device address and the first device address are consistent.

[0058] In this embodiment, the address consistency design enables the system to be seamlessly compatible with different types of CPUs and Tri-mode cards, and the consistent device address simplifies the transmission path of the lighting signal, reduces communication delays and errors, and ensures accurate transmission of the lighting signal.

[0059] In an exemplary embodiment, after forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: in the event that a first target hard disk among the N target hard disks fails, receiving an interrupt request issued by the first target hard disk through the second connector corresponding to the first target hard disk through the sixth interface bus corresponding to the first target hard disk, wherein the N target hard disks are arranged on the backplane; generating an interrupt instruction according to the interrupt request, and sending the interrupt instruction to the second type pin of the first connector corresponding to the sixth interface bus through the sixth interface bus, so as to send the interrupt instruction to the logic control device through the second type pin of the second connector corresponding to the sixth interface bus, so as to shut down the first target hard disk.

[0060] It should be clear that in this embodiment, N target hard disks are set on the backplane, and the indicator light signal is used to reflect the operating status of the target hard disk. For example, the indicator light is on, which means that the target hard disk is in normal working condition, and the indicator light is off, which means that the target hard disk has a fault.

[0061] In an exemplary embodiment, after turning off the first target hard disk, the method further includes: when the difference between the time when the first target hard disk is turned off and the current time is greater than a preset time, sending a startup instruction to the logic control device through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

[0062] Optionally, assuming that three target hard disks (i.e., the first target hard disk) among the N target hard disks fail, these three target hard disks will send an interrupt request to the CPU. These three target hard disks send the interrupt request to the second connectors corresponding to these three target hard disks through their corresponding three interface buses (i.e., the sixth interface bus). Since the second connector is connected to the first connector, the above interrupt request is transmitted to the CPU through the first connector. After receiving the interrupt request, the CPU generates an interrupt instruction, and then sends the interrupt instruction to the logic control device through the sixth interface bus, the second type pin of the first connector corresponding to the sixth interface bus, and the second type pin of the second connector corresponding to the sixth interface bus. After receiving the interrupt instruction, the logic control device will immediately execute the operation of shutting down the first target hard disk to prevent the faulty hard disk from further affecting the overall performance of the system.

[0063] Assuming that the hard disk failure is temporary or there is a problem at the software level, it is necessary to attempt to restart the failed hard disk. Therefore, when the difference between the time when the hard disk is turned off and the current time is greater than the preset time, the startup instruction is sent to the logic control device through the sixth interface bus, again using the second type pin of the first connector and the second type pin of the second connector. The setting of this preset time threshold is to ensure that the CPU has enough time to perform fault diagnosis and status evaluation before attempting to restart the hard disk, avoiding instability and waste of resources caused by frequent restarts. After receiving the startup instruction, the logic control device will immediately execute the operation of restarting the first target hard disk. This process may involve operations such as resetting the hardware status of the hard disk, refreshing the firmware configuration, or re-establishing the data communication link, all of which are aimed at trying to restore the normal working state of the hard disk.

[0064] In this embodiment, an interrupt instruction is quickly generated through the interrupt request sent by the first target hard disk, thereby realizing a rapid response to the fault. When the difference between the shutdown time of the first target hard disk and the current time exceeds the preset time, a startup instruction can be automatically sent through the same communication path to restart the first target hard disk. This recovery mechanism ensures that the system can try to restore the normal operation of the hard disk without manual intervention, thereby enhancing the self-healing ability and availability of the system.

[0065] In an exemplary embodiment, before sending N enable signals to the first type pins of N first connectors respectively, the method further includes: sending a target address through an integrated circuit interconnect bus to determine a target IO expander that communicates with the central processing unit from a plurality of IO expanders, wherein the plurality of IO expanders are connected to the central processing unit; sending a register address to the target IO expander to determine a target register that controls the N enable signals, wherein the target register exists in an internal storage space of the target IO expander; writing 0 at a target position of the target register to control the first enable signal to be a low level, and writing 1 at the target position to control the second enable signal to be a high level.

[0066] The CPU sends a target address signal through the I2C bus. The I2C bus is a two-wire serial bus for communication between a microcontroller and multiple peripheral devices. In this scenario, since multiple IO expanders are connected to the CPU, the CPU needs to determine the target IO expander that needs to be communicated with by sending a specific address signal. Once the target IO expander is determined, the CPU will further send a register address signal to the IO expander through the I2C bus. The IO expander usually contains multiple registers for storing and controlling different IO signal states. By sending a specific register address, the CPU can accurately locate the target register that controls N enable signals. This step ensures that subsequent write operations can directly act on the register that manages the enable signal, thereby achieving precise signal control. After the target register is successfully located, the CPU will perform a write operation to control the first enable signal to be low (0) or to control the second enable signal to be high (1). This operation is performed directly at the target location of the target register, and the state of the enable signal can be adjusted instantly by changing a specific bit in the register. For example, if a certain bit of the target register is set to 0, the first enable signal associated therewith will be pulled low, whereas if the bit is set to 1, the second enable signal will be pulled high.

[0067] In this embodiment, through the address communication of the I2C bus, the CPU and multiple IO expanders perform intelligent selection and communication. Even if there are more IO expanders or enable signals, the expansion and adaptation of the control logic can be easily achieved through dynamic address sending and register positioning.

[0068] In an exemplary embodiment, after forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: when the first enable signal exists among the N enable signals, lighting up the indicator light corresponding to the first enable signal through the logic control device; and when the second enable signal exists among the N enable signals, turning off the indicator light corresponding to the second enable signal through the logic control device.

[0069] When the first enable signal exists among the N enable signals, that is, the first enable signal is in a low level state, it is regarded as an enable or activation signal. In this case, the logic control device (such as CPLD) detects the existence of the first enable signal and interprets the first enable signal as an instruction to light up the indicator light. Therefore, the indicator light corresponding to the first enable signal will be lit. On the contrary, when the second enable signal exists among the N enable signals, that is, the second enable signal is in a high level state, it is regarded as a disable or shield signal. When the logic control device detects the second enable signal, it will understand the second enable signal as a command to turn off the indicator light. Therefore, the indicator light corresponding to the second enable signal will be turned off.

[0070] In this embodiment, by distinguishing different enable signal states, the logic control device can accurately control the lighting or extinguishing of the indicator light, which not only improves the friendliness of the user interface and the accuracy of information, but also simplifies hardware design and software control, reduces costs, and enhances the overall performance and reliability of the system.

[0071] In order to better understand the process of the above-mentioned method for sending the indicator light signal, the above-mentioned method for sending the indicator light signal is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0072] Figure 3 is a first schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application. Figure 3 As shown, the specific steps include:

[0073] In the prior art, the CPU, as a master device, can communicate with multiple slave devices to control the LED indication status of each peripheral component interconnect express port (PCIePort for short). The core of this design is that each CPU is equipped with only one set of virtual pin interface (VirtualPin Port, VPP for short) buses, and this set of VPP buses needs to cover the indicator signal management of all PCIe Ports under the CPU. Therefore, when designing the motherboard, this set of VPP buses is connected to an independent connector to facilitate signal transmission and management.

[0074] In order to distinguish different PCIe ports, the concept of Strap Pin is introduced on the motherboard. Strap Pin is a specific pin set on the PCIe connector to identify different PCIe ports, so as to achieve precise control of indicator light signals in complex system environments. However, the effectiveness of the VPP signal is affected by the state of the Virtual Machine Device Queues (VMD). When VMD is in the off state, the VPP signal may transmit the wrong indicator light signal, which will cause confusion in the LED indication state and is not conducive to system status monitoring.

[0075] In order to solve the above technical problems, the CPU obtains the VMD status information corresponding to the PCIe Port and transmits the VMD status information to the CPLD on the backplane through the I2C bus. The CPLD is the indicator light management unit on the backplane. The information transmission between the CPU and the CPLD ensures that the CPLD can accurately parse the VPP indicator light signal and execute the correct LED control instruction according to the VMD status.

[0076] Specifically, in the backplane design, the VPP Header and the Multipurpose Card I / O (MCIO) connector are connected to the corresponding connector on the motherboard through cables to achieve the transmission of VPP indicator signals and PCIe signals. At the same time, the I2C Header is also connected to the I2C bus on the motherboard through cables to receive the VMD status information transmitted by the CPU. After receiving the VPP signal, the CPLD first uses the Strap Pin connected to the MCIO connector to identify which PCIe Port information is received, and then parses the VMD status of the corresponding PCIe Port from the I2C bus. Based on the judgment of the VMD status, if VMD is turned on, the CPLD will extract the indicator signal of the VPP address corresponding to the PCIe Port from the VPP signal, and control the LED indication status of the corresponding hard disk through the General Purpose Input / Output (GPIO) interface to achieve accurate indicator control.

[0077] In this design, a close association is formed between the Strap Pin, PCIe Port, VPP address and VMD status. The backplane CPLD must first obtain the PCIe Port information through the Strap Pin, and then parse the corresponding VMD status from the I2C bus, and further obtain the VPP address, ultimately ensuring that the indicator light signal parsed from the VPP signal is correct, thereby accurately controlling the LED indication status of the hard disk.

[0078] Figure 4 is a second schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application, such as Figure 4 As shown, the specific steps include:

[0079] As an integrated multi-functional interface card, the Tri-mode card uses the VPP signal to control the indicator light status of the hard disk, thereby realizing an intuitive indication of the hard disk operation status, wherein the Tri-mode card is connected to the hard disk. The Tri-mode card integrates the VPP signal in each MCIO connector. Each connector contains two sets of VPP indicator light signals, and these two sets of signals carry the indicator light signals of all the hard disks under the MCIO connector. This means that no matter how many hard disks are under the connector, only one set of VPP signals needs to be parsed to obtain the indicator light control instructions of all the hard disks, thereby realizing unified control and indicator light operation of all the hard disks under the entire connector.

[0080] Specifically, the MCIO connector of the Tri-mode card is directly connected to the MCIO connector on the backplane through a cable. In the backplane design, the first set of VPP signals of the MCIO connector is routed to the CPLD. In this way, the CPLD can receive and parse the first set of VPP signals from the Tri-mode card, and extract the indicator light signals for controlling the two hard disks. Based on the parsed information, the CPLD controls the LED on the corresponding hard disk through the GPIO signal it outputs, thereby realizing visual feedback on the hard disk status.

[0081] Figure 5 is a third schematic diagram of a method for sending an indicator light signal according to an embodiment of the present application, such as Figure 5 As shown, the specific steps include:

[0082] In this embodiment, the original VPP signal of the CPU (equivalent to the indicator light signal in this embodiment) is connected to the I2CSwitch (equivalent to the channel expansion component in this embodiment). Through the I2C Switch, the original single VPP signal is expanded into two independent transmission channels: VPP_CH1 and VPP_CH2. Each transmission channel has a specific function. VPP_CH1 is responsible for transmitting the indicator light signal of the PCIE_PEx_[0:7] port (equivalent to the first of the two third interface buses in this embodiment), while VPP_CH2 is responsible for transmitting the information of the PCIE_PEx_[8:15] port (equivalent to the second of the two third interface buses in this embodiment). This design means that the indicator light instructions of each PCIe x8 port are transmitted and controlled independently, which improves the accuracy and flexibility of indicator light control.

[0083] At the same time, in order to ensure that this design is compatible with the Tri-mode card (equivalent to the hard disk interface card in this embodiment), two groups of VPP signals (VPP_CH1 and VPP_CH2) are connected to the B8 / B9 pins of the MCIO connector (equivalent to the second type of pins in this embodiment), which are specific points for the Tri-mode card to receive indicator light signals. In this way, whether the CPU is directly connected to the backplane or connected to the backplane through the Tri-mode card, the receiving method and pin definition of the VPP signal are consistent. In addition, the VPP slave device address of all PCIe Ports is set to be consistent with the slave device address of the Tri-mode card, for example, the VPP slave device address of the PCIePort and the slave device address of the Tri-mode card are both set to 0x40. Specifically, in the Basic Input Output System (BIOS), the VPP_CH1 channel address corresponding to PCIE_PEx_[0:7] is set to 0xE0, the VPP slave device address is 0x40, and the VPP_CH2 channel address corresponding to PCIE_PEx_[8:15] is set to 0xE0, and the VPP slave device address can also be 0x40. The purpose of this is that although the devices under each PCIe Port share the same VPP slave device address (0x40), due to the different channel addresses, the CPU can still accurately control the lighting behavior of each device. This design strategy not only simplifies the hardware link, but also improves the system's compatibility with different device configurations, so that the lighting control logic remains consistent between the CPU direct backplane and the Tri-mode card direct backplane, without the need for additional hardware or software adjustments.

[0084] In this embodiment, the IOExpander (equivalent to the IO expander in this embodiment) is also connected to the CPU through the I2C bus (equivalent to the integrated circuit interconnection bus in this embodiment), wherein the IO Expander expands two enable signals: FM_VPP_CH1_EN_N and FM_VPP_CH2_EN_N, which are respectively connected to the B28 pins of the two MCIO connectors (equivalent to the first type of pins in this embodiment) to control the enable or disable state of the corresponding VPP channels (VPP_CH1 and VPP_CH2). Taking VPP_CH1 as an example, when the VMD state corresponding to PCIE_PEx_[0:7] is on, the CPU sets FM_VPP_CH1_EN_N to a low level through the I2C bus, thereby allowing the CPLD on the backplane to parse the indicator light signal of VPP_CH1; and when the VMD state is off, the CPU sets FM_VPP_CH1_EN_N to a high level, which means that the CPLD needs to shield the indicator light signal of VPP_CH1 to avoid triggering the indicator light behavior under inapplicable conditions. Similarly, the control logic of VPP_CH2 is consistent with that of VPP_CH1, ensuring the consistency and effectiveness of the control of all PCIe port indicator lights.

[0085] In terms of hardware connection, the MCIO connector of the backplane (equivalent to the second connector in this embodiment) is connected to the MCIO connector of the mainboard (equivalent to the first connector in this embodiment) through a cable. Specifically, when the backplane is connected to the mainboard, the B8 / B9 pin of the mainboard MCIO connector transmits the VPP signal to the A8 / A9 pin of the backplane MCIO connector (equivalent to the second type of pin in this embodiment), and then the CPLD on the backplane (equivalent to the logic control device in this embodiment) is connected to the A8 / A9 pin and the A28 pin through a cable. The CPLD determines whether to parse the VPP signal on the A8 / A9 pin and whether to perform indicator light control based on the state of the FM_VPPx_EN_N signal received from the A28 pin (equivalent to the first type of pin in this embodiment). If the FM_VPPx_EN_N signal is low, the CPLD parses the VPP signal and executes the corresponding indicator light behavior; conversely, if the signal is high, the CPLD will not parse the VPP signal to avoid misoperation or incorrect indicator light indication.

[0086] Through the above design, not only can the CPU realize complex indicator light control of the direct-connected backplane, but also the consistency and compatibility of the indicator light control solution are ensured when replacing or using different types of CPUs or Tri-mode cards by unifying the pin definition and control logic with the Tri-mode card.

[0087] Figure 6is a fourth schematic diagram of a device for sending an indicator light signal according to an embodiment of the present application, such as Figure 6 As shown, the specific steps include:

[0088] In this embodiment, the mainboard is connected to the HSCONN (equivalent to the fourth connector in this embodiment) of the Tri-mode card through a cable to transmit N enable signals and N indicator light signals to the Tri-mode card. HSCONN transmits the N enable signals and N indicator light signals to the controller of the Tri-mode card through the PCIe bus, and the controller forwards the N enable signals and N indicator light signals to the MCIO connector of the Tri-mode card (equivalent to the third connector in this embodiment). It is worth noting that each MCIO connector in the Tri-mode card integrates two groups of VPP signals (B8 / B9 and B26 / B27), but these two groups of signals both contain the indicator light signals of all connected target hard disks, so only one group of VPP signals needs to be parsed to control the indicator light status of all target hard disks under the connector.

[0089] In this embodiment, the VPP signal of the B8 / B9 pin is selected as the parsing target of the indicator light behavior. When the Tri-mode card is connected to the backplane, the MCIO connector on the backplane is connected to the MCIO connector on the mainboard by adopting a cable design with the A and B side pins reversed. This ensures that the VPP signal of the B8 / B9 pin of the Tri-mode card can pass through the cable smoothly, and finally reach the A8 / A9 pin of the backplane MCIO connector, and then be transmitted to the CPLD for signal parsing. As the control center on the backplane, the CPLD is responsible for receiving and parsing these VPP signals, parsing the indicator light signal of the 0x40 slave address, so as to accurately control the LED indication of each hard disk.

[0090] At the same time, the B28 pin of the Tri-mode card MCIO connector is used as a ground signal and is connected to the A28 pin of the MCIO connector of the backplane through a cable. In the design, the ground signal of the B28 pin will steadily pull down the enable signal FM_VPPx_EN_N, which is equivalent to telling the CPLD on the backplane to always parse the VPP signal of the A8 / A9 pin regardless of the state of VMD. In this way, even in the Tri-mode card environment, the CPLD can stably and accurately parse the VPP signal and control the hard disk LED to display status information.

[0091] In summary, the design shown in this embodiment realizes the compatible transmission and analysis of the VPP indicator signal between the Tri-mode card and the backplane. It not only simplifies the design complexity of hardware and software, but also ensures that no matter how the CPU type changes, the indicator control system on the backplane can accurately reflect the working status of the hard disk under the Tri-mode card, effectively overcoming the problem of indicator control logic redesign caused by CPU type changes in the prior art.

[0092] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0093] Figure 7 is a structural block diagram of an integrated hard disk according to a method for sending an indicator light signal according to an embodiment of the present application, such as Figure 7 As shown, the integrated hard disk includes:

[0094] A mainboard 700, on which a central processing unit 704 and N first connectors 706 are disposed, wherein the transmission channels of the virtual pin interface of the central processing unit 704 have been expanded to N channels through a channel expansion component, and the N transmission channels are connected to the N first connectors 706 on the mainboard in a one-to-one correspondence;

[0095] A backplane 702 , on which N second connectors 710 and a logic control device 708 are disposed;

[0096] The central processor 704 is used to send N enable signals to the first type pins of the N first connectors 706 respectively, so as to forward the N enable signals to the logic control device 708 through the first type pins of the N second connectors 710 connected one-to-one with the N first connectors 706, wherein the N second connectors 710 and the logic control device 708 are arranged on the backplane 702; and send N indicator light signals to the second type pins of the N first connectors 706 respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device 708 through the second type pins of the N second connectors 710, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device 708 to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device 708 to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0097] The integrated hard disk also includes: a hard disk interface card 712 connected to both the mainboard 700 and the backplane 702, and the central processor 704, which is used to forward the N enable signals to the logic control device 708 through the fourth connector 716, the first type pins of the N second connectors 710, and the first type pins of N third connectors 714 when the central processor 704 is connected to the backplane 702 through the hard disk interface card 712, wherein the N third connectors 714 are arranged on the hard disk interface card 712, and the first type pins of the N third connectors 714 are set as ground pins; when the first type pins of the N third connectors 714 are set as ground pins, the hard disk interface card 712 is prohibited from adjusting the level status of the received N enable signals.

[0098] In an embodiment of the present application, N enable signals are respectively sent to the first type pins of N first connectors, so that the N enable signals are forwarded to the logic control device through the first type pins of N second connectors connected one-to-one with the N first connectors, wherein the second connector and the logic control device are both arranged on the backplane; N indicator light signals are respectively sent to the second type pins of the N first connectors through the N transmission channels, so that the N indicator light signals are forwarded to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal in the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal in the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1. The above technical solution solves the problem that in the related art, when the CPU type changes, the lighting control logic needs to be redesigned, resulting in high design costs.

[0099] In an exemplary embodiment, the hard disk interface card 712 is also used to forward the N enable signals to the logic control device through the first type pins of the N second connectors and the first type pins of the N third connectors when the central processing unit is connected to the backplane through the hard disk interface card, wherein the N third connectors are arranged on the hard disk interface card, the first type pins of the N third connectors have been set as ground pins, and the hard disk interface card is connected to both the mainboard and the backplane; when the first type pins of the N third connectors have been set as ground pins, the hard disk interface card is prohibited from adjusting the level status of the N received enable signals.

[0100] In an exemplary embodiment, the central processing unit 704 is also used to forward the N indicator light signals and the N enable signals to the same fourth connector through the N first connectors, wherein the fourth connector, the N third connectors and the controller are all arranged on the hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; the N indicator light signals and the N enable signals are forwarded to the controller through the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected through the first interface bus; the controller is used to forward the N indicator light signals and the N enable signals to the N third connectors.

[0101] In an exemplary embodiment, the hard disk interface card 712 is also used to forward the N indicator light signals to the N third connectors through the controller and N second interface buses, so as to forward the N indicator light signals to the logic control device through the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

[0102] In an exemplary embodiment, the central processor 704 is also used to control the enable signal corresponding to the fourth interface bus to be the first enable signal when the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is in an open state, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or when the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is in a closed state, control the enable signal corresponding to the fifth interface bus to be the second enable signal, wherein the N third interface buses are respectively connected to the central processor and the N first connectors.

[0103] In an exemplary embodiment, the central processor 704 is also used to obtain the first device address of the hard disk interface card and determine the second device addresses of N target hard disks corresponding to N third interface buses; and set the second device address to the first device address through a write operation.

[0104] In an exemplary embodiment, the central processor 704 is also used to determine a target position where a first character that is inconsistent between the second device address and the first device address is located; obtain a second character corresponding to the target position from the first device address; and modify the first character at the target position in the second device address to the second character, so as to modify the second device address to be consistent with the first device address.

[0105] In an exemplary embodiment, the central processor 704 is also used to receive an interrupt request sent by the first target hard disk through the second connector corresponding to the first target hard disk through the sixth interface bus corresponding to the first target hard disk, when a first target hard disk among the N target hard disks fails, wherein the N target hard disks are arranged on the backplane; generate an interrupt instruction according to the interrupt request, and send the interrupt instruction through the sixth interface bus to the second type pin of the first connector corresponding to the sixth interface bus, so as to send the interrupt instruction to the logic control device through the second type pin of the second connector corresponding to the sixth interface bus, so as to shut down the first target hard disk.

[0106] In an exemplary embodiment, the central processing unit 704 is also used to send a startup instruction to the logic control device through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk when the difference between the time when the first target hard disk was shut down and the current time is greater than a preset time.

[0107] In an exemplary embodiment, the central processor 704 is further configured to send a target address through an integrated circuit interconnect bus to determine a target IO expander communicating with the central processor from a plurality of IO expanders, wherein the plurality of IO expanders are connected to the central processor; send a register address to the target IO expander to determine a target register for controlling the N enable signals, wherein the target register exists in an internal storage space of the target IO expander; write 0 at a target position of the target register to control the first enable signal to be at a low level, and write 1 at the target position to control the second enable signal to be at a high level.

[0108] In an exemplary embodiment, the central processor 704 is also used to, when the first enable signal exists among the N enable signals, light up the indicator light corresponding to the first enable signal through the logic control device; and when the second enable signal exists among the N enable signals, turn off the indicator light corresponding to the second enable signal through the logic control device.

[0109] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0110] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0111] S1, sending N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of N second connectors connected to the N first connectors in a one-to-one correspondence, wherein the second connectors and the logic control device are both arranged on the backplane;

[0112] S2, sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0113] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0114] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0115] Optionally, in this embodiment, the computer program may be configured to perform the following steps by means of the computer program:

[0116] S1, sending N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of N second connectors connected to the N first connectors in a one-to-one correspondence, wherein the second connectors and the logic control device are both arranged on the backplane;

[0117] S2, sending N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1.

[0118] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0119] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0120] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for sending an indicator light signal, characterized in that: Applied to an integrated hard disk, the integrated hard disk comprises: a mainboard, a backplane connected to the mainboard, the transmission channels of the virtual pin interface of the central processing unit on the mainboard have been expanded to N through a channel expansion component, and the N transmission channels are connected to the N first connectors on the mainboard in a one-to-one correspondence, including: Sending N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of N second connectors connected to the N first connectors in a one-to-one correspondence, wherein the second connectors and the logic control device are both arranged on the backplane, and the first type pins of the first connectors are connected to the first type pins of the second connectors; The N indicator light signals are respectively sent to the second type pins of the N first connectors through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal among the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal among the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1, and the second type pin of the first connector is connected to the second type pin of the second connector.

2. The method for sending an indicator light signal according to claim 1, characterized in that: Before respectively sending the N indicator light signals to the second type pins of the N first connectors through the N transmission channels, the method further includes: In the case where the central processing unit is connected to the backplane via a hard disk interface card, the N enable signals are forwarded to the logic control device via the first type pins of the N second connectors and the first type pins of the N third connectors, wherein the N third connectors are provided on the hard disk interface card, the first type pins of the N third connectors are provided as ground pins, and the hard disk interface card is connected to both the mainboard and the backplane; In a case where the first type pins of the N third connectors have been set as ground pins, the hard disk interface card is prohibited from adjusting the level states of the N received enable signals.

3. The method for sending indicator light signals according to claim 2, characterized in that: Before the N enable signals are forwarded to the logic control device through the first type pins of the N second connectors and the first type pins of the N third connectors, the method further includes: forwarding the N indicator light signals and the N enable signals to the same fourth connector through the N first connectors, wherein the fourth connector, the N third connectors and the controller are all arranged on the hard disk interface card, and the fourth connector and the N third connectors are connected through the controller; The N indicator light signals and the N enable signals are forwarded to the controller via the fourth connector and the first interface bus, wherein the fourth connector and the controller are connected via the first interface bus; the controller is used to forward the N indicator light signals and the N enable signals to the N third connectors.

4. The method for sending indicator light signals according to claim 3, characterized in that: After forwarding the N indicator light signals and the N enable signals to the controller through the fourth connector and the first interface bus, the method further includes: The N indicator light signals are forwarded to the N third connectors through the controller and N second interface buses, so as to be forwarded to the logic control device through the second type pins of the N third connectors and the second type pins of the N second connectors, wherein the N second interface buses are respectively connected to the same controller and the N third connectors.

5. The method for sending an indicator light signal according to claim 1, characterized in that: Before sending the N enable signals to the first type pins of the N first connectors respectively, the method further includes: When the state of the virtual machine device queue corresponding to the fourth interface bus among the N third interface buses is in the open state, the enable signal corresponding to the fourth interface bus is controlled to be the first enable signal, wherein the addresses of the N third interface buses are consistent with the addresses of the N second interface buses; and / or When the state of the virtual machine device queue corresponding to the fifth interface bus among the N third interface buses is in the closed state, the enable signal corresponding to the fifth interface bus is controlled to be the second enable signal, wherein the N third interface buses are respectively connected to the central processing unit and the N first connectors.

6. The method for sending indicator light signals according to claim 1, characterized in that: Before sending the N enable signals to the first type pins of the N first connectors respectively, the method further includes: Acquire the first device address of the hard disk interface card, and determine the second device addresses of N target hard disks corresponding to N third interface buses, wherein the hard disk interface card is connected to the central processor and the backplane; The second device address is set to the first device address through a write operation.

7. The method for sending indicator light signals according to claim 6, characterized in that: Setting the second device address to the first device address through a write operation includes: Determine a target position where a first character that is inconsistent between the second device address and the first device address is located; Acquire a second character corresponding to the target position from the first device address; The first character at the target position in the second device address is modified to the second character, so as to modify the second device address to be consistent with the first device address.

8. The method for sending indicator light signals according to claim 1, characterized in that: After forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: In the case that a first target hard disk among the N target hard disks fails, receiving an interrupt request sent by the first target hard disk through a second connector corresponding to the first target hard disk through a sixth interface bus corresponding to the first target hard disk, wherein the N target hard disks are arranged on the backplane; An interrupt instruction is generated according to the interrupt request, and the interrupt instruction is sent through the sixth interface bus to the second type pin of the first connector corresponding to the sixth interface bus, so as to send the interrupt instruction to the logic control device through the second type pin of the second connector corresponding to the sixth interface bus to shut down the first target hard disk.

9. The method for sending indicator light signals according to claim 8, characterized in that: After shutting down the first target hard disk, the method further includes: When the difference between the time of shutting down the first target hard disk and the current time is greater than the preset time, a startup instruction is sent to the logic control device through the second type pin of the first connector corresponding to the sixth interface bus and the second type pin of the second connector corresponding to the sixth interface bus to restart the first target hard disk.

10. The method for sending indicator light signals according to claim 1, characterized in that: Before sending the N enable signals to the first type pins of the N first connectors respectively, the method further includes: Sending a target address through an integrated circuit interconnect bus to determine a target IO expander that communicates with the central processor from a plurality of IO expanders, wherein the plurality of IO expanders are connected to the central processor; Sending a register address to the target IO expander to determine a target register that controls the N enable signals, wherein the target register exists in an internal storage space of the target IO expander; Writing 0 in the target position of the target register controls the first enable signal to be at a low level, and writing 1 in the target position controls the second enable signal to be at a high level.

11. The method for sending indicator light signals according to claim 1, characterized in that: After forwarding the N indicator light signals to the logic control device through the second type pins of the N second connectors, the method further includes: When the first enable signal exists among the N enable signals, lighting an indicator light corresponding to the first enable signal through the logic control device; When the second enable signal exists among the N enable signals, the indicator light corresponding to the second enable signal is turned off by the logic control device.

12. An integrated hard disk, characterized in that: include: A mainboard, wherein a central processing unit and N first connectors are arranged on the mainboard, the transmission channels of the virtual pin interface of the central processing unit have been expanded to N channels through a channel expansion component, and the N transmission channels are connected to the N first connectors on the mainboard in a one-to-one correspondence; A backplane, wherein N second connectors and logic control devices are provided on the backplane; The central processing unit is used to send N enable signals to the first type pins of N first connectors respectively, so as to forward the N enable signals to the logic control device through the first type pins of N second connectors connected one-to-one with the N first connectors, wherein the N second connectors and the logic control device are arranged on a backplane, and the first type pin of the first connector is connected to the first type pin of the second connector; and send N indicator light signals to the second type pins of the N first connectors respectively through the N transmission channels, so as to forward the N indicator light signals to the logic control device through the second type pins of the N second connectors, wherein the low-level first enable signal in the N enable signals is used to instruct the logic control device to parse the indicator light signal corresponding to the first enable signal, and the high-level second enable signal in the N enable signals is used to instruct the logic control device to shield the indicator light signal corresponding to the second enable signal, and N is an integer greater than 1, and the second type pin of the first connector is connected to the second type pin of the second connector.

13. The integrated hard disk according to claim 12, characterized in that: The integrated hard disk further comprises: a hard disk interface card connected to both the main board and the backplane, the central processor, which is used to forward the N enable signals to the logic control device through the first type pins of the N second connectors and the first type pins of the N third connectors when the central processor is connected to the backplane through the hard disk interface card, wherein the N third connectors are provided on the hard disk interface card, and the first type pins of the N third connectors are provided as ground pins; In a case where the first type pins of the N third connectors have been set as ground pins, the hard disk interface card is prohibited from adjusting the level states of the N received enable signals.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 11 when executed by a processor.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 11 are implemented.

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