Program detection method and apparatus

Abstract

The application provides a program detection method and device, which can help a user to quickly complete the check of program running on a weak memory environment, improve the detection efficiency of the program, and be applied to program detection. The method comprises the following steps: receiving a program provided by a user, and obtaining a result of the program running on the weak memory environment according to a query parameter and the program. The query parameter is used to indicate a maximum interval of reordering of two operations of the program.

Description

[0001] This application is a divisional application, the original application number is: 202011608587.6, the original application date is December 29, 2020, and the entire contents of the original application are incorporated into the present application by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication, in particular to a program detection method and device. BACKGROUND

[0003] The strong memory model and the weak memory model are two storage models. The strong memory model describes that each instruction implies acquire and release semantics. The acquire semantics can be used to prevent the out-of-order of read-acquire and any read-write operation after it, and the release semantics can be used to prevent the out-of-order of write-release and any read-write operation before it. That is, the write operation sequence of a core on the memory can be observed by other cores of the central processing unit (CPU) in the same order. The weak memory model describes that any read-write operation on the memory in an independent thread can exchange the order with other read-write operations without changing the behavior of the thread.

[0004] Due to the lag of the software ecological environment of the weak memory model, the program developed based on the strong memory model platform may cause abnormal phenomena such as program crash, restart or calculation result error after being transplanted to the weak memory model platform. Therefore, experienced program developers need to repeatedly test and debug the program to analyze whether the program running on the weak memory model platform will cause abnormal phenomena. However, the above-mentioned abnormal phenomena such as program crash, restart or calculation result error have low recurrence probability, are limited by test cases and test environment, have high cost of reproducing problems, and require high professional ability of test personnel. SUMMARY

[0005] The embodiments of the present application provide a program detection method and device, which can help users to quickly complete the check of the program running on the weak memory model platform, and can improve the detection efficiency of the program.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, a program detection method is provided. The program detection method comprises: receiving a program provided by a user, and obtaining a result of the program running in a weak memory environment according to a query parameter and the program. The query parameter is used to indicate a maximum interval of reordering of two operations of the program.

[0008] Based on the program detection method in the first aspect, the program detection apparatus receives the program provided by the user, and obtains the result of the program running in the weak memory environment according to the query parameter used to indicate the maximum interval of reordering of the two operations of the program, which can help the user to quickly complete the checking of the program running in the weak memory environment, and can improve the detection efficiency of the program and reduce the professional requirement for the user.

[0009] In a possible design, the obtaining of the result of the program running in the weak memory environment according to the query parameter and the program can include: obtaining the result of the program running in the weak memory environment according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread. Optionally, the first operation and the third operation can be a pair of read-write operations on a same variable, the second operation and the fourth operation can be a pair of read-write operations on the same variable, the first operation and the second operation can be operations on different variables, and the third operation and the fourth operation can be operations on the different variables. In this way, the user does not need to test the program, and the detection efficiency of the program can be improved.

[0010] In a possible design, the program detection method provided in the first aspect can further include: detecting the first operation in the first thread, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread of the program according to a memory read-write mode query rule, and obtaining the result of the program running in the weak memory environment.

[0011] Optionally, the memory read-write mode query rule can be determined according to the query parameter, and the memory read-write mode query rule can be used to determine whether the first thread and the second thread overlap in time. In this way, if the program satisfies the memory read-write mode query rule, the result is incorrect, for example, the weak memory order problem is prone to occur; and if the program does not satisfy the memory read-write mode query rule, the result is correct, for example, the result of running on a weak memory model platform is correct, the user does not need to repeatedly test the program, and the result of the program running in the weak memory environment can be quickly obtained.

[0012] Optionally, the memory read-write mode query rule can comprise a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule. In this way, the running result of a program comprising at least two threads, one of which comprises a read-read operation and the other of which comprises a write-write operation, on a weak memory environment can be checked, and / or the running result of a program comprising at least two threads, one of which comprises a read-write operation and the other of which comprises a write-read operation, on a weak memory environment can be checked.

[0013] In a possible design, the query parameter can be determined by a user, and the query parameter can comprise an in-chip write operation delay. Optionally, the query parameter can further comprise a cross- NUMA write operation delay and / or a cross- NUMA read operation delay. In this way, the memory read-write mode query can be performed according to the query parameter input by the user.

[0014] In a possible design, the program detection method provided in the first aspect can further comprise: obtaining a value corresponding to the query parameter. The value corresponding to the query parameter can comprise a value corresponding to the in-chip write operation delay. Optionally, the value corresponding to the query parameter can further comprise a value corresponding to the cross- NUMA write operation delay and / or a value corresponding to the cross- NUMA read operation delay.

[0015] Optionally, the weak memory environment can be a running environment corresponding to a running device of a non-uniform memory access architecture (NUMA).

[0016] In a possible design, the program detection method provided in the first aspect can further comprise: providing a result to a user. The result can comprise a modification suggestion. In this way, the user can manually modify the program according to the modification suggestion, thereby helping the user to quickly locate a position in the program that causes an error of the program, quickly complete modification of the program, and improve the modification efficiency of the program.

[0017] Optionally, the result can comprise correct. Alternatively, the result can comprise an error and / or a modification suggestion.

[0018] Optionally, the modification suggestion can comprise position information of code that needs to be modified, for example, a code line number and / or a program file name, and the modification suggestion can be used for the program detection apparatus to modify the program or for the user to manually modify the program.

[0019] In a possible design, the program detection method provided in the first aspect can further comprise: modifying the program according to the modification suggestion in response to a determination indication of the user. In this way, the user can be directly helped to complete modification of the program, and the modification efficiency of the program is further improved.

[0020] In a second aspect, a program detection apparatus is provided. The program detection apparatus comprises a receiving unit and an obtaining unit. The receiving unit is configured to receive a program provided by a user. The obtaining unit is configured to obtain a result of running the program in a weak memory environment according to a query parameter and the program. The query parameter is used to indicate a maximum interval of reordering of two operations of the program.

[0021] In a possible design, the obtaining unit is further configured to obtain the result of running the program in the weak memory environment according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread. Optionally, the first operation and the third operation are a pair of read-write operations on a same variable, the second operation and the fourth operation are a pair of read-write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on the different variables.

[0022] In a possible design, the obtaining unit is further configured to detect the first operation in the first thread, the second operation in the first thread, the third operation in the second thread of the program and the fourth operation in the second thread of the program according to a memory read-write pattern query rule, and obtain the result of running the program in the weak memory environment.

[0023] Optionally, the memory read-write pattern query rule can be determined according to the query parameter, and the memory read-write pattern query rule can be used to determine whether the first thread and the second thread overlap in time.

[0024] In a possible design, the memory read-write pattern query rule can comprise a read-read, write-write reordering query rule, and / or a read-write, write-read reordering query rule.

[0025] In a possible design, the query parameter can be determined by the user, and the query parameter can comprise an on-chip write operation delay. Optionally, the query parameter can further comprise a cross- NUMA write operation delay and / or a cross- NUMA read operation delay. In this way, the memory read-write pattern query can be performed according to the query parameter input by the user.

[0026] In a possible design, the obtaining unit is further configured to obtain a value corresponding to the query parameter. The value corresponding to the query parameter can comprise a value corresponding to the on-chip write operation delay. Optionally, the value corresponding to the query parameter can further comprise a value corresponding to the cross- NUMA write operation delay and / or a value corresponding to the cross- NUMA read operation delay.

[0027] Optionally, the weak memory environment can be a running environment corresponding to a running device of a non-uniform memory access architecture (NUMA).

[0028] In a possible design, the program detection apparatus in the second aspect can further include an output unit. The output unit can be configured to provide a result to a user. The result can include a modification suggestion.

[0029] Optionally, the result can include a correct result. Alternatively, the result can include an error and / or a modification suggestion.

[0030] Optionally, the modification suggestion can include location information of the code that needs to be modified, for example, a code line number and / or a program file name. The modification suggestion can be used for the program detection apparatus to modify the program or for a user to manually modify the program.

[0031] In a possible design, the obtaining unit can be further configured to modify the program according to the modification suggestion in response to a determination indication of the user.

[0032] In a possible design, the program detection apparatus can be placed in a cloud server.

[0033] It should be noted that the receiving unit and the output unit can be separately arranged or integrated in one module, i.e., a transceiver module. The specific implementation of the receiving unit and the output unit is not limited in the present application.

[0034] Optionally, the program detection apparatus in the second aspect can further include a storage module. The storage module can store a program or an instruction. When the obtaining unit executes the program or the instruction, the program detection apparatus can execute the program detection method in any possible implementation of the first aspect.

[0035] It should be noted that the program detection apparatus in the second aspect can be a computer device, a server or a cloud server, or can be a chip (system) or other components or assemblies that can be arranged in the computer device, the server or the cloud server, and the present application does not limit the program detection apparatus.

[0036] In addition, the technical effects of the program detection apparatus in the second aspect can refer to the technical effects of the program detection method in the first aspect, which will not be repeated here.

[0037] In a third aspect, a program detection apparatus is provided. The program detection apparatus includes a processor and a memory. The memory is configured to store a computer program. The processor is configured to execute the computer program stored in the memory, so that the program detection apparatus executes the program detection method in any possible implementation of the first aspect.

[0038] In a possible design, the program detection apparatus in the third aspect can further include a transceiver. The transceiver can be a transceiver circuit or an input / output port. The transceiver can be configured to enable the program detection apparatus to communicate with other devices.

[0039] In the present application, the program detection apparatus of the third aspect can be a computer device, a server or a cloud server, or a chip or a chip system arranged inside the computer device, the server or the cloud server.

[0040] In addition, the technical effects of the program detection apparatus of the third aspect can refer to the technical effects of the program detection method of any one of the implementation manners of the first aspect, which will not be described herein again.

[0041] In the fourth aspect, a chip system having a weak memory environment is provided, which includes a processor and an input / output port, the processor is coupled with a memory containing instructions, and is configured to control the chip system to implement the processing functions involved in any one of the implementation manners of the first aspect; and the input / output port is configured to implement the transceiving functions involved in any one of the implementation manners of the first aspect.

[0042] In a possible design, the chip system further includes a memory configured to store program instructions and data for implementing the functions involved in the first aspect.

[0043] The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0044] In the fifth aspect, a computer readable storage medium is provided, which includes computer instructions stored therein; when the computer instructions run on a computer, the computer is caused to perform the program detection method according to any one of the possible implementation manners of the first aspect.

[0045] In the sixth aspect, a computer program product containing instructions is provided, which includes a computer program or instructions; when the computer program or instructions run on a computer, the computer is caused to perform the program detection method according to any one of the possible implementation manners of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 Flowchart of the program detection method provided by the embodiments of the present application Figure 1 ;

[0047] Figure 2 Application of the program detection method provided by the embodiments of the present application Figure 1 ;

[0048] Figure 3 Flowchart of the program detection method provided by the embodiments of the present application Figure 2 ;

[0049] Figure 4 Structure of the CPU provided by the embodiments of the present application Figure 1;

[0050] Figure 5 Interface diagram of the program detection device provided for the embodiment of the present application Figure 1 ;

[0051] Figure 6 Example diagram of the program provided for the embodiment of the present application

[0052] Figure 7 Interface diagram of the program detection device provided for the embodiment of the present application Figure 2 .

[0053] Figure 8 Analysis example of the program provided for the embodiment of the present application Figure 1 .

[0054] Figure 9 Analysis example of the program provided for the embodiment of the present application Figure 2 .

[0055] Figure 10 Application diagram of the program detection method provided for the embodiment of the present application Figure 2 .

[0056] Figure 11 Structure diagram of the program detection device provided for the embodiment of the present application Figure 1 .

[0057] Figure 12 Structure diagram of the program detection device provided for the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0058] The technical solutions in the present application will be described below with reference to the drawings.

[0059] The present application will present various aspects, embodiments or features around a system which can include multiple devices, components, modules, etc. It should be understood and appreciated that each system can include additional devices, components, modules, etc., and / or can not include all the devices, components, modules, etc. discussed in connection with the drawings. In addition, combinations of these solutions can also be used.

[0060] In addition, in the embodiments of the present application, the words such as "exemplarily", "for example" and the like are used to represent as an example, illustration or explanation. Any embodiment or design scheme described as "exemplary" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the word "exemplary" is intended to present the concept in a specific manner.

[0061] In the embodiments of this application, "operation instruction" and "operation" can be used interchangeably. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent. "Sentence", "program sentence" and "code" can be used interchangeably. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent.

[0062] In the description of this application, unless otherwise specified, the meaning of "multiple" is two or more. "And / or" in this paper is only a description of the association between objects, which means that there are three relationships, for example, A and / or B, which can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone.

[0063] First, in order to facilitate understanding, the following first introduces the related terms and concepts that may be involved in the embodiments of this application.

[0064] (1) Total store ordering (TSO) consistency model

[0065] The TSO consistency model describes that there is only one global order of memory write operations in the multiple cores of the central processing unit (CPU), and the TSO consistency model belongs to a strong memory model.

[0066] The embodiments of this application provide a program detection method, which can be used to detect the correctness of the program running on a weak memory model platform, such as the correctness of the program running on an Advanced RISC Machine (ARM) platform. The program detection method can be used alone or integrated with third-party software. The program detection device provided by the embodiments of this application can be a computer device, a server or a cloud server, etc., or a chip or other component with program detection function applied in a computer device, a server or a cloud server.

[0067] The embodiments of this application will be described below in conjunction with Figures 1-10 The program detection method provided by the embodiments of this application will be described in detail.

[0068] Figure 1 The flowchart of the program detection method provided by the embodiments of this application Figure 1 The program detection method provided by the embodiments of this application can be used to check software developed by a compiled language, such as C language or C++ language, etc.

[0069] As Figure 1 shown, the program detection method includes the following steps:

[0070] S101, receiving a program provided by a user.

[0071] Figure 2 Application of the program detection method provided by the embodiments of the present application Figure 1 .

[0072] As shown in Figure 2 , the program detection device receives a program provided by a user. Taking C / C++ software as an example, the program can be a C / C++ software source code. The program can include one or more threads.

[0073] Optionally, the program detection method provided by the embodiments of the present application can include: using a compiler to convert the program provided by the user into intermediate code (IR).

[0074] Exemplarily, taking the Clang / LLVM compiler as an example, it is assumed that the program provided by the user is XXX.c, the program is compiled by the Clang / LLVM compiler to generate intermediate code, for example, clang-emit-llvm-c-g XXX.c-o XXX.bc. Optionally, the program detection device Weakmemcheck analyzes the intermediate file XXX.bc of the program.

[0075] In combination with Figure 3 (a) or Figure 3 (b), the program provided by the user is compiled by the compiler to generate intermediate code IR, and the program detection device analyzes the intermediate code, which can realize static analysis of the source code, without running the program provided by the user, so as to be non-invasive to the user software, guarantee the security of the program of the user and be convenient to operate.

[0076] S102, according to the query parameter and the program, obtaining a result of the program running in a weak memory environment.

[0077] Optionally, the weak memory environment is a running environment corresponding to a running device of a non-uniform memory access architecture (NUMA).

[0078] Exemplarily, the weak memory environment can be a running environment of a weak memory model device, or a weak memory model platform, etc.

[0079] Exemplarily, the query parameter is used to indicate a maximum interval of reordering of two operations of the program. Optionally, the query parameter can include a type of the query parameter and / or a value corresponding to the query parameter.

[0080] In some embodiments, the type of the query parameter can comprise an intra-chip write operation delay. Illustratively, the intra-chip write operation delay can be used to indicate a maximum interval of two store instructions within a chip that can be reordered.

[0081] Illustratively, the memory instruction can be used to save data in a register to a memory, and the intra-chip write operation delay can be used to detect whether two or more store instructions within a NUMA node can be reordered. For more details about the intra-chip write operation delay, reference can be made to the detailed description of the Figure 4 below.

[0082] Optionally, the type of the query parameter can further comprise a cross- NUMA write operation delay and / or a cross- NUMA read operation delay. Illustratively, the cross- NUMA write operation delay can be used to indicate a maximum interval of two store instructions across NUMA nodes that can be reordered, and the cross- NUMA read operation delay can be used to indicate a maximum interval of two load instructions across NUMA nodes that can be reordered, where the instructions across NUMA nodes refer to instructions in which a process of one NUMA node accesses memory of another NUMA node.

[0083] Illustratively, the load instruction can be used to read data from a memory into a register, and the cross- NUMA write operation delay can be used to detect whether two or more store instructions between two or more NUMA nodes can be reordered, and the cross- NUMA read operation delay can be used to detect whether two or more load instructions between two or more NUMA nodes can be reordered. For more details about the cross- NUMA write operation delay and the cross- NUMA read operation delay, reference can be made to the detailed description of the Figure 4 below.

[0084] In some embodiments, the value corresponding to the query parameter can comprise a value corresponding to the intra-chip write operation delay.

[0085] Illustratively, assuming that the value corresponding to the intra-chip write operation delay is set to 8, a maximum interval of two store instructions that can be reordered is 8 memory operation instructions. That is, if the interval between two store instructions is less than or equal to 8 memory operation instructions, it is considered that the two store instructions can be reordered; if the interval between the two store instructions is greater than 8 memory operation instructions, it is considered that the two store instructions cannot be reordered. The memory operation instruction can comprise a store instruction and / or a load instruction.

[0086] Optionally, the value corresponding to the query parameter can further comprise a value corresponding to the cross- NUMA write operation delay and / or a value corresponding to the cross- NUMA read operation delay.

[0087] Exemplarily, assuming that the value corresponding to the cross- NUMA write operation delay is set as 8, the maximum interval of the reordering of two storage instructions is 8 memory operation instructions. That is, if the interval between the two storage instructions is less than or equal to 8 memory operation instructions, it is considered that the two storage instructions will be reordered; if the interval between the two storage instructions is greater than 8 memory operation instructions, it is considered that the two storage instructions will not be reordered.

[0088] Similarly, assuming that the value corresponding to the cross- NUMA read operation delay is set as 8, the maximum interval of the reordering of two load instructions is 8 memory operation instructions. That is, if the interval between the two load instructions is less than or equal to 8 memory operation instructions, it is considered that the two load instructions will not be reordered; if the interval between the two load instructions is greater than 8 memory operation instructions, it is considered that the two load instructions will not be reordered.

[0089] Optionally, the type of the query parameter can include an in-chip read operation delay, and the value corresponding to the query parameter can include a value corresponding to the in-chip read operation delay. Exemplarily, the in-chip read operation delay can be used to indicate the maximum interval of the reordering of two load instructions, and the in-chip read operation delay can be used to detect whether the reordering will occur between two or more load instructions in a NUMA node. The specific implementation manner of the in-chip read operation delay is similar to the in-chip write operation delay described above, which will not be described herein again.

[0090] It should be noted that, taking the memory operation instruction 1 and the memory operation instruction 2 included in the program as an example, the reordering can refer to the change of the execution order of the memory operation instruction 1 and the memory operation instruction 2. For example, the order recorded in the code of the program file is that the memory operation instruction 1 is executed before the memory operation instruction 2, and if the program is run in a weak memory environment, due to the characteristics of the weak memory environment, the memory operation instruction 2 is executed first, and then the memory operation instruction 1 is executed.

[0091] In some embodiments, the memory read-write mode query can be performed according to a query parameter. The query parameter is used to describe the memory read-write delay of different cores of the CPU hardware in-chip and out-of-chip, and construct the memory read-write mode query rule.

[0092] Optionally, the query parameter can be determined according to the structure of the CPU.

[0093] Figure 4 The structure of the CPU provided in the embodiments of the present application Figure 1 .

[0094] As Figure 4As shown, the CPU includes two memories, memory 0 and memory 1, which correspond to cores and caches respectively. Memory 0 corresponds to core 0, core 1, cache 0, and cache 1. A store buffer corresponds to the connection between core 0 and cache 0, and a store buffer corresponds to the connection between core 1 and cache 1. Memory 1 corresponds to core 2, core 3, cache 2, and cache 3. A store buffer corresponds to the connection between core 2 and cache 2, and a store buffer corresponds to the connection between core 3 and cache 3. Optionally, a NUMA load buffer and / or a NUMA store buffer correspond to the connection between memory 0 and memory 1. For example, core 0 and core 1 can perform read operations on memory 1 through the NUMA load buffer, and core 0 and core 1 can perform write operations on memory 1 through the NUMA store buffer. Similarly, core 2 and core 3 can perform read operations on memory 0 through the NUMA load buffer, and core 2 and core 3 can perform write operations on memory 0 through the NUMA store buffer.

[0095] In combination Figure 4 The architecture including memory 0, core 0, core 1, cache 0, cache 1, and the corresponding store buffers can be referred to as NUMA node 0. A read operation by core 0 or core 1 within NUMA node 0 on memory (memory 0) or cache (cache 0 and cache 1, and the corresponding store buffers) within NUMA node 0 can be referred to as an on-chip read operation. For example, a read operation by core 0 on memory 0 can be referred to as an on-chip read operation. A write operation by core 0 or core 1 within NUMA node 0 on memory (memory 0) or cache (cache 0 and cache 1, and the corresponding store buffers) within NUMA node 0 can be referred to as an on-chip write operation. For example, a write operation by core 0 on memory 0 can be referred to as an on-chip write operation.

[0096] Similarly, the architecture including memory 1, core 2, core 3, cache 2, and cache 3, corresponding Store Buffer can be referred to as NUMA node 1, and the read operation of core 2 or core 3 in NUMA node 1 to the memory (memory 1) or cache (cache 2, cache 3, and corresponding Store Buffer) in NUMA node 1 can be referred to as an on-chip read operation. For example, the read operation of core 2 to memory 1 can be referred to as an on-chip read operation. The write operation of core 2 or core 3 in NUMA node 1 to the memory (memory 1) or cache (cache 2, cache 3, and corresponding Store Buffer) in NUMA node 1 can be referred to as an on-chip write operation. For example, the write operation of core 2 to memory 1 can be referred to as an on-chip write operation.

[0097] Exemplarily, the memory operation between NUMA node 0 and NUMA node 1 can be referred to as a cross- NUMA memory operation, and the memory operation includes a read operation and / or a write operation. For example, the read operation of core 0 in NUMA node 0 to memory 1 in NUMA node 1 can be referred to as a cross- NUMA read operation, and the write operation of core 0 in NUMA node 0 to memory 1 in NUMA node 1 can be referred to as a cross- NUMA write operation. Similarly, the read operation of core 2 in NUMA node 1 to memory 0 in NUMA node 0 can be referred to as a cross- NUMA read operation, and the write operation of core 2 in NUMA node 1 to memory 0 in NUMA node 0 can be referred to as a cross- NUMA write operation, which is not listed one by one here.

[0098] Exemplarily, in combination with Figure 4 If the CPU includes a Store Buffer, the on-chip write operation delay and / or the value corresponding to the on-chip write operation delay can be determined. If the CPU includes a NUMA Load Buffer, the cross- NUMA write operation delay and / or the value corresponding to the cross- NUMA write operation delay can be determined. If the CPU includes a NUMA Store Buffer, the cross- NUMA read operation delay and / or the value corresponding to the cross- NUMA read operation delay can be determined. Optionally, if the CPU includes a Load Buffer, the on-chip read operation delay and / or the value corresponding to the on-chip read operation delay can be determined. Among them, the Load Buffer can be correspondingly arranged between the core 0 and the cache 0, and similarly, the Load Buffer can be correspondingly arranged between the core 1 and the cache 1, between the core 2 and the cache 2, and between the core 3 and the cache 3 (not shown in FIG. 1). Figure 4 Exemplarily, the memory operation between NUMA node 0 and NUMA node 1 can be referred to as a cross- NUMA memory operation, and the memory operation includes a read operation and / or a write operation. For example, the read operation of core 0 in NUMA node 0 to memory 1 in NUMA node 1 can be referred to as a cross- NUMA read operation, and the write operation of core 0 in NUMA node 0 to memory 1 in NUMA node 1 can be referred to as a cross- NUMA write operation. Similarly, the read operation of core 2 in NUMA node 1 to memory 0 in NUMA node 0 can be referred to as a cross- NUMA read operation, and the write operation of core 2 in NUMA node 1 to memory 0 in NUMA node 0 can be referred to as a cross- NUMA write operation, which is not listed one by one here.

[0099] In some embodiments, the query parameter can be determined by the program detection apparatus.

[0100] For example, the program detection apparatus can determine the type of the query parameter, such as the in-memory write operation delay, or the cross- NUMA write operation delay and / or the cross- NUMA read operation delay.

[0101] For example, the program detection apparatus can determine the value corresponding to the query parameter. For example, the program detection apparatus can determine the value corresponding to the in-memory write operation delay, the value corresponding to the cross- NUMA write operation delay and / or the value corresponding to the cross- NUMA read operation delay according to the test set.

[0102] In some embodiments, the query parameter can be determined by the user.

[0103] In combination with Figure 2 , the program detection apparatus can analyze the program according to the query parameter determined by the user, and obtain the result of the program running in the weak memory environment.

[0104] Optionally, the user can determine the type of the query parameter.

[0105] For example, the user can input the query parameter in the display interface of the program detection apparatus. Figure 5 Interface of the program detection apparatus provided by the embodiments of the present application Figure 1 In combination with Figure 5 (a), the user can input the instruction corresponding to the query parameter in the area of the display interface for inputting the query parameter. For example, the instruction StoreBuffer corresponding to the in-memory write operation delay can be inputted. Optionally, the instruction NUMAStoreSize corresponding to the cross- NUMA write operation delay and / or the instruction NUMALoadSize corresponding to the cross- NUMA read operation delay can also be inputted.

[0106] Alternatively, for example, the display interface of the program detection apparatus can include a selection box of the in-memory write operation delay, and can also include a selection box of the cross- NUMA write operation delay and / or a selection box of the cross- NUMA read operation delay. For example, the user can determine the type of the query parameter by checking the selection box corresponding to the type of the query parameter. In combination with Figure 5 (b), the user can check the selection box corresponding to the in-memory write operation delay to determine the in-memory write operation delay. Similarly, the user can check the selection box corresponding to the cross- NUMA write operation delay to determine the cross- NUMA write operation delay. If the cross- NUMA read operation delay is not used, the selection box corresponding to the cross- NUMA read operation delay can not be operated.

[0107] Optionally, the user can determine the value corresponding to the query parameter.

[0108] In combination with Figure 5 In (a) or Figure 5 In (b), the user can input the corresponding value in the area of input value corresponding to the type of each query parameter. For example, the user can input 8 in the area of input value corresponding to the on-chip write operation delay. Similarly, 8 can be input in the area of input value corresponding to the cross- NUMA write operation delay, and 8 can be input in the area of input value corresponding to the cross- NUMA read operation delay.

[0109] It should be noted that the above is only an example provided by the embodiments of the present application, and the embodiments of the present application do not limit how the query parameter is determined. For example, the type of the query parameter can be determined by the program detection device, and the value corresponding to the query parameter can be determined by the user. Alternatively, the type of the query parameter is determined by the user, and the value of the query parameter is determined by the program detection device. Alternatively, after the program detection device determines the type of the query parameter and / or the value corresponding to the query parameter, the user can modify the type of the query parameter and / or the value corresponding to the query parameter.

[0110] In a possible design, the program detection method provided by the embodiments of the present application can further include: obtaining the value corresponding to the query parameter.

[0111] Optionally, the value corresponding to the query parameter can be pre-set, and / or the value corresponding to the query parameter can be provided by the user through the input value area corresponding to the type of the query parameter in the display interface.

[0112] In a possible design, S102 can include: obtaining the result of the program running in the weak memory environment according to the query parameter, the interval between the first operation in the first thread and the second operation in the first thread of the program, and the interval between the third operation in the second thread and the fourth operation in the second thread of the program.

[0113] Optionally, the first operation and the third operation can be a pair of read-write operations on a same variable, the second operation and the fourth operation can be a pair of read-write operations on the same variable, the first operation and the second operation can be operations on different variables, and the third operation and the fourth operation can be operations on different variables. For example, the variable can be a shared variable. The pair of operations can be: the first operation is a read operation on a first variable, and the third operation is a write operation on the first variable; or, the first operation is a write operation on the first variable, and the third operation is a read operation on the first variable. Similarly, the second operation is a read operation on a second variable, and the fourth operation is a write operation on the second variable; or, the second operation is a write operation on the second variable, and the fourth operation is a read operation on the second variable. The first variable can include a global variable, a shared variable, etc., and the second variable can include a global variable, a shared variable, etc.

[0114] Figure 6 An example diagram of a program provided by an embodiment of the present application.

[0115] As shown in Figure 6 the program includes a first thread thread1 at line 14 and a second thread thread2 at line 21, an interval between a write operation on a variable population in thread1 (line 17) and a write operation on a variable syn_flag in thread1 (line 18) can be calculated, an interval between a read operation on the variable syn_flag in thread2 (line 23) and a read operation on the variable population in thread2 (line 24) can be calculated, and a result of running the program in a weak memory environment can be obtained according to a query parameter and the two intervals.

[0116] In a possible design, the program detection method provided by an embodiment of the present application can further include: detecting, by using a memory read-write mode query rule, a first operation in a first thread of the program, a second operation in the first thread, a third operation in a second thread of the program, and a fourth operation in the second thread, and obtaining a result of running the program in a weak memory environment.

[0117] Exemplarily, for specific implementation manners of the first operation, the second operation, the third operation, and the fourth operation, refer to the specific implementation manners described above, which will not be described herein again.

[0118] Optionally, the memory read-write mode query rule can be determined according to a query parameter, and the memory read-write mode query rule can be used to determine whether the first thread and the second thread overlap in time.

[0119] In combination Figure 6 , the memory read-write mode query rule can be used to detect Figure 6The thread1 and thread2 in the program shown are detected to obtain the result that the program runs in a weak memory environment.

[0120] Exemplarily, the memory read-write mode query rule can include a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule.

[0121] Exemplarily, the read-read, write-write out-of-order query rule can include one or more conditions as follows: the first operation instruction and the second operation instruction are two adjacent operation instructions in the first thread, the first operation instruction is a write operation instruction on the first variable, the second operation instruction is a write operation instruction on the second variable, the third operation instruction and the fourth operation instruction are two adjacent operation instructions in the second thread, the third operation instruction is a read operation instruction on the first variable, and the fourth operation instruction is a read operation instruction on the second variable; the first operation instruction and the third operation instruction are in a race condition, and the second operation instruction and the fourth operation instruction are in a race condition; the interval between the first operation instruction and the second operation instruction is less than the sum of the value corresponding to the in-chip write operation delay and the value corresponding to the cross- NUMA write operation delay; and the interval between the third operation instruction and the fourth operation instruction is less than the value corresponding to the cross- NUMA read operation delay. In this way, the read-read, write-write out-of-order query rule can be used to check the running result of a program including at least two threads, and one thread including read-read operations and the other thread including write-write operations in a weak memory environment.

[0122] Exemplarily, the read-write, write-read out-of-order query rule can include one or more conditions as follows: the fifth operation instruction and the sixth operation instruction are two adjacent operation instructions in the first thread, the fifth operation instruction is a write operation instruction on the third variable, the sixth operation instruction is a read operation instruction on the fourth variable, and the seventh operation instruction and the eighth operation instruction are two adjacent operation instructions in the second thread, the seventh operation instruction is a read operation instruction on the third variable, and the eighth operation instruction is a write operation instruction on the fourth variable; the fifth operation instruction and the seventh operation instruction are in a race condition, and the sixth operation instruction and the eighth operation instruction are in a race condition; the interval between the fifth operation instruction and the sixth operation instruction is less than the sum of the value corresponding to the in-chip write operation delay and the values corresponding to the cross- NUMA write operation delay and the cross- NUMA read operation delay, and the interval between the third operation instruction and the eighth operation instruction is less than the sum of the value corresponding to the in-chip write operation delay and the values corresponding to the cross- NUMA write operation delay and the cross- NUMA read operation delay. In this way, the read-write, write-read out-of-order query rule can be used to check the running result of a program including at least two threads, and one thread including read-write operations and the other thread including write-read operations in a weak memory environment.

[0123] Specifically, a competition relationship can occur when the execution order of two operation instructions affects the execution result. The third variable can include global variables, shared variables, etc., and the fourth variable can also include global variables, shared variables, etc.

[0124] Program statements that satisfy the above memory read / write pattern query rules can be identified as dangerous statements that may result in errors due to instruction reordering in a weak memory environment.

[0125] Thus, if the program meets the memory read / write pattern query rules, the result will be incorrect, which may easily lead to weak memory ordering problems; if the program does not meet the memory read / write pattern query rules, the result will be correct, which may result in correct operation on a weak memory model platform. Users do not need to repeatedly test the program, and the results of the program running in a weak memory environment can be obtained quickly.

[0126] In one possible design, the program detection method provided in this application embodiment may further include: providing results to the user. Optionally, the results may include: correct. Alternatively, the results may include errors and / or modification suggestions.

[0127] For example, "correct" indicates that the program can run correctly in a weak memory environment, while "incorrect" indicates that the program will crash, exit, or produce incorrect calculation results when running in a weak memory environment. Modification suggestions can include the location information of the code that needs to be modified, such as the line number and / or the program file name. These suggestions can be used by a program detection device to modify the program or by the user to manually modify the program to ensure it runs correctly in a weak memory environment. This helps users quickly locate the location in the program that causes errors, quickly complete program modifications, and improve the efficiency of program modification.

[0128] Optionally, if the result is correct, the test result can be displayed to the user through the display interface. If the result is incorrect, the test result and / or modification suggestions can be displayed to the user through the display interface.

[0129] Figure 7 A schematic diagram of the interface of the program testing device provided in the embodiments of this application. Figure 2 .like Figure 7 As shown, if the result is an error, the display interface can show the error result, the corresponding program file name, and the line number of the error statement.

[0130] In one possible design, the program detection method provided in this application embodiment may further include: modifying the program according to modification suggestions in response to a user's confirmation instruction.

[0131] Combination Figure 7The user selects the repair region in the display interface, and the program detection device can modify the program according to the modification suggestion in response to the determination indication of the user. Alternatively, the user selects the non-repair region in the display interface, and the program can be manually modified according to the modification suggestion. In this way, the user can be directly helped to complete the modification of the program, and the modification efficiency of the program is further improved.

[0132] Based on Figure 1 The program detection method and the program detection device can help the user to quickly complete the check of the program running in the weak memory environment, and can improve the detection efficiency of the program, and the professional ability requirement of the user is low.

[0133] In some embodiments, in combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example. Figure 3 Figure 3 In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example.

[0134] Step one, analyze the alias relationship of all variables in the program.

[0135] In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example. Figure 6 Figure 8 In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example. Figure 6 Figure 8 In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example.

[0136] Step two, perform variable dependency analysis on the program.

[0137] Exemplarily, the function relationship and the variable dependency relationship in the program provided by the user are analyzed, and a related thread relationship graph and a function call relationship graph are constructed. The multi-thread related application programming interface (API) used in the program is analyzed, and a thread data structure based on thread call context and function call context is constructed to distinguish the context of different thread operations and analyze the variable dependency relationship. The multi-thread related API can include thread related functions such as pthread_create, pthread_mutex_lock, etc.

[0138] In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example. Figure 6 Figure 8 In combination with (a) in the method or (b) in the device, the program checking method provided by the embodiments of the present application can further include the following steps one to eight. The following is described by taking the program including the first thread and the second thread as an example. Figure 6 ​​​​The shown program performs variable dependence analysis, and the obtained results are as shown in Figure 8 The main function main (including its functions and instructions), the first thread thread1 (including its functions and instructions), and the second thread thread2 (including its functions and instructions) are shown.

[0139] In this way, the program is decomposed, the function call context of the first thread and the function call context of the second thread are sorted out, and the thread analysis method based on the thread call context and the function call context can be implemented.

[0140] Step three, analyze the first variable in the program.

[0141] Exemplarily, one or more first variables in the program are analyzed, and the thread call context and the function call context accessed by each of the one or more first variables are distinguished. The first variable can be a variable included in both the first thread and the second thread, and the first variable can include a shared variable, a global variable, etc. In this way, the shared variable access point identification method based on the thread call context and the function call context can be implemented. Exemplarily, the search of the shared variable can be completed based on an alias analysis algorithm to improve efficiency, and the context coding technology can be used to analyze the shared variable in the program to improve the calculation accuracy.

[0142] In combination with Figure 6 and Figure 8 , the shared variable analysis is performed on the program shown in Figure 6 The variable search results my_city->population: {line 17, 24, 31}, my_city->sync_flag: {line 18, 23, 30} are obtained as shown in Figure 8

[0143] Step four, analyze the lock variable in the program.

[0144] Exemplarily, it is analyzed whether any statement in the program uses a lock variable. One or more mutex lock variables used by the first thread and the second thread are analyzed, and the thread call context and the function call context of each of the one or more mutex lock variables are distinguished. The context coding technology can be used to analyze the lock variable in the program to improve the calculation accuracy.

[0145] In combination with Figure 6 and Figure 8 , the lock variable analysis is performed on the program shown in Figure 6 Since the program shown in Figure 6 does not include a lock variable, the analysis result in Figure 8 does not include the analysis result of the lock variable.

[0146] ​Step 5: Analyze the possibility of the basic program blocks, including the first variable, occurring in parallel.

[0147] For example, a static vector time algorithm can be used to analyze the possibility of parallel occurrence (MHP) of each statement in each basic block (BB) containing the first variable. By constructing vector timestamps for basic blocks that include read or write operations on the first variable, the relative logical time of execution of this basic block within the program or thread can be simulated. This allows for parallel analysis at the basic block level, based on the overall program thread call context and function call context.

[0148] Combination Figure 6 and Figure 8 ,right Figure 6 The procedure shown can be used to perform MHP analysis to obtain results such as... Figure 8 The vector timestamp construction results of the first thread (thread1) and the second thread (thread2) shown indicate that the execution time of the statements in thread1 and thread2 overlaps, and the statements in thread1 and thread2 may be executed concurrently.

[0149] Figure 9 Analysis examples of the programs provided for embodiments of this application Figure 2 . Figure 9 To Figure 6 The analysis results of the program shown (e.g., the file name is weekConsistency.c).

[0150] like Figure 9 As shown, Note 1: ST is an abbreviation for Static Thread. Note 2: We precisely record the call string of each variable. Note 3: In call string types such as A(b)->C(d), A represents the caller, and b represents the call instruction. Note 4: A(b)->C means that A calls C by instruction b.

[0151] Use the above five steps to... Figure 6 Analyzing the program shown (e.g., filename weekConsistency.c), the following information can be obtained: The group includes: a write operation to the global variable `population` in thread1 (line 17 of the source code weekConsistency.c), and a read operation to the global variable `population` in thread2 (line 24 of the source code weekConsistency.c); the group also includes: a write operation to the global variable `syrn_flag` in thread1 (line 18 of the source code weekConsistency.c), and a read operation to the global variable `syrn_flag` in thread2 (line 23 of the source code weekConsistency.c). The time interval between statements on lines 17 and 18 of thread1 overlaps with the time interval between statements on lines 23 and 24 of thread2, indicating that the statements in thread1 and thread2 may execute concurrently.

[0152] It should be noted that steps three to five above describe the internal analysis of a single thread. These steps can be executed on both the first and second threads within the program. This application does not limit the specific implementation method. For example, steps three to five can be executed on the first thread first, and then on the second thread. Alternatively, step three can be executed on the first thread first, and then on the second thread. Similarly, step four can be executed on the first thread first, and then on the second thread.

[0153] It should be noted that the embodiments of this application do not limit the order of steps three to five described above. (In conjunction with...) Figure 3 In (b), steps three, four, and five can be parallel. The execution order of steps three, four, and five does not affect the corresponding execution results of each step.

[0154] Step 6: Query the memory read / write mode of the program.

[0155] Regarding the specific implementation of step six, please refer to the above-mentioned query rules using memory read / write mode to detect the first operation, the second operation, the third operation, and the fourth operation in the first thread of the program to obtain the results of the program running in a weak memory environment. This will not be elaborated here.

[0156] For example, combined Figure 3In the middle (b), according to the results of the above steps three to five, the statements in the program are queried to obtain the first statement, the first statement includes read and write operations on the same variable, and the read and write operations on the variable are not write-protected, and the read and write operations on the variable can be concurrently executed by the first thread and the second thread, and the read and write operations on the variable can constitute a race condition.

[0157] In combination Figure 6 And Figure 8 , the memory read-write mode query is performed on the program shown in Figure 6 Because Figure 6 The dangerous statement is not included in the program shown in Figure 8 Therefore, the results shown in

[0158] Step seven, obtaining the results of the program running in a weak memory environment.

[0159] Exemplarily, the first statement is marked as a dangerous statement, which can also be referred to as dangerous code, and the modification suggestion can be determined according to the dangerous code and the operation type included in the dangerous code. The modification suggestion can include the code line number and / or program file name of the dangerous code, and the operation type can include a write operation or a read operation.

[0160] Step eight, providing the results to the user.

[0161] Optionally, the results can include: correct. Alternatively, the results can include errors and / or modification suggestions. For specific implementation of S706, refer to the related description above, which will not be repeated here.

[0162] Optionally, the font color of the dangerous code can be converted to a color different from the font color of other codes in the program, and displayed to the user through the display interface.

[0163] Figure 10 Application of the program detection method provided by the embodiments of the present application Figure 2 As shown in Figure 10 , assuming that the program A provided by the user is a program running on a strong memory model platform, the program detection device provided by the embodiments of the present application detects the program A by using the program detection method provided by the embodiments of the present application, and obtains the result as error. The user manually or the program detection device automatically modifies the program A, such as inserting a memory shielding instruction to repair the existing problem, and after being compiled by the compiler, the obtained program A' can correctly run on a weak memory model platform, which can improve the efficiency of program detection and modification.

[0164] Based on Figure 3 (a) or Figure 3The program detection method shown in (b) can analyze the read and write operations on global variables and the relative time sequence relationship in the program provided by the user, obtain whether there is a problem when the program runs on a weak memory environment, and also obtain the location of the problematic code, and help the user to automatically or manually repair, thereby improving the detection and repair efficiency of the program.

[0165] The above Figures 1-10 The program detection method provided by the embodiments of the present application is described in detail. The following Figures 11-12 The program detection device provided by the embodiments of the present application is described in detail.

[0166] Figure 11 The structure of the program detection device provided by the embodiments of the present application is shown in Figure 1 The program detection device can be applied to the function of the program detection device in the program detection method shown in Figure 11 For the convenience of description, Figure 11 only the main components of the program detection device are shown.

[0167] As shown in Figure 11 , the program detection device 1100 includes a receiving unit 1101 and an obtaining unit 1102. The receiving unit 1101 is configured to receive a program provided by a user. The obtaining unit 1102 is configured to obtain a result of the program running on a weak memory environment according to a query parameter and the program. The query parameter is used to indicate a maximum interval of reordering of two operations of the program.

[0168] In a possible design, the obtaining unit 1102 is further configured to obtain the result of the program running on the weak memory environment according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread. Optionally, the first operation and the third operation are a pair of read-write operations on a same variable, the second operation and the fourth operation are a pair of read-write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on different variables.

[0169] In a possible design, the obtaining unit 1102 is further configured to detect the first operation in the first thread of the program, the second operation in the first thread, the third operation in the second thread of the program, and the fourth operation in the second thread by using a memory read-write mode query rule, and obtain the result of the program running on the weak memory environment.

[0170] Optionally, the memory read-write mode query rule can be determined according to the query parameter, and the memory read-write mode query rule can be used to determine whether the first thread and the second thread overlap in time.

[0171] In a possible design, the memory read-write mode query rule can include a read-read, write-write out-of-order query rule, and / or a read-write, write-read out-of-order query rule.

[0172] In a possible design, the query parameter can be determined by a user, and the query parameter can include an on-chip write operation delay.

[0173] Optionally, the query parameter can further include a cross- NUMA write operation delay and / or a cross- NUMA read operation delay. In this way, the memory read-write mode query can be performed according to the query parameter input by the user.

[0174] In a possible design, the obtaining unit 1102 is further configured to obtain a value corresponding to the query parameter. The value corresponding to the query parameter can include a value corresponding to the on-chip write operation delay.

[0175] Optionally, the value corresponding to the query parameter can further include a value corresponding to the cross- NUMA write operation delay and / or a value corresponding to the cross- NUMA read operation delay.

[0176] Optionally, the weak memory environment can be a running environment of a running device of a non-uniform memory access architecture (NUMA).

[0177] In a possible design, the program detection apparatus 1100 can further include an output unit 1103. The output unit 1103 is configured to provide a result to a user. The result can include a modification suggestion.

[0178] Optionally, the result can include a correct. Alternatively, the result can include an error and / or a modification suggestion.

[0179] Optionally, the modification suggestion can include location information of the code that needs to be modified, for example, a code line number and / or a program file name, and the modification suggestion can be used for the program detection apparatus to modify the program or for the user to manually modify the program.

[0180] In a possible design, the obtaining unit 1102 is further configured to modify the program according to the modification suggestion in response to a determination indication of the user.

[0181] In a possible design, the program detection apparatus 1100 can be placed in a cloud server.

[0182] It should be noted that the receiving unit 1101 and the output unit 1103 can be separately arranged or integrated in one module, i.e., a transceiver module (not shown in the figure). The specific implementation of the receiving unit 1101 and the output unit 1103 is not limited in the present application. Figure 11

[0183] ​Optionally, the program detection device 1100 may further include a storage module ( Figure 1 (Not shown in the image), this storage module stores programs or instructions. When the acquisition unit 1102 executes the program or instructions, the program detection device 1100 can execute. Figure 11 The program detection device in the program detection method shown has the following function.

[0184] It should be noted that the program detection device 1100 may be a computer device, server or cloud server, or a chip (system) or other component or part that can be set in a computer device, server or cloud server. This application does not limit this.

[0185] also, Figure 1 The technical effects of the program testing device 1100 shown can be referenced. Figure 12 The technical effects of the detection method shown are not elaborated here.

[0186] Figure 2 This is a schematic diagram of the structure of the program testing device provided in the embodiments of this application. Figure 12 The detection device can be a computer device, server, or cloud server, or it can be a chip (system) or other component or part that can be installed in a computer device, server, or cloud server. This application does not limit this.

[0187] like Figure 12 As shown, the program detection device 1200 may include a processor 1201. Optionally, the program detection device 1200 may also include a memory 1202 and a transceiver 1203. The processor 1201 is coupled to the memory 1202 and the transceiver 1203, for example, they can be connected via a communication bus.

[0188] The following is combined with Figure 12 A detailed description of each component of the program testing device 1200 is provided below:

[0189] Processor 1201 is the control center of program detection device 1200. It can be a single processor or a collective term for multiple processing elements. For example, processor 1201 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0190] The processor 1201 can execute various functions of the program detection apparatus 1200 by running or executing software programs stored in the memory 1202 and calling data stored in the memory 1202.

[0191] In a specific implementation, as an example, the processor 1201 can include one or more CPUs, such as the CPU0 and the CPU1 shown in FIG. 1. Figure 12

[0192] In a specific implementation, as an example, the program detection apparatus 1200 can also include multiple processors, such as the processor 1201 and the processor 1204 shown in FIG. 1. Each of the processors can be a single-CPU or a multi-CPU. The processor herein can refer to one or more devices, circuits, and / or processing cores for processing data (for example, computer program instructions). Figure 12

[0193] The memory 1202 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magneto-optical disk, a magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory 1202 can be integrated with the processor 1201 or exist independently and be coupled to the processor 1201 through an input / output port (not shown in FIG. 1) of the program detection apparatus 1200, and embodiments of the present application do not make a specific limitation hereon. Figure 12

[0194] The memory 1202 is configured to store software programs for executing the solutions of the present application, and the processor 1201 is configured to control the execution. The above specific implementation manners can refer to the above method embodiments, and will not be described here again.

[0195] ​​​Transceiver 1203 is used for communication with other devices. Furthermore, transceiver 1203 may include a receiver and a transmitter. Figure 12 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function. The transceiver 1203 can be integrated with the processor 1201 or exist independently, and is connected via the input / output port of the program detection device 1200 (…). Figure 12 (Not shown in the image) is coupled to the processor 1201, and this embodiment does not specifically limit this.

[0196] It should be noted that, ​ The structure of the program testing device 1200 shown does not constitute a limitation on the program testing device. The actual program testing device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0197] This application provides a chip system. The chip system includes a processor and input / output ports. The processor is used to implement the processing functions involved in the above-described method embodiments, and the input / output ports are used to implement the transmit / receive functions involved in the above-described method embodiments.

[0198] In one possible design, the chip system also includes a memory for storing program instructions and data that implement the functions involved in the above method embodiments.

[0199] This chip system can consist of chips or include chips and other discrete components.

[0200] This application provides a computer-readable storage medium, comprising: computer instructions stored in the computer-readable storage medium; when the computer instructions are executed on a computer, the computer causes the computer to perform the program detection method described in the above method embodiments.

[0201] This application provides a computer program product containing instructions, including a computer program or instructions, which, when run on a computer, cause the computer to execute the program detection method described in the above method embodiments.

[0202] It should be appreciated that a processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can be any conventional processor.

[0203] It should also be understood that the memory in the embodiments of the present application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0204] The above-described embodiments can be implemented in part or in whole through software, hardware (e.g., circuitry), firmware, or any combination thereof. When implemented in software, the above-described embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When loaded and executed by a computer, the computer instructions or computer programs can produce the processes or functions described above in accordance with the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, such as from a website site, a computer, a server, or a data center to another website site, a computer, a server, or a data center through a wired (e.g., infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium or a collection of medium accessible by a computer or a data storage device such as a server, a data center, etc. containing one or more available medium. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state disk.

[0205] It should be understood that the term "and / or" in this document is merely used to describe an associated relationship between associated objects, and can represent three relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone, where A and B can be singular or plural. In addition, the character " / " in this document generally represents an "or" relationship between the front and rear associated objects, but can also represent an "and / or" relationship. The specific meaning can be understood according to the context before and after.

[0206] In this application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions means any combination of the items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0207] It should be understood that in various embodiments of the present application, the size of the sequence number of the above-described processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0208] Those skilled in the art can clearly understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0209] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0210] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0211] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0212] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0213] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0214] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A program detection method characterized by comprising: The method comprises: receiving a program provided by a user; obtaining a result of running the program in a weak memory environment according to a query parameter and the program, wherein the query parameter comprises a type of the query parameter and / or a value corresponding to the query parameter, and the type of the query parameter and / or the value corresponding to the query parameter are used to indicate a maximum interval of reordering of two instructions in the program, and the program is incorrectly run in the weak memory environment when an interval of the two instructions is less than or equal to the maximum interval, and the program is correctly run in the weak memory environment when the interval of the two instructions is greater than the maximum interval.

2. The program detection method according to claim 1, wherein The obtaining of the result of running the program in the weak memory environment according to the query parameter and the program comprises: obtaining the result of running the program in the weak memory environment according to the query parameter, an interval between a first operation in a first thread of the program and a second operation in the first thread, and an interval between a third operation in a second thread of the program and a fourth operation in the second thread, wherein the first operation and the third operation are a pair of read-write operations on a same variable, the second operation and the fourth operation are a pair of read-write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on the different variables.

3. The program detection method according to claim 2, wherein The method further comprises: detecting the first operation in the first thread, the second operation in the first thread, the third operation in the second thread, and the fourth operation in the second thread of the program according to a memory read-write mode query rule to obtain the result of running the program in the weak memory environment.

4. The program detection method according to claim 3, wherein The memory read-write mode query rule is determined according to the query parameter, and the memory read-write mode query rule is used to determine whether the first thread and the second thread overlap in time.

5. The process monitoring method according to any one of claims 1 to 4, characterized in that, The query parameter is determined by the user, and the query parameter comprises an on-chip write operation delay.

6. The program detection method according to claim 5, wherein The weak memory environment is a running environment corresponding to a running device of a non-uniform memory access architecture (NUMA).

7. The program detection method according to claim 6, wherein The method further comprises: providing the result to the user, wherein the result comprises a modification suggestion.

8. The program detection method according to claim 7, wherein The method further comprises: modifying the program according to the modification suggestion in response to a determination indication of the user.

9. A program detection device characterized by comprising: The method comprises: receiving a program provided by a user; obtaining a result of running the program in a weak memory environment according to a query parameter and the program, wherein the query parameter comprises a type of the query parameter and / or a value corresponding to the query parameter, and the type of the query parameter and / or the value corresponding to the query parameter are used to indicate a maximum interval of reordering of two instructions in the program, and the program is incorrectly run in the weak memory environment when an interval of the two instructions is less than or equal to the maximum interval, and the program is correctly run in the weak memory environment when the interval of the two instructions is greater than the maximum interval.

10. The program detection apparatus according to claim 9, wherein The acquisition unit is further configured to acquire the result of the program running on the weak memory environment according to the query parameter, intervals between a first operation in a first thread of the program and a second operation in the first thread, and intervals between a third operation in a second thread of the program and a fourth operation in the second thread; the first operation and the third operation are a pair of read-write operations on a same variable, the second operation and the fourth operation are a pair of read-write operations on the same variable, the first operation and the second operation are operations on different variables, and the third operation and the fourth operation are operations on the different variables.

11. The program detection apparatus according to claim 9, wherein The acquisition unit is further configured to detect, by using a memory read-write mode query rule, a first operation in a first thread of the program, a second operation in the first thread, a third operation in a second thread of the program, and a fourth operation in the second thread, and acquire the result of the program running on the weak memory environment.

12. The program detection apparatus according to Claim 11, characterized by The memory read-write mode query rule is determined according to the query parameter, and the memory read-write mode query rule is used to determine whether the first thread and the second thread overlap in time.

13. Procedure detection apparatus according to any one of claims 9-12, characterized in that, The query parameter is determined by the user, and the query parameter includes an on-chip write operation delay.

14. The program detection apparatus according to Claim 13, characterized by The weak memory environment is a running environment corresponding to a non-uniform memory access architecture (NUMA) running device.

15. The program detection apparatus according to claim 14, characterized by Further comprising: An output unit, wherein The output unit is configured to provide the result to the user, and the result includes a modification suggestion.

16. The program detection apparatus according to claim 15, wherein The acquisition unit is further configured to modify the program according to the modification suggestion in response to a determination indication of the user.

17. The program detection apparatus according to claim 9, wherein The program detection apparatus is placed in a cloud server.

18. A program detection device characterized by comprising: The apparatus includes a processor coupled with a memory; The memory is configured to store a computer program; The processor is configured to execute the computer program stored in the memory, so that the apparatus performs the program detection method according to any one of claims 1-8.

19. A computer program product, characterised in that, The computer program product includes computer program code, which, when executed on a computer, causes the computer to perform the program detection method according to any one of claims 1-8.

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