Network-on-chip design method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a network-on-chip design method and device, electronic equipment and a readable storage medium, and the method comprises the steps: constructing a target behavior model based on a target design demand; generating a target code based on the target behavior model and a preset code library; under the condition that the target code does not meet the preset constraint target, the target behavior model is optimized, and the target code is updated based on the optimized target behavior model until the target code meets the preset constraint target; and generating an on-chip network code file based on the target code meeting the preset constraint target. Through the mode of performing constraint verification on the target code in the design process and optimizing and adjusting the target behavior model, the code optimization and adjustment range in the design process is narrowed, the code modification cost is reduced, and on the premise of ensuring that the target design requirement of the network-on-chip and the preset constraint target are verified to meet the expectation, the optimization and adjustment efficiency of the network-on-chip is improved. And the code generation efficiency of the network-on-chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a design method, device, electronic device and readable storage medium for a network on chip. Background Art

[0002] With the continuous development of integrated circuit technology, the number of processor cores, memory and other IP cores integrated on a single chip continues to increase, and the traditional bus communication method can no longer meet the growing communication needs. Network-on-chip (NOC) has become a key solution to this problem. As an emerging on-chip communication architecture, NOC has become a key technology for multi-processor architecture by providing a high-bandwidth, low-latency, and scalable communication mechanism. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for the collaborative work of processors.

[0003] In the related art, the code files of the network on chip are often written manually. Moreover, after the code files of the network on chip are generated, in order to ensure the operational stability of the network on chip, the code files need to be verified and evaluated. If the verification and evaluation results do not meet expectations, the code files of the manual network on chip need to be rewritten manually. The code modification cost is high and the labor cost is high, which leads to low efficiency of the network on chip code generation. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present invention provides a design method, device, electronic device and readable storage medium of an on-chip network.

[0005] In a first aspect, the present invention provides a method for designing a network on chip, the method comprising: Build target behavior model based on target design requirements; Generate target code based on the target behavior model and the preset code library; In the case where the target code does not meet the preset constraint target, optimizing the target behavior model and updating the target code based on the optimized target behavior model until the target code meets the preset constraint target; Based on the target code that meets the preset constraint target, an on-chip network code file is generated.

[0006] Optionally, the target design requirements include architecture design requirements, functional design requirements, and performance parameter design requirements for the network on chip; and constructing the target behavior model based on the target design requirements includes: Based on the architecture design requirements, the functional design requirements and the performance parameter design requirements, determine the system framework information of the network on chip, the module configuration information corresponding to at least two functional modules required by the network on chip, and the parameter configuration information; The target behavior model is constructed using a target language based on the system framework information, the module configuration information corresponding to the at least two functional modules, and the parameter configuration information.

[0007] Optionally, the method further comprises: Perform constraint checking based on the target code and the preset constraint target to obtain a checking result; When the target code does not meet the preset constraint target, optimizing the target behavior model and updating the target code based on the optimized target behavior model until the target code meets the preset constraint target, including: In the case where the inspection result is a first inspection result, optimizing the target behavior model based on the first inspection result; the first inspection result is used to indicate that the target code does not meet the preset constraint target; Generate a first target code based on the optimized target behavior model and the preset code library; In the case where the first target code does not satisfy the preset constraint target, re-execute the step of optimizing the target behavior model based on the first inspection result; When the inspection result is the second inspection result, the first target code is determined as the target code; the second inspection result is used to indicate that the first target code meets the preset constraint target.

[0008] Optionally, after constructing the target behavior model based on the target design requirement, the method further includes: Performing simulation analysis on the target behavior model to determine whether the target behavior model meets the target design requirements; The generating target code based on the target behavior model and the preset code library includes: When the target behavior model meets the target design requirement, a target code is generated based on the target behavior model and a preset code library.

[0009] Optionally, the preset constraint targets include physical layout constraints, delay constraints, power consumption constraints, and bandwidth constraints of physical links for the on-chip network.

[0010] Optionally, the method further comprises: Obtain user product requirements input by users; The user product requirements are regularized and divided to obtain the target design requirements and the preset constraint targets; the target design requirements include the requirement content of the functional dimension in the user product requirements, and the preset constraint targets include the requirement content of the hardware constraint dimension in the user product requirements.

[0011] Optionally, generating the target code based on the target behavior model and a preset code library includes: Obtaining the preset code library; Based on the preset code library, the target behavior model is converted into target code using a code generation tool.

[0012] In a second aspect, the present invention provides a design device for a network on chip, the device comprising: The first building module is used to build a target behavior model based on target design requirements; A first generating module, used for generating target code based on the target behavior model and a preset code library; A first optimization module, configured to optimize the target behavior model and update the target code based on the optimized target behavior model when the target code does not meet the preset constraint target, until the target code meets the preset constraint target; The second generating module is used to generate an on-chip network code file based on the target code that meets the preset constraint target.

[0013] Optionally, the target design requirements include architecture design requirements, functional design requirements and performance parameter design requirements for the on-chip network; the first building module includes: A first determination module is used to determine system framework information of the network on chip, module configuration information corresponding to at least two functional modules required by the network on chip, and parameter configuration information based on the architecture design requirements, the functional design requirements, and the performance parameter design requirements; The first construction submodule is used to construct the target behavior model using a target language based on the system framework information, the module configuration information corresponding to the at least two functional modules, and the parameter configuration information.

[0014] Optionally, the device further comprises: A first checking module, used for performing a constraint check based on the target code and the preset constraint target to obtain a check result; The first optimization module comprises: A first optimization submodule is used to optimize the target behavior model based on the first inspection result when the inspection result is a first inspection result; the first inspection result is used to indicate that the target code does not meet the preset constraint target; A first generating submodule, used for generating a first target code based on the optimized target behavior model and the preset code library; A first execution module, configured to re-execute the step of optimizing the target behavior model based on the first inspection result when the first target code does not meet the preset constraint target; The second determination module is used to determine the first target code as the target code when the inspection result is a second inspection result; the second inspection result is used to indicate that the first target code meets the preset constraint target.

[0015] Optionally, the device further comprises: A first analysis module, used to perform simulation analysis on the target behavior model to determine whether the target behavior model meets the target design requirement; The first generating module comprises: The second generating submodule is used to generate target code based on the target behavior model and a preset code library when the target behavior model meets the target design requirement.

[0016] Optionally, the preset constraint targets include physical layout constraints, delay constraints, power consumption constraints, and bandwidth constraints of physical links for the on-chip network.

[0017] Optionally, the device further comprises: A first acquisition module is used to acquire user product requirements input by a user; The first processing module is used to regularize and divide the user product requirements to obtain the target design requirements and the preset constraint targets; the target design requirements include the requirement content of the functional dimension in the user product requirements, and the preset constraint targets include the requirement content of the hardware constraint dimension in the user product requirements.

[0018] Optionally, the first generating module includes: A second acquisition module, used to acquire the preset code library; The first conversion module is used to convert the target behavior model into target code based on the preset code library by using a code generation tool.

[0019] In a third aspect, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the on-chip network design method described in any one of the first aspects when executing the program.

[0020] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps in the on-chip network design method in any one of the embodiments of the first aspect above.

[0021] The embodiment of the present invention provides a design method for a network on chip, which constructs a target behavior model based on a target design requirement; generates a target code based on the target behavior model and a preset code library; when the target code does not meet the preset constraint target, optimizes the target behavior model and updates the target code based on the optimized target behavior model until the target code meets the preset constraint target; generates a network on chip code file based on the target code that meets the preset constraint target. In the embodiment of the present invention, the design process of the network on chip is split, and the target behavior model is first constructed based on the target design requirement and then the target code is generated, so that when the target code does not meet the preset constraint condition, the target behavior model can be optimized so that the target code meets the preset constraint target, and then the network on chip code file can be generated based on the target code. In this way, before generating the network on chip code file, the embodiment of the present invention ensures that the target code is generated based on the target design requirement and meets the preset constraint target by performing constraint verification on the target code in the design process and optimizing and adjusting the target behavior model to obtain the target code that meets the preset constraint target. There is no need to perform verification and evaluation at one time after generating the network on chip code file, and the process of verifying and evaluating whether the code design meets the design expectation is set in the design process, which reduces the scope of code optimization and adjustment in the design process. At the same time, compared with manually rewriting the on-chip network code file, the process of optimizing the target behavior model is less complex, thereby reducing the cost of code modification. On the premise of ensuring that the target code is generated based on the target design requirements and the preset constraint targets are verified to meet expectations, the code generation efficiency of the on-chip network is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 is a flowchart of a method for designing a network on chip provided by an embodiment of the present invention; Figure 2 It is a flowchart of specific steps of a design method of a network on chip provided by an embodiment of the present invention; Figure 3 is a structural diagram of a design device for a network on chip provided by an embodiment of the present invention; Figure 4 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Figure 1 is a flowchart of a method for designing a network on chip provided by an embodiment of the present invention. Figure 1 As shown, the method may include: Step 101: Build a target behavior model based on target design requirements.

[0026] In the embodiment of the present invention, the target design requirements refer to the specific functions and performance indicators that need to be met when designing the on-chip network. The target design requirements can specifically be product requirements for the on-chip network. The product requirements can include different requirements such as functional requirements, interface requirements, and performance requirements. The product requirement document of the on-chip network elaborates on the various requirements of the product to ensure that the development team can accurately understand and achieve the product goals.

[0027] Based on the target design requirements, behavioral modeling is performed to build a target behavior model. Behavioral modeling is a systematic process that involves understanding the functional requirements of the system in the target design requirements, defining the interactions between modules, and using high-level programming languages ​​to describe these behaviors. Among them, the high-level programming language can be C language, C++ language, etc. The target behavior model focuses on a more flexible and abstract description of the hardware logic, and the focus of the description is on the functional implementation of the hardware logic. The target behavior model provides an in-depth understanding of the system performance and optimization suggestions by simulating various communication protocols, process control mechanisms, and pipeline architectures of routers in the on-chip network system. Among them, the target design requirements may include architectural design requirements, functional design requirements, and performance parameter design requirements for the on-chip network. The architectural design requirements may include architectural requirements such as the number of nodes, topology, and network specifications. The functional design requirements may include communication, routing, and traffic design requirements. The performance parameter design requirements may include performance requirements such as bandwidth requirement information, clock requirement information, and energy consumption requirement information.

[0028] Write a target behavior model that meets the target design requirements, including the correct data types and control structures, to ensure that the behavior and performance of the target behavior model meet the target design requirements.

[0029] Exemplarily, the steps of building a target behavior model based on the target design requirements can be divided into determining the system framework, module division and encapsulation, and configuring and implementing performance parameters, such as clock parameter configuration, communication protocol and process control parameter configuration, etc. Specifically, the basic system framework of the on-chip network system can be determined first, including the number of nodes, network specifications, topology, etc. These framework information will serve as the basis for building the target behavior model. According to the functional design requirements in the target design requirements, the on-chip network system is divided into multiple modules, such as communication module, control module, router module, etc. And each module is encapsulated using C++ classes to achieve decoupling between modules and code reuse. Based on the performance parameter design requirements in the target design requirements, configure the clock parameter information, including clock frequency, clock cycle, etc. These parameters will directly affect the performance of the NoC system. At the same time, according to the communication protocol and process control mechanism of the NoC system, the corresponding algorithms and logic are implemented in the target behavior model.

[0030] Optionally, step 101 may include the following steps: Step 201: Based on the architecture design requirements, the functional design requirements and the performance parameter design requirements, determine the system framework information of the network on chip, the module configuration information corresponding to at least two functional modules required by the network on chip, and the parameter configuration information.

[0031] In an embodiment of the present invention, based on the architecture design requirements, functional design requirements and performance parameter design requirements, the system framework information of the network on chip, at least two functional modules required by the network on chip, module configuration information corresponding to at least two functional modules, and parameter configuration information are determined. Among them, the system framework information may include the topological structure information of the network on chip. Based on the topological structure information, the physical layout and connection between nodes and channels in the network on chip, such as Mesh structure, ring structure, etc., can be determined. The system framework information may also include interface information of the network on chip, and the interface information is used to define the interactive interface between the network on chip system and the external environment, including the source of the input signal and the destination of the output signal. Exemplarily, the architecture design requirements of the system can be obtained, including the number of processor cores, memory structure, and I / O interface information, and the topological structure information, interface information, etc. that can support the architecture design requirements are determined as the system framework information.

[0032] The at least two functional modules required by the on-chip network may include functional units involved in achieving the target design requirements, such as a communication module, a control module, a routing module, etc. The module configuration information corresponding to the at least two functional modules may include the module name or module identification of the functional module, interface information (including data format, signal timing, input interface input, output interface output and bidirectional interface in / output, etc.), configuration parameters (including interface protocol, signal mapping relationship, bit width requirements, etc.), module start information (including the port list corresponding to the functional module and the module name of the functional module, etc.), and interaction information between modules (including data transmission, control signals and synchronization mechanisms, etc.). Exemplarily, the functional design requirements may be obtained, including various functions required to be implemented by the on-chip network and performance requirements related to the functions, such as data transmission mode requirements, buffer size requirements corresponding to the routing function, etc., at least two functional modules are determined according to the various functions required to be implemented by the on-chip network, and, according to the performance requirements related to the functions, the configuration information of at least two functional modules is determined.

[0033] The parameter configuration information may include network specification information, clock configuration information, and energy consumption configuration information. The network specification information may include parameters such as network bandwidth, data packet size, and transmission speed. According to the performance parameter design requirements, such as data transmission volume requirements, determine the bandwidth, data packet size, and transmission speed that can meet the data transmission volume requirements to meet the communication requirements between multiple functional modules. The network bandwidth may include peak bandwidth and average bandwidth. According to the clock design requirements in the performance parameter design requirements, such as time delay requirements, communication speed requirements, etc., determine the clock configuration information. The clock configuration information may include clock frequency, clock cycle, etc. The clock configuration information is used to define the clock frequency and clock cycle of the system. The clock configuration information can affect the communication speed and processing capacity of the system. At the same time, the clock configuration information can also define the synchronization and timing relationship between each functional module in the on-chip network system, which is crucial to ensure the stability and reliability of the system. According to the requirements for power consumption in the performance parameter design requirements, such as the maximum power consumption limit requirements under normal working conditions, determine the energy consumption configuration information. It can be understood that in the process of determining the system framework information, the module configuration information corresponding to at least two functional modules, and the parameter configuration information, it is necessary to comprehensively consider the architecture design requirements, functional design requirements, and performance parameter design requirements, and then determine reasonable system framework information, the module configuration information corresponding to at least two functional modules, and the parameter configuration information.

[0034] Step 202: Using a target language, construct the target behavior model based on the system framework information, the module configuration information corresponding to the at least two functional modules, and the parameter configuration information.

[0035] In an embodiment of the present invention, after determining the system framework information, the module configuration information corresponding to at least two functional modules, and the parameter configuration information, a high-level programming language is selected as the target language (such as C language, C++ language, etc.) to perform behavioral modeling, and implement the behavioral logic corresponding to different functional modules, including data processing, control decision-making, state transition, synchronization mechanism, etc., to obtain a target behavior model. Exemplarily, the overall architecture model of the on-chip network system can be established based on the system framework information using modeling tools (such as SystemC, Matlab / Simulink, etc.). For each functional module, a behavioral-level model corresponding to the functional module is constructed according to the module configuration information. The behavioral-level model corresponding to the constructed functional module is integrated into the system framework model to obtain a target behavior model. According to the parameter configuration information, the parameters of the target behavior model are configured to complete the construction of the target behavior model.

[0036] In an embodiment of the present invention, based on the architecture design requirements, functional design requirements and performance parameter design requirements included in the target design requirements, behavioral level modeling is performed using a target language to construct a target behavior model that meets the on-chip network architecture, function and performance parameter requirements.

[0037] Step 102: Generate target code based on the target behavior model and a preset code library.

[0038] In an embodiment of the present invention, a register transfer level (RTL) code library is pre-constructed as a preset code library. The preset code library can be used as an RTL expression of a high-level language function. Based on the target behavior model and the preset code library, the target behavior model described in the target language is converted into code to generate a target code. The target code can be a hardware description language (HDL) text of a circuit module with independent functions designed by the HDL, such as a register transfer level (RTL) code.

[0039] After the target code is generated, the target code is statically checked, synthesized, simulated, etc. Specifically, static checking tools are used to check the syntax and semantics of the target code to ensure that the code complies with the language specification and identify potential errors or bad practices. The target code is converted into a gate-level netlist, which is a circuit description composed of logic gates and triggers. Use simulation tools to perform functional verification on the target code or the synthesized gate-level netlist to ensure that the design works as expected. Simulation can include unit testing, integration testing, and system-level testing.

[0040] Optionally, step 102 may include the following steps: Step 301: Obtain the preset code library.

[0041] In an embodiment of the present invention, a preset code library is constructed according to design requirements, such as a general library, a dedicated library, or a custom library. The preset code library may include multiple module codes and component codes, such as basic functional unit codes. The component codes and module codes in the preset code library are pre-verified by simulation to ensure that their functions and performance meet the design requirements.

[0042] Step 302: Based on the preset code library, use a code generation tool to convert the target behavior model into a target code.

[0043] In an embodiment of the present invention, based on a preset code library, a code generation tool is used to automatically map the target behavior model to RTL code, i.e., target code. The code generation tool may be a tool or platform such as MATLAB / Simulink or a high-level synthesis tool. During the code conversion process, the code may be optimized and adjusted as necessary according to the design requirements. During the generation process of the target code, the target behavior model is used to provide input and guidance for generating the target code. The target behavior model describes the functional behavior of the on-chip network system, including the relationship between input and output, state transition, data path, etc. The preset code library and the target behavior model are imported into the code generation tool so that the code generation tool can use the modules and components in the preset code library and the target behavior model for code conversion when generating the target code. The code generation tool is started to start the process of generating the target code from the target behavior model: the code generation tool will traverse and analyze the code of the target behavior model, extract all the algorithm and data flow information, including identifying the input, output, state variables, operation operations and the relationship between them in the target behavior model, and map it to the RTL-level hardware structure in the preset code library to obtain the target code. The mapping process can specifically include mapping the algorithm to the operation on the register or data path, and mapping the data flow to the data transmission path between registers. In this process, the code generation tool will also optimize and adjust the code conversion process according to the configuration parameters and the modules and components in the preset code library.

[0044] In an embodiment of the present invention, a target behavior model is converted into a target code by using a preset code library and a code generation tool, thereby realizing code conversion of the target behavior model generated based on the target language, which can improve the flexibility, performance and resource utilization of the on-chip network design and shorten the development cycle.

[0045] Step 103: When the target code does not meet the preset constraint target, the target behavior model is optimized and the target code is updated based on the optimized target behavior model until the target code meets the preset constraint target.

[0046] In an embodiment of the present invention, after the target code is generated, the target code is subjected to constraint judgment, and when the target code does not meet the preset constraint target, the target behavior model is optimized. Among them, the preset constraint target focuses more on the restrictions at the physical level and is a rule that must be followed during the design process. The preset constraint target may include physical layout constraints, delay constraints, power consumption constraints, and bandwidth constraints of physical links for the on-chip network. For example, the preset constraint target may include specific constraint targets such as the delay latency of a single node being a clock cycle, the number of wiring layers not exceeding b, the chip area not exceeding c, and the power consumption being less than d. The preset constraint target may be determined according to the actual design requirements of the on-chip network. Since the focus is on the realization of system functions in the process of building the target behavior model, after converting the target behavior model into the target code, it is necessary to verify whether its functions and performance on the hardware meet the preset constraint targets. User requirements and physical constraints will affect each other during the design process. For example, increasing the number of nodes may increase the chip area and power consumption, while optimizing the network topology and routing algorithm can alleviate these effects to a certain extent. Therefore, when the target code does not meet the preset constraint target, it means that the target code does not meet the hardware constraint target, and therefore, the target behavior model can be optimized and adjusted.

[0047] Based on the optimized and adjusted target behavior model and the preset code library, the target code is regenerated to complete the update of the target code, and a constraint judgment is performed on the updated target code, that is, whether the target code meets the preset constraint target. If the target code does not meet the preset constraint target, the target behavior model is optimized and adjusted again until the target code meets the preset constraint target.

[0048] Step 104: Generate a network-on-chip code file based on the target code that meets the preset constraint target.

[0049] In an embodiment of the present invention, when the target code meets the preset constraint target, the target code is characterized to meet the target design requirements and the preset constraint target at the same time, that is, the target code meets both the functional design requirements and the hardware design requirements. Therefore, after the target code is subjected to static inspection, synthesis, simulation and other processing, an on-chip network code file can be generated based on the target code. The on-chip network code file is a code file for building an on-chip network that meets the design expectations. Exemplarily, based on the target code, the generation of the on-chip network code file can be implemented by EDA (Electronic Design Automation) tools such as Vivado, etc. Specifically, the target code can be imported into the EDA tool, and the on-chip network code file can be generated using the EDA tool. The on-chip network code file may include a configuration file, a bitstream file, etc., which are used to configure a hardware platform such as an FPGA or ASIC to build and generate an on-chip network.

[0050] In summary, the embodiment of the present invention provides a design method for an on-chip network, which constructs a target behavior model based on the target design requirements; generates a target code based on the target behavior model and a preset code library; when the target code does not meet the preset constraint target, optimize the target behavior model and update the target code based on the optimized target behavior model until the target code meets the preset constraint target; and generate an on-chip network code file based on the target code that meets the preset constraint target. In the embodiment of the present invention, the design process of the on-chip network is split, and the target behavior model is first constructed based on the target design requirements and then the target code is generated. Therefore, when the target code does not meet the preset constraint conditions, the target behavior model can be optimized so that the target code meets the preset constraint target, and then the on-chip network code file can be generated based on the target code. In this way, before generating the on-chip network code file, the embodiment of the present invention ensures that the target code is generated based on the target design requirements and meets the preset constraint target by performing constraint verification on the target code in the design process and optimizing and adjusting the target behavior model to obtain the target code that meets the preset constraint target. There is no need to verify and evaluate it once after generating the on-chip network code file. The process of verifying and evaluating whether the code design meets the design expectations is set in the design process, which reduces the scope of code optimization and adjustment in the design process. At the same time, compared with manually rewriting the on-chip network code file, the process of optimizing the target behavior model is less complex, thereby reducing the cost of code modification. On the premise of ensuring that the target code is generated based on the target design requirements and the preset constraint targets are verified to meet expectations, the code generation efficiency of the on-chip network is improved.

[0051] Optionally, the embodiment of the present invention may further include the following steps: Step 401: Obtain user product requirements input by the user.

[0052] In the embodiment of the present invention, a user product requirement input by a user is obtained, and the user product requirement input by the user may be a product requirement document (PRD). Exemplarily, the file format of the user product requirement may be in xls format.

[0053] Step 402: Regularize and divide the user product requirements to obtain the target design requirements and the preset constraint targets; the target design requirements include the requirement content of the functional dimension in the user product requirements, and the preset constraint targets include the requirement content of the hardware constraint dimension in the user product requirements.

[0054] In an embodiment of the present invention, user product requirements are used as constraints for the entire design process of the on-chip network, and the user product requirements are regularized, that is, the user product requirements are expressed in a standardized and structured manner to eliminate expression ambiguity. The user product requirements are transformed and divided into requirements to obtain target design requirements that describe functional requirements from a development perspective and preset constraint targets that describe hardware requirements. The target design requirements include the requirements content of the functional dimension in the user product requirements, and the format of the target design requirements may include but is not limited to the xml format and the yaml format. The embodiment of the present invention does not limit the format requirements of the target design requirements. The preset constraint target includes the requirements content of the hardware constraint dimension in the user product requirements. Accordingly, after the on-chip network code file is generated, it can be verified to confirm whether the on-chip network code file meets the design expectations of the user product requirements. Exemplarily, the user product requirements can be regularized, and the user product requirements can be divided and sorted into functional side requirements and hardware side requirements to obtain the target design requirements and preset constraint targets in xml format or yaml format.

[0055] In an embodiment of the present invention, by regularizing the user product requirements to obtain the target design requirements and preset constraint objectives, the user product requirements can be divided into different dimensions by defining clear formats and rules to obtain requirement contents of different dimensions, thereby ensuring the consistency and accuracy of the requirements and facilitating the subsequent construction of codes based on the requirement contents of different dimensions.

[0056] Optionally, after step 101, the embodiment of the present invention may include the following steps: Step 501: Perform simulation analysis on the target behavior model to determine whether the target behavior model meets the target design requirement.

[0057] Accordingly, step 102 may include the following steps: Step 502: When the target behavior model meets the target design requirement, generate a target code based on the target behavior model and a preset code library.

[0058] In the embodiment of the present invention, a simulation tool is used to simulate and verify the target behavior model to obtain a simulation result, which is used to evaluate whether the performance of the NoC system represented by the target behavior model meets expectations. At the same time, if the target behavior model does not meet the target design requirements, the target behavior model is optimized and adjusted according to the simulation results. If the target behavior model meets the target design requirements, the target code is generated based on the target behavior model and a preset code library.

[0059] In the embodiment of the present invention, by performing simulation analysis on the target behavior model, when the target behavior model meets the target design requirements, the target code is regenerated to ensure that the target behavior model meets the target design requirements.

[0060] Optionally, the embodiment of the present invention may further include the following steps: Step 601: Perform constraint check based on the target code and the preset constraint target to obtain a check result.

[0061] In an embodiment of the present invention, a constraint check is performed based on the target code and the preset constraint target to obtain a check result. The check result may include a first check result and a second check result, wherein the first check result is used to indicate that the target code does not meet the preset constraint target, and the second check result is used to indicate that the target code meets the preset constraint target. Exemplarily, a tool provided by an integrated development environment (such as Vivado) can be used to perform constraint checking. These tools are generally able to automatically analyze the target code and the synthesized netlist and check whether they meet the preset constraint target. Specifically, the preset constraint target can be set in an integrated development environment through an XDC (Xilinx Design Constraints) file or other means. The tool provided by the integrated development environment is used to perform constraint checking on the target code to determine whether the target code meets the preset constraint target. According to the check result output by the tool, it is determined whether the target code violates any preset constraint target. It can be understood that when the target code does not meet the preset constraint target, according to the check result output by the tool, it can be analyzed which constraint target the target code specifically does not meet. Exemplarily, it can be achieved by checking whether the delay of signal transmission corresponding to the target code meets the set delay constraint; checking whether the power consumption corresponding to the target code exceeds the power consumption constraint; checking whether the layout constraint is met based on the layout state corresponding to the target code; and analyzing and checking whether the bandwidth utilization and transmission efficiency corresponding to the target code meet the bandwidth constraint of the physical link.

[0062] Accordingly, step 103 may include the following steps: Step 602: When the inspection result is a first inspection result, the target behavior model is optimized based on the first inspection result; the first inspection result is used to indicate that the target code does not meet the preset constraint target.

[0063] In an embodiment of the present invention, when the inspection result is the first inspection result, that is, when the target code does not meet the preset constraint target, the target behavior model is optimized based on the first inspection result. Exemplarily, the first inspection result can be analyzed to determine the specific constraint target that the current target code does not meet, and based on the specific constraint target that the current target code does not meet, the target behavior model is analyzed to determine the optimization content that needs to be adjusted for the specific constraint target that the current target code does not meet, and the target behavior model is optimized based on the optimization content. For example, when the target code does not meet the delay constraint, the clock parameters and other contents corresponding to the target behavior model can be optimized and adjusted; when the target code does not meet the physical layout constraint, the topological structure corresponding to the target behavior model can be optimized; when the target code does not meet the power consumption constraint, the routing algorithm corresponding to the target behavior model can be optimized. In the process of optimizing the target behavior model, it is possible to choose to adjust the target design requirements according to the optimization content, and rebuild the target behavior model based on the adjusted target design requirements.

[0064] Step 603: Generate a first target code based on the optimized target behavior model and the preset code library.

[0065] In the embodiment of the present invention, the first target code is generated based on the optimized target behavior model and the preset code library. It is understandable that the method of generating the first target code is similar to the method of generating the target code in step 102, and will not be repeated here.

[0066] Step 604: When the first target code does not satisfy the preset constraint target, re-execute the step of optimizing the target behavior model based on the first inspection result.

[0067] In the embodiment of the present invention, a constraint check is performed based on the first target code and the preset constraint target to obtain a check result. If the check result is the first check result, that is, the first target code does not meet the preset constraint target, the target behavior model is optimized again based on the first check result.

[0068] Step 605: When the inspection result is the second inspection result, the first target code is determined as the target code; the second inspection result is used to indicate that the first target code meets the preset constraint target.

[0069] In the embodiment of the present invention, when the inspection result is the second inspection result, that is, the first target code meets the preset constraint target, the first target code after the optimization iteration is characterized to meet the target design requirements and the preset constraint target, that is, the target code meets both the functional design requirements and the hardware design requirements, then the first target code can be determined as the final target code. Based on the target code, an on-chip network code file is generated.

[0070] In an embodiment of the present invention, a constraint check is performed on the target code against a preset constraint target, and it is determined whether the target behavior model needs to be iteratively optimized based on the check result. If the target code does not meet the preset constraint target, the target behavior model is optimized, and the design requirements and constraint targets are comprehensively considered to design a target code that meets the design expectations.

[0071] For example, Figure 2 A flowchart showing the specific steps of a design method for an on-chip network is shown in FIG. Figure 2 As shown, obtain the product requirement document, the file format of which can be in xls format, regularize the product requirement document, and obtain the target design requirements in yaml format. Construct the target behavior model based on the target design requirements. Generate Verilog code, i.e., the target code, based on the preset code base and the target behavior model. Spyglass can be used to perform constraint checks on the target code for preset constraint targets. If the target code does not meet the preset constraint targets, the target behavior model is re-analyzed based on the check results of the constraint check, such as delay analysis, node distance analysis, etc., to readjust the target design requirements and rebuild the target behavior model. If the target code meets the preset constraint targets, static checking, synthesis, simulation, etc. are performed on the target code based on EDA to generate an on-chip network code file, including a bitstream file bitstream. Verify and confirm the on-chip network code file to confirm whether the on-chip network code file meets the design expectations required by the product requirement document.

[0072] Figure 3 is a schematic diagram of the structure of a design device for a network on chip provided by an embodiment of the present invention, such as Figure 3 As shown, the device may specifically include: The first construction module 701 is used to construct a target behavior model based on target design requirements; A first generating module 702, configured to generate target code based on the target behavior model and a preset code library; A first optimization module 703 is used to optimize the target behavior model and update the target code based on the optimized target behavior model when the target code does not meet the preset constraint target, until the target code meets the preset constraint target; The second generating module 704 is configured to generate a network on chip code file based on the target code that meets the preset constraint target.

[0073] Optionally, the target design requirements include architecture design requirements, functional design requirements and performance parameter design requirements for the on-chip network; the first building module 701 includes: A first determination module is used to determine system framework information of the network on chip, module configuration information corresponding to at least two functional modules required by the network on chip, and parameter configuration information based on the architecture design requirements, the functional design requirements, and the performance parameter design requirements; The first construction submodule is used to construct the target behavior model using a target language based on the system framework information, the module configuration information corresponding to the at least two functional modules, and the parameter configuration information.

[0074] Optionally, the device further comprises: A first checking module, used for performing a constraint check based on the target code and the preset constraint target to obtain a check result; The first optimization module 703 includes: A first optimization submodule is used to optimize the target behavior model based on the first inspection result when the inspection result is a first inspection result; the first inspection result is used to indicate that the target code does not meet the preset constraint target; A first generating submodule, used for generating a first target code based on the optimized target behavior model and the preset code library; A first execution module, configured to re-execute the step of optimizing the target behavior model based on the first inspection result when the first target code does not meet the preset constraint target; The second determination module is used to determine the first target code as the target code when the inspection result is a second inspection result; the second inspection result is used to indicate that the first target code meets the preset constraint target.

[0075] Optionally, the device further comprises: A first analysis module, used to perform simulation analysis on the target behavior model to determine whether the target behavior model meets the target design requirement; The first generating module 702 includes: The second generating submodule is used to generate target code based on the target behavior model and a preset code library when the target behavior model meets the target design requirement.

[0076] Optionally, the preset constraint targets include physical layout constraints, delay constraints, power consumption constraints, and bandwidth constraints of physical links for the on-chip network.

[0077] Optionally, the device further comprises: A first acquisition module is used to acquire user product requirements input by a user; The first processing module performs regularization and demand division processing on the user product requirements to obtain the target design requirements and the preset constraint targets; the target design requirements include the demand content of the functional dimension in the user product requirements, and the preset constraint targets include the demand content of the hardware constraint dimension in the user product requirements.

[0078] Optionally, the first generating module 702 includes: A second acquisition module, used to acquire the preset code library; The first conversion module is used to convert the target behavior model into target code based on the preset code library by using a code generation tool.

[0079] The present invention also provides an electronic device, see Figure 4 , including: a processor 801, a memory 802, and a computer program 8021 stored in the memory and executable on the processor, wherein when the processor executes the program, the on-chip network design method of the aforementioned embodiment is implemented.

[0080] The present invention also provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the on-chip network design method of the aforementioned embodiment.

[0081] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0082] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0083] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0084] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0085] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0086] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0087] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0088] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0089] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0091] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for designing a network on chip, characterized in that: The method comprises: Build target behavior model based on target design requirements; Generate target code based on the target behavior model and the preset code library; In the case where the target code does not meet the preset constraint target, optimizing the target behavior model and updating the target code based on the optimized target behavior model until the target code meets the preset constraint target; Based on the target code that meets the preset constraint target, an on-chip network code file is generated.

2. The method according to claim 1, characterized in that The target design requirements include architecture design requirements, functional design requirements and performance parameter design requirements for the on-chip network; The target behavior model is constructed based on the target design requirements, including: Based on the architecture design requirements, the functional design requirements and the performance parameter design requirements, determine the system framework information of the network on chip, the module configuration information corresponding to at least two functional modules required by the network on chip, and the parameter configuration information; The target behavior model is constructed using a target language based on the system framework information, the module configuration information corresponding to the at least two functional modules, and the parameter configuration information.

3. The method according to claim 1, characterized in that The method further comprises: The method further comprises: performing a constraint check based on the target code and the preset constraint target to obtain a check result; optimizing the target behavior model and updating the target code based on the optimized target behavior model when the target code does not meet the preset constraint target, until the target code meets the preset constraint target, including: In the case where the inspection result is a first inspection result, optimizing the target behavior model based on the first inspection result; the first inspection result is used to indicate that the target code does not meet the preset constraint target; Generate a first target code based on the optimized target behavior model and the preset code library; In the case where the first target code does not satisfy the preset constraint target, re-execute the step of optimizing the target behavior model based on the first inspection result; When the inspection result is the second inspection result, the first target code is determined as the target code; the second inspection result is used to indicate that the first target code meets the preset constraint target.

4. The method according to claim 1, characterized in that: After constructing the target behavior model based on the target design requirements, the method further includes: Performing simulation analysis on the target behavior model to determine whether the target behavior model meets the target design requirements; The generating target code based on the target behavior model and the preset code library includes: When the target behavior model meets the target design requirement, a target code is generated based on the target behavior model and a preset code library.

5. The method according to claim 1, characterized in that The method further comprises: Obtain user product requirements input by users; The user product requirements are regularized and divided to obtain the target design requirements and the preset constraint targets; the target design requirements include the requirement content of the functional dimension in the user product requirements, and the preset constraint targets include the requirement content of the hardware constraint dimension in the user product requirements.

6. The method according to claim 1 or 4, characterized in that: The generating target code based on the target behavior model and the preset code library includes: Obtaining the preset code library; Based on the preset code library, the target behavior model is converted into target code using a code generation tool.

7. The method according to claim 1, characterized in that The preset constraint targets include physical layout constraints, delay constraints, power consumption constraints, and bandwidth constraints of physical links for the on-chip network.

8. A design device for a network on chip, characterized in that: The device comprises: The first building module is used to build a target behavior model based on target design requirements; A first generating module, used for generating target code based on the target behavior model and a preset code library; A first optimization module, configured to optimize the target behavior model and update the target code based on the optimized target behavior model when the target code does not meet the preset constraint target, until the target code meets the preset constraint target; The second generating module is used to generate an on-chip network code file based on the target code that meets the preset constraint target.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for designing a network on chip as claimed in any one of claims 1 to 7 is implemented.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the on-chip network design method described in any one of claims 1-7.

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