Hybrid iterative error correction and redundancy decoding operations for memory subsystems

Abstract

The invention relates to hybrid iterative error correction and redundancy decoding operations for memory subsystems. Data stored on each of a set of memory components may be read. Corresponding data stored on a number of the group of memory components that cannot be decoded using an error correction code decoding operation may be identified. A determination may be made whether a number of the plurality of memory components containing the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. In response to determining that the number of the set of memory components containing the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device may perform a redundant error correction decoding operation to correct the data stored on each of the set of memory components.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with the invention name “Hybrid Iterative Error Correction and Redundant Decoding Operations for Memory Subsystems”, application number 201980057915.7, and application date July 23, 2019. Technical Field

[0003] The present disclosure relates generally to memory subsystems, and more particularly to allocating mutable media type memory components in a memory subsystem. Background Art

[0004] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, nonvolatile memory components and volatile memory components. In general, a host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0005] On the one hand, the present disclosure provides a method, which includes: reading data stored on each of a plurality of memory components; identifying that corresponding data stored on a number of the plurality of memory components cannot be decoded using an error correction code (ECC) decoding operation; determining whether the number of the plurality of memory components containing the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition; and in response to determining that the number of the plurality of memory components containing the corresponding data that cannot be decoded from the ECC decoding operation satisfies the threshold condition, performing a redundant error correction decoding operation by a processing device to correct the data stored on each of the plurality of memory components.

[0006] On the other hand, the present disclosure also provides a system, which includes: multiple memory components; and a processing device, which is operatively coupled to the multiple memory components to: read data stored on each of the multiple memory components; identify that corresponding data stored on several of the multiple memory components cannot be decoded using an error correction code (ECC) decoding operation; determine whether the number of the multiple memory components containing the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition; and in response to determining that the number of the multiple memory components containing the corresponding data that cannot be decoded from the ECC decoding operation satisfies the threshold condition, perform a redundant error correction decoding operation to correct the data stored on each of the multiple memory components.

[0007] On the other hand, the present disclosure also provides a non-temporary computer-readable storage medium comprising instructions, which, when executed by a processing device, cause the processing device to perform the following operations: read multiple data blocks from multiple memory components; perform redundant error correction decoding operations on the multiple data blocks to correct specific data blocks containing errors among the multiple data blocks; and in response to correcting the specific data block containing the error, perform redundant reconstruction operations to reconstruct data of other data blocks containing errors among the multiple data blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0010] Figure 2 is a flow chart of an example method to perform a hybrid iterative error correction code decoding operation and a redundant error correction decoding operation on data based on a threshold condition in accordance with some embodiments.

[0011] Figure 3 An example data stripe containing errors in a data block stored on a memory component is shown according to some embodiments of the present disclosure, where the Figure 2 The method performs an iterative error correction code decoding operation and a redundant error correction decoding operation based on a threshold condition.

[0012] Figure 4 is a flow chart of an example method for performing redundant error correction decoding operations and redundant reconstruction operations on data in a data block of a memory component according to some embodiments.

[0013] Figure 5 1 shows example data striping in data blocks stored on a memory component according to some embodiments of the present disclosure, where the data is striped using Figure 4 The method performs redundant error correction decoding operations and redundant reconstruction operations to remove errors from data.

[0014] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure are directed to providing a memory subsystem that includes hybrid iterative error correction code decoding operations and redundant error correction decoding operations for data in the memory subsystem. The memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. In general, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem, and can request to retrieve data from the memory subsystem.

[0016] Conventionally, there are several techniques used to attempt to improve performance and / or reduce any errors in the data contained in the memory subsystem. One technique, referred to as Redundant Array of Independent Disks (RAID) or Redundant Array of Independent NAND (RAIN), can be used to improve the reliability and / or performance of data storage. A RAID system may include two or more memory components operating in parallel. A RAID system may use mirroring of data, segmentation of data, or some combination thereof, depending on which level (e.g., 0, 1, 5, 6, 10, etc.) of RAID is being used. Mirroring refers to storing data at least twice, once on a first memory component and a second time on a second memory component of the memory subsystem. When one of the memory components fails, the data on the other memory component can be used for data recovery, and operation of the memory subsystem can continue.

[0017] Striping refers to splitting data into several blocks of data that are written across each memory component in the array. Using a large number of memory components simultaneously can improve the performance of the memory subsystem by allowing reads and / or writes to occur simultaneously. In addition, in some conventional systems, parity data (e.g., checksums) can be calculated from the blocks of data that are striped across the memory components, and the parity data can be stored on its own individual memory component as part of a stripe with other blocks of data. The memory subsystem can use the parity data to reconstruct the data of one of the other memory components if the data contains errors. For example, when the data of one of the memory components contains errors, redundant operations (e.g., logical operations) can be performed on the error-free data of the other memory components to reconstruct the data with errors. In general, redundant operations can ensure that errors in the data are removed by reconstructing the data for the memory component containing the data with errors.

[0018] This particular technique may be limited to: removing errors for data of one memory component in a RAID level 5 (referred to herein as "RAID 5") configuration because parity data is written to one memory component; and removing errors for data of two memory components in a RAID level 6 (referred to herein as "RAID 6") configuration because parity data is written to two memory components. That is, if in a RAID 5 configuration, more than one memory component contains errors, then a conventional memory subsystem may not recover the data stored on the memory components. Similarly, if in a RAID 6 configuration, more than two memory components contain errors, then a conventional memory subsystem may not recover the data stored on the memory components. Additional redundancy may be added to further improve the reliability of the data. However, it may be desirable (e.g., for efficiency, cost savings, etc.) to increase the data reliability and robustness of the memory subsystem without adding more memory components or dies containing redundant data.

[0019] Another conventional technique for improving the reliability of data stored in a memory subsystem is an error correction code. An error correction code may refer to a technique for expressing a sequence of data so that errors introduced into the data can be detected and corrected based on other remaining data. The sequence of data may be referred to as a codeword. Types of error correction codes may include block codes (e.g., Hamming codes, Reed Solomon codes, etc.). Typically, an encoder encodes data to be written with additional data to form a codeword and divides the codeword across the memory components of the memory subsystem. When the divided data is to be read, a decoder decodes the codeword by removing the additional data bits and providing the desired original data. Conventionally, error correction codes are not used in conjunction with redundant operations (e.g., RAID).

[0020] Aspects of the present disclosure address the above and other deficiencies by providing a memory subsystem that includes a hybrid iterative error correction code decoding operation and a redundant error correction decoding operation for data in the memory subsystem. The memory subsystem that uses the hybrid iterative error correction code decoding operation to correct and redundant error correction decoding operations can tolerate a higher average bit error rate while achieving a codeword failure rate similar to that of previous conventional systems that use redundancy techniques (e.g., RAID) or error correction operations alone. Therefore, the hybrid technique provides a more robust and reliable memory subsystem because it can correct more bit errors than conventional systems while maintaining a codeword failure rate similar to conventional systems.

[0021] To achieve these benefits, some embodiments may include combining a first level of decoding that performs an error correction code decoding operation to correct data stored in one or more memory components using an error correction code, and a second level of decoding that performs a redundant error correction decoding operation to correct the data stored in the one or more memory components using parity data. The error correction code decoding operation may refer to applying an error correction code to data to attempt to decode the data in a stripe. The error correction code decoding operation does not use any information about the location of the error bit. A redundant error correction decoding operation is a type of error correction code decoding operation. The redundant error correction decoding operation may or may not use information about the location of the error bit. The first level of error correction code decoding operation may be stronger than the second level of redundant error correction decoding operation. That is, the first level of error correction code decoding operation may generally correct more errors than the second level of redundant error correction decoding operation. For example, the first level of error correction code decoding operation may correct a first number of bits (e.g., 20) in a 128-byte codeword, and the redundant error correction decoding operation may correct a second number of bits (e.g., 1 symbol) that is less than the first number of bits.

[0022] Data stored on each of the memory components of the memory subsystem may be read. The data may have been encoded as a codeword, and an error correction code decoding operation may be used to attempt to decode the codeword. A codeword may refer to expressing the data in a specific sequence to achieve error detection and correction. Undecodable corresponding data stored on several memory components may be identified. A determination may be made as to whether the number of memory components satisfies a threshold condition. The threshold condition may indicate the number of corresponding data on the several memory components that cannot be reconstructed by a redundant reconstruction operation. A redundant reconstruction operation may refer to performing a logical operation on the data to reconstruct the data. The redundant reconstruction operation uses information on the exact error location, and the number of known error locations does not exceed a threshold. In a RAID 6 configuration, the threshold number is two for corresponding data on the several memory components that cannot be reconstructed by a redundant reconstruction operation. Therefore, in the example, if three or more of the corresponding data on the several memory components cannot be reconstructed by a redundant reconstruction operation, the threshold condition is satisfied.

[0023] If it is determined that the number of memory components meets the threshold condition, then a redundant error correction decoding operation may be performed to correct the data stored on each of the memory components. After performing the redundant error correction decoding operation, the decoding of the codeword may be attempted again using the error correction code decoding operation. If the decoding fails, the corresponding data stored on the number of memory components may be identified. A determination may be made again as to whether the threshold condition is still met. If the threshold condition is still met, then the redundant error correction decoding operation may be performed again. Thus, there is an iterative aspect of the disclosed technology.

[0024] If at any time, it is determined that the corresponding data of the threshold number of memory components do not satisfy the threshold condition, then a redundant reconstruction operation may be performed to reconstruct the corresponding data stored at the number of memory components. The redundant operation may also be referred to as erasure decoding, which means that the location of the decoding failure on the memory components is known. The redundant reconstruction operation may include identifying decodable data stored at a second number of memory components, and applying a logical operation (e.g., an exclusive OR (XOR)) based on the data stored at the second number of memory components to reconstruct the corresponding data on the memory components that could not be decodable.

[0025] Advantages of the present disclosure include, but are not limited to, providing improved data reliability of a memory subsystem by using hybrid iterative error correction and redundant decoding operations. When a threshold condition is met (e.g., redundant operations cannot be used) to correct one or more errors in a memory component, data reliability can be improved by repeatedly using error correction code decoding and redundant error correction decoding operations. Additionally, when the threshold condition is not met, data reliability can also be improved by using redundant reconstruction operations to reconstruct data in the memory component. These benefits can be achieved without adding additional redundant memory components to the memory subsystem, thereby reducing the size and / or cost of a data center. Furthermore, improving the data reliability of the memory subsystem can improve memory subsystem performance overall because access operations can succeed.

[0026] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is described. The memory subsystem 110 may include media, such as memory components 112A to 112N. The memory components 112A to 112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, serial advanced technology attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, universal serial bus (USB) interfaces, fiber channels, serial attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0028] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Furthermore, the memory cells of the memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0029] The memory system controller 115 (hereinafter referred to as the "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N, as well as other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes an embedded memory that is configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown to include a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may also include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A to 112N.

[0032] The memory subsystem 110 may include a management component 113 (e.g., circuitry, dedicated logic, programmable logic, firmware, etc.) to perform the operations described herein. In some embodiments, the controller 115 includes at least a portion of the management component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the management component 113 is part of the host system 110, an application, or an operating system.

[0033] The management component 113 may perform a hybrid iterative error correction code decoding operation and a redundant error correction decoding operation on the data stored in the memory subsystem 110. A threshold condition may be used to determine whether to perform a redundant error correction decoding operation or a redundant reconstruction operation to reconstruct the data in the memory subsystem 110. The error correction code decoding operation may include any suitable type of error correction code to correct one or more bit errors (e.g., flipped bits) stored in the memory components 112A to 112N. The redundant error correction decoding operation may include applying parity data to correct the one or more bit errors when the threshold condition is met. When the threshold condition is not met, the redundant reconstruction operation may include performing a logical operation on the data stored on the memory component where the decoding was successful to reconstruct the data stored on the memory component where the decoding was unsuccessful.

[0034] Figure 2 1 is a flow chart of an example method 200 for performing a hybrid iterative error correction code decoding operation and a redundant error correction decoding operation on data based on a threshold condition according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The management component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the embodiment shown should be understood as an example only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0035] At block 210, processing logic reads data stored on each of a set of memory components 112A-112N. In some embodiments, the data blocks of data stored on each of the set of memory components 112A-112N may be collectively referred to as data stripes. In some embodiments, the data may be a codeword that is encoded prior to storing the codeword on the set of memory components 112A-112N. Different data blocks of the codeword may be written across corresponding data blocks of the set of memory components 112A-112N. The codeword may be encoded based on the type of error correction code that will be used when a threshold condition is met.

[0036] In some embodiments, a maximum distance separable code, such as a Reed-Solomon code, may be used. Reed-Solomon codes encode data blocks by adding extra redundant bits to the data. For example, k data symbols of s bits may each be encoded into an n symbol codeword, where a parity symbol is added to the k data symbols. A mathematical operation (e.g., a polynomial) may be generated based on the data blocks, and the mathematical operation may be used to obtain the parity bits. Parity bits may be added to the data blocks, and different ones of the data blocks containing the parity bits may be stored in different memory components 112A to 112N.

[0037] Various reasons (e.g., noisy communications, memory component failures, asynchronous power loss, etc.) may cause the data of a codeword to contain errors (e.g., flipped bits, missing bits, etc.) If errors exist in the codewords stored across memory components 112A- 112N, parity bits or other bits of the codewords may be used in raw mathematical operations to obtain the raw data block and / or parity bits and correct the errors in the codewords.

[0038] At block 220, the processing device decodes the data from each of the set of memory components 112A-112N using an error correction code decoding operation. The error correction code decoding operation may include applying an error correction code to a codeword in an attempt to decode the codeword (e.g., remove parity bits) and / or repair one or more bit errors. For example, applying the error correction code to the data stored on each of the set of memory components 112A-112N may result in obtaining updated data that includes at least one corrected bit. If a Reed-Solomon code is used, the mathematical operation (e.g., a polynomial) used to encode the codeword may be used with one or more original bits and / or parity bits of the codeword to obtain correction bits to which the bits containing the errors will be changed.

[0039] At block 230, the processing device determines whether the decoding is successful for each data. A decoding failure may occur when one or more of the corresponding data includes an error on the set of memory components 112A-112N. If the decoding is successful for each data, then at block 240, the processing device provides the decoded data. The decoded data may be provided to a requestor (e.g., host system 120) requesting access to the data.

[0040] If, for each data, decoding is unsuccessful, then at block 250, the processing device identifies that the corresponding data stored on the number of the groups of memory components 112A to 112N is not decodable. At block 260, the processing device determines whether the number of the groups of memory components 112A to 112N satisfies a threshold condition. As previously discussed, the threshold condition may indicate the number of corresponding data on the number of the groups of memory components 112A to 112N that cannot be reconstructed through a redundant reconstruction operation (e.g., a logical "exclusive OR" operation). The number may vary based on the type of RAID configuration used. For example, the number is two for RAID 6, and thus the threshold condition is satisfied when three or more corresponding data on three or more memory components 112A to 112N cannot be reconstructed through a redundant reconstruction operation. Thus, the number of corresponding data on the number of the groups of memory components 112A to 112N that cannot be reconstructed through a redundant reconstruction operation may be any suitable number.

[0041] At block 270, in response to determining that the corresponding data of the threshold number of the set of memory components 112A to 112N do not satisfy the threshold condition, the processing device performs a redundant reconstruction operation to reconstruct the corresponding data stored at the number of the set of memory components 112A to 112N that includes one or more errors. To perform the redundant reconstruction operation, the processing device may identify decodable data stored at the second number of the set of memory components 112A to 112N. Additionally, the processing device may apply a logical operation (e.g., an exclusive OR) based on the data stored at the second number of the set of memory components 112A to 112N to reconstruct the corresponding data stored at the number of the set of memory components 112A to 112N where the data cannot be decoded. After reconstructing the corresponding data, at block 240, the processing device may provide the data to the requestor.

[0042] At block 280, in response to determining that the number of the groups of memory components 112A-112N do satisfy the threshold condition, the processing device may perform a redundant error correction decoding operation to correct the data stored on each of the groups of memory components 112A-112N. In some embodiments, the redundant error correction decoding operation performed by the processing device at block 220 may be a second level of decoding and may include performing RAID error correction decoding by applying parity data to user data stored on each of the groups of memory components 112A-112N to obtain updated data including at least one corrected bit.

[0043] In some embodiments, the processing device may return to block 220 to decode the codeword again using an error correction code decoding operation and determine whether the threshold condition is still satisfied. For example, after performing the redundant error correction decoding operation, the processing device may attempt to decode the codeword again. At block 230, the processing device may again determine whether the decoding was successful for each data. If yes, the processing device may provide the decoded data to the requester at block 240. If no, the processing device may identify (block 250) the corresponding data stored on the number of the groups of memory components 112A to 112N that cannot be decoded again, and determine (block 260) whether the number of the groups of memory components 112A to 112N still satisfies the threshold condition. In response to determining that the group of memory components 112A to 112N still satisfies the threshold condition after the error correction code decoding operation has been performed, the processing device may again perform (block 280) the redundant error correction decoding operation to correct another portion of the data stored at the group of memory components 112A to 112N. The processing device may again return to block 220 to repeat the process until the threshold condition is no longer met. In this manner, iterating the primary decoding (error correction code decoding operation) and the secondary decoding (redundant error correction decoding operation) may improve error correction performance by correcting more errors than performing the primary decoding itself or the secondary decoding itself.

[0044] In response to determining (block 260) that the set of memory components 112A-112N do not satisfy the threshold condition, the processing device may perform (block 240) a redundant reconstruction operation to reconstruct the corresponding data stored at the set of memory components 112A-112N. The corresponding data may include other portions of the data having one or more errors that were not corrected by the error correction operation.

[0045] Figure 3 1. Example data stripes 310, 320, and 330 containing errors in data blocks stored on memory components 112A to 112N are shown, using Figure 2The method 200 performs iterative error correction code decoding operations and redundant error correction decoding operations based on threshold conditions. In some embodiments, the stripes of data 310, 320, and 330 may represent codewords encoded before the codewords are written to the memory components 112A to 112N. Therefore, the stripes of data 310, 320, and 330 may include the original data blocks to be stored, as well as additional parity data determined using error correction codes and added to the original data blocks. Each stripe of data 310, 320, and 330 may include one kilobyte of data or any suitable amount of data. The stripes of data 310, 320, and 330 may be read in any order as determined by the host system 120 and immediately upon request by a user of the host system 120. In Figure 3 In the following discussion of , it should be understood that RAID 6 is being used, and therefore the threshold condition is three or more data stored on the set of memory components 112A to 112N that cannot be reconstructed through a redundant reconstruction operation.

[0046] If it is determined that the data stripe 310 is to be read, each data block 340A to 340N of the stripe 310 stored on the memory components 112A to 112N may be read. Decoding of the data stripe 310 may be attempted, but as shown, the data blocks 340A and 340B of the stripe 310 include data with one or more errors (represented by X), and decoding of each data cannot be successfully completed. The decoding may include performing the error correction code decoding operation (e.g., first-level decoding) described above. An identification may be made that the corresponding data on several (e.g., two) of the groups of memory components 112A and 112B cannot be decoded. In addition, a determination may be made as to whether the number of memory components 112A and 112B satisfies a threshold condition. For this data stripe 310, the threshold condition is not satisfied because only two (e.g., less than three) corresponding data on the two memory components 112A and 112B include data that cannot be reconstructed by a redundant reconstruction operation due to errors. Therefore, since the threshold condition is not satisfied, a redundant reconstruction operation may be performed on the data decodable in data blocks 340C and 340D to 340N to reconstruct the data in data blocks 340A and 340B of data stripe 310. Once data reconstruction is complete and errors are removed, data stripe 310 may be decoded.

[0047] If it is determined that data stripe 330 is to be read, each data block 350A to 350N of stripe 310 stored on memory components 112A to 112N may be read. Decoding of data stripe 330 may be attempted, but as shown, data blocks 350A, 350B, 350C, and 350D of stripe 310 include data with one or more errors, and decoding of each data cannot be successfully completed. In some embodiments, decoding may include performing an error correction code decoding operation (e.g., a first-level decoding) as described above. Identification that corresponding data on a number (e.g., four) of the groups of memory components 112A, 112B, 112C, and 112D cannot be decoded may be performed. Additionally, a determination may be made as to whether the number of memory components 112A, 112B, 112C, and 112D satisfies a threshold condition. For this data stripe 330, the threshold condition is met because four (e.g., more than three) corresponding data on the four memory components 112A, 112B, 112C, and 112D contain data that cannot be decoded due to errors. Therefore, since the threshold condition is met, a redundant error correction decoding operation may be performed to correct the data stored on each of the memory components 112A, 112B, 112C, and 112D. In some embodiments, as described above, the redundant error correction decoding operation may be referred to as a secondary decoding.

[0048] After performing the redundant error correction decoding operation, the iterative process may perform the error correction code decoding operation again, and a determination may be made whether the threshold condition is still met. Depending on whether the threshold condition is met, a redundant error correction decoding operation (secondary decoding) or a redundant reconstruction operation may be performed to remove the remaining errors. For example, if the threshold condition is still met, the redundant error correction decoding operation may be performed again on the data stripe 330 to correct one or more errors in the data. If the threshold condition is no longer met, a redundant reconstruction operation may be performed to reconstruct the data that could not be decoded in the data block. Once the errors are removed from the data stripe 330, the data stripe may be decoded and provided to the requester.

[0049] Figure 4 1 is a flow chart of an example method 400 for performing redundant error correction decoding operations and redundant reconstruction operations on data in data blocks of memory components 112A-112N according to some embodiments. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The management component 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the embodiment shown should be understood as an example only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are possible.

[0050] At block 410, a processing device reads a data block from a set of memory components 112A to 112N. The data block may include a data stripe representing a codeword encoded using an error correction code. In some embodiments, the processing device may use an error correction code (e.g., a level 1 ECC decoding) to decode the codeword. In some instances, the data block may include one or more bit errors that prevent corresponding data of some of the data blocks from being successfully decoded. As previously described, a level 1 error correction code decoding operation may include applying an error correction code to data stored on each of the set of memory components 112A to 112N to obtain updated data including at least one corrected bit. Applying the error correction code may include applying a mathematical operation to a portion or all of the data of the data block to derive the corrected bit. The corrected bit may be used to change a bit having an error. The processing device may determine that the number of the set of memory components 112A to 112N that includes a data block having one or more errors satisfies a threshold condition.

[0051] At block 420, the processing device performs a redundant error correction decoding operation on the data blocks to correct a particular one of the data blocks that includes an error. As previously described, the redundant error correction decoding operation (secondary decoding) may include using parity data with data stored on each of the set of memory components 112A-112N to obtain updated data including at least one corrected bit.

[0052] In some embodiments, after performing the error correction operation, the processing device may again use the error correction code decoding operation (primary decoding) to repeatedly attempt to decode the data in the data block. If the decoding is not successfully completed for each data, the processing device may determine whether the threshold condition is still satisfied. The process of performing the primary error decoding and the secondary decoding while the threshold condition is still satisfied may be repeatedly performed until the threshold condition is no longer satisfied. If it is determined that the number of the group of memory components including the data block containing errors (e.g., cannot be decoded) does not satisfy the threshold condition, a redundancy reconstruction operation may be performed.

[0053] Therefore, in response to correcting the particular data block containing the error, the processing device may perform a redundant reconstruction operation to reconstruct the data of the other data blocks containing the error at block 430. To perform the redundant reconstruction operation, the processing device may identify a subset of the data blocks of the group of memory components 112A to 112N that do not contain the error. In addition, the processing device may apply a logical operation (e.g., "exclusive OR") based on the subset of the data blocks to reconstruct the data of the other data blocks containing the error.

[0054] Figure 5 5 shows an example data stripe 500 in data blocks 510A, 510B, and 510C stored on memory components 112A, 112B, and 112C, using Figure 4 The method 400 performs redundant error correction decoding operations 520 and redundant reconstruction operations 530 to remove errors from the data. Although only three memory components 112A, 112B, and 112C are depicted, it should be understood that any suitable number of memory components may be used. Figure 5 In the following description of , it should be understood that RAID 6 is being used, and therefore, the threshold condition is three or more data stored on the group of memory components 112A to 112N that cannot be reconstructed through a redundant reconstruction operation.

[0055] Method 400 may begin at circle 502, where it is determined that data stripe 500 is to be read. Thus, each data block 510A, 510B, and 510C of stripe 500 stored on memory components 112A, 112B, and 112C may be read. Decoding of stripe 500 may be attempted (e.g., using an error correction code decoding operation), and one or more bit errors may be repaired. However, decoding of each data in stripe 500 may fail because, as shown, data blocks 510A, 510B, and 510C of stripe 500 include data with one or more errors (represented by Xs). A determination may be made that the number (e.g., three) of memory components 112A, 112B, and 112C that include data blocks 510A, 510B, and 510C with errors satisfies a threshold condition (e.g., three or more memory components with data that cannot be reconstructed through a redundant reconstruction operation). Thus, since the threshold condition is satisfied, error correction operation 520 may be performed to correct a particular block of data among blocks of data 510A, 510B, and 510C on each of memory components 112A, 112B, 112C, and 112D.

[0056] Redundant error correction decoding operation 520 (secondary decoding) may include applying parity data to data blocks 510A, 510B, and 510C to obtain updated data having at least one corrected bit. As depicted, after performing redundant error correction decoding operation 520, data in data block 510C is corrected by redundant error correction decoding operation 520 and errors (indicated by the check mark) are removed. Also as depicted, data blocks 510A and 510B still include errors, and the read of stripe 500 cannot be completed. A determination may be made that the number (e.g., two) of memory components 112A, 112B, and 112C that include data blocks with errors (e.g., data blocks 510A and 510B) no longer satisfies a threshold condition (e.g., less than three).

[0057] In some embodiments, when the threshold condition is not met, a redundancy reconstruction operation 530 may be performed. The redundancy reconstruction operation 530 may apply a logical operation (e.g., "XOR") to the data in the data block without errors (e.g., data block 510C) to reconstruct the data in the data blocks 510A and 510B containing errors. After reconstructing the data in the data blocks 510A 510B, the errors are removed from their corresponding data (indicated by the check mark). The error-free data stripe 500 may be read and / or provided to the requester (e.g., the host system 120).

[0058] Figure 6 An example machine of a computer system 600 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a computer system that includes, is coupled to, or uses a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 The operation of the management component 113) of the host system (e.g., Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to a local or local network, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0059] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0060] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0061] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for implementing the operations and steps discussed herein. The computer system 600 may also include a network interface device 608 to communicate over a network 620.

[0062] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0063] In one embodiment, instructions 626 include implementing instructions corresponding to a management component (e.g., Figure 1The term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0064] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical control of a physical quantity. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0065] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0066] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0068] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0069] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: performing an error correction code (ECC) decoding operation to decode one or more data units stored in a stripe across a plurality of memory devices; responsive to the ECC decoding operation being unsuccessful, determining whether a number of memory devices in the plurality of memory devices including a first subset of the one or more data units for which the ECC decoding operation was unsuccessful satisfies a threshold criterion; and In response to determining that the number of memory devices satisfies the threshold criterion, performing, by a processing device, one or more iterations of redundant error correction decoding operations to correct the first subset of the one or more data units stored in the stripe across the plurality of memory devices until the number of memory devices does not satisfy the threshold criterion.

2. The method according to claim 1, further comprising: In response to determining that the number of memory devices does not satisfy the threshold criterion, a redundancy reconstruction operation is performed to reconstruct the first subset of the one or more data units stored in the stripe across the plurality of memory devices.

3. The method according to claim 2, further comprising: Identifying data stored at a second subset of the one or more data units that were successfully decoded, wherein the redundant reconstruction operation corresponds to applying a logical operation based on the data stored at the second subset of the one or more data units to reconstruct the first subset of the one or more data units.

4. The method of claim 1 , wherein performing the redundant error correction decoding operation comprises: Parity data is applied to the stripe of data stored across the plurality of memory devices to obtain updated data including at least one corrected bit.

5. The method according to claim 1, further comprising: performing a second ECC decoding operation on the one or more data units stored in the stripe across the plurality of memory devices after performing the redundant error correction decoding operation; after the second ECC decoding operation has been performed, determining that a portion of the first subset of the one or more data units for which the second ECC decoding operation was unsuccessful satisfies the threshold criterion; and In response to determining that a number of the portion of the first subset of the one or more data units satisfies the threshold criterion after the second ECC decoding operation has been performed, performing a second redundant error correction decoding operation to correct another portion of the one or more data units stored in the stripe across the multiple memory devices.

6. The method according to claim 5, further comprising: performing a third ECC decoding operation on the one or more data units after performing the second redundancy error correction decoding operation; after the third ECC decoding operation has been performed, determining that a second portion of the first subset of the one or more data units for which the third ECC decoding operation was unsuccessful does not satisfy the threshold criterion; and A redundant reconstruction operation is performed to reconstruct corresponding data stored at the second portion of the first subset of the one or more data units, the corresponding data including other portions of the data having one or more errors that are uncorrectable by the third ECC decoding operation.

7. The method of claim 1, wherein each of the one or more data units stored in the stripe is stored on a different memory device in the plurality of memory devices.

8. A system comprising: a plurality of memory devices; as well as a processing device operatively coupled to the plurality of memory devices to perform operations comprising the steps of: performing an error correction code (ECC) decoding operation to decode one or more data units stored in a stripe across the plurality of memory devices; responsive to the ECC decoding operation being unsuccessful, determining whether a number of memory devices in the plurality of memory devices including a first subset of the one or more data units for which the ECC decoding operation was unsuccessful satisfies a threshold criterion; and In response to determining that the number of memory devices satisfies the threshold criterion, performing, by a processing device, one or more iterations of redundant error correction decoding operations to correct the first subset of the one or more data units stored in the stripe across the plurality of memory devices until the number of memory devices does not satisfy the threshold criterion.

9. The system of claim 8, wherein the processing device is configured to perform operations further comprising: In response to determining that the number of memory devices does not satisfy the threshold criterion, a redundancy reconstruction operation is performed to reconstruct the first subset of the one or more data units stored in the stripe across the plurality of memory devices.

10. The system of claim 9, wherein the processing device is configured to perform operations further comprising: Identifying data stored at a second subset of the one or more data units that were successfully decoded, wherein the redundant reconstruction operation corresponds to applying a logical operation based on the data stored at the second subset of the one or more data units to reconstruct the first subset of the one or more data units.

11. The system of claim 8, wherein performing the redundant error correction decoding operation comprises: Parity data is applied to the stripe of data stored across the plurality of memory devices to obtain updated data including at least one corrected bit.

12. The system of claim 8, wherein the processing means is configured to perform operations further comprising: performing a second ECC decoding operation on the one or more data units stored in the stripe across the plurality of memory devices after performing the redundant error correction decoding operation; after the second ECC decoding operation has been performed, determining that a portion of the first subset of the one or more data units for which the second ECC decoding operation was unsuccessful satisfies the threshold criterion; and In response to determining that a number of the portion of the first subset of the one or more data units satisfies the threshold criterion after the second ECC decoding operation has been performed, performing a second redundant error correction decoding operation to correct another portion of the one or more data units stored in the stripe across the multiple memory devices.

13. The system of claim 12, wherein the processing means is configured to perform operations further comprising: performing a third ECC decoding operation on the one or more data units after performing the second redundancy error correction decoding operation; After the third ECC decoding operation has been performed, determining that a second portion of the first subset of the one or more data units for which the third ECC decoding operation was unsuccessful does not satisfy the threshold criterion; and A redundant reconstruction operation is performed to reconstruct corresponding data stored at the second portion of the first subset of the one or more data units, the corresponding data including other portions of the data having one or more errors that are uncorrectable by the third ECC decoding operation.

14. The system of claim 8, wherein each of the one or more data units stored in the stripe is stored on a different memory device among the plurality of memory devices.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: performing an error correction code (ECC) decoding operation to decode one or more data units stored in a stripe across a plurality of memory devices; responsive to the ECC decoding operation being unsuccessful, determining whether a number of memory devices in the plurality of memory devices that include a first subset of the one or more data units for which the ECC decoding operation was unsuccessful satisfies a threshold criterion; and In response to determining that the number of memory devices satisfies the threshold criterion, performing, by a processing device, one or more iterations of redundant error correction decoding operations to correct the first subset of the one or more data units stored in the stripe across the plurality of memory devices until the number of memory devices does not satisfy the threshold criterion.

16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations comprising: In response to determining that the number of memory devices does not satisfy the threshold criterion, a redundancy reconstruction operation is performed to reconstruct the first subset of the one or more data units stored in the stripe across the plurality of memory devices.

17. The non-transitory computer-readable storage medium of claim 16, wherein the instructions cause the processing device to perform operations comprising: Identifying data stored in a second subset of the one or more data units that were successfully decoded, wherein the redundant reconstruction operation corresponds to applying a logical operation based on the data stored at the second subset of the one or more data units to reconstruct the first subset of the one or more data units.

18. The non-transitory computer-readable storage medium of claim 15, wherein performing the redundant error correction decoding operation comprises: Parity data is applied to the stripe of data stored across the plurality of memory devices to obtain updated data including at least one corrected bit.

19. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations comprising: performing a second ECC decoding operation on the one or more data units stored in the stripe across the plurality of memory devices after performing the redundant error correction decoding operation; after the second ECC decoding operation has been performed, determining that a portion of the first subset of the one or more data units for which the second ECC decoding operation was unsuccessful satisfies the threshold criterion; and In response to determining that a number of the portion of the first subset of the one or more data units satisfies the threshold criterion after the second ECC decoding operation has been performed, performing a second redundant error correction decoding operation to correct another portion of the one or more data units stored in the stripe across the multiple memory devices.

20. The non-transitory computer-readable storage medium of claim 19, wherein the instructions cause the processing device to perform operations comprising: performing a third ECC decoding operation on the one or more data units after performing the second redundancy error correction decoding operation; After the third ECC decoding operation has been performed, determining that a second portion of the first subset of the one or more data units for which the third ECC decoding operation was unsuccessful does not satisfy the threshold criterion; and A redundant reconstruction operation is performed to reconstruct corresponding data stored at the second portion of the first subset of the one or more data units, the corresponding data including other portions of the data having one or more errors that are uncorrectable by the third ECC decoding operation.

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