Topology calculation method and device for electric power error prevention, medium and program product

Abstract

The invention provides a topology calculation method and device for electric power error prevention, a medium and a program product. The method comprises the following steps: constructing an electrical topology network of a line; network topology calculation is carried out, network clock parameters are set to identify the time for executing each round of network topology calculation, in one round of network topology calculation, for each source in the electrical topology network, the source is used as a starting point, and according to the connectivity of elements in the electrical topology network, the network clock parameters are set to identify the time for executing each round of network topology calculation; traversing pins and / or contacts in the electrical topology network, and transmitting a potential value corresponding to the source and a network clock parameter value corresponding to the current round; the current round of network topology calculation is finished, and a grounding island, a power island and a suspended island of the electrical topology network are obtained; in the same round of network topology calculation, when the grounding island and the power island are intersected, the electrical topology network is abnormal. By means of the technical scheme, rapid calculation can be conducted according to the electrical topology network, and electrical conflict detection is achieved.

Description

Technical Field

[0001] The present invention relates to the field of power system error prevention, and in particular to a topology calculation method, device, medium and program product for power error prevention. Background Art

[0002] In the power system, misoperation accidents can cause serious consequences, seriously threatening the safety of the power grid, personnel and equipment, and seriously affecting the safe and stable operation of the power system. At present, the power error prevention system generally uses logical expressions to describe the error prevention rules. The error prevention rules described by logical expressions must cover all equipment in the plant, which is a huge amount of work for large plants. Moreover, manual review and verification of logical expressions are prone to errors. In addition, the error prevention rules for adding and deleting equipment require professionals to rewrite and review, which also brings a huge workload to engineers. Summary of the invention

[0003] In view of the above problems in the prior art, an embodiment of the present invention provides a topology calculation method for preventing power errors, which can realize electrical conflict detection through fast calculation.

[0004] In order to achieve the above object, on the one hand, a topology calculation method for preventing power errors is provided, comprising:

[0005] The electrical topology network of the circuit is constructed by one-to-one correspondence between the elements in the electrical topology network and the real devices in the circuit, wherein the elements in the electrical topology network include: a source, a wire and a switch; the source includes: a voltage source and a ground source; wherein in the electrical topology network, the elements are connected to each other through pins, and multiple pins are connected through contacts, one pin points to one contact, and one contact points to multiple pins;

[0006] Performing network topology calculation for the electrical topology network, setting network clock parameters to identify the time of executing each round of network topology calculation, wherein in one round of network topology calculation, for each source in the electrical topology network, taking the source as the starting point, traversing the pins and / or contacts in the electrical topology network according to the connectivity of the elements in the electrical topology network, transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round;

[0007] When the network clock parameter values ​​corresponding to the current round are transmitted once in all sources of the electrical topology network, the network topology calculation of the current round is completed, and the grounding island, power island and suspended island of the electrical topology network are obtained, wherein the grounding island is a set of nodes to which the potential value of the grounding source is transmitted when the grounding source is used as the starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is used as the starting point; the suspended island is a set of nodes whose network clock parameter values ​​are less than the network clock parameter values ​​corresponding to the current round;

[0008] In the same round of network topology calculation, when the ground island and the power island intersect, the electrical topology network is abnormal.

[0009] Preferably, in the topology calculation method, the initial value of the network clock parameter is 0.

[0010] Preferably, in the topology calculation method, after each round of network topology calculation, the value of the network clock parameter is automatically incremented.

[0011] Preferably, the topology calculation method, before traversing the pins and / or contacts in the electrical topology network and transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round, further comprises:

[0012] For the currently traversed pin and / or contact, determine whether the value of the network clock parameter currently corresponding to the currently traversed pin and / or contact is less than the network clock parameter value corresponding to the current round; if so, transfer the network clock parameter value corresponding to the current round to the currently traversed pin and / or contact; otherwise, stop transferring the network clock parameter value corresponding to the current round to the currently traversed pin and / or contact.

[0013] Preferably, in the topology calculation method, the network clock parameter value of a pin or a contact in the electrical topology network identifies the round of network topology calculation in which the pin or the contact participates.

[0014] Preferably, in the topology calculation method, in the same round of network topology calculation, when there is no intersection between the ground island and the power island, the electrical topology network is normal.

[0015] On the other hand, a topology calculation device for power error prevention is provided, comprising a memory and a processor, wherein the memory stores at least one program, and the at least one program is executed by the processor to implement the steps of any of the topology calculation methods described above.

[0016] On the other hand, a computer-readable storage medium is provided, wherein at least one program is stored in the storage medium, and the at least one program is executed by a processor to implement the steps of any of the topology calculation methods described above.

[0017] In yet another aspect, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the topology calculation methods described above are implemented.

[0018] The above technical solution has the following technical effects:

[0019] The technical solution of the embodiment of the present invention constructs the electrical topology network of the line by one-to-one correspondence between the elements in the electrical topology network and the actual devices in the line, which can achieve what you see is what you get and facilitate the judgment of actual line faults; in addition, the embodiment of the present invention sets the network clock parameter to identify the time of executing each round of network topology calculation in the network topology calculation, and passes the value of the network clock parameter in the topology calculation to determine the round in which the network element participates in the topology calculation, and judges whether the ground island and the power island intersect, that is, there is an intersection, according to the calculation results of the same round, if so, it is determined that the network is abnormal. The embodiment of the present invention realizes the verification of the anti-error rules by means of the electrical network topology; it provides a solution for the anti-error verification of general electrical connection scenarios by cleverly designing the devices and connection models of the participating electrical networks, and can perform rapid calculations based on the electrical topology network to realize electrical conflict detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a flow chart of a topology calculation method for preventing power errors according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a conductor as a network element in an electrical topology network;

[0022] Figure 3 The electrical topology network is a schematic diagram of a structure of a switch as a network element in a corresponding electrical topology network diagram;

[0023] Figure 4 The electrical topology network is a schematic diagram of a structure as a source of network elements in a corresponding electrical topology network diagram;

[0024] Figure 5 This is an example of a typical electrical topology network;

[0025] Figure 6 is a schematic diagram of the structure of an exemplary electrical topology network model;

[0026] Figure 7A schematic diagram of a process of performing topology calculation on an electrical topology network in one embodiment;

[0027] Figure 8 is an exemplary electrical topology network. DETAILED DESCRIPTION

[0028] To further illustrate the various embodiments, the present invention provides drawings. These drawings are part of the disclosure of the present invention, which are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, a person of ordinary skill in the art should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0029] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0030] Embodiment 1:

[0031] Figure 1 FIG. 1 is a flow chart of a topology calculation method for preventing power errors according to an embodiment of the present invention. Figure 1 The topology calculation method for preventing power errors in this embodiment includes the following steps:

[0032] The electrical topology network of the circuit is constructed by one-to-one correspondence between the elements in the electrical topology network and the real devices in the circuit. The elements in the electrical topology network include: sources, wires and switches; the sources include: voltage sources and ground sources; wherein, in the electrical topology network, the elements are connected to each other through pins, and multiple pins are connected through contacts, one pin points to one contact, and one contact points to multiple pins;

[0033] A network topology calculation is performed for an electrical topology network, and a network clock parameter is set to identify the time of executing each round of network topology calculation, wherein in a round of network topology calculation, for each source in the electrical topology network, the source is used as a starting point, and according to the connectivity of the components in the electrical topology network, the pins and / or contacts in the electrical topology network are traversed to transfer the potential value corresponding to the source and the network clock parameter value corresponding to the current round; in a specific implementation, the initial value of the network clock parameter is 0, and when the first round of network topology calculation is started, the value of the network clock parameter is 1; after each round of network topology calculation is completed, the value of the network clock parameter is incremented;

[0034] When the network clock parameter values ​​corresponding to the current round are transmitted once in all sources of the electrical topology network, the network topology calculation of the current round is completed, and the ground island, power island and suspended island of the electrical topology network are obtained, wherein the ground island is a set of nodes to which the potential value of the ground source is transmitted when the ground source is used as the starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is used as the starting point; the suspended island is a set of nodes whose network clock parameter values ​​are less than the network clock parameter values ​​corresponding to the current round; wherein the network clock parameter values ​​corresponding to the ground island and the power island are equal to the network clock parameter values ​​corresponding to the current round; the above nodes include: pins and / or contacts;

[0035] In the same round of network topology calculation, when the ground island and the power island intersect, the electrical topology network is abnormal.

[0036] Preferably, in the same round of network topology calculation, when there is no intersection between the ground island and the power island, the electrical topology network is normal.

[0037] In a specific implementation, further, the potential value of the node belonging to the ground island is 0; the potential value of the node belonging to the power island is equal to the potential value of the voltage source as the starting point.

[0038] Embodiment 2:

[0039] The following is a detailed description of a specific implementation of the composition and construction of an electrical topology network and network topology calculation in a topology calculation method for preventing power errors according to an embodiment of the present invention.

[0040] 1. Definitions of concepts related to the electrical topology network constructed in the embodiments of the present invention:

[0041] 1.1 Cell

[0042] Components are the basic components of electrical networks. The interconnection of components forms an electrical network. Components contain functions, operations, and pins. The function determines the operation of the component in the network, processes the input of the pin and inputs the result to a specific pin; the operation represents the additional functions supported, such as the opening / closing of a switch; and the pin is the port for the component to perform input and output.

[0043] 1.2 Pin

[0044] Pins are the basic components of components. The electrical quantity of components is input and output through pins, which are used to drive the function of components.

[0045] 1.3Joint

[0046] A contact represents the interconnection relationship between pins and is a collection of pins.

[0047] 1.4 Graph

[0048] The collection of components is interconnected through pins to form a diagram, that is, an electrical network topology diagram corresponding to the electrical topology network of the circuit.

[0049] 2. Electrical components and networks

[0050] 2.1 Wire

[0051] The elements of the electrical topology network constructed in the embodiment of the present invention include: wires. Figure 2 It is a schematic diagram of the structure of the wires used as network elements in the electrical topology network. Figure 2 , in the electrical topology network, the wire contains two pins; the function of this component is to pass the input of one pin to another pin; there is no other operation.

[0052] 2.2 Switch

[0053] The elements of the electrical topology network constructed in the embodiment of the present invention include: switches. Figure 3 It is a schematic diagram of the structure of the switch as a network element in the electrical topology network, that is, the corresponding electrical topology network diagram. Figure 3 In an electrical topology network, a switch comprises two pins; the function of the component is to transfer the input of one pin to another pin according to the switch state; it has two operations, an on operation and a off operation.

[0054] 2.3 Source

[0055] The elements of the electrical topology network constructed in the embodiment of the present invention include: a source, wherein the source includes: a ground or a voltage source. Figure 4 It is a schematic diagram of the structure of the electrical topology network as the source of the network element in the corresponding electrical topology network diagram. Figure 4 , the source contains one pin; the function of this component is to generate an output voltage and has no other operations. Among them, a ground source is a source with a zero output voltage, and a voltage source is a source with a non-zero output voltage. The source is the starting point for network topology calculations.

[0056] The topological network of the prior art is obtained by abstracting the lines. Usually, the wires are treated as equipotential points and do not appear as components in the topological network. The prior art also omits the source when performing network calculations and directly calculates on the network. The topological calculation method of the embodiment of the present invention uses the source for calculations.

[0057] 2.4 Electrical topology network

[0058] An electrical network, i.e., an electrical topology network, is a diagram consisting of electrical components and their connections. In a preferred embodiment of the present invention, the constructed electrical topology network only includes: a source, a conductor, and a switch. In an embodiment of the present invention, an electrical network includes: a voltage source, which serves as an incoming line; a ground source; and at least one other component, such as a conductor or a switch. Figure 5 This is an example of a typical electrical topology network.

[0059] 3. Construction and calculation of electrical topology network

[0060] 3.1 Construction of electrical topology network

[0061] In an electrical topology network, components are connected to each other through pins, and multiple pins are connected through contacts. One pin points to one contact, and one contact points to multiple pins. Figure 6 It is a structural diagram of an exemplary electrical topology network model.

[0062] like Figure 6 Compared with the topological network constructed by the prior art, the electrical topological network constructed by the embodiment of the present invention has different connection modes for the pins in the electrical topological network constructed by the embodiment of the present invention; the electrical topological network in the embodiment of the present invention directly constructs the topological network on the components, while the prior art generally constructs the topological network through a linked list, abstracting the electrical circuits before constructing the topological network; the embodiment of the present invention defines the components in the electrical topological network first, so that the components correspond to the real devices, constructs the entire electrical topological network through the connection of the real devices, and performs topological calculations on the entire electrical topological network. In the embodiment of the present invention, the electrical topological network and the real devices are in a one-to-one correspondence, and what you see is what you get. The topological network construction of the prior art is to abstract first and then construct, which will cause the problem that many connection features of the real devices are gone. For example, if a wire connects multiple devices, after abstraction in the prior art, the wire will disappear in the electrical topological network, while the electrical topological network construction method of the embodiment of the present invention is used, and the wire as a kind of component still exists in the electrical topological network.

[0063] 3.2 Topology calculation using the electrical topology network constructed by the embodiment of the present invention

[0064] In order to perform fast network topology calculations, an embodiment of the present invention defines a network clock parameter as an auxiliary parameter for calculation when performing topology calculations on an electrical network. In a specific implementation, a variable tick is used to represent the network clock parameter. The network clock parameter is used to identify the moment when the electrical topology network performs the current round of network topology calculations, which is equivalent to the role of a network clock. It is assigned a value during calculations, and its value corresponds to the moment when the current round of calculations is performed, that is, it corresponds to the current round. Preferably, the initial value of tick is zero. The value of tick increases with the round of network topology calculations; preferably, tick is taken at the beginning of each round of calculations, and the tick value is incremented by 1 each time the electrical topology network completes a round of network topology calculations.

[0065] In a round of topology calculation of an electrical topology network, starting from a source such as a voltage source as a starting point, according to the connectivity of the components in the electrical topology network, the electrical quantities at the starting point such as the potential value and the value of the network clock parameter tick corresponding to the current round of calculation are transmitted in the entire electrical topology network and transmitted to each node in the network; after all sources are calculated, that is, when the value of the network clock parameter tick corresponding to the current round of calculation is transmitted to all sources, the network topology calculation of this round is completed.

[0066] Figure 7 FIG. 1 is a schematic diagram of a process for performing topology calculation on an electrical topology network in an embodiment. Figure 7 , the topology calculation of this embodiment includes the following steps:

[0067] 701, taking a source to start calculation; the source may be any source in the electrical topology network, such as a voltage source;

[0068] 702, obtaining a tick value, the tick value corresponding to the moment of the current round of calculation is the tick value corresponding to the current round of calculation, and the tick value is used as the tick value of the source; illustratively, if the initial value of the tick value is 0, the calculation is the first round of calculation, and tick=1;

[0069] 703, according to the connectivity of the elements in the network, the value of the source, that is, the potential value or the voltage value and the tick value thereof, is transmitted, specifically, outputted through a pin;

[0070] 704, determine whether there is a contact point; if so, proceed to step 705; otherwise, execute step 708, end the calculation of the current source, and continue to execute step 709 to determine whether there are other sources; if there are other sources, proceed to step 701; otherwise, end the current round of calculation process;

[0071] 705, input the potential value and tick value into the corresponding component through the contact point of the pin for processing;

[0072] Since there may be loops in the electrical topology network, such as when the input and output of a component are connected, the topology calculation may enter an infinite loop. To avoid the topology calculation from entering an infinite loop, when the corresponding potential value and tick value are transmitted to the corresponding pin or contact, step 706 is first executed to determine whether the current tick value of the corresponding pin or contact is valid. For example, the validity is determined by determining whether the current tick value of the corresponding pin or contact is less than the current tick value to be transmitted. If it is less than, it is determined that the current tick value of the corresponding pin or contact is valid, and the path corresponding to the corresponding pin or contact has not been calculated. Step 707 is executed to continue. The current topology calculation processes the input potential value and tick value through the components corresponding to the corresponding pins or contacts, and outputs them to other connected pins, and then goes to step 703; otherwise, it means that there is a problem with the current network, and the current tick value of the corresponding pin or contact is invalid, and the current topology calculation process ends; wherein, if the current tick value of the corresponding pin or contact is equal to the tick value to be transmitted, it means that the tick value to be transmitted has passed through the path corresponding to the corresponding pin or contact, which means that the node corresponding to the corresponding pin or contact has been subjected to the current round of topology calculation. In the specific implementation, for each contact in the network, a corresponding variable is used to store the tick value corresponding to each node such as a pin or contact; this value is updated to the tick value transmitted in the current round of calculation with each round of calculation.

[0073] After completing a round of network topology calculation, the electrical topology network is divided into at most three complementary and intersecting parts: ground island, power island and / or suspended island. Among them, the suspended island can be empty, that is, there is no node belonging to the suspended island. Among them, the ground island is a set of all nodes transferred to the network topology calculation starting from the ground source; the potential value of all nodes in the ground island is 0, and the tick value is equal to the tick value corresponding to the current round of calculation. The power island is a set of all nodes transferred to the network topology calculation starting from the voltage source; the potential value of all nodes in the voltage island is equal to the voltage value of the starting voltage source, and the tick value is equal to the tick value corresponding to the current round of calculation. The elements contained in the suspended island are all nodes whose tick values ​​are less than the tick values ​​of the nodes in the power island or the ground island.

[0074] In a specific implementation, it is possible to determine which components are not currently in a working state based on the nodes included in the suspended island.

[0075] Figure 8 is an exemplary electrical topology network. Figure 8 , the exemplary electrical topology network includes a 220V voltage source, 2 switches and a ground source. Figure 8 When both switches in are disconnected, the topology calculation method according to the embodiment of the present invention is used for Figure 8 The electrical topology network shown is calculated including:

[0076] When the first round of calculation is started with the 220V voltage source as the starting point, the tick value of the voltage source is 1, and the voltage value of 220V and the tick value of the voltage source 1 are transmitted to the first pin of the first switch, that is, the result obtained by the calculation of the first pin of the first switch corresponds to (value: 220, tick: 1) in the figure; since the first switch and the second switch are both in the open state, the potential value 220V and the tick value 1 of the voltage source are only transmitted to the first pin 801 of the first switch, and the calculation for the voltage source is completed; then the topological calculation starting with the ground source in this round of calculation is performed, and the tick value corresponding to the calculation in this round is 1, so the 0V potential value and the tick value 1 are transmitted from the ground source, and since the first switch and the second switch are both in the open state, the potential value 0V and the tick value 1 of the ground source are only transmitted to the first pin 802 of the second switch, and the calculation for the ground source is completed; since the network only contains two sources, so at this point, the tick value 1 has been transmitted to all sources, and the calculation of this round is completed. As a result, the power island only contains the first pin of the first switch; the ground island only contains the second pin of the second switch, and the tick values ​​of other pins and nodes are 0, which is less than 1, and they all belong to floating islands. Since the power island and the ground island have no intersection, the electrical topology network meets the error prevention rules and the network is normal.

[0077] For this electrical topology network, at most one of the two switches can be closed. If both are closed, there is a short circuit and a fault. Using the topology calculation method of the embodiment of the present invention, if both switches are closed, the ground island and the voltage island have an intersection, and the network can be judged to be abnormal.

[0078] Embodiment three:

[0079] The present invention also provides a topology calculation device for power error prevention, which includes a processor, a memory, and a computer program stored in the memory and run on the processor. The processor includes one or more processing cores, and the memory is connected to the processor via a bus. The memory is used to store program instructions. When the processor executes the computer program, the steps in the above method embodiment of embodiment 1 of the present invention are implemented.

[0080] Further, as an executable solution, the topological calculation device for preventing power errors may be a computer unit, which may be a computing device such as a desktop computer, a notebook, a PDA, and a cloud server. The computer unit may include, but is not limited to, a processor and a memory. Those skilled in the art may understand that the composition structure of the above-mentioned computer unit is only an example of a computer unit and does not constitute a limitation on the computer unit, and may include more or less components than the above-mentioned, or a combination of certain components, or different components. For example, the computer unit may also include input and output devices, network access devices, buses, etc., which are not limited in the embodiments of the present invention.

[0081] Further, as an executable solution, the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the computer unit, and various interfaces and lines are used to connect the various parts of the entire computer unit.

[0082] The memory can be used to store the computer program and / or module, and the processor realizes various functions of the computer unit by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required for a function; the data storage area can store data created according to the use of the mobile phone, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0083] Embodiment 4:

[0084] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method in the embodiment of the present invention are implemented.

[0085] If the module / unit integrated in the computer unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory) and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction.

[0086] Embodiment five:

[0087] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the method described above are implemented.

[0088] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.

Claims

1. A topology calculation method for preventing power errors, characterized in that: include: The electrical topology network of the circuit is constructed by one-to-one correspondence between the elements in the electrical topology network and the real devices in the circuit, wherein the elements in the electrical topology network include: a source, a wire and a switch; the source includes: a voltage source and a ground source; wherein in the electrical topology network, the elements are connected to each other through pins, and multiple pins are connected through contacts, one pin points to one contact, and one contact points to multiple pins; Performing network topology calculation for the electrical topology network, setting network clock parameters to identify the time of executing each round of network topology calculation, wherein in one round of network topology calculation, for each source in the electrical topology network, taking the source as the starting point, traversing the pins and / or contacts in the electrical topology network according to the connectivity of the elements in the electrical topology network, transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round; When the network clock parameter values ​​corresponding to the current round are transmitted once in all sources of the electrical topology network, the network topology calculation of the current round is completed, and the grounding island, power island and suspended island of the electrical topology network are obtained, wherein the grounding island is a set of nodes to which the potential value of the grounding source is transmitted when the grounding source is used as the starting point; the power island is a set of nodes to which the potential value of the voltage source is transmitted when the voltage source is used as the starting point; the suspended island is a set of nodes whose network clock parameter values ​​are less than the network clock parameter values ​​corresponding to the current round; In the same round of network topology calculation, when the ground island and the power island intersect, the electrical topology network is abnormal.

2. The topology calculation method according to claim 1, characterized in that: The initial value of the network clock parameter is 0.

3. The topology calculation method according to claim 1, characterized in that: After each round of network topology calculation, the value of the network clock parameter is automatically incremented.

4. The topology calculation method according to claim 1, characterized in that: Before traversing the pins and / or contacts in the electrical topology network and transferring the potential value corresponding to the source and the network clock parameter value corresponding to the current round, the method further includes: For the currently traversed pin and / or contact, determine whether the value of the network clock parameter currently corresponding to the currently traversed pin and / or contact is less than the network clock parameter value corresponding to the current round; if so, transfer the network clock parameter value corresponding to the current round to the currently traversed pin and / or contact; otherwise, stop transferring the network clock parameter value corresponding to the current round to the currently traversed pin and / or contact.

5. The topology calculation method according to claim 1, characterized in that: The network clock parameter value of a pin or a contact in the electrical topology network identifies the round of network topology calculation in which the pin or the contact participates.

6. The topology calculation method according to claim 1, characterized in that: In the same round of network topology calculation, when there is no intersection between the ground island and the power island, the electrical topology network is normal.

7. A topology calculation device for preventing power errors, characterized in that: The method comprises a memory and a processor, wherein the memory stores at least one program, and the at least one program is executed by the processor to implement the steps of the topology calculation method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: The storage medium stores at least one program, and the at least one program is executed by a processor to implement the steps of the topology calculation method according to any one of claims 1 to 6.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the topology calculation method according to any one of claims 1 to 6 are implemented.

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