Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate, a gate metal wiring layer, an oxide layer, a shading layer, a source metal wiring layer and a drain metal wiring layer, the gate metal wiring layer is formed on one side of the substrate, and the oxide layer is formed on the side, away from the substrate, of the gate metal wiring layer. The shading layer, the source electrode metal wiring layer and the drain electrode metal wiring layer are formed on the side, away from the grid electrode metal wiring layer, of the oxide layer, and the shading layer is located between the source electrode metal wiring layer and the drain electrode metal wiring layer. According to the transistor, the shading layer is formed on the side, away from the gate insulating layer, of the oxide layer, damage to the oxide layer by etching, an external light source and the like is avoided through the shading layer, and meanwhile the preparation accuracy of the shading layer is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Oxide Thin Film Transistor (Oxide-TFT) has the advantages of high transmittance, high stability, low cost, etc. Low Temperature Polysilicon Thin Film Transistor (LTPS-TFT) has the advantages of high resolution, fast response, high brightness, high contrast, etc.

[0003] Low Temperature Polycrystalline Oxide (LTPO) circuits combine the advantages of LTPS-TFT and Oxide-TFT, which can ensure high pixel density (Pixel Per Inch, PPI), low power consumption and high image quality of display products. Therefore, they are often used in active matrix organic light-emitting diode (AMOLED) products. Summary of the invention

[0004] In view of the above defects or deficiencies in the prior art, it is desirable to provide an array substrate, a display panel and a display device, which can simultaneously form a light shielding layer, a source metal wiring layer and a drain metal wiring layer by one-time patterning of a mask on a side of the oxide layer away from the gate insulating layer. The light shielding layer can avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, and avoid direct irradiation of the oxide layer by an external light source, while ensuring the accuracy of the preparation of the light shielding layer.

[0005] In a first aspect, the present application provides an array substrate. The array substrate comprises a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer and a drain metal wiring layer, wherein the gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on a side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer and the drain metal wiring layer are formed on a side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer.

[0006] In combination with the first aspect, in a possible implementation, a length of the light shielding layer in a first direction is greater than a length of the oxide layer in the first direction; and the first direction is parallel to the substrate and perpendicular to an extension direction of the oxide layer.

[0007] In combination with the first aspect, in a possible implementation manner, in the first direction, a distance between an edge of the light shielding layer and an edge of the oxide layer is between 1-1.5 um.

[0008] In combination with the first aspect, in a possible implementation manner, there is a first gap between the light shielding layer and the source metal wiring layer, and there is a second gap between the light shielding layer and the drain metal wiring layer.

[0009] In combination with the first aspect, in a possible implementation manner, the gap widths of the first gap and the second gap are between 1-2 um.

[0010] In combination with the first aspect, in a possible implementation manner, the array substrate further includes a gate insulating layer, and the gate insulating layer is formed between the oxide layer and the light shielding layer.

[0011] In combination with the first aspect, in a possible implementation manner, the array substrate includes a connection hole, and the light shielding layer is connected to the gate metal wiring layer through the connection hole.

[0012] In combination with the first aspect, in a possible implementation manner, the oxide layer includes a channel region contacting the light shielding layer, and a non-channel region other than the channel region, and the non-channel region includes a conductive material.

[0013] In a second aspect, the present application further provides a display panel. The display panel comprises a planarization layer, an anode layer, a pixel definition layer, and the array substrate described in the first aspect, wherein the planarization layer is formed on a side of the substrate away from the array substrate, the anode layer is formed on a side of the planarization layer away from the array substrate, and the pixel definition layer is formed on a side of the anode layer away from the planarization layer.

[0014] In a third aspect, the present application further provides a display device, which includes the display panel as described in the second aspect.

[0015] The embodiment of the present application provides an array substrate, a display panel and a display device, wherein the array substrate includes a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer and a drain metal wiring layer, wherein the gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on the side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer and the drain metal wiring layer are formed on the side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer. The array substrate provided by the embodiment of the present application forms a light shielding layer on the side of the oxide layer away from the gate insulating layer, and the light shielding layer is used to avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, and to avoid direct irradiation of the oxide layer by an external light source, while ensuring the preparation accuracy of the light shielding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A schematic diagram of the stacked structure of a display panel in conventional technology; Figure 2 is a schematic diagram of a stacked structure of an array substrate in one embodiment; Figure 3 is a top view of an array substrate in one embodiment; Figure 4 is a cross-sectional schematic diagram of an array substrate in one embodiment; Figure 5 is a schematic diagram of another stacked structure of an array substrate in an embodiment; Figure 6 is another cross-sectional schematic diagram of an array substrate in one embodiment; Figure 7 is another top view of an array substrate in one embodiment; Figure 8 is a schematic diagram of a circuit structure of a display panel in one embodiment; Fig. 9 is a schematic diagram of a stacked structure of a display panel in one embodiment; Fig.10 A schematic diagram of a process flow of display panel in one embodiment; Fig.11 is a schematic diagram of another stacked structure of a display panel in one embodiment; Fig.12 FIG. 4 is another schematic diagram of a process flow of a display panel in an embodiment.

[0017] Description of reference numerals: 10 - substrate, 20 - gate metal wiring layer, 30 - oxide layer, 40 - light shielding layer, 50 - source metal wiring layer, 60 - drain metal wiring layer, 70 - gate insulation layer, 80 - connection hole. DETAILED DESCRIPTION

[0018] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone.

[0020] In the description of the present invention, it is necessary to understand that the terms "length", "width", "thickness", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0022] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0024] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0025] Low Temperature Polycrystalline Oxide (LTPO) circuits combine the advantages of Low Temperature Polysilicon Thin Film Transistor (LTPS-TFT) and oxide thin film transistor (Oxide-TFT), which can ensure high pixel density (Pixel Per Inch, PPI), low power consumption and high image quality of display products. Therefore, they are often used in active matrix organic light-emitting diode (AMOLED) products.

[0026] In virtual reality (VR) and augmented reality (AR) display devices with ultra-high pixel density, LTPO circuits often adopt a 3T1C design, which includes 3 transistors and 1 capacitor.

[0027] like Figure 1 As shown, a schematic diagram of the stacked structure of a display panel is provided. On the substrate PI, a source-drain metal wiring layer SD2 Data, a barrier layer Barrier, a bottom light shielding layer (Back Shield, BS), a buffer layer Buffer, a polysilicon layer polysilicon, a gate insulating layer GI1 (Gate Insulator, GI), a gate metal layer Gate1, a gate insulating layer GI2, a gate metal layer Gate2, a gate insulating layer GI3, an oxide layer Oxide, a source-drain metal wiring layer SD1, a passivation layer PVX1 (Passivation, PVX), a source-drain metal wiring layer SD3, a planarization layer (Planarization, PLN), a passivation layer PVX2, an anode layer AND and a pixel definition layer (Pixel Definition Layer, PDL) are sequentially formed.

[0028] Among them, the source and drain metal wiring layer SD2 Data, the barrier layer Barrier, the buffer layer Buffer, the polysilicon layer polysilicon, the gate insulating layer GI1 (Gate Insulator, GI), and the gate metal layer Gate1 constitute an LTPS-TFT, namely M1 in the figure. The gate metal layer Gate1, the gate insulating layer GI2, the gate metal layer Gate2, the gate insulating layer GI3, the oxide layer Oxide, and the source and drain metal wiring layer SD1 constitute an Oxide-TFT, namely M2 in the figure. The bottom light shielding layer (Back Shield, BS), the buffer layer Buffer, the polysilicon layer polysilicon, the gate insulating layer GI1 (Gate Insulator, GI), and the gate metal layer Gate1 constitute an LTPS-TFT, namely M3 in the figure. The gate metal layer Gate1, the gate insulating layer GI2, the gate metal layer Gate2, the gate insulating layer GI3, and the source and drain metal wiring layer SD1 constitute a capacitor Cst. N1 is the contact between M1, M3 and Cst, and N2 is the contact between M2, M3 and Cst.

[0029] SD3 is an end of SD1 and is used to be connected to an external compensation circuit SENS.

[0030] However, the oxide layer of oxide-TFT is easily damaged during the preparation and use process. For example, when etching to form the source metal wiring layer and the drain metal wiring layer, the etching process is likely to damage the oxide layer of oxide-TFT; when PVX is deposited, the presence of metal substances can easily cause the oxide layer to become conductive, affecting the performance of the oxide layer; during the use of oxide-TFT, external light sources can also easily affect the performance of the oxide layer, thereby affecting the stability of oxide-TFT. This will then affect the function of the display device using oxide-TFT.

[0031] Therefore, an embodiment of the present application provides an array substrate, which uses a light shielding layer to avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, and prevents an external light source from directly irradiating the oxide layer.

[0032] like Figure 2As shown, an embodiment of the present application provides an array substrate, which includes a substrate 10, a gate metal wiring layer 20, an oxide layer 30, a shading layer 40, a source metal wiring layer 50 and a drain metal wiring layer 60, the gate metal wiring layer 20 is formed on one side of the substrate 10, the oxide layer 30 is formed on the side of the gate metal wiring layer 20 away from the substrate 10, the shading layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60 are formed on the side of the oxide layer 30 away from the gate metal wiring layer 20, and the shading layer 40 is located between the source metal wiring layer 50 and the drain metal wiring layer 60.

[0033] The light shielding layer 40 , the source metal wiring layer 50 and the drain metal wiring layer 60 are formed by one patterning. The gate metal wiring layer 20 , the oxide layer 30 , the source metal wiring layer 50 and the drain metal wiring layer 60 form an oxide thin film transistor.

[0034] In the embodiment of the present application, a light-shielding layer 40 can be formed by using a light-proof material on the side of the oxide layer 30 away from the substrate 10. The light-shielding layer 40 can be metal or non-metal, as long as the light-shielding layer 40 is not transparent. For example, it can be metal titanium, aluminum, copper, etc., or non-metal a-Si.

[0035] Since the light shielding layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60 are all overlapped with the oxide layer, the light shielding layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60 can be formed by patterning at one time through the same mask Mask, so that the light shielding layer 40 is located in the middle area of ​​the side of the oxide layer 30 away from the substrate 10, and the source metal wiring layer 50 and the drain metal wiring layer 60 are respectively located on both sides of the light shielding layer 40, that is, they are overlapped with the edge area of ​​the side of the oxide layer 30 away from the substrate 10. One-time patterning can avoid problems such as short circuit caused by contact between the light shielding layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60, and at the same time ensure the accuracy of the positions of the three relative to the oxide layer, avoid the position deviation of any functional layer, and thus ensure the performance of the transistor. At the same time, retaining the light shielding layer 40 on the oxide layer 30 can avoid etching damage to the channel region of the oxide layer 30 when forming the source metal wiring layer 50 and the drain metal wiring layer 60; and prevent external light sources from directly irradiating the oxide layer and affecting the performance of the oxide layer.

[0036] In a possible implementation, the light shielding layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60 can be made of the same material, for example, the same metal. Therefore, during the preparation process, a metal layer is directly formed on the side of the oxide layer 30 away from the substrate 10, and then the metal layer is etched using a mask to simultaneously form the light shielding layer 40, the source metal wiring layer 50 and the drain metal wiring layer 60, thereby simplifying the process flow and improving the preparation efficiency of the array substrate.

[0037] It is understandable that a gate insulating layer GI may be disposed between the gate metal wiring layer 20 and the oxide layer 30 to prevent the gate metal wiring layer 20 from affecting the performance of the oxide layer 30 .

[0038] A passivation layer PVX can be formed on the side of the source metal wiring layer 50 and the drain metal wiring layer 60 away from the substrate 10 to isolate the external corrosive medium (water vapor, etc.) and the internal structure of the array substrate, and prevent water vapor from entering the transistor, especially the oxide layer, to avoid affecting the performance of the transistor. However, the passivation layer covering the oxide layer 30 easily leads to the conductorization of the oxide layer 30. In the present application, the light shielding layer 40 can achieve the isolation between the passivation layer and the oxide layer 30 to avoid the conductorization of the oxide layer 30.

[0039] In summary, in the preparation process of the array substrate in the embodiment of the present application, a substrate 10 is first formed, and then a gate metal wiring layer 20 is formed on one side of the substrate 10, a gate insulating layer is formed on the side of the gate metal wiring layer 20 away from the substrate 10, an oxide layer 30 is formed on the side of the gate insulating layer away from the gate metal wiring layer 20, and a layer of material is formed on the side of the oxide layer 30 away from the gate insulating layer, and a mask is used for one-time patterning to form a light shielding layer 40, a source metal wiring layer 50, and a drain metal wiring layer 60. Among them, the light shielding layer 40 is located between the source metal wiring layer 50 and the drain metal wiring layer 60.

[0040] The substrate 10 may be made of materials such as polyimide (PI); and the oxide layer 30 may be made of indium gallium zinc oxide (IGZO).

[0041] The array substrate provided in the embodiment of the present application includes a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer and a drain metal wiring layer, the gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on the side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer and the drain metal wiring layer are formed on the side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer. Among them, the light shielding layer, the source metal wiring layer and the drain metal wiring layer are formed by one patterning. The array substrate provided in the embodiment of the present application is formed by one patterning of Mask on the side of the oxide layer away from the gate insulating layer. The light shielding layer is used to avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, avoid direct irradiation of the oxide layer by an external light source, and ensure the preparation accuracy of the light shielding layer.

[0042] In one embodiment, Figure 3 , which is a top view of the stacked structure of the array substrate. The length of the light shielding layer 40 in the first direction is greater than the length of the oxide layer 30 in the first direction.

[0043] In the embodiment of the present application, in order to realize the light shielding layer 40 for the oxide layer 30, the area of ​​the oxide layer 30 exposed outside the source metal wiring layer 50 and the drain metal wiring layer 60 should be covered as much as possible. Therefore, in the first direction, both ends of the light shielding layer 40 should extend beyond the oxide layer 30, that is, the length of the light shielding layer 40 in the first direction is greater than the length of the oxide layer 30 in the first direction.

[0044] The first direction is parallel to the substrate and perpendicular to the extension direction of the oxide layer 30, that is, the AA' direction in the figure.

[0045] It is understandable that, under normal circumstances, the extension direction of the oxide layer 30 (ie, BB' direction in the figure) is perpendicular to the extension direction of the gate metal wiring layer 20 (ie, Bottom Gate in the figure). Therefore, the first direction can also be the extension direction of the gate metal wiring layer 20.

[0046] like Figure 4 , which is a schematic cross-sectional view in the first direction, in which the length of the light shielding layer 40 (ie, GLS) is greater than the length of the oxide layer 30 .

[0047] For either end of the light shielding layer, the distance of the light shielding layer 40 beyond the oxide layer 30 is within a certain range to avoid material loss. Preferably, in the first direction, the distance between the edge of the light shielding layer 40 and the edge of the oxide layer 30 is between 1-1.5um. That is, the range of parameter b in the figure is 1-1.5um.

[0048] In one embodiment, in order to prevent the light shielding layer 40 from contacting any one or both of the source metal wiring layer 50 and the drain metal wiring layer 60, which may cause a short circuit in the transistor, there should be a gap between the light shielding layer 40 and the source metal wiring layer 50 and the drain metal wiring layer 60. That is, there is a first gap between the light shielding layer 40 and the source metal wiring layer 50, and there is a second gap between the light shielding layer 40 and the drain metal wiring layer 60.

[0049] In the embodiment of the present application, the gap width of the first gap and the gap width of the second gap may be the same or different.

[0050] Preferably, the gap width of the first gap and the second gap is the same, which is represented by parameter a in the figure. The gap width should be within a certain range to avoid a larger gap width, so that the area of ​​the oxide layer 30 not covered by the light shielding layer 40 is larger, resulting in etching, external light sources, etc. affecting the performance of the oxide layer 30. At the same time, it should be avoided that the gap width is smaller, so that the area of ​​the oxide layer 30 covered by the light shielding layer 40 is larger, resulting in the sensitivity of the transistor being affected. Therefore, preferably, the gap width of the first gap and the second gap is between 1-2um. That is, the range of parameter a in the figure is 1-2um.

[0051] In a possible implementation, the oxide layer 30 includes a channel region contacting the light shielding layer 40 and a non-channel region other than the channel region, and the non-channel region includes a conductive material.

[0052] When the light shielding layer 40 is covered on the oxide layer 30, the area in contact with the light shielding layer 40 is the channel area, and the area other than the channel area is the non-channel area. The source metal wiring layer 50 and the drain metal wiring layer 60 are connected to the non-channel area of ​​the oxide layer 30. Conductive materials, such as ions, are injected into the non-channel area of ​​the oxide layer 30 to conduct the non-channel area, so as to achieve ohmic connection between the source metal wiring layer 50, the drain metal wiring layer 60 and the oxide layer 30, and ensure the normal function of the transistor.

[0053] In the array substrate provided by the embodiment of the present application, the length of the light shielding layer in the direction perpendicular to the extension direction of the oxide layer is greater than the length of the oxide layer, and there is a gap between the light shielding layer and the source metal wiring layer and the drain metal wiring layer. The embodiment of the present application limits the length relationship between the light shielding layer and the oxide layer to ensure the coverage of the oxide layer by the light shielding layer and avoid the influence of etching, external light sources, etc. on the oxide layer; at the same time, the distance between the light shielding layer and the source metal wiring layer and the drain metal wiring layer is limited to avoid short circuit problems while ensuring the functionality of the oxide layer.

[0054] The light shielding layer 40 described in the above embodiment is not energized and does not contact other metal layers, which is equivalent to a floating gate. In another embodiment of the present application, the light shielding layer 40 can be connected to the gate metal wiring layer 20, so that the transistor has better performance, such as a larger range of amplification, stronger anti-interference ability, etc. In this case, since the light shielding layer 40 is conductive, Figure 5 As shown, the array substrate further includes a gate insulating layer 70 , and the gate insulating layer 70 is formed between the oxide layer 30 and the light shielding layer 40 .

[0055] When the light shielding layer 40 is conductive, the light shielding layer 40 and the oxide layer 30 are isolated by the gate insulating layer 70 to prevent the oxide layer 30 from being conductive.

[0056] like Figure 6 As shown, it is a cross-sectional schematic diagram of the stacked structure of the array substrate, the light shielding layer 40 is connected to the gate metal wiring layer 20 through a via hole, that is, the array substrate includes a connection hole 80, and the light shielding layer 40 is connected to the gate metal wiring layer 20 through the connection hole 80.

[0057] It can be understood that the light shielding layer 40 avoids the oxide layer 30 and is connected to the gate metal wiring layer 20. Figure 7 As shown, it is a top view of the stacked structure of the array substrate. In the first direction, one end of the light shielding layer 40 is connected to the gate metal wiring layer 20 through the connection hole 80, and the distance between the end and the oxide layer 20 is greater than the diameter of the connection hole 80. The other end also exceeds the edge of the oxide layer 20, and the distance between the end and the edge of the oxide layer 20 can be between 1-1.5um.

[0058] In the array substrate provided in the embodiment of the present application, the light shielding layer can be connected to the gate metal wiring layer through the connecting hole, so that the light shielding layer is energized and thus functional, thereby improving the performance of the array substrate while avoiding the influence of etching, external light sources, etc. on the oxide layer.

[0059] In one embodiment, a display panel is provided, which includes a planarization layer PLN, an anode layer AND, a pixel definition layer PDL, and the array substrate described in the above embodiment, wherein the planarization layer is formed on a side of the base away from the array substrate, the anode layer is formed on a side of the planarization layer away from the array substrate, and the pixel definition layer is formed on a side of the anode layer away from the planarization layer.

[0060] In a possible implementation, a passivation layer may be formed between the planarization layer PLN and the anode layer AND.

[0061] like Figure 8As shown in FIG. 1 , it is a schematic diagram of the circuit structure corresponding to the display panel. The working process of the circuit includes three stages, T1 reset stage, T2 compensation stage and T3 light-emitting stage. Among them, M1 and M3 are LTPS-TFT, M2 is Oxide-TFT, Cst is a capacitor, Data is a data signal, Gate is a gate drive signal, and SENS is an external compensation circuit. Among them, M3 is the driving transistor of the pixel circuit.

[0062] During the operation of the circuit, the change of the gate-source voltage Vgs of M3 will cause the current I passing through the OLED to change, thereby affecting the uniformity of the brightness of the OLED and further affecting the display uniformity of the display panel. Therefore, in the reset stage T1, M2 is turned on, M1 and M3 are turned off, and the capacitor Cst is discharged so that the voltage of the capacitor Cst reaches the reset voltage Vint.

[0063] In the T2 compensation stage, first turn on M1, turn off M2, write the data voltage Vdata into the N1 point, and charge the capacitor Cst; then turn off M1, turn on M2, and SENS determines the voltage of the N2 point as Vdata-Vth based on Vdata through the FPGA algorithm, and performs voltage compensation on the N2 point based on the determined voltage, so that the voltage difference between the voltages of the N1 point and the N2 point reaches Vth, that is, the gate-source voltage of M3 reaches Vth (the threshold voltage of M3 conduction) before the OLED emits light, and M3 is in the critical state of the on state. This can avoid the influence of the M3 on the current during the T3 light-emitting stage, avoid the brightness change of the OLED, and ensure the display uniformity of the display panel.

[0064] In the light-emitting stage T3, since the data voltage Vdata has been written into the gate of M3 in the compensation stage T2, M3 is turned on. Therefore, VDD is input to M3 to light up the OLED.

[0065] like Fig. 9 , which is a schematic diagram of a stacked structure of a display panel, shows other devices besides the transistor M2 described in the above embodiment, for example, low-temperature polysilicon transistors M1 and M3, a capacitor Cst, etc.

[0066] A source-drain metal wiring layer 11 (SD2 Data), a barrier layer 12 (Barrier), a bottom light shielding layer 13 (BS), a buffer layer 14 (Buffer1), a polysilicon layer 15 (poly), a gate insulating layer 16 (GI1), a gate metal wiring layer 20 (Gate1), a gate insulating layer 21 (GI2), a gate metal wiring layer 22 (Gate2), a gate insulating layer 23 (GI3), an oxide layer 30 (Oxide), a light shielding layer 40, a source-drain metal wiring layer 51 (SD1), a source metal wiring layer 50, a drain metal wiring layer 60, a passivation layer 61 (PVX1), a source-drain metal wiring layer 62 (SD3), a planarization layer 63 (PLN), a passivation layer 64 (PVX2), an anode layer 65 (AND) and a pixel definition layer 66 (PDL) are sequentially formed on the substrate 10.

[0067] Among them, the source and drain metal wiring layer 11 (SD2 Data), the barrier layer 12 (Barrier), the buffer layer 14 (Buffer1), the polysilicon layer 15 (poly), the gate insulation layer 16 (GI1), and the gate metal wiring layer 20 (Gate1) constitute M1. The gate metal wiring layer 20 (Gate1), the gate insulation layer 21 (GI2), the gate metal wiring layer 22 (Gate2), the gate insulation layer GI3, the oxide layer Oxide, and the source and drain metal wiring layer SD1 constitute Oxide-TFT, that is, M2 in the figure. The bottom light shielding layer 13 (BS), the buffer layer 14 (Buffer1), the polysilicon layer 15 (poly), the gate insulation layer 16 (GI1), and the gate metal wiring layer 20 (Gate1) constitute M3. The gate metal wiring layer 20 (Gate1), the gate insulating layer 21 (GI2), the gate metal wiring layer 22 (Gate2), the gate insulating layer 23 (GI3), and the source-drain metal wiring layer 51 (SD1) form a capacitor Cst.

[0068] The source-drain metal wiring layer 62 (SD3) is the end of the drain metal wiring layer 60 and is used to connect to the external compensation circuit SENS.

[0069] Fig. 9 In the oxide transistor in the display panel, a light shielding layer G-LS is formed on the side of the oxide layer away from the substrate, and the light shielding layer G-LS can be metal or non-metal, as long as the light shielding layer G-LS is opaque. For example, it can be metal titanium, aluminum, copper, etc., or non-metal a-Si.

[0070] Since the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D are all overlapped with the oxide layer, the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D can be formed by patterning at one time through the same mask Mask, so that the light shielding layer G-LS is located in the middle area of ​​the oxide layer Oxide away from the substrate side, and the source metal wiring layer S and the drain metal wiring layer D are respectively located on both sides of the light shielding layer G-LS, that is, they are overlapped with the edge area of ​​the oxide layer 30 away from the substrate side. One-time patterning can avoid problems such as short circuit caused by contact between the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D, and at the same time ensure the accuracy of the positions of the three relative to the oxide layer, avoid the position deviation of any functional layer, and thus ensure the performance of the transistor. At the same time, retaining the light shielding layer G-LS on the oxide layer can avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer S and the drain metal wiring layer D; and avoid external light sources directly irradiating the oxide layer and affecting the performance of the oxide layer.

[0071] In a possible implementation, the light shielding layer G-LS, the source metal wiring layer S, and the drain metal wiring layer D can be made of the same material, for example, the same metal. Therefore, during the preparation process, a metal layer is directly formed on the side of the oxide layer Oxide away from the substrate, and then the metal layer is etched using a mask to simultaneously form the light shielding layer G-LS, the source metal wiring layer S, and the drain metal wiring layer D, thereby simplifying the process flow and improving the preparation efficiency of the array substrate.

[0072] It can be understood that a gate insulating layer GI may be disposed between the gate metal wiring layer Gate1 and the oxide layer Oxide to prevent the gate metal wiring layer Gate1 from affecting the performance of the oxide layer Oxide.

[0073] A passivation layer PVX can be formed on the side of the source metal wiring layer S and the drain metal wiring layer D away from the substrate to isolate the external corrosive medium (water vapor, etc.) and the internal structure of the array substrate, preventing water vapor from entering the transistor, especially the oxide layer, to avoid affecting the performance of the transistor. However, the passivation layer covering the oxide layer Oxide can easily lead to the conductorization of the oxide layer Oxide. In this application, the light shielding layer G-LS can achieve isolation between the passivation layer and the oxide layer Oxide to avoid the conductorization of the oxide layer Oxide.

[0074] In summary, during the preparation process of the display panel, Fig.10As shown, a substrate is first formed, and a source-drain metal wiring layer SD2 Data, a barrier layer Barrier, a bottom shading layer (Back Shield, BS), a buffer layer Buffer1, a polysilicon layer polysilicon, a gate insulating layer GI1 (Gate Insulator, GI), a gate metal layer Gate1, a gate insulating layer GI2, a gate metal layer Gate2, a gate insulating layer GI3, and an oxide layer Oxide are sequentially formed on one side of the substrate; then, a shading layer G-LS, a source metal wiring layer S, and a drain metal wiring layer D are formed by patterning at one time using a Mask; then, a passivation layer PVX1 (Passivation, PVX), a source-drain metal wiring layer SD3, a planarization layer PLN, a passivation layer PVX2, an anode layer AND, and a pixel definition layer PDL are sequentially formed on the side of the shading layer G-LS away from the oxide layer Oxide.

[0075] In another possible implementation, the shading layer G-LS is connected to the gate metal wiring layer Gate1. In this case, the shading layer G-LS can serve as another gate of the transistor. The transistor is a dual-gate transistor. When voltage is applied to the two gates, it can simultaneously affect the movement of charge carriers in the oxide layer, effectively increasing the on-state current value of the transistor, thereby improving the performance of the transistor.

[0076] In this case, since the light shielding layer G-LS is conductive, the array substrate further includes a gate insulating layer GI4, and the gate insulating layer GI4 is formed between the oxide layer Oxide and the light shielding layer G-LS.

[0077] When the light shielding layer G-LS is conductive, the light shielding layer G-LS and the oxide layer Oxide are isolated by the gate insulating layer GI4 to prevent the oxide layer Oxide from being conductive.

[0078] The light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through a via hole, that is, the array substrate includes a connection hole, and the light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through the connection hole.

[0079] It can be understood that the light shielding layer G-LS avoids the oxide layer Oxide and is connected to the gate metal wiring layer Gate1. In the first direction, one end of the light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through a connection hole, and the distance between the end and the oxide layer Gate1 is greater than the diameter of the connection hole. The other end also exceeds the edge of the oxide layer Gate1, and the distance between the end and the edge of the oxide layer Gate1 can be between 1-1.5um.

[0080] In the case where the light shielding layer G-LS is connected to the gate metal layer Gate1, the stacked structure of the display panel is as follows: Fig.11As shown in FIG. 1 , the preparation process of the display panel is as follows Fig.12 As shown: first, a substrate is formed, and on one side of the substrate, a source and drain metal wiring layer SD2 Data, a barrier layer Barrier, a bottom shading layer (Back Shield, BS), a buffer layer Buffer1, a polysilicon layer polysilicon, a gate insulating layer GI1 (Gate Insulator, GI), a gate metal layer Gate1, a gate insulating layer GI2, a gate metal layer Gate2, a gate insulating layer GI3, an oxide layer Oxide, and a gate insulating layer GI4 are formed in sequence; then, a shading layer G-LS, a source metal wiring layer S, and a drain metal wiring layer D are formed by patterning at one time using a Mask; then, a passivation layer PVX1 (Passivation, PVX), a source and drain metal wiring layer SD3, a planarization layer PLN, a passivation layer PVX2, an anode layer AND, and a pixel definition layer PDL are formed in sequence on the side of the shading layer G-LS away from the oxide layer Oxide.

[0081] The display panel provided in the embodiment of the present application includes a planarization layer, an anode layer, a pixel definition layer, and an array substrate. The planarization layer is formed on a side of the substrate away from the array substrate, the anode layer is formed on a side of the planarization layer away from the array substrate, and the pixel definition layer is formed on a side of the anode layer away from the planarization layer. The array substrate includes a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer, and a drain metal wiring layer. The gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on a side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are formed on a side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer. Among them, the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are formed by one-time patterning. In the display panel provided in the embodiment of the present application, the array substrate is on the side of the oxide layer away from the gate insulating layer, and the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are simultaneously formed by one-time patterning of Mask. The light shielding layer prevents etching damage to the channel region of the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, and prevents external light sources from directly irradiating the oxide layer, thereby ensuring the performance of the array substrate and thus ensuring the performance of the display panel.

[0082] In one embodiment, a display device is provided, the display device comprising the display panel described in the above embodiment. The display panel comprises a planarization layer PLN, an anode layer AND, a pixel definition layer PDL, and the array substrate described in the above embodiment, the planarization layer is formed on a side of the substrate away from the array substrate, the anode layer is formed on a side of the planarization layer away from the array substrate, and the pixel definition layer is formed on a side of the anode layer away from the planarization layer.

[0083] In a possible implementation, a passivation layer may be formed between the planarization layer PLN and the anode layer AND.

[0084] In the oxide transistor in the display panel, a light shielding layer G-LS is formed on the side of the oxide layer away from the substrate. The light shielding layer G-LS can be metal or non-metal, as long as the light shielding layer G-LS is opaque. For example, it can be metal titanium, aluminum, copper, etc., or non-metal a-Si.

[0085] Since the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D are all overlapped with the oxide layer, the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D can be formed by patterning at one time through the same mask Mask, so that the light shielding layer G-LS is located in the middle area of ​​the oxide layer Oxide away from the substrate side, and the source metal wiring layer S and the drain metal wiring layer D are respectively located on both sides of the light shielding layer G-LS, that is, they are overlapped with the edge area of ​​the oxide layer 30 away from the substrate side. One-time patterning can avoid problems such as short circuit caused by contact between the light shielding layer G-LS, the source metal wiring layer S and the drain metal wiring layer D, and at the same time ensure the accuracy of the positions of the three relative to the oxide layer, avoid the position deviation of any functional layer, and thus ensure the performance of the array substrate. At the same time, retaining the light shielding layer G-LS on the oxide layer can avoid etching damage to the channel region of the oxide layer when forming the source metal wiring layer S and the drain metal wiring layer D; and avoid external light sources directly irradiating the oxide layer and affecting the performance of the oxide layer.

[0086] In a possible implementation, the light shielding layer G-LS, the source metal wiring layer S, and the drain metal wiring layer D can be made of the same material, for example, the same metal. Therefore, during the preparation process, a metal layer is directly formed on the side of the oxide layer Oxide away from the substrate, and then the metal layer is etched using a mask to simultaneously form the light shielding layer G-LS, the source metal wiring layer S, and the drain metal wiring layer D, thereby simplifying the process flow and improving the preparation efficiency of the array substrate.

[0087] It can be understood that a gate insulating layer GI may be disposed between the gate metal wiring layer Gate1 and the oxide layer Oxide to prevent the gate metal wiring layer Gate1 from affecting the performance of the oxide layer Oxide.

[0088] A passivation layer PVX can be formed on the side of the source metal wiring layer S and the drain metal wiring layer D away from the substrate to isolate the external corrosive medium (water vapor, etc.) and the internal structure of the array substrate, preventing water vapor from entering the transistor, especially the oxide layer, to avoid affecting the performance of the transistor. However, the passivation layer covering the oxide layer Oxide can easily lead to the conductorization of the oxide layer Oxide. In this application, the light shielding layer G-LS can achieve isolation between the passivation layer and the oxide layer Oxide to avoid the conductorization of the oxide layer Oxide.

[0089] In summary, in the preparation process of the display panel, a substrate is first formed, and then a source and drain metal wiring layer SD2 Data, a barrier layer Barrier, a bottom shading layer (Back Shield, BS), a buffer layer Buffer1, a polysilicon layer polysilicon, a gate insulating layer GI1 (Gate Insulator, GI), a gate metal layer Gate1, a gate insulating layer GI2, a gate metal layer Gate2, a gate insulating layer GI3, and an oxide layer Oxide are formed in sequence on one side of the substrate; then, a shading layer G-LS, a source metal wiring layer S and a drain metal wiring layer D are patterned at one time using a Mask; then, a passivation layer PVX1 (Passivation, PVX), a source and drain metal wiring layer SD3, a planarization layer PLN, a passivation layer PVX2, an anode layer AND and a pixel definition layer PDL are formed in sequence on the side of the shading layer G-LS away from the oxide layer Oxide.

[0090] In another possible implementation, the light shielding layer G-LS is connected to the gate metal wiring layer Gate1, so that the array substrate has better performance, such as a larger range of amplification, stronger anti-interference ability, etc. In this case, since the light shielding layer G-LS is conductive, the array substrate also includes a gate insulating layer GI4, and the gate insulating layer GI4 is formed between the oxide layer Oxide and the light shielding layer G-LS.

[0091] When the light shielding layer G-LS is conductive, the light shielding layer G-LS and the oxide layer Oxide are isolated by the gate insulating layer GI4 to prevent the oxide layer Oxide from being conductive.

[0092] The light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through a via hole, that is, the array substrate includes a connection hole, and the light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through the connection hole.

[0093] It can be understood that the light shielding layer G-LS avoids the oxide layer Oxide and is connected to the gate metal wiring layer Gate1. In the first direction, one end of the light shielding layer G-LS is connected to the gate metal wiring layer Gate1 through a connection hole, and the distance between the end and the oxide layer Gate1 is greater than the diameter of the connection hole. The other end also exceeds the edge of the oxide layer Gate1, and the distance between the end and the edge of the oxide layer Gate1 can be between 1-1.5um.

[0094] In view of the situation that the light shielding layer G-LS is connected to the gate metal layer Gate1, the preparation process of the display panel is as follows: first, a substrate is formed, and on one side of the substrate, a source and drain metal wiring layer SD2 Data, a barrier layer Barrier, a bottom light shielding layer (Back Shield, BS), a buffer layer Buffer1, a polysilicon layer polysilicon, a gate insulating layer GI1 (GateInsulator, GI), a gate metal layer Gate1, a gate insulating layer GI2, a gate metal layer Gate2, a gate insulating layer GI3, an oxide layer Oxide, and a gate insulating layer GI4 are formed in sequence; then, a light shielding layer G-LS, a source metal wiring layer S, and a drain metal wiring layer D are patterned at one time by a Mask; then, a passivation layer PVX1 (Passivation, PVX), a source and drain metal wiring layer SD3, a planarization layer PLN, a passivation layer PVX2, an anode layer AND, and a pixel definition layer PDL are formed in sequence on the side of the light shielding layer G-LS away from the oxide layer Oxide.

[0095] The display device provided in the embodiment of the present application includes a display panel, the display panel includes a planarization layer, an anode layer, a pixel definition layer, and an array substrate, the planarization layer is formed on the side of the substrate away from the array substrate, the anode layer is formed on the side of the planarization layer away from the array substrate, and the pixel definition layer is formed on the side of the anode layer away from the planarization layer. The array substrate includes a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer, and a drain metal wiring layer, the gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on the side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are formed on the side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer. Wherein, the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are formed by one-time patterning. In the display panel provided in the embodiment of the present application, the array substrate is on the side of the oxide layer away from the gate insulating layer, and the light shielding layer, the source metal wiring layer, and the drain metal wiring layer are simultaneously formed by one-time patterning of Mask. The shading layer is used to avoid etching damage to the channel area of ​​the oxide layer when forming the source metal wiring layer and the drain metal wiring layer, to avoid direct irradiation of the oxide layer by external light sources, to avoid affecting the performance of the array substrate, thereby ensuring the performance of the display panel and thus ensuring the performance of the display device.

[0096] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes a substrate, a gate metal wiring layer, an oxide layer, a light shielding layer, a source metal wiring layer and a drain metal wiring layer, the gate metal wiring layer is formed on one side of the substrate, the oxide layer is formed on a side of the gate metal wiring layer away from the substrate, the light shielding layer, the source metal wiring layer and the drain metal wiring layer are formed on a side of the oxide layer away from the gate metal wiring layer, and the light shielding layer is located between the source metal wiring layer and the drain metal wiring layer.

2. The array substrate according to claim 1, characterized in that: The length of the light shielding layer in the first direction is greater than the length of the oxide layer in the first direction; the first direction is parallel to the substrate and perpendicular to the extension direction of the oxide layer.

3. The array substrate according to claim 2, characterized in that: In the first direction, the distance between the edge of the light shielding layer and the edge of the oxide layer is between 1-1.5 um.

4. The array substrate according to claim 1, characterized in that: There is a first gap between the light shielding layer and the source metal wiring layer, and there is a second gap between the light shielding layer and the drain metal wiring layer.

5. The array substrate according to claim 4, characterized in that: The gap width of the first gap and the second gap is between 1-2 um.

6. The array substrate according to claim 1, characterized in that: The transistor further includes a gate insulating layer formed between the oxide layer and the light shielding layer.

7. The array substrate according to claim 6, characterized in that: The transistor comprises a connection hole, and the light shielding layer is connected to the gate metal wiring layer through the connection hole.

8. The array substrate according to claim 1, characterized in that: The oxide layer includes a channel region contacting the light shielding layer, and a non-channel region except the channel region, wherein the non-channel region includes a conductive material.

9. A display panel, characterized in that: The display panel includes a planarization layer, an anode layer, a pixel definition layer, and an array substrate as described in any one of claims 1 to 8, wherein the planarization layer is formed on a side of a base away from the array substrate, the anode layer is formed on a side of the planarization layer away from the array substrate, and the pixel definition layer is formed on a side of the anode layer away from the planarization layer.

10. A display device, characterized in that: The display device comprises the display panel as claimed in claim 9.

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