Light emitting device

Abstract

The invention relates to a light emitting device, a method of manufacturing the light emitting device, and a display apparatus. The light emitting device may include: a substrate; the first electrode and the second electrode are arranged on the substrate; an insulating layer disposed on the substrate on which the first electrode and the second electrode are formed, and including a groove extending in a first direction intersecting the first electrode and the second electrode, and first and second contact portions configured to expose one region of the first electrode and one region of the second electrode; light emitting elements disposed in the recess between the first electrode and the second electrode, and each including a first end and a second end electrically connected to the first electrode and the second electrode; a first contact electrode electrically connected to the light emitting element on a first end and electrically connected to the first electrode on a first contact portion; and a second contact electrode electrically connected to the light emitting element on a second end and electrically connected to the second electrode on a second contact portion.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a light emitting device, a method of manufacturing the light emitting device, and a display apparatus having the light emitting device. Background Art

[0002] Recently, a technology for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and manufacturing light-emitting devices using the light-emitting elements has been developed. For example, a light-emitting device has been developed in which ultra-small light-emitting elements each having a micrometer-level or nanometer-level size are arranged in each light-emitting region to form a light source. Such a light-emitting device can be used as a light source in various electronic devices such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure relate to a light emitting device including a plurality of light emitting elements, a method of manufacturing the light emitting device, and a display apparatus including the light emitting device.

[0005] Technical Solution

[0006] According to aspects of the present disclosure, a light-emitting device may include: a substrate; a first electrode and a second electrode, which are arranged on the substrate and spaced apart from each other; an insulating layer, which is arranged on the substrate on which the first electrode and the second electrode are formed, and includes a groove extending in a first direction intersecting the first electrode and the second electrode, and a first contact portion and a second contact portion configured to expose a region of the first electrode and a region of the second electrode, respectively; a plurality of light-emitting elements, which are arranged in the groove and located between the first electrode and the second electrode, and each include a first end and a second end, the first end and the second end are respectively and electrically connected to the first electrode and the second electrode; a first contact electrode, which is electrically connected to the light-emitting element at the first end and is electrically connected to the first electrode at the first contact portion; and a second contact electrode, which is electrically connected to the light-emitting element at the second end and is electrically connected to the second electrode at the second contact portion.

[0007] In an embodiment, each of the light emitting elements may be a rod-type light emitting diode having a length extending in the first direction.

[0008] In an implementation, the width of the groove may be greater than the diameter or width of each of the light emitting elements.

[0009] In an embodiment, the size of the light emitting element may range from nanometer scale to micrometer scale.

[0010] In an implementation, the first electrode and the second electrode may be disposed to face each other in parallel in at least one region on the substrate, and each may extend in a second direction intersecting the first direction.

[0011] In an implementation, the insulating layer may include at least one organic insulating layer including a polymer.

[0012] In an implementation, the insulating layer may further include at least one inorganic insulating layer disposed between the substrate and the organic insulating layer.

[0013] In an implementation, the light emitting device may include a plurality of grooves arranged in a second direction intersecting the first direction.

[0014] In an embodiment, the light emitting device may further include: a first partition wall disposed between the substrate and the first electrode; and a second partition wall disposed between the substrate and the second electrode.

[0015] In an implementation, the light emitting device may further include a first insulating pattern disposed on a region of the light emitting element and between the first contact electrode and the second contact electrode.

[0016] In an implementation, the light emitting device may further include a second insulating pattern covering an upper portion of the first insulating pattern and an upper portion of the first contact electrode.

[0017] In an implementation, one end of the second contact electrode may be disposed on one end of the second insulation pattern adjacent to the second end.

[0018] According to aspects of the present disclosure, a method for manufacturing a light-emitting device may include: forming a first partition wall and a second partition wall spaced apart from each other on a substrate; forming a first electrode and a second electrode on the first partition wall and the second partition wall, respectively; forming at least one insulating layer on the substrate on which the first electrode and the second electrode are formed; forming at least one groove intersecting the first electrode and the second electrode in the surface of the insulating layer; providing a plurality of light-emitting elements on the insulating layer including the grooves, and aligning the light-emitting elements by forming an electric field between the first electrode and the second electrode; forming a first contact portion and a second contact portion by etching the insulating layer so that a region of the first electrode and a region of the second electrode are exposed; forming a first contact electrode on a region of the substrate including a first end of the light-emitting element and the first contact portion; and forming a second contact electrode on a region of the substrate including a second end of the light-emitting element and the second contact portion.

[0019] In an embodiment, forming at least one insulating layer may include: forming an inorganic insulating layer on the substrate having the first electrode and the second electrode formed thereon; and forming an organic insulating layer on the inorganic insulating layer.

[0020] In an embodiment, forming the at least one groove may include: disposing a grinding device on the organic insulating layer to contact the organic insulating layer; and moving at least one of the substrate and the grinding device in a direction intersecting the first electrode and the second electrode and pressing the organic insulating layer.

[0021] In an embodiment, forming the at least one groove may include: disposing a grinding device on the organic insulating layer; and forming a plurality of grooves in a surface of the organic insulating layer by pressing the organic insulating layer at intervals of a predetermined distance.

[0022] In an embodiment, forming the first contact portion and the second contact portion may include: forming a first insulating pattern on a region of the light emitting element so that the first end and the second end of the light emitting element are exposed, and etching the organic insulating layer over a region of the first electrode and a region of the second electrode; and etching the inorganic insulating layer so that a region of the first electrode and a region of the second electrode are exposed.

[0023] In an embodiment, forming a first contact electrode and a second contact electrode may include: forming a first contact electrode on a first end of a light emitting element and a first contact portion so that the first contact electrode contacts the first end of the light emitting element and a region of the first electrode; forming a second insulating pattern on the first contact electrode; and forming a second contact electrode on a second end of the light emitting element and the second contact portion so that the second contact electrode contacts the second end of the light emitting element and a region of the second electrode.

[0024] In an embodiment, aligning the light emitting element may include applying a solution in which the plurality of light emitting elements are dispersed onto the substrate through an inkjet printing scheme or a slit coating scheme.

[0025] According to aspects of the present disclosure, a display device may include: a substrate including a display area; and a pixel disposed in the display area. The pixel may include: a first electrode and a second electrode disposed on the substrate and spaced apart from each other; an insulating layer disposed on the substrate on which the first electrode and the second electrode are formed, and including a groove extending in a first direction intersecting the first electrode and the second electrode and a first contact portion and a second contact portion configured to expose a region of the first electrode and a region of the second electrode, respectively; a plurality of light-emitting elements disposed in the groove between the first electrode and the second electrode, and each including a first end and a second end, the first end and the second end being respectively and electrically connected to the first electrode and the second electrode; a first contact electrode electrically connected to the light-emitting element at the first end and electrically connected to the first electrode at the first contact portion; and a second contact electrode electrically connected to the light-emitting element at the second end and electrically connected to the second electrode at the second contact portion.

[0026] Beneficial Effects

[0027] In the light emitting device, the method for manufacturing the light emitting device, and the display device including the light emitting device according to the embodiment of the present disclosure, a plurality of light emitting elements can be effectively and uniformly aligned between the first electrode and the second electrode. Therefore, the emission characteristics of the light emitting device and the display device including the light emitting device can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A and Figure 1B 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 2A and Figure 2B 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 3A and Figure 3B 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 4 and Figure 5 Each is a plan view showing a light emitting device according to an embodiment of the present disclosure.

[0032] Figure 6 is a perspective view showing first and second electrodes, a groove, and a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 7 and Figure 8 is shown along Figure 4 Cross-sectional views of different embodiments of the cross-sectional view taken along line II'.

[0034] Fig. 9 is shown along Figure 5 A cross-sectional view of an embodiment of a cross-sectional view taken along line II-II'.

[0035] FIG. 10A to FIG. 10K It is shown in sequence that the manufacturing Figure 7 A cross-sectional view of a method for producing a light emitting device as shown in FIG.

[0036] Fig.11 is a plan view showing a display device according to an embodiment of the present disclosure.

[0037] FIG. 12A to FIG. 12C It is shown Fig.11 Circuit diagrams of different implementations of pixels.

[0038] Fig.13 It is shown Fig.11 A plan view of a pixel, and specifically, Fig.13 is a plan view showing a light emitting unit of each pixel.

[0039] Fig.14 is along Fig.13 A cross-sectional view taken along line III-III'. DETAILED DESCRIPTION

[0040] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, and which may be variously modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0041] In order to clearly explain the present disclosure, some elements that are not directly related to the features of the present disclosure in the drawings may be omitted. In addition, the size, proportion, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that in all the drawings, the same reference numerals are used to represent the same or similar elements, and repeated explanations will be omitted.

[0042] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first part such as a layer, film, region or plate is disposed on a second part, the first part may not only be directly disposed on the second part, but also a third part may be between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions depending on the viewing angle or direction.

[0043] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0044] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B 1 is a perspective view and a cross-sectional view showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1A to 3B A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0045] refer to Figure 1A and Figure 1B The light emitting element LD according to the embodiment of the present disclosure may include a first conductive semiconductor layer (first semiconductor layer) 11, a second conductive semiconductor layer (second semiconductor layer) 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light emitting element LD may be composed of a stacked body formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0046] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction (L), the light emitting element LD may have a first end and a second end relative to the longitudinal direction (L).

[0047] In an embodiment, one of the first and second conductive semiconductor layers 11 and 13 may be disposed on a first end of the light emitting element LD, and the other of the first and second conductive semiconductor layers 11 and 13 may be disposed on a second end of the light emitting element LD.

[0048] In an embodiment, the light emitting element LD may be manufactured in the form of a rod. In this specification, the term "rod type" includes a rod-like shape and a bar-like shape, such as a cylindrical shape and a prism shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0049] In an embodiment, the light emitting element LD may have a small size corresponding to a nanometer size or a micrometer size, for example, a diameter D and / or a length L corresponding to a micrometer to nanometer range. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., a display device) that uses a light emitting device using the light emitting element LD as a light source.

[0050] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0051] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0052] If an electric field having a predetermined voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0053] The second conductive semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a different type from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0054] In an embodiment, the insulating film INF may be disposed on the outer peripheral surface of the light emitting element LD (e.g., the outer side surface of the cylinder). For example, the insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film INF may further surround at least a portion of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow the opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD with respect to the longitudinal direction (L), for example, each of the top surface and the bottom surface of the cylinder may be exposed instead of covering each of the top surface and the bottom surface of the cylinder.

[0055] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0056] In an embodiment, the light emitting element LD may further include additional other components as well as the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13. For example, the light emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13.

[0057] For example, Figure 2A and Figure 2B As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive semiconductor layer 13. In an embodiment, as Figure 3A and Figure 3B As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive semiconductor layer 11 .

[0058] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0059] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0060] If the insulating film INF is provided on the surface of the light emitting element LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting element LD), etc. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0061] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on each light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0062] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, the light emitting element LD may be surface treated (e.g., by a coating process) so that when a plurality of light emitting elements LD are mixed with a fluid solution and then provided to each light emitting region (e.g., the light emitting region of each pixel), the light emitting element LD may be uniformly distributed rather than unevenly aggregated in the solution.

[0063] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices including display devices that require a light source. For example, a plurality of ultra-small light-emitting elements LD can be arranged in each pixel area of ​​a light-emitting display panel to form a light-emitting unit for each pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in various devices that require a light source, such as lighting equipment.

[0064] Figure 4 and Figure 5 are plan views respectively showing light emitting devices according to embodiments of the present disclosure. In the embodiments, Figure 4 and Figure 5 The light emitting devices are shown, each of which includes a first power line PL1 and a second power line PL2, or is directly coupled to the first power line PL1 and the second power line PL2. However, the light emitting device according to the present disclosure is not limited to Figure 4 and Figure 5 For example, in an embodiment of the present disclosure, the light emitting device may be coupled to the first power line PL1 and / or the second power line PL2 via at least one circuit element (eg, a pixel circuit), an intermediate connection line, and the like.

[0065] Reference Figure 4 and Figure 5The light emitting device according to the embodiment of the present disclosure may include a substrate SUB, a first partition wall (first wall or first bank) PW1 and a second partition wall (second wall or second bank) PW2 disposed on the substrate SUB, first electrodes ELT1 and second electrodes ELT2 disposed on the first partition wall PW1 and the second partition wall PW2, respectively, a plurality of light emitting elements LD disposed between the first electrode ELT1 and the second electrode ELT2, and first contact electrodes CNE1 and second contact electrodes CNE2 electrically connecting first ends EP1 and second ends EP2 of the light emitting elements LD to the first electrodes ELT1 and the second electrodes ELT2, respectively. However, the light emitting device according to the present disclosure is not limited to Figure 4 and Figure 5 For example, in an embodiment of the present disclosure, at least one light emitting area EMA included in the light emitting device may include only a single light emitting element LD.

[0066] The light emitting device may further include a first connection electrode CNL1 coupling the first electrode ELT1 to the first power line PL1 and a second connection electrode CNL2 coupling the second electrode ELT2 to the second power line PL2. In an embodiment, the first connection electrode CNL1 and the second connection electrode CNL2 may be respectively and integrally coupled to the first electrode ELT1 and the second electrode ELT2, or may be electrically connected to the first electrode ELT1 and the second electrode ELT2 via at least one contact hole, etc. In the case where the first connection electrode CNL1 and the second connection electrode CNL2 are respectively and integrally coupled to the first electrode ELT1 and the second electrode ELT2, each of the first connection electrode CNL1 and the second connection electrode CNL2 may be regarded as a region of a corresponding electrode of the first electrode ELT1 and the second electrode ELT2.

[0067] The substrate SUB may form a basic component of the light-emitting device, and may be a rigid substrate or a flexible substrate. For example, the substrate SUB may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. For example, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate. In other words, in the present disclosure, the material or properties of the substrate SUB are not particularly limited.

[0068] The first partition wall PW1 and the second partition wall PW2 may be disposed in a region on the substrate SUB at positions spaced apart from each other, for example, in a predetermined light emitting region EMA. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be disposed on the same layer of the substrate SUB at positions spaced apart from each other by a predetermined distance in a first direction DR1 (for example, a lateral direction), and each extends in a second direction DR2 (for example, a vertical direction) intersecting the first direction DR1. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same structure, shape and / or height, but the present disclosure is not limited thereto.

[0069] The first electrode ELT1 and the second electrode ELT2 may be disposed on the first partition wall PW1 and the second partition wall PW2, respectively, and protrude into shapes corresponding to the first partition wall PW1 and the second partition wall PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by a predetermined distance in the first direction DR1, and each may extend in a second direction DR2 intersecting the first direction DR1. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed to face each other in parallel in the first direction DR1 in at least one region on the substrate SUB (for example, at least in the light emitting region EMA), and extend in the second direction DR2 intersecting the first direction DR1.

[0070] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at the same layer and / or height, but the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0071] In an embodiment, the first electrode ELT1 may be coupled to the first power line PL1 through the first connection electrode CNL1. In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. For example, when the first connection electrode CNL1 extends in the first direction DR1, the first electrode ELT1 may extend in the second direction DR2 intersecting the first direction DR1.

[0072] In an embodiment, the first electrode ELT1 may be integrally coupled to the first connection electrode CNL1. For example, the first electrode ELT1 may be formed to be unidirectionally branched from the first connection electrode CNL1. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be separately formed and electrically connected to each other through at least one contact hole, a through hole, etc.

[0073] In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be integrally coupled to the first power line PL1. In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be formed separately from the first power line PL1 and electrically connected to the first power line PL1 via at least one contact hole and / or at least one circuit element. Therefore, the first power to be supplied to the first power line PL1 may be transmitted to the first electrode ELT1.

[0074] In an embodiment, the second electrode ELT2 may be coupled to the second power line PL2 through the second connection electrode CNL2. In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. For example, when the second connection electrode CNL2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 intersecting the first direction DR1.

[0075] In an embodiment, the second electrode ELT2 may be integrally coupled to the second connection electrode CNL2. For example, the second electrode ELT2 may be formed to be unidirectionally bifurcated from the second connection electrode CNL2. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be formed separately and electrically connected to each other through at least one contact hole, a through hole, etc.

[0076] In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be integrally coupled to the second power line PL2. In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be formed separately from the second power line PL2 and electrically connected to the second power line PL2 via at least one contact hole and / or at least one circuit element. Therefore, the second power to be supplied to the second power line PL2 may be transmitted to the second electrode ELT2.

[0077] In an embodiment, the first power supply and the second power supply may have different potentials. For example, the potential difference between the first power supply and the second power supply may be equal to or greater than the threshold voltage of the light emitting element LD. In an embodiment, the first power supply and the second power supply may have a potential that enables at least one light emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2 to be coupled in a forward direction. In other words, the voltage between the first power supply and the second power supply may have a value that enables at least one light emitting element LD included in the light emitting device to emit light.

[0078] In an embodiment, the light emitting element LD may be coupled in parallel to each other between the first electrode ELT1 and the second electrode ELT2. For example, the light emitting element LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in a first direction DR1 (eg, in a lateral direction) in a region where the first electrode ELT1 and the second electrode ELT2 are disposed to face each other.

[0079] In an implementation, one end of each of the light emitting elements LD may overlap at least the first contact electrode CNE1. Figure 4 As shown in , the first end EP1 of the light emitting element LD may overlap with the first electrode ELT1 and the first contact electrode CNE1. Figure 5 As shown in FIG, the first end EP1 of the light emitting element LD may overlap only with the first contact electrode CNE1 but not with the first electrode ELT1. The first end EP1 of the light emitting element LD may be electrically connected to the first electrode ELT1 through the first contact electrode CNE1.

[0080] In an embodiment, the other end of each of the light emitting elements LD may overlap at least with the second contact electrode CNE2. Figure 4 As shown in , the second end EP2 of the light emitting element LD may overlap with the second electrode ELT2 and the second contact electrode CNE2. Figure 5 As shown in FIG. 1 , the second end EP2 of the light emitting element LD may overlap only with the second contact electrode CNE2 but not with the second electrode ELT2. The second end EP2 of the light emitting element LD may be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0081] However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the opposite ends of the light emitting element LD (i.e., at least one of the first end EP1 and the second end EP2) may be in direct contact with the first electrode ELT1 or the second electrode ELT2, and thus be electrically connected to the first electrode ELT1 or the second electrode ELT2.

[0082] although Figure 4 and Figure 5 The light emitting elements LD are shown to be uniformly oriented in any one direction (e.g., in the first direction DR1), but the present disclosure is not limited thereto. For example, at least one light emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2 in a diagonal direction, or may not be completely coupled between the first electrode ELT1 and the second electrode ELT2.

[0083] In an embodiment, each of the light emitting elements LD may be formed of a rod-type light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range of nanometer to micrometer scale. Figures 1A to 3B As shown in , each light emitting element LD may be an ultra-small rod-type light emitting diode having a diameter D and / or a length L in the range of nanometer to micrometer order.

[0084] In an embodiment, the light emitting element LD may be prepared in a dispersed form in a predetermined solution, and then provided to a predetermined light emitting area EMA defined in the light emitting device by an inkjet printing scheme, a slit coating scheme, or the like. For example, the light emitting element LD may be mixed with a volatile solvent and dropped onto each light emitting area EMA. Here, if the first power and the second power are applied to the first electrode ELT1 and the second electrode ELT2 respectively through the first power line PL1 and the second power line PL2, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD is self-aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, in an embodiment, since the first contact electrode CNE1 and the second contact electrode CNE2 are respectively formed on opposite ends of the light emitting element LD (i.e., formed on the first end EP1 and the second end EP2), the light emitting element LD may be more reliably coupled between the first electrode ELT1 and the second electrode ELT2.

[0085] In an embodiment, the first contact electrode CNE1 may be formed to cover both the first end EP1 of the light emitting element LD and at least one region of the first electrode ELT1, whereby the first end EP1 of the light emitting element LD may be physically coupled and / or electrically connected to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed to cover both the second end EP2 of the light emitting element LD and at least one region of the second electrode ELT2, whereby the second end EP2 of the light emitting element LD may be physically coupled and / or electrically connected to the second electrode ELT2.

[0086] When the first power is applied to the first end EP1 of the light emitting element LD via the first power line PL1, the first electrode ELT1, etc. and the second power is applied to the second end EP2 of the light emitting element LD via the second power line PL2, the second electrode ELT2, etc., at least one light emitting element LD coupled in the forward direction between the first electrode ELT1 and the second electrode ELT2 may emit light. Therefore, the light emitting device may emit light.

[0087] In an embodiment of the present disclosure, the light emitting device includes at least one groove GRV, and the at least one groove GRV extends in a first direction DR1 intersecting (e.g., intersecting at right angles) the first electrode ELT1 and the second electrode ELT2 in at least one area including the light emitting area EMA. For example, the light emitting device may include a plurality of grooves GRV formed in an insulating layer disposed between the substrate SUB and the light emitting element LD. In an embodiment, the plurality of grooves GRV may be arranged in parallel with each other in the corresponding light emitting area EMA in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited to the aforementioned structure, and for example, the shape and / or arrangement of the grooves GRV formed in each light emitting area EMA may be changed in various ways.

[0088] In an embodiment of the present disclosure, the light emitting device may include a light emitting element LD, each of which is disposed in any one of the grooves GRV, such that the light emitting element LD is disposed between the first electrode ELT1 and the second electrode ELT2. For example, at least some of the light emitting elements LD distributed in each light emitting region EMA may be disposed between the first electrode ELT1 and the second electrode ELT2, such that they are located in any one of the grooves GRV formed in the corresponding light emitting region EMA.

[0089] According to the aforementioned embodiment, at least one groove GRV extending in a direction intersecting the first electrode ELT1 and the second electrode ELT2 is formed in the light emitting device. For example, after at least one groove GRV is formed in one surface of the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed, the light emitting element LD may be provided in each light emitting area EMA. Therefore, the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 with more uniform directivity. Therefore, according to the aforementioned embodiment, the light emitting element LD may be more uniformly aligned in the light emitting area EMA.

[0090] Figure 6 is a perspective view showing the first electrode ELT1 and the second electrode ELT2, the groove GRV and the light emitting element LD according to an embodiment of the present disclosure. In an embodiment, Figure 6 Focus on Figure 4 The region of the light emitting area EMA shown in FIG. 1 (eg, a region disposed between the first electrode ELT1 and the second electrode ELT2 facing each other) schematically shows the mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2, the groove GRV, and the light emitting element LD. Figure 6 In the description of the embodiments of the present invention, the same reference numerals are used to represent Figure 4 and Figure 5 The components of the embodiments are similar or identical to those of the embodiments, and their detailed description will be omitted.

[0091] Reference Figures 4 to 6 , the light emitting device according to an embodiment of the present disclosure may further include an insulating layer INS formed on the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed. In an embodiment, the insulating layer INS may include at least one groove GRV extending in a first direction DR1 intersecting with an extending direction (e.g., a second direction DR2) of the first electrode ELT1 and the second electrode ELT2. A plurality of light emitting elements LD may be disposed in the at least one groove GRV.

[0092] Here, the insulating layer INS may be partially opened on a plurality of contact portions (not shown) to provide electrical connection between the first electrode ELT1, the second electrode ELT2 and the light emitting element LD. In this case, each groove GRV may have an overall shape extending in the first direction DR1, and may extend discontinuously in the first direction DR1 in a shape in which the groove GRV is partially disconnected or opened on an area corresponding to each contact portion. For example, each groove GRV may extend continuously in the first direction DR1 in at least one area between the first electrode ELT1 and the second electrode ELT2, and may be partially removed in an area above each of the first electrode ELT1 and the second electrode ELT2. The connection structure between the first electrode ELT1, the second electrode ELT2 and the light emitting element LD will be described in detail below.

[0093] In an embodiment, the insulating layer INS may include at least one organic insulating layer. In addition, the insulating layer INS may also selectively include at least one inorganic insulating layer. For example, the insulating layer INS may be formed of an organic insulating layer in at least the upper region where the groove GRV is formed.

[0094] In an embodiment, the light emitting element LD disposed in at least one groove GRV may have an arrangement shape corresponding to the shape of the corresponding groove GRV. For example, each of the light emitting elements LD may be a rod-type light emitting diode. The rod-type light emitting diode may be arranged to have a length L extending in the first direction DR1 in which the corresponding groove GRV extends.

[0095] In an embodiment, each groove GRV may be formed to stably accommodate at least one light emitting element LD therein. For example, each groove GRV may have a width W in the second direction DR2 that is greater than the diameter D or width of each of the light emitting elements LD. In addition, in an embodiment, each groove GRV may have a depth DP in a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2, the depth DP corresponding to half or more of the thickness of each of the light emitting elements LD (the diameter D in the case where the light emitting elements LD each have a cylindrical shape), but the depth DP of the groove GRV is not limited thereto.

[0096] In manufacturing the light emitting device according to the aforementioned embodiment, a groove GRV extending in the first direction DR1 intersecting the first electrode ELT1 and the second electrode ELT2 is formed in the insulating layer INS disposed on the first electrode ELT1 and the second electrode ELT2, and the light emitting element LD is provided on the insulating layer INS. In this case, the light emitting element LD can be aligned between the first electrode ELT1 and the second electrode ELT2 with more uniform directivity by the groove GRV in the surface of the insulating layer INS. For example, among the light emitting elements LD provided to the light emitting area EMA, the number of light emitting elements LD disposed in the lateral direction along the first direction DR1 between the first electrode ELT1 and the second electrode ELT2 can be increased compared to the case where the groove GRV is not formed.

[0097] Figure 7 and Figure 8 is shown along Figure 4 1 and 2 , and specifically, illustrate different embodiments related to the shapes of the first partition wall PW1 and the second partition wall PW2. Fig. 9 is shown along Figure 5 1 is a cross-sectional view of an embodiment of a cross-sectional view taken along line II-II′ of FIG. 1 , and specifically, illustrates an embodiment in which the light emitting element LD does not overlap with the first electrode ELT1 and the second electrode ELT2 .

[0098] Reference Figures 4 to 9According to an embodiment of the present disclosure, a light emitting device may include a substrate SUB, a first electrode ELT1 and a second electrode ELT2 disposed on the substrate SUB, a plurality of light emitting elements LD connected between the first electrode ELT1 and the second electrode ELT2, at least one insulating layer INS disposed between the light emitting element LD and the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed, and a first contact electrode CNE1 and a second contact electrode CNE2 connecting a first end EP1 and a second end EP2 of the light emitting element LD to the first electrode ELT1 and the second electrode ELT2, respectively. In addition, the light-emitting device may further include a buffer layer BFL arranged between the substrate SUB and the first electrode ELT1 and the second electrode ELT2, a first partition wall PW1 arranged between the substrate SUB and a region of the first electrode ELT1, a second partition wall PW2 arranged between the substrate SUB and a region of the second electrode ELT2, a first insulating pattern INP1 arranged above a region of the light-emitting element LD, a second insulating pattern INP2 arranged above the first contact electrode CNE1, and at least one of an outer coating layer OC covering a surface of the substrate SUB on which the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, etc. are formed.

[0099] In an embodiment, the substrate SUB may form a basic component of the light emitting device and may be a rigid substrate or a flexible substrate. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. In other words, in the present disclosure, the material or properties of the substrate SUB are not particularly limited.

[0100] The buffer layer BFL may be formed on one surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into electrodes, wires, and / or circuit elements disposed on the buffer layer BFL. In an embodiment, the buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0101] The first partition wall PW1 and the second partition wall PW2 may be disposed on one surface of the substrate SUB on which the buffer layer BFL is formed. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be disposed on one surface of the substrate SUB at positions spaced apart from each other. For example, the first partition wall PW1 and the second partition wall PW2 may be disposed on the same layer on the substrate SUB at positions spaced apart from each other by a predetermined distance. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same structure, shape and / or height, but the present disclosure is not limited thereto.

[0102] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material having an inorganic material and / or an organic material. In addition, each of the first partition wall PW1 and the second partition wall PW2 may have a single-layer structure or a multi-layer structure. In other words, the material and / or stacking structure of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited.

[0103] Each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Figure 7 As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-sectional shape that decreases in width from the bottom to the top thereof. Figure 8 As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section whose width gradually decreases upward. In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or repositioned.

[0104] The first electrode ELT1 and the first contact electrode CNE1 may be disposed on the first partition wall PW1. The second electrode ELT2 and the second contact electrode CNE2 may be disposed on the second partition wall PW2. At least one electrode and / or an insulating layer disposed on each of the first partition wall PW1 and the second partition wall PW2 may have a shape corresponding to a shape of a corresponding one of the first partition wall PW1 and the second partition wall PW2, but the present disclosure is not limited thereto.

[0105] The first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other on the substrate SUB on which the first partition wall PW1 and the second partition wall PW2 are disposed. For example, the first electrode ELT1 may be disposed on the first partition wall PW1 to cover the first partition wall PW1. The second electrode ELT2 may be disposed on the second partition wall PW2 to cover the second partition wall PW2. In an embodiment, any one of the first electrode ELT1 and the second electrode ELT2 may be an anode electrode, and the other may be a cathode electrode.

[0106] The first electrode ELT1 and the second electrode ELT2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively. For example, the first electrode ELT1 may have an inclined surface or a curved surface corresponding to the shape of the first partition wall PW1, and the second electrode ELT2 may have an inclined surface or a curved surface corresponding to the shape of the second partition wall PW2. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may not be provided in the light emitting device. In this case, each of the first electrode ELT1 and the second electrode ELT2 may have a substantially flat shape.

[0107] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed on the same plane on the substrate SUB and have substantially the same height. Thus, if the first electrode ELT1 and the second electrode ELT2 have the same height, the light emitting element LD may be more reliably coupled between the first electrode ELT1 and the second electrode ELT2. However, the present disclosure is not limited thereto. For example, the shape, structure and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0108] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure, and its cross-sectional structure is not particularly limited. For example, the first electrode ELT1 may have a multi-layer structure including a first reflective electrode REF1 and a first conductive capping layer CPL1. The second electrode ELT2 may have a multi-layer structure including a second reflective electrode REF2 and a second conductive capping layer CPL2.

[0109] Each of the first reflective electrode REF1 and the second reflective electrode REF2 may be formed of a conductive material having a predetermined reflectivity. For example, each of the first reflective electrode REF1 and the second reflective electrode REF2 may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof; however, the present disclosure is not limited thereto. Each of the first reflective electrode REF1 and the second reflective electrode REF2 may be formed of various reflective conductive materials.

[0110] The first reflective electrode REF1 and the second reflective electrode REF2 may enable light emitted from opposite ends of each of the light emitting elements LD (i.e., the first end EP1 and the second end EP2 of the light emitting element LD) to travel in a direction in which an image is displayed (e.g., in a forward direction). Specifically, if each of the first reflective electrode REF1 and the second reflective electrode REF2 has an inclination or curvature corresponding to the shape of a corresponding one of the first partition wall PW1 and the second partition wall PW2, light emitted from the first end EP1 and the second end EP2 of each of the light emitting elements LD may be reflected by the first reflective electrode REF1 and the second reflective electrode REF2, whereby the light may travel more reliably in the forward direction of the light emitting device (e.g., in an upward direction of the substrate SUB). Thus, the efficiency of light emitted from the light emitting element LD may be improved.

[0111] In an embodiment of the present disclosure, each of the first partition wall PW1 and the second partition wall PW2 may also be used as a reflective member. For example, the first partition wall PW1 and the second partition wall PW2 together with the first reflective electrode REF1 and the second reflective electrode REF2 disposed on the first partition wall PW1 and the second partition wall PW2 may be used as a reflective component for enhancing the efficiency of light emitted from each of the light emitting elements LD.

[0112] The first conductive capping layer CPL1 and the second conductive capping layer CPL2 may be selectively disposed on the first reflective electrode REF1 and the second reflective electrode REF2, respectively. For example, the first conductive capping layer CPL1 may be disposed on the first reflective electrode REF1 to cover the first reflective electrode REF1. The second conductive capping layer CPL2 may be disposed on the second reflective electrode REF2 to cover the second reflective electrode REF2.

[0113] Each of the first conductive capping layer CPL1 and the second conductive capping layer CPL2 may be formed of a transparent conductive material such as ITO or IZO to minimize the loss of light emitted from the light emitting element LD. However, the present disclosure is not limited thereto. For example, the material of the first conductive capping layer CPL1 and the second conductive capping layer CPL2 may be changed in various ways.

[0114] The first conductive capping layer CPL1 and the second conductive capping layer CPL2 may prevent the first reflective electrode REF1 and the second reflective electrode REF2 from being damaged due to defects that may occur in the process of manufacturing the light emitting device, and may enhance the adhesion between the substrate SUB and the first reflective electrode REF1 and the second reflective electrode REF2. In an embodiment, at least one of the first conductive capping layer CPL1 and the second conductive capping layer CPL2 may be omitted.

[0115] The insulating layer INS is formed on the substrate SUB on which the first and second electrodes ELT1 and ELT2 are disposed. In an embodiment of the present disclosure, at least one groove GRV extending in a first direction DR1 intersecting a second direction DR2 in which the first and second electrodes ELT1 and ELT2 extend is formed on the surface of the insulating layer INS at least between the first and second electrodes ELT1 and ELT2.

[0116] In an embodiment, the insulating layer INS may include at least one organic insulating layer. In addition, the insulating layer INS may also selectively include at least one inorganic insulating layer. For example, the insulating layer INS may include at least one inorganic insulating layer (hereinafter, referred to as "first insulating layer INS1") disposed on the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed, and an organic insulating layer (hereinafter, referred to as "second insulating layer INS2") disposed on the first insulating layer INS1.

[0117] In an embodiment, the first insulating layer INS1 may include, for example, silicon nitride SiN x , but the material used to form the first insulating layer INS1 is not limited thereto. For example, the first insulating layer INS1 may be configured of at least one of various known inorganic insulating layer materials. In addition, the first insulating layer INS1 may be configured of a single layer or multiple layers, and its cross-sectional structure is not particularly limited.

[0118] In an embodiment, the second insulating layer INS2 may include a polymeric organic material and be formed to have flexibility. For example, the second insulating layer INS2 may be a polyimide coating formed of polyimide, but the material used to form the second insulating layer INS2 is not limited thereto. For example, the second insulating layer INS2 may be formed of at least one of various known organic insulating layer materials. In addition, the second insulating layer INS2 may be configured by a single layer or a multilayer, and its cross-sectional structure is not particularly limited.

[0119] At least one groove GRV extending in the first direction DR1 intersecting the first electrode ELT1 and the second electrode ELT2 is formed in the surface of the second insulating layer INS2. In an embodiment, the groove GRV may be formed by a rubbing scheme, but the method of forming the groove GRV is not limited thereto. Due to the groove GRV formed in the second insulating layer INS2, the light emitting element LD may be disposed on the second insulating layer INS2 with more uniform directivity. In other words, in an embodiment, the second insulating layer INS2 may form a polymer alignment layer.

[0120] In an embodiment, the insulating layer INS may include a first contact portion CNT1 and a second contact portion CNT2 that allow regions of the first electrode ELT1 and the second electrode ELT2 to be exposed, respectively. For example, each of the first insulating layer INS1 and the second insulating layer INS2 may be partially opened so that the first electrode ELT1 and the second electrode ELT2 are exposed over the regions of the first electrode ELT1 and the second electrode ELT2.

[0121] In an embodiment, a plurality of light emitting elements LD may be disposed on a substrate SUB on which an insulating layer INS is disposed. The light emitting element LD may be disposed on a second insulating layer INS2 and between a first electrode ELT1 and a second electrode ELT2 in a plan view of the substrate SUB. Each of the light emitting elements LD may have a first end EP1 and a second end EP2 on respective opposite sides thereof in a longitudinal direction (L).

[0122] In an embodiment, the light emitting element LD may be horizontally disposed on one surface of the substrate SUB. In addition, the light emitting element LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in a lateral direction so that its longitudinal direction (L) corresponds to the first direction DR1. For example, the first end EP1 of the light emitting element LD may be disposed to face the first electrode ELT1. The second end EP2 of the light emitting element LD may be disposed to face the second electrode ELT2.

[0123] In an embodiment, if Figure 7 and Figure 8 As shown in , the first end EP1 and the second end EP2 of the light emitting element LD may overlap with the first electrode ELT1 and the second electrode ELT2, respectively. Fig. 9 As shown in FIG. 1 , the first end EP1 and the second end EP2 of the light emitting element LD may overlap only the first contact electrode CNE1 and the second contact electrode CNE2 , respectively, but not the first electrode ELT1 and the second electrode ELT2 .

[0124] The first and second ends EP1 and EP2 of the light emitting element LD may be electrically connected to the first and second electrodes ELT1 and ELT2 through the first and second contact electrodes CNE1 and CNE2 , respectively.

[0125] In an embodiment of the present disclosure, by using a combination of a physical alignment scheme of a groove GRV formed in the surface of the second insulating layer INS2 and an electrical alignment scheme using an electric field formed by applying a voltage between the first electrode ELT1 and the second electrode ELT2, the light emitting element LD can be aligned between the first electrode ELT1 and the second electrode ELT2 to have a more uniform directivity. For example, the light emitting element LD can be guided and arranged in the groove GRV, and can be arranged so that its first end EP1 and the second end EP2 face the first electrode ELT1 and the second electrode ELT2, respectively. Therefore, the light emitting element LD can be arranged between the first electrode ELT1 and the second electrode ELT2, so that each light emitting element LD is arranged in any one groove GRV in the first direction DR1 in which the groove GRV extends.

[0126] although Figures 4 to 9 Only effective light emitting elements are shown, and the first end EP1 and the second end EP2 of each of the light emitting elements are connected to the first electrode ELT1 and the second electrode ELT2, but the light emitting device may include not only effective light emitting elements but also at least one light emitting element (not shown) that is not completely connected between the first electrode ELT1 and the second electrode ELT2.

[0127] In other words, at least some of the light emitting elements LD provided to the light emitting area EMA of the light emitting device may be aligned between the first electrode ELT1 and the second electrode ELT2 and electrically connected to the first electrode ELT1 and the second electrode ELT2. Specifically, as described in the embodiments of the present disclosure, in the case where the light emitting elements LD are aligned by a combination of a physical alignment scheme and an electrical alignment scheme, the number of light emitting elements LD aligned with uniform directionality between the first electrode ELT1 and the second electrode ELT2 may be further increased.

[0128] The first contact electrode CNE1 and the second contact electrode CNE2 are disposed on the substrate SUB on which the light emitting element LD is disposed. The first contact electrode CNE1 and the second contact electrode CNE2 may electrically connect the light emitting element LD between the first electrode ELT1 and the second electrode ELT2.

[0129] In an embodiment, the first contact electrode CNE1 may be formed to cover not only the first end EP1 of the light emitting element LD but also the first contact portion CNT1. Therefore, the first contact electrode CNE1 may be electrically connected to the light emitting element LD by contacting the light emitting element LD at the first end EP1 of the light emitting element LD, and may be electrically connected to the first electrode ELT1 by contacting the first electrode ELT1 at the first contact portion CNT1. In other words, the first end EP1 of the light emitting element LD and the first electrode ELT1 may be electrically connected to each other through the first contact electrode CNE1.

[0130] In an embodiment, the second contact electrode CNE2 may be formed to cover not only the second end EP2 of the light emitting element LD but also the second contact portion CNT2. Therefore, the second contact electrode CNE2 may be electrically connected to the light emitting element LD by contacting the light emitting element LD at the second end EP2 of the light emitting element LD, and may be electrically connected to the second electrode ELT2 by contacting the second electrode ELT2 at the second contact portion CNT2. In other words, the second end EP2 of the light emitting element LD and the second electrode ELT2 may be electrically connected to each other through the second contact electrode CNE2.

[0131] In an embodiment of the present disclosure, the light emitting device may include at least one insulating pattern (or insulating layer) provided to ensure electrical stability (e.g., insulating characteristics) between the first contact electrode CNE1 and the second contact electrode CNE2. For example, the light emitting device may include a first insulating pattern INP1 provided on a region of the light emitting element LD between the first contact electrode CNE1 and the second contact electrode CNE2, and a second insulating pattern INP2 configured to cover the first insulating pattern INP1 and an upper portion of the first contact electrode CNE1.

[0132] In an embodiment, the first insulating pattern INP1 may be disposed on the light emitting element LD to cover at least one region of the light emitting element LD, and may be formed to allow the first end EP1 and the second end EP2 of the light emitting element LD to be exposed. In an embodiment, the first insulating pattern INP1 may include at least one organic insulating layer and / or an inorganic insulating layer, and the material or property of the at least one organic insulating layer and / or the inorganic insulating layer is not particularly limited. For example, the first insulating pattern INP1 may include, for example, silicon nitride SiN x , but the material used to form the first insulating pattern INP1 is not limited thereto. In addition, the first insulating pattern INP1 may be configured by a single layer or multiple layers, and its cross-sectional structure is not particularly limited. For example, the first insulating pattern INP1 may be formed of a plurality of layers including a lower pattern layer LPT and an upper pattern layer UPT, and the lower pattern layer LPT and the upper pattern layer UPT are formed of the same material or different materials, but the present disclosure is not limited thereto.

[0133] The first contact electrode CNE1 described above may be disposed on the substrate SUB on which the first insulating pattern INP1, etc. are formed. In an implementation, one end of the first contact electrode CNE1 may be disposed on one end of the first insulating pattern INP1 located on the first end EP1 of the light emitting element LD.

[0134] In an embodiment, the second insulating pattern INP2 may be formed on the substrate SUB on which the first insulating pattern INP1 and the first contact electrode CNE1 are formed to cover the upper portions of the first insulating pattern INP1 and the first contact electrode CNE1. However, the second insulating pattern INP2 may be formed to allow the second end EP2 of the light emitting element LD to be exposed. In an embodiment, the second insulating pattern INP2 may include at least one organic insulating layer and / or an inorganic insulating layer, and the material or property of the at least one organic insulating layer and / or the inorganic insulating layer is not particularly limited. In addition, the second insulating pattern INP2 may include a material that is the same as or different from that of the first insulating pattern INP1. For example, the second insulating pattern INP2 may include, for example, silicon nitride SiN x , but the material used to form the second insulating pattern INP2 is not limited thereto. In addition, the second insulating pattern INP2 may be configured of a single layer or multiple layers, and its cross-sectional structure is not particularly limited.

[0135] The second contact electrode CNE2 described above may be disposed on the substrate SUB on which the second insulating pattern INP2, etc. are formed. In an embodiment, one end of the second contact electrode CNE2 may be disposed on one end of the second insulating pattern INP2 adjacent to the second end EP2 of the light emitting element LD.

[0136] The overcoat layer OC may be disposed on the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are disposed. In an embodiment, the overcoat layer OC may be formed of a single layer or a plurality of layers. For example, the overcoat layer OC may include a thin film encapsulation layer including a plurality of inorganic insulating layers overlapping each other and at least one organic insulating layer interposed between the inorganic insulating layers. However, the material and / or cross-sectional structure of the overcoat layer OC are not particularly limited and may be changed in various ways.

[0137] According to the above embodiments, the efficiency and uniformity of aligning the light emitting element LD in the light emitting area EMA can be improved by combining the physical alignment scheme and the electrical alignment scheme. Therefore, the emission characteristics of the light emitting device, such as emission brightness, emission efficiency and / or emission uniformity, can be enhanced.

[0138] FIG. 10A to FIG. 10K It is shown in sequence that the manufacturing Figure 7 A cross-sectional view of a method for producing a light emitting device as shown in FIG.

[0139] refer to Fig. 10A, a buffer layer BFL is formed on one surface of a substrate SUB, and a first partition wall PW1 and a second partition wall PW2 are formed at positions spaced apart from each other on the substrate SUB on which the buffer layer BFL is formed. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be formed by a process of forming an insulating layer including an inorganic material and / or an organic material and / or a patterning process (e.g., a mask process), and may be formed by various types of known processes. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be simultaneously formed on the same layer (or the same plane) on the substrate SUB using the same material, but the present disclosure is not limited thereto.

[0140] Reference Fig. 10B , the first and second electrodes ELT1 and ELT2 are formed on the first and second partition walls PW1 and PW2. In an embodiment, the first and second electrodes ELT1 and ELT2 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes.

[0141] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may be formed of a single layer or multiple layers. For example, the first electrode ELT1 may be formed of a plurality of layers including a first reflective electrode REF1 and a first conductive capping layer CPL1. The second electrode ELT2 may be formed of a plurality of layers including a second reflective electrode REF2 and a second conductive capping layer CPL2. In this case, the step of forming the first electrode ELT1 and the second electrode ELT2 may include the steps of forming the first reflective electrode REF1 and the second reflective electrode REF2 on the first partition wall PW1 and the second partition wall PW2, respectively, and forming the first conductive capping layer CPL1 and the second conductive capping layer CPL2 on the first reflective electrode REF1 and the second reflective electrode REF2.

[0142] In addition, the first electrode ELT1 and the second electrode ELT2 may be simultaneously formed on the same layer on the substrate SUB, but the present disclosure is not limited thereto. In the case where the first electrode ELT1 and the second electrode ELT2 are simultaneously formed, the number of mask processes for manufacturing the light emitting device may be reduced or minimized.

[0143] refer to Fig. 10C and Fig. 10D At least one insulating layer INS is formed on the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed. For example, the first insulating layer INS1 and the second insulating layer INS2 are continuously formed on the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed.

[0144] In an embodiment, the insulating layer INS may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the insulating layer INS may be formed of a single layer or multiple layers. For example, after at least one inorganic insulating layer (ie, the first insulating layer INS1) is formed using at least one inorganic material, an organic insulating layer (ie, the second insulating layer INS2) may be formed on the first insulating layer INS1 using at least one organic material. In an embodiment, the second insulating layer INS2 may be formed by, for example, coating a polymer organic layer including polyimide, but the material of the second insulating layer INS2 and / or the method of forming the second insulating layer INS2 is not limited thereto.

[0145] Reference Fig. 10E , at least one groove GRV is formed in the surface of the insulating layer INS (ie, at least the surface of the second insulating layer INS2). In an embodiment, the groove GRV may be formed by a rubbing scheme using a grinding device RUD.

[0146] For example, by disposing the grinding device RUD on the second insulating layer INS2 so that the grinding device RUD contacts the second insulating layer INS2, and pressing the second insulating layer INS2 while moving the substrate SUB and / or the grinding device RUD in a unidirectional or reciprocating manner at least once in a first direction DR1 intersecting the first electrode ELT1 and the second electrode ELT2, a groove GRV may be formed on the surface of the second insulating layer INS2. In detail, the grinding device RUD may include a roller ROL rotatable in at least one direction and a rubbing cloth RUC wound around the roller ROL. In an embodiment, if at least one of the substrate SUB and the roller ROL moves in the first direction DR1 while the rubbing cloth RUC contacts the surface of the second insulating layer INS2, at least one groove GRV intersecting the first electrode ELT1 and the second electrode ELT2 may be formed in the surface of the second insulating layer INS2.

[0147] In an embodiment, the grinding device RUD is disposed on the second insulating layer INS2, and the second insulating layer INS2 may be pressed at a predetermined distance interval. Figure 4 As shown in FIG, a plurality of grooves GRV extending parallel to each other in a direction intersecting the first and second electrodes ELT1 and ELT2 may be formed in the surface of the second insulating layer INS2. In an embodiment, the plurality of grooves GRV may be formed simultaneously or sequentially.

[0148] Reference Fig.10F, a plurality of light emitting elements LD are provided on an insulating layer INS including at least one groove GRV, and an electric field may be formed by applying a predetermined voltage (e.g., an AC voltage) between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the light emitting element LD may be provided to a predetermined light emitting area EMA by applying a solution in which a plurality of light emitting elements LD are dispersed to the substrate SUB using an inkjet printing scheme, a slit coating scheme, or the like. However, the scheme for providing the light emitting element LD is not limited to the above scheme, and the light emitting element LD may be provided to the light emitting area EMA in various other ways. In an embodiment, an electric field may be formed by applying an AC voltage between the first electrode ELT1 and the second electrode ELT2, but the type of voltage or signal applied between the first electrode ELT1 and the second electrode ELT2 is not limited thereto.

[0149] If an electric field is formed between the first electrode ELT1 and the second electrode ELT2, the light emitting element LD is aligned between the first electrode ELT1 and the second electrode ELT2. Here, the light emitting element LD may be more uniformly aligned in the light emitting area EMA with a more uniform directivity by the groove GRV formed in the surface of the insulating layer INS. For example, the number of light emitting elements LD uniformly and laterally arranged along the first direction DR1 between the first electrode ELT1 and the second electrode ELT2 may be increased compared to a comparative example in which the groove GRV is not formed. For example, the first end EP1 of the light emitting element LD may be arranged to face the first electrode ELT1. The second end EP2 of the light emitting element LD may be arranged to face the second electrode ELT2.

[0150] Reference Figure 10G , a first insulating pattern INP1 (e.g., a lower pattern layer LPT of the first insulating pattern INP1) is formed on the substrate SUB on which the light emitting element LD is arranged. For example, the lower pattern layer LPT may be formed on the region of the light emitting element LD so that the first end EP1 and the second end EP2 of the light emitting element LD are exposed. In an embodiment, the lower pattern layer LPT may be formed by a process of forming an insulating layer including an inorganic material and / or an organic material and / or a patterning process (e.g., a mask process), and may be formed by various types of known processes.

[0151] In addition, in the step of forming the lower pattern layer LPT, the second insulating layer INS2 may be etched so that a region of the first insulating layer INS1 corresponding to each of the first electrode ELT1 and the second electrode ELT2 is exposed. For example, during a mask process of patterning the lower pattern layer LPT, an opening may be formed in the second insulating layer INS2 over the regions of the first electrode ELT1 and the second electrode ELT2.

[0152] Reference Fig. 10H, the first contact portion CNT1 and the second contact portion CNT2 may be formed in the insulating layer INS by etching the first insulating layer INS1 so that the region of each of the first electrode ELT1 and the second electrode ELT2 is exposed. Although in the present embodiment, the first contact portion CNT1 and the second contact portion CNT2 are formed in the insulating layer INS by etching the first insulating layer INS1 after the second insulating layer INS2 has been etched, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first contact portion CNT1 and the second contact portion CNT2 may be formed by etching the first insulating layer INS1 and the second insulating layer INS2 together over the region of each of the first electrode ELT1 and the second electrode ELT2 so that the region of the first electrode ELT1 and the second electrode ELT2 is exposed.

[0153] Reference Fig.10I , when the lower pattern layer LPT of the first insulating pattern INP1, the second end EP2 of the light emitting element LD, and the second electrode ELT2 including the second contact portion CNT2 are covered with the mask MAS, the first contact electrode CNE1 is formed on the region including the first end EP1 of the light emitting element LD and the first contact portion CNT1 of the substrate SUB. For example, the first contact electrode CNE1 may be formed on the region of the light emitting element LD and the first electrode ELT1 so that the first contact electrode CNE1 contacts the region of the first end EP1 of the light emitting element LD and the first electrode ELT1.

[0154] Reference Fig.10J , the second insulating pattern INP2 is formed on the first contact electrode CNE1 to at least cover the first contact electrode CNE1. In addition, in the step of forming the second insulating pattern INP2 (for example, in the step of patterning the second insulating pattern INP2), the second insulating pattern INP2 may be formed by etching together Fig.10I The mask MAS shown in FIG. 1 is used to form the upper pattern layer UPT of the first insulating pattern INP1. In an embodiment, the upper pattern layer UPT and the second insulating pattern INP2 may be formed continuously. Alternatively, in an embodiment, the first insulating pattern INP1 having a single-layer structure and formed only of the lower pattern layer LPT without the upper pattern layer UPT may be formed by adjusting the position of the mask MAS, or the first insulating pattern INP1 having a multi-layer structure may be formed before forming the mask MAS.

[0155] refer to Figure 10K, a second contact electrode CNE2 is formed on a region of the substrate SUB including the second end EP2 of the light emitting element LD and the second contact portion CNT2. For example, the second contact electrode CNE2 may be formed on a region of the light emitting element LD and the second electrode ELT2 so that the second contact electrode CNE2 contacts the second end EP2 of the light emitting element LD and the region of the second electrode ELT2.

[0156] Thereafter, an overcoat layer OC may be formed on the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are disposed. Figure 7 A light-emitting device according to an embodiment of the present invention, etc.

[0157] As described above, in the embodiment of the present disclosure, before providing the light emitting element LD to the light emitting area EMA of the light emitting device, a second insulating layer INS2 formed of at least one organic insulating layer is formed. Thereafter, at least one groove GRV is formed in the second insulating layer INS2 by a rubbing scheme using a grinding device RUD.

[0158] Specifically, in an embodiment of the present disclosure, each groove GRV is formed in a first direction DR1, and each of the light emitting elements LD is aligned in the first direction DR1. In an embodiment, the first direction DR1 may be a direction perpendicular to the first electrode ELT1 and the second electrode ELT2, but the present disclosure is not limited thereto. For example, the first direction DR1 may include not only a direction perpendicular to the first electrode ELT1 and the second electrode ELT2, but also a direction diagonally passing through the first electrode ELT1 and the second electrode ELT2. In other words, the first direction DR1 may include various directions intersecting the first electrode ELT1 and the second electrode ELT2.

[0159] In the embodiment of the present disclosure, the light emitting element LD is provided to the light emitting area EMA after forming the groove GRV in the second insulating layer INS2 by a rubbing scheme, etc. Therefore, the light emitting element LD or the insulating film INF surrounding the surface of the light emitting element LD can be prevented from being damaged by a rubbing process, etc.

[0160] In addition, in the embodiment of the present disclosure, a predetermined voltage is applied between the first electrode ELT1 and the second electrode ELT2 while or after providing the light emitting element LD. Therefore, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD can be self-aligned.

[0161] In other words, according to the above-mentioned embodiment, by compositely using the groove GRV formed in the second insulating layer INS2 by a rubbing process or the like and the electric field formed between the first electrode ELT1 and the second electrode ELT2, the light emitting element LD provided to the light emitting area EMA can be aligned in a physical scheme and an electrical scheme. According to an embodiment of the present disclosure, compared with the light emitting device of the comparative example using only the physical alignment scheme or the electrical alignment scheme, the light emitting element LD can be more uniformly aligned between the first electrode ELT1 and the second electrode ELT2, and the contact ratio between the light emitting element LD and the first electrode ELT1 and the second electrode ELT2 can be enhanced. Therefore, the emission characteristics of the light emitting device, including emission brightness, emission efficiency and / or emission uniformity, can be enhanced.

[0162] Fig.11 is a plan view showing a display device according to an embodiment of the present disclosure. Fig.11 A display device is shown as an example of a device that can use the light emitting device according to the above embodiment as a light source, and specifically, a display panel PNL provided in the display device is shown. According to the embodiment, Fig.11 The structure of the display panel PNL is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit unit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further disposed on the display panel PNL.

[0163] Reference Fig.11 , the display panel PNL according to an embodiment of the present disclosure may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. Specifically, the substrate SUB may include a display area DA displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed on the substrate SUB in the display area DA.

[0164] In an embodiment, the display area DA may be disposed in the central portion of the display panel PNL, and the non-display area NDA may be disposed in the peripheral portion of the display panel PNL so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0165] The substrate SUB may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the substrate SUB may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal.

[0166] One area on the substrate SUB is defined as a display area DA in which the pixels PXL are disposed, and another area of ​​the substrate SUB is defined as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA surrounding the display area DA. Different types of lines and / or internal circuits connected to the pixels PXL may be disposed in the non-display area NDA.

[0167] Each of the pixels PXL may include at least one light source, and the at least one light source (for example, the light emitting device described as the light source in the foregoing embodiment) is driven by a corresponding scan signal and a corresponding data signal. For example, each of the pixels PXL may include at least one pair of first electrodes and second electrodes ( Figures 4 to 9 ELT1 and ELT2) and multiple light-emitting elements ( Figures 4 to 9 The first electrode and the second electrode are arranged at positions spaced apart from each other in each pixel region on the substrate SUB, and a plurality of light emitting elements are connected in parallel to each other between the first electrode and the second electrode. In addition, each of the light emitting elements may be an ultra-small rod-type light emitting diode having a small size ranging from nanometer to micrometer.

[0168] In an embodiment, each pixel PXL may be an active pixel, but the present disclosure is not limited thereto. For example, the type, structure and / or driving scheme of the pixel PXL in the display device according to the present disclosure is not particularly limited. In other words, each pixel PXL may form a pixel of various known passive or active light-emitting display devices.

[0169] FIG. 12A to FIG. 12C It is shown Fig.11 1 is a circuit diagram of different implementations of a pixel PXL. Specifically, FIG. 12A to FIG. 12C Different embodiments of the pixel PXL that can be provided in an active light emitting display device are shown. For example, FIG. 12A to FIG. 12C Each of the pixels PXL shown in FIG. 1 may be arranged Fig.11 The pixels PXL may have substantially the same or similar structures.

[0170] Reference Fig. 12A The pixel PXL according to an embodiment of the present disclosure may include a light emitting unit EMU configured to generate light having brightness corresponding to a data signal and a pixel circuit PXC configured to drive the light emitting unit EMU.

[0171] In an embodiment, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel to each other between a first power supply VDD and a second power supply VSS. Here, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, during at least one emission cycle of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0172] although Fig. 12A An embodiment is shown in which the light emitting elements LD of the light emitting unit EMU forming each pixel PXL are connected in parallel to each other in the same direction (e.g., forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in an embodiment, some of the light emitting elements LD may be connected to each other in the forward direction between the first power supply VDD and the second power supply VSS, and other light emitting elements LD may be connected to each other in the reverse direction. Alternatively, in an embodiment, at least one pixel PXL may include only a single light emitting element LD.

[0173] In an embodiment, a first end (eg, Figures 4 to 9 EP1) can be formed by a first electrode (e.g., Figures 4 to 9 The ELT1 of the light emitting element LD is commonly connected to the corresponding pixel circuit PXC, and is connected to the first power supply VDD through the pixel circuit PXC. Figures 4 to 9 EP2) can be formed by a second electrode (e.g., Figures 4 to 9 For convenience, hereinafter, the first electrode ELT1 and the second electrode ELT2 included in each light emitting unit EMU will be referred to as a first pixel electrode and a second pixel electrode, respectively.

[0174] Each light emitting unit EMU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed on the display area DA.

[0175] The pixel circuit PXC may be coupled to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0176] A first electrode of the first transistor (driving transistor; T1) may be coupled to a first power supply VDD, and a second electrode of the first transistor T1 may be coupled to the light emitting element LD via a first pixel electrode (i.e., a first electrode ELT1 of a corresponding light emitting unit EMU). Here, the first electrode and the second electrode of the first transistor T1 may be different electrodes. For example, if the first electrode is a source electrode, the second electrode is a drain electrode. A gate electrode of the first transistor T1 is coupled to a first node N1. The first transistor T1 may control a driving current to be provided to the light emitting unit EMU in response to a voltage of the first node N1.

[0177] A first electrode of the second transistor (switching transistor; T2) is coupled to the data line Dj, and a second electrode of the second transistor T2 is coupled to the first node N1. A gate electrode of the second transistor T2 is coupled to the scan line Si.

[0178] When a scan signal of a gate-on voltage (e.g., a low voltage) is provided from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj. During each frame period, a data signal of a corresponding frame is provided to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0179] One electrode of the storage capacitor Cst is coupled to the first power source VDD, and the other electrode of the storage capacitor Cst is coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period and maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0180] 12 , the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown as being formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0181] For example, Fig. 12B As shown in , both the first transistor T1 and the second transistor T2 can be N-type transistors. In addition to the fact that the connection positions of some circuit elements have been changed according to the change of the types of the first transistor T1 and the second transistor T2, Fig. 12B The configuration and operation of the pixel PXL shown in FIG. 1 are substantially similar to those of FIG. Fig. 12A Therefore, the configuration and operation of the pixel PXL will be omitted. Fig. 12B A detailed description of the pixel PXL.

[0182] The structure of the pixel circuit PXC is not limited to Fig. 12A and Fig. 12B In other words, the pixel circuit PXC may be formed by a well-known pixel circuit, which may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a well-known pixel circuit. Fig. 12C The pixel circuit PXC of the embodiment shown in FIG. 1 is configured in the same manner.

[0183] refer to Fig. 12C , the pixel circuit PXC may be coupled not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL disposed on the i-th row of the display area DA may also be coupled to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC may be coupled not only to the first power supply VDD and the second power supply VSS, but also to a third power supply. For example, the pixel circuit PXC may also be coupled to an initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0184] A first electrode of the first transistor T1 is coupled to the first power supply VDD via the fifth transistor T5, and a second electrode of the first transistor T1 is coupled to the light emitting unit EMU via the sixth transistor T6. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be provided to the light emitting unit EMU in response to a voltage of the first node N1.

[0185] The second transistor T2 is coupled between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is coupled to the corresponding scan line Si. When a scan signal of a gate-on voltage is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the data line Dj is transmitted to the first electrode of the first transistor T1.

[0186] The third transistor T3 is coupled between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is coupled to the corresponding scan line Si. When a scan signal of a gate-on voltage is provided from the scan line Si, the third transistor T3 may be turned on to electrically connect the second electrode of the first transistor T1 to the first node N1. Therefore, if the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0187] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is coupled to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal of a gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be a minimum voltage of the data signal or a voltage less than that.

[0188] The fifth transistor T5 is coupled between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal of a gate-off voltage (for example, a high voltage) is provided to the emission control line Ei, the fifth transistor T5 may be turned off, and the fifth transistor T5 may be turned on in other cases.

[0189] The sixth transistor T6 is coupled between the first transistor T1 and the light emitting unit EMU (e.g., coupled to the first pixel electrode (e.g., the second node N2) at one end of each of the light emitting elements LD). The gate electrode of the sixth transistor T6 is coupled to a corresponding emission control line, e.g., the i-th emission control line Ei. When an emission control signal of a gate-off voltage is provided to the emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0190] The seventh transistor T7 is connected between the light emitting unit EMU (for example, a first pixel electrode connected to one end of each of the light emitting elements LD) and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first pixel electrode.

[0191] The storage capacitor Cst is coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both a voltage of a data signal applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0192] Despite Fig. 12C In the embodiment, the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0193] The structure of the pixel PXL applicable to the present disclosure is not limited to FIG. 12A to FIG. 12C , and each pixel PXL may have various well-known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a well-known pixel circuit, which may have various structures and / or operate through various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first pixel electrode and the second pixel electrode of the light-emitting unit EMU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0194] Fig.13 It is shown Fig.11 A plan view of a pixel PXL, and specifically, Fig.13 is a plan view showing a light emitting unit EMU of each pixel PXL. Fig.14 is along Fig.13 A cross-sectional view taken along line III-III'.

[0195] In an embodiment, Fig.13 The light emitting unit EMU shown in FIG. 1 may be the same as that according to the above-mentioned embodiment (for example, Figure 4 The configuration of the light-emitting device of the embodiment shown in the etc. is basically similar or the same configuration. Fig.14 The display element layer LDL shown in FIG. Fig.13 The cross section of the light emitting unit EMU can be substantially similar to or identical to the cross section of the light emitting unit EMU according to Figure 7 The light emitting device of the embodiment shown in the above is configured in a cross-sectional manner. Fig.13 and Fig.14 In the drawings, the same reference numerals are used to denote Figure 4 and Figure 7 The components of the embodiments are the same or similar components, and their detailed description will be omitted.

[0196] Reference Figure 13 to Figure 14 , each pixel PXL may include a pixel circuit layer PCL and a display element layer LDL stacked on a substrate SUB.

[0197] In an embodiment, the pixel circuit layer PCL may include a plurality of circuit elements disposed in the display area DA. For example, the pixel circuit layer PCL may include a plurality of circuit elements formed in the corresponding pixel area PXA to form a corresponding pixel circuit (eg, FIG. 12A to FIG. 12C of PXC).

[0198] For example, the pixel circuit layer PCL may include at least one transistor T and a storage capacitor Cst disposed in each pixel region PXA. Fig.14 Only any one transistor T of the transistors provided in the pixel circuit PXC is shown as a representative example, and the transistors used to form each pixel circuit PXC may have substantially the same or similar cross-sectional structures. In addition, in the present disclosure, the structure of each transistor T is not limited to Fig.14 For example, each transistor T may have various well-known cross-sectional structures. In addition, in the embodiments of the present disclosure, a plurality of transistors configured to configure a corresponding pixel circuit PXC may have different types and / or structures.

[0199] In addition, the pixel circuit layer PCL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a passivation layer PSV sequentially stacked on one surface of the substrate SUB. In an embodiment, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the passivation layer PSV may be sequentially stacked between the substrate SUB and the display element layer LDL. The pixel circuit layer PCL may further include at least one buffer layer BFL disposed between the substrate SUB and the circuit element. In an embodiment, at least one of the buffer layer BFL, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the passivation layer PSV may be formed on the entire area of ​​one surface of the substrate SUB including the display area DA and the non-display area NDA.

[0200] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into each transistor T. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0201] In an embodiment, each transistor T may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Fig.14 An embodiment in which the first transistor electrode ET1 and the second transistor electrode ET2 are formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 forming at least one transistor T disposed in each pixel area PXA may be integrally coupled to the semiconductor layer SCL of the corresponding transistor T.

[0202] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, any one of the first region and the second region may be a source region, and the other may be a drain region.

[0203] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0204] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the first interlayer insulating layer ILD1 and overlap at least one region of the semiconductor layer SCL.

[0205] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL, and at least one insulating layer (e.g., a plurality of insulating layers) may be interposed between the first transistor electrode ET1 and the second transistor electrode ET2 and the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL, and the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may be interposed between the first transistor electrode ET1 and the second transistor electrode ET2 and the semiconductor layer SCL. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be in contact with the first region and the second region of the semiconductor layer SCL through corresponding contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, respectively.

[0206] In an embodiment, the storage capacitor Cst may include a first capacitor electrode CSE1 and a second capacitor electrode CSE2, which are disposed at positions spaced apart from each other on different layers. For example, the first capacitor electrode CSE1 may be disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The second capacitor electrode CSE2 may be disposed on at least one conductive layer forming the transistor T, for example, on the same layer as the semiconductor layer SCL, the gate electrode GE, and at least one of the first transistor electrode ET1 and the second transistor electrode ET2. For example, the second capacitor electrode CSE2 together with the gate electrode GE of the transistor T may be disposed between the gate insulating layer GI and the first interlayer insulating layer ILD1.

[0207] Although for descriptive purposes, Fig.14 It is shown that each of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 is formed of a single layer, but the present disclosure is not limited thereto. For example, at least one of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be formed of a plurality of layers, and the stacking structure and / or position of the first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be changed in various ways.

[0208] The display element layer LDL is a layer on which the light emitting unit EMU of each pixel PXL is disposed, and may be formed in the same manner as described in reference 1. Figure 4 and Figure 7 The light emitting device of the described embodiment is configured in the same manner. For example, the display element layer LDL may include a first electrode ELT1 and a second electrode ELT2 disposed in each pixel region PXA over the pixel circuit layer PCL and a plurality of light emitting elements LD connected in parallel to each other between the first electrode ELT1 and the second electrode ELT2. For example, the display element layer LDL may include a plurality of light emitting elements LD disposed in each pixel region PXA over the pixel circuit layer PCL and configuring each light emitting unit EMU.

[0209] In an embodiment, the first electrode ELT1 (ie, the first pixel electrode) of the display element layer LDL may be electrically connected to at least one circuit element disposed in the corresponding pixel area PXA. For example, the first pixel electrode may be connected to the at least one circuit element disposed in the corresponding pixel area PXA through at least one contact hole (eg, through the passivation layer PSV) Fig.13 The first contact hole CH1) is electrically connected to Fig. 12A and Fig. 12B The first transistor T1 shown in Fig. 12C The sixth transistor T6 and the seventh transistor T7 are shown in FIG.

[0210] The second electrode ELT2 (i.e., the second pixel electrode) of the display element layer LDL may be electrically connected to a power line (or control line) not shown through a second contact hole CH2, etc. In an embodiment, the power line may be provided on the same layer as the layer of at least one conductive layer formed on the pixel circuit layer PCL, and electrically connected to the second electrode ELT2 of the display element layer LDL through the second contact hole CH2, but the present disclosure is not limited thereto.

[0211] As described in the aforementioned embodiment, the light emitting unit EMU of each pixel PXL may be configured by a light emitting device using at least one light emitting element LD. In addition, in the embodiment of the present disclosure, each pixel region PXA of the display element layer LDL may include at least one groove GRV formed in the insulating layer INS (specifically, the second insulating layer INS2 formed of an organic insulating layer) in the first direction DR1 intersecting the first electrode ELT1 and the second electrode ELT2. Therefore, the emission characteristics of the display device can be enhanced.

[0212] Since the light emitting device according to the embodiment of the present disclosure has been described above, a detailed description of each light emitting unit EMU corresponding to the light emitting device and the display element layer LDL for configuring the light emitting unit EMU will be omitted.

[0213] In the light emitting device, the method of manufacturing the light emitting device, and the display device including the light emitting device according to various embodiments of the present disclosure, a plurality of light emitting elements LD can be uniformly aligned with high efficiency between the first electrode ELT1 and the second electrode ELT2 disposed in each light emitting region EMA or the pixel region PXA. Therefore, the emission characteristics of the light emitting device and the display device including the light emitting device, for example, emission brightness, emission efficiency, and / or emission uniformity, can be enhanced.

[0214] Although the scope of the present disclosure has been described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0215] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A light emitting device, comprising: substrate; A first electrode and a second electrode, disposed on the substrate and spaced apart from each other; an insulating layer disposed on the substrate on which the first electrode and the second electrode are formed, and including a groove at least partially overlapping the first electrode and the second electrode in a plan view, and a first contact portion and a second contact portion configured to expose a portion of the first electrode and a portion of the second electrode, respectively; a plurality of light emitting elements disposed on the groove and between the first electrode and the second electrode, each of the light emitting elements comprising a first end and a second end electrically coupled to the first electrode and the second electrode, respectively; a first contact electrode electrically coupled to the first end of the light emitting element and electrically coupled to the first electrode through the first contact portion; as well as A second contact electrode is electrically coupled to the second end of the light emitting element and is electrically coupled to the second electrode through the second contact portion.

2. The light emitting device according to claim 1, wherein: Each of the light emitting elements has a size ranging from a nanometer scale to a micrometer scale, and includes a rod-type light emitting diode having a length extending along the groove.

3. The light emitting device according to claim 2, wherein: The width of the groove is greater than the diameter or width of one of the light emitting elements.

4. The light emitting device according to claim 1, wherein: The groove is partially disconnected at least in a portion of a region overlapping the first contact portion and the second contact portion.

5. The light emitting device according to claim 1, wherein: The groove includes a partially open opening.

6. The light emitting device according to claim 1, wherein: The groove is partially removed in regions above the first electrode and the second electrode.

7. The light emitting device according to claim 1, wherein: The first electrode and the second electrode are disposed in parallel with each other in a region on the substrate, and each of the first electrode and the second electrode extends in a direction intersecting the groove. The light emitting device according to claim 1 , wherein the groove comprises a plurality of grooves.

9. The light emitting device according to claim 1, further comprising: a first partition wall disposed between the substrate and the first electrode; as well as The second partition wall is disposed between the substrate and the second electrode.

10. A light emitting device, comprising: substrate; A first electrode and a second electrode, disposed on the substrate and spaced apart from each other; an insulating layer disposed on the substrate on which the first electrode and the second electrode are formed, and including an opening at least partially overlapping the first electrode and the second electrode in a plan view, and configured to expose a portion of the first electrode and a portion of the second electrode and a first contact portion and a second contact portion; a plurality of light emitting elements disposed on the opening and between the first electrode and the second electrode, each of the light emitting elements comprising a first end and a second end electrically coupled to the first electrode and the second electrode, respectively; a first contact electrode electrically coupled to the first end of the light emitting element and electrically coupled to the first electrode through the first contact portion; as well as A second contact electrode is electrically coupled to the second end of the light emitting element and is electrically coupled to the second electrode through the second contact portion.

11. The light emitting device according to claim 10, wherein: Each of the light emitting elements has a size ranging from a nanometer scale to a micrometer scale, and includes a rod-type light emitting diode.

12. The light emitting device according to claim 10, further comprising: A first insulating pattern is disposed on the light emitting element and between the first contact electrode and the second contact electrode. 13 . The light emitting device of claim 12 , further comprising a second insulating pattern configured to cover an upper portion of the first insulating pattern and the first contact electrode.

14. The light emitting device according to claim 13, wherein: One end of the second contact electrode is disposed on one end of the second insulating pattern adjacent to the second end of one of the light emitting elements.

15. The light emitting device according to claim 10, wherein: The opening overlaps the first contact portion and the second contact portion in a plan view, but does not overlap the light emitting element.

16. The light emitting device according to claim 15, wherein: The opening includes a plurality of openings.

17. The light emitting device according to claim 10, wherein: The opening exposes at least a portion of the first electrode and at least a portion of the second electrode.

18. The light emitting device according to claim 13, wherein: The opening overlaps the second insulation pattern in a plan view, but does not overlap the first insulation pattern.

19. The light emitting device according to claim 16, wherein: The plurality of openings are spaced apart from one another.

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