Pixel and organic light emitting display device including same

Abstract

A pixel and an organic light emitting display device including the same are provided. The pixel includes: a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region; a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region; a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region; the shielding pattern is overlapped with the first sub-source region and the second sub-drain region and is not overlapped with the first sub-channel region, and the width of the first sub-channel region is larger than that of the second sub-channel region.

Description

[0001] This application is a divisional application of the invention patent application "Pixel and organic light-emitting display device including the pixel" with application date of June 14, 2019 and application number 201910514975.9. Technical Field

[0002] The present disclosure herein relates to a pixel and an organic light emitting display device including the pixel. Background Art

[0003] The organic light emitting display device includes a plurality of pixels. Each of the plurality of pixels includes an organic light emitting diode and a circuit part for controlling the organic light emitting diode. The circuit part includes at least a switching transistor, a driving transistor and a storage capacitor.

[0004] The organic light emitting diode includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode. When a voltage greater than a threshold voltage is applied to the organic light emitting layer between the anode and the cathode, the organic light emitting diode emits light. Summary of the invention

[0005] The present disclosure provides a pixel capable of improving display quality and an organic light emitting display device having the pixel.

[0006] An embodiment of the present disclosure provides a pixel, the pixel comprising: a light-emitting diode, comprising an anode and a cathode; a first transistor, comprising a first drain region electrically connected to the anode of the light-emitting diode, a first gate electrode, a first channel region overlapping with the first gate electrode in a plan view, and a first source region facing the first drain region, and the first channel region is located between the first drain region and the first source region; a first sub-transistor, comprising a first sub-gate electrode, a first sub-channel region overlapping with the first sub-gate electrode in a plan view, a first sub-drain region connected to the first gate electrode, and a first sub-drain region facing the first sub-drain region a sub-source region, and the first sub-channel region is located between the first sub-drain region and the first sub-source region; a second sub-transistor, including a second sub-gate electrode, a second sub-channel region overlapping with the second sub-gate electrode in a plan view, a second sub-drain region connected to the first sub-source region, and a second sub-source region facing the second sub-drain region, and the second sub-channel region is located between the second sub-drain region and the second sub-source region; and a shielding pattern overlapping with the first sub-source region and the second sub-drain region in a plan view, and not overlapping with the first sub-channel region, wherein the width of the first sub-channel region is greater than the width of the second sub-channel region.

[0007] The shielding pattern may be configured to receive a driving voltage.

[0008] The shielding pattern may overlap the first sub-source region and the second sub-drain region to form an auxiliary capacitor.

[0009] The shielding pattern may not overlap the second sub-channel region in a plan view.

[0010] The pixel may further include an extension portion which is located on a layer different from that of the first gate electrode and overlaps the first gate electrode to form a capacitor.

[0011] The shielding pattern may be located on the same layer as the extending portion.

[0012] A length of the first sub-channel region may be shorter than a length of the second sub-channel region.

[0013] The pixel may further include a sixth transistor including a sixth source region connected to the first drain region of the first transistor, a sixth drain region connected to the anode of the light emitting diode, and a sixth channel region between the sixth source region and the sixth drain region.

[0014] The pixel may further include a connection member connected to the first gate electrode and located on a layer different from that of the first gate electrode, wherein the first sub-drain region is connected to the connection member.

[0015] The pixel may further include an upper shielding pattern located on the same layer as the connection member and overlapping the first sub-source region and the second sub-drain region in a plan view.

[0016] The pixel may further include a fourth transistor, the fourth transistor including a fourth gate electrode, a fourth channel region overlapping the fourth gate electrode in a plan view, a fourth drain region connected to the first gate electrode, and a fourth source region facing the fourth drain region, and the fourth channel region is located between the fourth drain region and the fourth source region.

[0017] In an embodiment of the present disclosure, a pixel includes: a light emitting diode including an anode and a cathode; a first transistor including a first drain region electrically connected to the anode of the light emitting diode, a first gate electrode, a first channel region overlapping with the first gate electrode in a plan view, and a first source region facing the first drain region, and the first channel region is located between the first drain region and the first source region; a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping with the first sub-gate electrode in a plan view, a first sub-drain region connected to the first gate electrode, and a first sub-source region facing the first sub-drain region, and the first sub-channel region is located between the first sub-drain region and the first sub-source region. regions; a second sub-transistor, including a second sub-gate electrode, a second sub-channel region overlapping with the second sub-gate electrode in a plan view, a second sub-drain region connected to the first sub-source region, and a second sub-source region facing the second sub-drain region, and the second sub-channel region is located between the second sub-drain region and the second sub-source region; a shielding pattern overlapping with the first sub-source region and the second sub-drain region in a plan view, and not overlapping with the first sub-channel region; and an upper shielding pattern located on a layer different from the layer of the shielding pattern and overlapping with the first sub-source region and the second sub-drain region in a plan view, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.

[0018] The pixel may further include a fourth transistor, the fourth transistor including a fourth gate electrode, a fourth channel region overlapping the fourth gate electrode in a plan view, a fourth drain region connected to the first gate electrode, and a fourth source region facing the fourth drain region, and the fourth channel region is located between the fourth drain region and the fourth source region.

[0019] Each of the shielding pattern and the upper shielding pattern may be configured to receive a driving voltage.

[0020] The shielding pattern may overlap the first sub-source region and the second sub-drain region to form an auxiliary capacitor, and the upper shielding pattern may overlap the first sub-source region and the second sub-drain region to form a second auxiliary capacitor.

[0021] The pixel may further include an extension portion located on a layer different from that of the first gate electrode, wherein the extension portion overlaps the first gate electrode to form a capacitor.

[0022] The shielding pattern may be located on the same layer as the extending portion.

[0023] In an embodiment of the present disclosure, an organic light emitting display device includes: a scan driving circuit configured to sequentially provide scan signals to scan lines, the scan lines extending in a first direction and arranged in a second direction orthogonal to the first direction; a data driving circuit configured to provide data signals to data lines, the data lines being insulated and crossing the scan lines; and a pixel including a light emitting diode having an anode and a cathode and a circuit portion configured to control light emission of the light emitting diode, the circuit portion including: a first transistor including a first drain region electrically connected to the anode of the light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region facing the first drain region, and the first channel region is located between the first drain region and the first source region; A first sub-transistor comprises a first sub-gate electrode, a first sub-channel region overlapping with the first sub-gate electrode in a plan view, a first sub-drain region connected to the first gate electrode, and a first sub-source region facing the first sub-drain region, and the first sub-channel region is located between the first sub-drain region and the first sub-source region; a second sub-transistor comprises a second sub-gate electrode, a second sub-channel region overlapping with the second sub-gate electrode in a plan view, a second sub-drain region connected to the first sub-source region, and a second sub-source region facing the second sub-drain region, and the second sub-channel region is located between the second sub-drain region and the second sub-source region; and a shielding pattern overlapping with the first sub-source region and the second sub-drain region in a plan view, and not overlapping with the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.

[0024] The shielding pattern may be configured to receive a driving voltage.

[0025] The circuit portion may further include an upper shielding pattern located on a layer different from that of the shielding pattern and overlapping the first sub-source region and the second sub-drain region in a plan view.

[0026] Therefore, the organic light emitting display device of the claimed embodiment can reduce leakage current through the third transistor by increasing the capacitance between the connection node of the third transistor having the dual gate electrode and the power supply voltage wiring. Therefore, the display quality of the organic light emitting display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain aspects of the present disclosure. In the drawings: Figure 1 is a block diagram showing an organic light emitting display device according to an embodiment of the present disclosure; Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure; Figure 3 is shown for driving Figure 2 A waveform diagram of a driving signal of a pixel shown in ; Figure 4 is a plan view of one pixel of an organic light emitting display device according to an embodiment; Figure 5 yes Figure 4 A cross-sectional view of the organic light emitting display device shown in taken along line VI-VI'; Figure 6 is used to explain Figure 2 An equivalent circuit diagram of an auxiliary capacitor and a parasitic capacitance formed by the first sub-transistor and the second sub-transistor shown in FIG. Figure 7 is a waveform diagram showing changes in voltage levels of the third node and the driving gate node according to changes in the scanning signal; Figure 8 and Fig. 9 yes Figure 4 An enlarged plan view of a first sub-transistor and a second sub-transistor of a pixel shown in FIG. Fig.10 An example is shown in which the length of the first sub-channel region of the first sub-transistor is shorter than the length of the second sub-channel region of the second sub-transistor; Fig.11 is a plan view of a portion of a pixel according to an embodiment of the present disclosure; Fig.12 yes Fig.11 A cross-sectional view of the organic light emitting display device shown in FIG. 1 taken along line VII-VII′; Fig.13 is a plan view of a portion of a pixel according to an embodiment of the present disclosure; and Fig.14 yes Fig.13 0 is a cross-sectional view of the organic light emitting display device shown in taken along line VIII-VIII′. DETAILED DESCRIPTION

[0028] In this specification, when a component (or region, layer, part (portion), etc.) is referred to as being "on", "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may be present between them.

[0029] The same reference numerals denote the same elements. In addition, in the drawings, the thickness, proportion, and size of components are exaggerated for efficient description.

[0030] “And / or” includes all of one or more combinations defined by the relevant components.

[0031] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, a first component may be referred to as a second component, and vice versa, without departing from the scope of the present disclosure. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In addition, terms such as “below”, “lower side”, “on”, and “upper side” are used to describe the relationship of the configurations shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. Generally, terms defined in dictionaries should be considered to have the same meaning as the contextual meaning of the relevant field, and unless explicitly defined herein, should not be understood abnormally or as having an overly formal meaning.

[0034] In various embodiments of the present disclosure, the terms "include" or its variations, "comprises" or its variations specify properties, regions, fixed numbers, steps, processes, elements and / or components, but do not exclude other properties, regions, fixed numbers, steps, processes, elements and / or components.

[0035] Hereinafter, another embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0036] Figure 1 is a block diagram of an organic light emitting display device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The organic light emitting display device includes a timing controller TC, a scan driving circuit SDC, a data driving circuit DDC and a display panel DP.

[0038] The timing controller TC receives an input image signal and converts the data format of the input image signal according to the interface specification with the data driving circuit DDC to generate image data RGB. The timing controller TC outputs a scan control signal SCS, the image data RGB and a data control signal DCS.

[0039] The scan drive circuit SDC receives a scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal for starting the operation of the scan drive circuit SDC and a clock signal for determining the output timing of the signal. The scan drive circuit SDC generates a plurality of scan signals and sequentially outputs the plurality of scan signals to a plurality of scan lines SL1 to SLn, which will be described later. In addition, the scan drive circuit SDC generates a plurality of light emitting control signals in response to the scan control signal SCS and outputs the plurality of light emitting control signals to a plurality of light emitting lines EL1 to ELn, which will be described later.

[0040] although Figure 1 , it is shown that a plurality of scan signals and a plurality of light emitting control signals are output from one scan driving circuit SDC, but the present disclosure is not limited thereto. In another embodiment, a plurality of scan driving circuits may divide and output a plurality of scan signals, and may divide and output a plurality of light emitting control signals. In addition, in another embodiment, a driving circuit for generating and outputting a plurality of scan signals and a driving circuit for generating and outputting a plurality of light emitting control signals may be separately classified.

[0041] The data driving circuit DDC receives the data control signal DCS and the image data RGB from the timing controller TC. The data driving circuit DDC converts the image data RGB into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the grayscale value of the image data RGB.

[0042] The display panel DP includes scan lines SL1 to SLn, emission lines EL1 to ELn, data lines DL1 to DLm, and pixels PX. The scan lines SL1 to SLn extend in a first direction DR1 and are arranged in a second direction DR2 orthogonal to the first direction DR1.

[0043] A plurality of light emitting lines EL1 to ELn may be arranged in parallel with the scan lines SL1 to SLn. The data lines DL1 to DLm insulatedly cross the scan lines SL1 to SLn.

[0044] Each pixel PX among the plurality of pixels PX is connected to a corresponding scan line among the scan lines SL1 to SLn, a corresponding light emitting line among the light emitting lines EL1 to ELn, and a corresponding data line among the data lines DL1 to DLm.

[0045] Each pixel PX receives a first driving voltage ELVDD and a second driving voltage ELVSS having a level lower than that of the first driving voltage ELVDD. Each pixel PX is connected to a driving voltage line 172 to which the first driving voltage ELVDD is applied. Each pixel PX is connected to an initialization voltage line 159 (see FIG. 159 ) for receiving an initialization voltage Vint. Figure 2 ).

[0046] Each pixel PX among the plurality of pixels PX may be electrically connected to two corresponding scan lines. Figure 1 As shown in FIG. 1 , the pixels PX of the second pixel row may be connected to the first scan line SL1 and the second scan line SL2 .

[0047] In an embodiment of the present disclosure, the display panel DP may further include a plurality of dummy scan lines. The display panel DP may further include a dummy scan line connected to a pixel PX of a first pixel row and a dummy scan line connected to a pixel PX of an nth (e.g., last) pixel row. In addition, the pixels (hereinafter referred to as pixels of a pixel column) connected to one of the data lines DL1 to DLm may be connected to each other. For example, two adjacent pixels in a pixel column may be electrically connected to each other.

[0048] Each pixel PX of the plurality of pixels PX includes an organic light emitting diode and a circuit portion for controlling light emission of the organic light emitting diode. The circuit portion may include a plurality of thin film transistors and capacitors. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a thin film transistor formed by the same process as that of the circuit portion.

[0049] Scan lines SL1 to SLn, light emitting lines EL1 to ELn, data lines DL1 to DLm, driving voltage lines 172, initialization voltage lines 159, pixels PX, scanning driving circuits SDC, and data driving circuits DDC may be formed on a base substrate by one or more instances of a photolithography process. An insulating layer may be formed on a base substrate by multiple instances of a deposition process or a coating process. Each insulating layer may be a thin film for covering the entire display panel DP, or may include at least one insulating pattern superimposed with a specific configuration of the display panel DP. The insulating layer includes an organic layer and / or an inorganic layer. In addition, a sealing layer for protecting the pixel PX may also be formed on the base substrate.

[0050] The display panel DP receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD may be provided to the plurality of pixels PX through the driving voltage line 172. The second driving voltage ELVSS may be provided to the plurality of pixels PX through an electrode or a power supply line formed on the display panel DP.

[0051] The display panel DP receives an initialization voltage Vint. The initialization voltage Vint may be provided to the plurality of pixels PX through an initialization voltage line 159.

[0052] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. Figure 3 It is used to explain Figure 2 A timing diagram of the operation of a pixel of an organic light emitting display device.

[0053] Figure 2 Shows the connection to Figure 1 0 is an equivalent circuit diagram of a pixel PXij including an i-th data line 171 among a plurality of data lines DL1 to DLm, a j-th scan line 151 among a plurality of scan lines SL1 to SLn, and a j-th light emitting line 153 among a plurality of light emitting lines EL1 to ELn. Figure 1 Each of the plurality of pixels PX shown in FIG. 1 may have a Figure 2 The equivalent circuit configuration of the pixel PXij shown in FIG. 1 is the same as the equivalent circuit of the pixel PXij shown in FIG. In the present embodiment, the circuit portion of the pixel PXij includes seven transistors T1 to T7 and a capacitor Cst. In addition, the first transistor T1 to the seventh transistor T7 may be a P-type channel transistor such as a PMOS transistor. However, the present disclosure is not limited thereto, and at least one of the first transistor T1 to the seventh transistor T7 may be an N-type channel transistor. In addition, the circuit configuration of the pixel according to the present disclosure is not limited to Figure 2 . Figure 2 The circuit portion shown in is only an example, and the configuration of the circuit portion may be modified and implemented.

[0054] Reference Figure 2 , a pixel PXij of the organic light emitting display device according to the embodiment includes signal lines 151, 152, 153, 154, 171, and 172. The pixel PXij may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 connected to the plurality of signal lines 151, 152, 153, 154, 171, and 172, a capacitor Cst, and at least one light emitting diode ED. In this embodiment, an example in which one pixel PXij includes one light emitting diode ED will be described.

[0055] The signal lines 151 , 152 , 153 , 154 , 171 , and 172 include scan lines 151 , 152 , and 154 , a control line (light emitting line) 153 , a data line 171 , and a driving voltage line 172 .

[0056] Scan lines 151, 152, and 154 may transmit scan signals GWj, GIj, and GBj, respectively. Scan signals GWj, GIj, and GBj may deliver gate-on and gate-off voltages capable of turning on / off transistors T2, T3, T4, and T7 included in pixels PXij.

[0057] The scan lines 151, 152, and 154 connected to the pixel PXij may include a first scan line 151 capable of transmitting a scan signal GWj, a second scan line 152 capable of transmitting a scan signal GIj having a gate-on voltage at a timing different from that of the first scan line 151, and a third scan line 154 capable of transmitting a scan signal GBj. In the present embodiment, an example in which the second scan line 152 transmits a gate-on voltage at a timing earlier than that of the first scan line 151 will be mainly described. For example, when the scan signal GWj is a j-th scan signal (Sj) (j is a natural number of 1 or greater) among the scan signals applied during one frame, the scan signal GIj may be a previous scan signal such as a (j-1)-th scan signal (S(j-1)), and the scan signal GBj may be a (j-1)-th scan signal (S(j-1)). However, the present disclosure is not limited thereto, and the scan signal GBj may be a scan signal other than the (j-1)-th scan signal (S(j-1)).

[0058] The control line 153 may transmit a control signal and may transmit a light emitting control signal capable of controlling light emission of a light emitting diode ED included in the pixel PXij. The light emitting control signal transmitted from the control line 153 may have a waveform different from that of a scan signal transmitted from the scan lines 151, 152, and 154. The data line 171 may transmit a data signal Di, and the driving voltage line 172 may transmit a first driving voltage ELVDD. The data signal Di may have different voltage levels according to a video signal input to the organic light emitting display device, and the first driving voltage ELVDD may have a substantially constant level.

[0059] The first scan line 151 can transmit the scan signal GWj to the second transistor T2 and the third transistor T3, the second scan line 152 can transmit the scan signal GIj to the fourth transistor T4, the third scan line 154 can transmit the scan signal GBj to the seventh transistor T7, and the control line 153 can transmit the light emitting control signal EMj to the fifth transistor T5 and the sixth transistor T6.

[0060] The gate electrode G1 of the first transistor T1 is connected to one end Cst1 of the capacitor Cst through the driving gate node GN, the source electrode S1 of the first transistor T1 is connected to the driving voltage line 172 through the fifth transistor T5, and the drain electrode D1 of the first transistor T1 is electrically connected to the anode of the light emitting diode ED through the sixth transistor T6. The first transistor T1 can receive the data signal Di transmitted from the data line 171 according to the switching operation of the second transistor T2, and can supply the driving current Id to the light emitting diode ED.

[0061] A gate electrode G2 of the second transistor T2 is connected to the first scan line 151, a source electrode S2 of the second transistor T2 is connected to the data line 171, a drain electrode D2 of the second transistor T2 is connected to the source electrode S1 of the first transistor T1 and is connected to the driving voltage line 172 through the fifth transistor T5. The second transistor T2 is turned on according to the scan signal GWj received through the first scan line 151, and supplies the data signal Di transmitted from the data line 171 to the source electrode S1 of the first transistor T1.

[0062] The third transistor T3 may have a dual-gate structure in which a first sub-transistor T3_1 and a second sub-transistor T3_2 are connected in series between a driving gate node GN and a drain electrode D1 of the first transistor T1. A first sub-gate electrode G3_1 of the first sub-transistor T3_1 and a second sub-gate electrode G3_2 of the second sub-transistor T3_2 are connected to a first scan line 151. A first sub-drain electrode D3_1 of the first sub-transistor T3_1 is commonly connected to a drain electrode D4 of a fourth transistor T4, one end Cst1 of a capacitor Cst, and a gate electrode G1 of the first transistor T1. A second sub-source electrode S3_2 of the second sub-transistor T3_2 is connected to the drain electrode D1 of the first transistor T1 and to the anode of the light emitting diode ED through a sixth transistor T6. A first sub-source electrode S3_1 of the first sub-transistor T3_1 and a second sub-drain electrode D3_2 of the second sub-transistor T3_2 are connected to each other. For example, the third transistor T3 may have a structure in which the first sub-gate electrode G3_1 of the first sub-transistor T3_1 and the second sub-gate electrode G3_2 of the second sub-transistor T3_2 are connected to each other on the gate insulating layer by wiring, and a high-concentration region having high conductivity is provided between the gates as a gate common region. In addition, in another embodiment, the third transistor T3 may be implemented as one transistor or three or more transistors.

[0063] The third transistor T3 is turned on according to the scan signal GWj received through the first scan line 151 to connect the gate electrode G1 and the drain electrode D1 of the first transistor T1 so that the first transistor T1 is connected as a diode (eg, diode connection).

[0064] The gate electrode G4 of the fourth transistor T4 is connected to the second scan line 152, the source electrode S4 of the fourth transistor T4 is connected to the terminal of the initialization voltage line 159 to receive the initialization voltage Vint, and the drain electrode D4 of the fourth transistor T4 is connected to one end Cst1 of the capacitor Cst, the gate electrode G1 of the first transistor T1, and the drain electrode of the third transistor T3 (for example, connected to D3_1). The fourth transistor T4 is turned on according to the scan signal GIj received through the second scan line 152 to transmit the initialization voltage Vint to the gate electrode G1 of the first transistor T1, so that the fourth transistor T4 can perform an initialization operation for initializing the voltage of the gate electrode G1 of the first transistor T1. The fourth transistor T4 may have the same dual-gate structure as the third transistor T3.

[0065] A gate electrode G5 of the fifth transistor T5 is connected to the control line 153 , a source electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172 , and a drain electrode D5 of the fifth transistor T5 is connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2 .

[0066] The gate electrode G6 of the sixth transistor T6 is connected to the control line 153, the source electrode S6 of the sixth transistor T6 is connected to the drain electrode D1 of the first transistor T1 and the source electrode (e.g., S3_2) of the third transistor T3, and the drain electrode D6 of the sixth transistor T6 is electrically connected to the anode of the light emitting diode ED. The fifth transistor T5 and the sixth transistor T6 are concurrently or simultaneously turned on according to the light emitting control signal EMj received through the control line 153, and through this, the first driving voltage ELVDD can be compensated by the diode-connected first transistor T1 and can be transmitted to the light emitting diode ED.

[0067] The gate electrode G7 of the seventh transistor T7 is connected to the third scan line 154, the source electrode S7 of the seventh transistor T7 is connected to the drain electrode D6 of the sixth transistor T6 and the anode of the light emitting diode ED, the drain electrode D7 of the seventh transistor T7 is connected to the terminal of the initialization voltage line 159 to receive the initialization voltage Vint, and is connected to the source electrode S4 of the fourth transistor T4. In other embodiments, the gate electrode G7 of the seventh transistor T7 may be connected to a separate control line.

[0068] As described above, one end Cst1 of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other end Cst2 of the capacitor Cst is connected to the driving voltage line 172. The cathode of the light emitting diode ED may be connected to a terminal for transmitting the second driving voltage ELVSS. The structure of the pixel PXij according to other embodiments is not limited to Figure 2 The structure shown in FIG. 1 may variously modify the number of transistors, the number of capacitors, and the connection relationship in one pixel PXij.

[0069] Will refer to Figure 2 and Figure 3 Hereinafter, an example in which the first to seventh transistors T1 to T7 are P-channel transistors will be described, and an operation of one frame will be described.

[0070] Reference Figure 2 and Figure 3 , scan signals (S(j-1), Sj, and (Sj+1)) each of which is a low level are sequentially applied to the first scan line 151 connected to the pixel PXij as the scan signal GWj within one frame.

[0071] During the initialization period, a low-level scan signal GIj is supplied through the second scan line 152. The scan signal GIj may be, for example, a (j-1)th scan signal (S(j-1)). The fourth transistor T4 is turned on in response to the low-level scan signal GIj, and the initialization voltage Vint is transmitted to the gate electrode G1 of the first transistor T1 through the fourth transistor T4, and the initialization voltage Vint initializes the first transistor T1.

[0072] Next, when a low-level scan signal GWj is supplied through the first scan line 151 during the data programming and compensation period, the second transistor T2 and the third transistor T3 are turned on in response to the low-level scan signal GWj. The scan signal GWj may be, for example, the j-th scan signal (Sj). At this time, the first transistor T1 is diode-connected through the turned-on third transistor T3 and is biased in the forward direction. Then, the compensation voltage Di-|Vth| (for example, see Figure 7 ) (the compensation voltage Di-|Vth| is a voltage corresponding to the data signal Di from the data line 171 reduced by the threshold voltage Vth of the first transistor T1) is applied to the gate electrode G1 of the first transistor T1. That is, the gate voltage applied to the gate electrode G1 of the first transistor T1 may be the compensation voltage Di-|Vth|.

[0073] The first driving voltage ELVDD and the compensation voltage Di-|Vth| are applied to respective ends of the capacitor Cst, and charges corresponding to a voltage difference between both ends may be stored in the capacitor Cst.

[0074] During the bypass period, the seventh transistor T7 receives a low-level scan signal GBj through the third scan line 154 and is turned on. The scan signal GBj may be the (j-1)th scan signal (S(j-1)). A portion of the drive current Id may pass through the seventh transistor T7 as a bypass current Ibp due to the turned-on seventh transistor (bypass transistor) T7.

[0075] Even when the minimum current of the driving transistor T1 for displaying a black image flows as a driving current, if the light emitting diode ED emits light, a black image cannot be properly displayed. Therefore, the bypass transistor T7 of the organic light emitting display device according to the present embodiment disperses a part of the minimum current of the driving transistor T1 as a bypass current Ibp to another current path other than the current path through the light emitting diode ED. Here, the minimum current of the driving transistor T1 refers to the current under the condition that the driving transistor T1 is turned off because the gate-source voltage (Vgs) of the driving transistor T1 is less than the threshold voltage (Vth). The minimum driving current (for example, a current of about 10pA or less) under the condition that the driving transistor T1 is turned off is transmitted to the light emitting diode ED to appear as a black brightness image.

[0076] It can be said that when the minimum driving current for displaying a black image flows, the bypass transmission of the bypass current Ibp has a large effect, and when a large driving current for displaying an image such as a normal image or a white image flows, the bypass current Ibp has almost no effect. Therefore, when the driving current for displaying a black image flows, the light-emitting current Ied of the light-emitting diode ED (the amount of the bypass current Ibp output through the bypass transistor T7 is subtracted from the driving current Id) can have a minimum current amount at a level that can reliably represent a black image. Therefore, by using the bypass transistor T7, an accurate black brightness image can be achieved, so that the contrast of the organic light-emitting display device can be improved. In this embodiment, the scan signal GBj as a bypass signal is the same as the previous scan signal (S(j-1)), but other embodiments are not necessarily limited to this.

[0077] Next, the light emitting control signal EMj supplied from the control line 153 during the light emitting period is changed from a high level to a low level. During the light emitting period, the fifth transistor T5 and the sixth transistor T6 are turned on by the light emitting control signal EMj of the low level. Then, a driving current Id corresponding to the voltage difference between the gate voltage of the gate electrode G1 of the first transistor T1 and the first driving voltage ELVDD is generated, and the driving current Id is supplied to the light emitting diode ED through the sixth transistor T6, so that the light emitting current Ied flows through the light emitting diode ED. During the light emitting period, the gate-source voltage (Vgs) of the first transistor T1 is maintained at (Di-|Vth|)-ELVDD by the capacitor Cst, and according to the current-voltage relationship of the first transistor T1, the driving current Id can be equal to the square of the value obtained by subtracting the threshold voltage (Vth) from the gate-source voltage (Vgs) (Di-ELVDD) 2 Therefore, the driving current Id can be determined regardless of the threshold voltage (Vth) of the first transistor T1. Figure 4 and Figure 5 To facilitate understanding, first, the planar structure of the pixel according to the embodiment will be mainly described, and then the cross-sectional structure will be described in detail.

[0078] Figure 4 is a plan view of one pixel of an organic light emitting display device according to an embodiment. Figure 5 yes Figure 4 0 is a cross-sectional view of the organic light emitting display device shown in taken along line VI-VI′.

[0079] The pixel PXij according to the embodiment may include a first conductive layer, the first conductive layer including a first scan line 151 for transmitting a scan signal GWj, a second scan line 152 for transmitting a scan signal GIj, a third scan line 154 for transmitting a scan signal GBj, and a control line 153 for transmitting a light emission control signal EMj. The first conductive layer may be located on one side of the substrate 110 in cross section, may include the same material, and may be located on a single layer. The substrate 110 may include an inorganic insulating material or an organic insulating material such as glass, plastic, etc., and may have various degrees of flexibility.

[0080] The scan lines 151, 152, and 154 and the control line 153 may extend substantially in the same direction (eg, in a first direction DR1) on a plane (eg, in a plan view). The first scan line 151 may be located between the second scan line 152 and the control line 153 on a plane.

[0081] The pixel PXij of the organic light-emitting display device according to the embodiment may further include a second conductive layer, the second conductive layer including a storage line 156 and an initialization voltage line 159, etc. The second conductive layer is located on a layer different from that of the first conductive layer with respect to the cross section. For example, the second conductive layer may be located on the first conductive layer in cross section (e.g., with reference to the cross-sectional view), may include the same material, and may be located on a single layer.

[0082] The storage line 156 and the initialization voltage line 159 extend relatively in the same direction (eg, in the first direction DR1 ) on a plane.

[0083] The storage line 156 may be located between the first scan line 151 and the control line 153 on a plane, and may include an extension portion 157. The extension portion 157 may be connected to the driving voltage line 172 through the contact hole 68 to receive the first driving voltage ELVDD.

[0084] The initialization voltage line 159 may transfer the initialization voltage Vint and may be disposed between the third scan line 154 and the control line 153 on a plane, but the present disclosure is not limited thereto.

[0085] The pixel PXij according to the embodiment includes a third conductive layer, the third conductive layer including a data line 171 for transmitting a data signal Di and a driving voltage line 172 for transmitting a first driving voltage ELVDD. The third conductive layer is located on a layer different from the first conductive layer and the second conductive layer in cross section. For example, the third conductive layer may be located on the second conductive layer in cross section, may include the same material, and may be located on a single layer.

[0086] The data line 171 and the driving voltage line 172 may extend substantially in the same planar direction (eg, in the second direction DR2 ), and may cross the scan lines 151 , 152 , and 154 , the control line 153 , the initialization voltage line 159 , and the storage line 156 .

[0087] The pixel PXij includes first to seventh transistors T1 to T7 and a capacitor Cst respectively connected to the scan lines 151, 152 and 154, the control line 153, the data line 171, the driving voltage line 172, and the light emitting diode ED.

[0088] The channel of each of the first to seventh transistors T1 to T7 of the pixel PXij may be formed inside one active pattern 130, and the active pattern 130 may be bent into various shapes. The active pattern 130 may include a semiconductor material such as polysilicon, an oxide semiconductor, etc. The active pattern 130 may be placed between the substrate 110 and the first conductive layer in cross section.

[0089] The active pattern 130 includes channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g for forming channels of the first to seventh transistors T1 to T7, respectively, and includes a conductive region. Specifically, the third transistor T3 and the fourth transistor T4 may have a dual-gate structure. In this case, the third transistor T3 includes two channel regions 131c_1 and 131c_2, and the fourth transistor T4 may include two channel regions 131d_1 and 131d_2.

[0090] The conductive region of the active pattern 130 is located on both sides of each of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g, and has a carrier concentration higher than that of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g. In the active pattern 130, the remaining portion except the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f, and 131g may be mainly a conductive region. A pair of conductive regions (serving as the source and drain regions of each of the first to seventh transistors T1 to T7) located on corresponding sides of each of the channel regions 131a, 131b, 131c_1, 131c_2, 131d_1, 131d_2, 131e, 131f and 131g of the first to seventh transistors T1 to T7 may be used as source and drain electrodes, respectively.

[0091] The first transistor T1 includes a channel region 131a, a source region 136a, and a drain region 137a, which are conductive regions of the active pattern 130 located on respective sides of the channel region 131a, and a driving gate electrode 155a overlapping the channel region 131a in a plane (eg, in a plan view).

[0092] The channel region 131a of the first transistor T1 may be bent at least once. For example, the channel region 131a may have a zigzag shape or a zigzag shape. Figure 4 An example is shown in which the channel region 131 a includes an approximately upside-down U-shape.

[0093] The source region 136a and the drain region 137a are connected to respective sides of the channel region 131a in a plane.

[0094] The driving gate electrode 155a may be included in the first conductive layer and may be connected to the connection member 174 through the contact hole 61. The connection member 174 may be included in the third conductive layer. The connection member 174 may extend mainly in a direction parallel to a direction in which the data line 171 extends. The connection member 174 together with the driving gate electrode 155a corresponds to Figure 2 The driving gate node GN shown in the circuit diagram shown in .

[0095] The second transistor T2 includes a channel region 131b, a source region 136b, a drain region 137b, and a gate electrode 155b overlapping the channel region 131b on a plane, the source region 136b and the drain region 137b being conductive regions of the active pattern 130 located on respective sides of the channel region 131b. The gate electrode 155b is a portion of the first scan line 151. The source region 136b is disposed above a plane based on the first scan line 151, connected to the channel region 131b, and connected to the data line 171 through the contact hole 62. The drain region 137b is disposed below a plane based on the first scan line 151, connected to the channel region 131b, and connected to the source region 136a of the first transistor T1.

[0096] The third transistor T3 may be formed in two parts to reduce or prevent leakage current. That is, the third transistor T3 may include a first sub-transistor T3_1 and a second sub-transistor T3_2 that are adjacent to and connected to each other.

[0097] The first sub-transistor T3_1 includes a first sub-channel region 131c_1, a first sub-source region 136c_1, and a first sub-drain region 137c_1 overlapping the first sub-channel region 131c_1 on a plane, and a first sub-gate electrode 155c_1 overlapping the first sub-channel region 131c_1, the first sub-source region 136c_1 and the first sub-drain region 137c_1 being conductive regions of the active pattern 130 located on respective sides of the first sub-channel region 131c_1. The first sub-gate electrode 155c_1 may be a portion of a protruding portion of the first scan line 151. The first sub-drain region 137c_1 is located above a plane based on the first scan line 151, and is connected to the connection member 174 through the contact hole 63.

[0098] The second sub-transistor T3_2 includes a second sub-channel region 131c_2, a second sub-source region 136c_2, and a second sub-drain region 137c_2 overlapping the first scan line 151 on a plane, and a second sub-gate electrode 155c_2 overlapping the second sub-channel region 131c_2, the second sub-source region 136c_2 and the second sub-drain region 137c_2 being conductive regions of the active pattern 130 located on respective sides of the second sub-channel region 131c_2. The second sub-gate electrode 155c_2 is a portion of the first scan line 151.

[0099] The second sub-source region 136c_2 of the second sub-transistor T3_2 is connected to the drain region 137a of the first transistor T1, and the second sub-drain region 137c_2 is connected to the first sub-source region 136c_1 of the first sub-transistor T3_1. The connection node between the first sub-source region 136c_1 of the first sub-transistor T3_1 and the second sub-drain region 137c_2 of the second sub-transistor T3_2 is referred to as a third node N3 (e.g., see Figure 2 and Figure 6 ).

[0100] The fourth transistor T4 may be formed in two parts to reduce or prevent leakage current. That is, the fourth transistor T4 may include a left fourth transistor T4_1 and a right fourth transistor T4_2 that are adjacent to and connected to each other.

[0101] The left fourth transistor T4_1 includes a channel region 131d_1, a source region 136d_1, and a drain region 137d_1 overlapping the second scan line 152 on a plane, and a gate electrode 155d_1 overlapping the channel region 131d_1, the source region 136d_1 and the drain region 137d_1 being conductive regions of the active pattern 130 located on respective sides of the channel region 131d_1. The gate electrode 155d_1 is a portion of the second scan line 152. The drain region 137d_1 is located below a plane based on the second scan line 152, is connected to the drain region 137c_1 of the first sub-transistor T3_1, and is connected to the connection member 174 through the contact hole 63.

[0102] The right fourth transistor T4_2 includes a channel region 131d_2, a source region 136d_2, and a drain region 137d_2 overlapping the second scan line 152 on a plane, and a gate electrode 155d_2 overlapping the channel region 131d_2, the source region 136d_2 and the drain region 137d_2 being conductive regions of the active pattern 130 located on respective sides of the channel region 131d_2. The gate electrode 155d_2 is a portion of the second scan line 152. The drain region 137d_2 is connected to the source region 136d_1 of the left fourth transistor T4_1, and the source region 136d_2 is connected to the connection member 175 through the contact hole 65.

[0103] The connection member 175 may be included in the second conductive layer or the third conductive layer in cross section. When the connection member 175 is included in the third conductive layer, the connection member 175 may be electrically connected to the initialization voltage line 159 through the contact hole 64. When the connection member 175 is included in the second conductive layer, the connection member 175 may be located on the same layer as the initialization voltage line 159, and the connection member 175 may be connected to the initialization voltage line 159.

[0104] A boundary between the channel region 131d_1 of the left fourth transistor T4_1 and the drain region 137d_1 of the left fourth transistor T4_1 directly connected to the connection member 174 for transmitting the voltage of the driving gate electrode 155a, and a boundary between the channel region 131d_1 and the source region 136d_1 may be covered by the driving voltage line 172 on a plane together with the channel region 131d_1. The channel region 131d_1, the boundary between the channel region 131d_1 and the source region 136d_1, and the boundary between the channel region 131d_1 and the drain region 137d_1 may completely overlap with the driving voltage line 172 on a plane, and may be located in the region of the driving voltage line 172 on a plane. On a plane, the horizontal width of each of the channel region 131d_1, the source region 136d_1, and the drain region 137d_1 of the left fourth transistor T4_1 is narrower than the horizontal width of the driving voltage line 172. The channel region 131 d_1 , the source region 136 d_1 , and the drain region 137 d_1 may all be located within the region of the driving voltage line 172 .

[0105] As another transistor directly connected to the connection member 174 for transmitting the voltage of the driving gate electrode 155 a , there is a first sub-transistor T3_1 .

[0106] The fifth transistor T5 includes a channel region 131e, a source region 136e, and a drain region 137e, which are conductive regions of the active pattern 130 on respective sides of the channel region 131e, and a gate electrode 155e overlapping the channel region 131e.

[0107] The gate electrode 155e is a part of the control line 153. The source region 136e is located below a plane based on the control line 153, connected to the channel region 131e, and connected to the driving voltage line 172 through the contact hole 67. The drain region 137e is located above a plane based on the control line 153, connected to the channel region 131e, and connected to the source region 136a of the first transistor T1.

[0108] The sixth transistor T6 includes a channel region 131f, a source region 136f and a drain region 137f, which are conductive regions of the active pattern 130 on respective sides of the channel region 131f, and a gate electrode 155f overlapping the channel region 131f.

[0109] The gate electrode 155f is a part of the control line 153. The source region 136f is located above a plane based on the control line 153, connected to the channel region 131f, and connected to the drain region 137a of the first transistor T1. The drain region 137f is located below a plane based on the control line 153, connected to the channel region 131f, and connected to the connection member 179 through the contact hole 69. The connection member 179 may be included in the third conductive layer.

[0110] The seventh transistor T7 includes a channel region 131g, a source region 136g, and a drain region 137g, which are conductive regions of the active pattern 130 on respective sides of the channel region 131g, and a gate electrode 155g overlapping the channel region 131g.

[0111] The gate electrode 155g is a portion of the third scan line 154. The source region 136g is located above a plane based on the third scan line 154, is connected to the channel region 131g, and is connected to the drain region 137f of the sixth transistor T6.

[0112] The drain region 137 g may be positioned below a plane based on the third scan line 154 , and may be connected to the connection member 175 through the contact hole 65 to receive the initialization voltage Vint.

[0113] The capacitor Cst may include a driving gate electrode 155a and an extension portion 157 of a storage line 156 overlapping each other on a plane as two terminals. The capacitor Cst may maintain a voltage difference corresponding to a difference between a voltage of the extension portion 157 of the storage line 156 receiving the first driving voltage ELVDD and a voltage of the driving gate electrode 155a. The extension portion 157 of the storage line 156 may have a larger plane area than that of the driving gate electrode 155a and may cover the entire area of ​​the driving gate electrode 155a. The extension portion 157 may be included in the second conductive layer.

[0114] The second conductive layer may further include a shielding pattern 158 overlapping the data line 171. The shielding pattern 158 may be connected to the driving voltage line 172 through the contact hole 66 to receive the first driving voltage ELVDD. The shielding pattern 158 shields the driving gate node GN (eg, see Figure 2 and Figure 6 ) and the voltage between the data line 171 to reduce or prevent the voltage variation of the driving gate node GN due to the variation of the data signal Di. On a plane, the width d1 (for example, see Figure 8-Figure 10 ) can be a certain distance (e.g., a predetermined distance of about 3 microns or greater).

[0115] The pixel PXij according to the embodiment may further include a fourth conductive layer, the fourth conductive layer including the pixel electrode 191a, the pixel conductive pattern 192, etc. The fourth conductive layer is located on a layer different from the first conductive layer, the second conductive layer, and the third conductive layer in cross section. For example, the fourth conductive layer may be located on the third conductive layer in cross section, may include the same material, and may be located on a single layer. The pixel electrode 191a may be arranged in a pentile matrix structure.

[0116] The pixel electrode 191a may be connected to the connection member 179 to receive a voltage through the contact hole 89. The pixel conductive pattern 192 may transmit an initialization voltage Vint.

[0117] The channel region 131c_1 of the first sub-transistor T3_1, the boundary between the channel region 131c_1 and the source region 136c_1, and the boundary between the channel region 131c_1 and the drain region 137c_1 are covered by the fourth conductive layer in a plane.

[0118] Will refer to Figure 5 A cross-sectional structure of an organic light emitting display device according to an embodiment is described in more detail.

[0119] The buffer layer 120 may be located on the substrate 110. The buffer layer 120 may reduce or prevent impurities from being transferred from the substrate 110 to an upper layer of the buffer layer 120 (eg, passing through the buffer layer 120 to the active pattern 130), thereby improving the characteristics of the active pattern 130 and relieving stress. The buffer layer 120 may include a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) of inorganic insulating material and / or organic insulating material. In other embodiments, at least a portion of the buffer layer 120 may be omitted.

[0120] The active pattern 130 as described above is located on the buffer layer 120 , and the first insulating layer 141 is located on the active pattern 130 .

[0121] The above-mentioned first conductive layer may be located on the first insulating layer 141. The first conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0122] The second insulating layer 142 may be on the first conductive layer and the first insulating layer 141 .

[0123] The above-mentioned second conductive layer may be located on the second insulating layer 142. The second conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0124] The third insulating layer 160 may be located on the second conductive layer and the second insulating layer 142 .

[0125] At least one of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may include, for example, silicon nitride (SiN x ) or silicon oxide (SiO x ) of inorganic insulating materials and / or organic insulating materials.

[0126] The first insulating layer 141, the second insulating layer 142 and the third insulating layer 160 may include or define a contact hole 61 disposed above the driving gate electrode 155a, a contact hole 62 disposed above the source region 136b of the second transistor T2, a contact hole 63 disposed on the drain region 137c_1 of the first sub-transistor T3_1 or the drain region 137d_1 of the left fourth transistor T4_1, a contact hole 64 disposed above the initialization voltage line 159, a contact hole 65 disposed on the source region 136d_2 of the right fourth transistor T4_2 or the drain region 137g of the seventh transistor T7, a contact hole 66 disposed above the shielding pattern 158, a contact hole 67 disposed above the source region 136e of the fifth transistor T5, a contact hole 68 disposed above the extension portion 157 of the storage line 156, and a contact hole 69 disposed on the drain region 137f of the sixth transistor T6.

[0127] The third conductive layer mentioned above may be located on the third insulating layer 160. The third conductive layer may include a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), and alloys thereof.

[0128] The extending portion 157 of the storage line 156 may overlap the driving gate electrode 155 a with the second insulating layer 142 therebetween to form a capacitor Cst.

[0129] The protective layer 180 is formed on the third conductive layer and the third insulating layer 160. The protective layer 180 may include an organic insulating material such as polyacrylic resin or polyimide resin, and the upper surface of the protective layer 180 may be substantially flat. The protective layer 180 may include or define a contact hole 89 located above the connection member 179.

[0130] The fourth conductive layer mentioned above may be located on the protection layer 180 .

[0131] A pixel defining layer (PDL) 350 may be positioned on the protective layer 180 and the fourth conductive layer. The PDL 350 has an opening portion 351 positioned above the pixel electrode 191a.

[0132] The light emitting layer 370 is located on the pixel electrode 191a. The light emitting layer 370 may be located in the opening portion 351. The light emitting layer 370 may include an organic light emitting material or an inorganic light emitting material.

[0133] The common electrode 270 is located on the light emitting layer 370. The common electrode 270 may also be formed on the PDL 350, and may extend across a plurality of pixels PXij (eg, continuously).

[0134] The pixel electrode 191 a , the light emitting layer 370 , and the common electrode 270 together form a light emitting diode ED.

[0135] A sealing layer for protecting the light emitting diode ED may be further positioned on the common electrode 270. The sealing layer may include inorganic films and organic films alternately stacked.

[0136] Figure 6 is used to explain Figure 2 0 is an equivalent circuit diagram of an auxiliary capacitor and a parasitic capacitance formed by the first sub-transistor and the second sub-transistor (eg, the first sub-transistor T3_1 and the second sub-transistor T3_2 ) shown in . Figure 7 is a waveform diagram showing changes in voltage levels of the third node and the driving gate node according to changes in the scanning signal.

[0137] Reference Figure 6 and Figure 7 , when the scan signal GWj of the low level VGL is supplied through the first scan line 151 during the data programming and compensation period, the second transistor T2, the first sub-transistor T3_1 and the second sub-transistor T3_2 are turned on in response to the low level scan signal GWj. At this time, the first transistor T1 is diode-connected through the turned-on first sub-transistor T3_1 and the turned-on second sub-transistor T3_2, and is forward biased. Then, the compensation voltage Di-|Vth| (the data signal Di supplied from the data line 171 reduces the threshold voltage (Vth) of the first transistor T1) is applied to the gate electrode G1 of the first transistor T1 (see Figure 2). That is, the driving gate node GN rises to the level of the compensation voltage Di-|Vth|. In the same manner, the third node N3 also rises to the level of the compensation voltage Di-|Vth|.

[0138] When the scan signal GWj changes from the low level VGL to the high level VGH, the first sub-transistor T3_1 and the second sub-transistor T3_2 are turned off, so that the third node N3 and the driving gate node GN should be maintained at a certain level (for example, maintained at a predetermined level such as the level of the compensation voltage Di-|Vth|). However, the voltage levels of the third node N3 and the driving gate node GN are changed by the auxiliary capacitor Cdd and the parasitic capacitor Cgs.

[0139] The voltage level of the driving gate node GN becomes high by Δa, the voltage level of the third node N3 increases by ΔV, and then becomes low by Δa.

[0140] ΔV is expressed by Equation 1, and Δa is expressed by Equation 2.

[0141] Equation 1

[0142] Equation 2

[0143] It can be seen from Equation 1 and Equation 2 that if the capacitance of the auxiliary capacitor Cdd increases, ΔV and Δa can be reduced.

[0144] Driver transistor T1 (see Figure 2) has a hysteresis characteristic in which the response characteristic in the current frame changes according to the operating state in the previous frame. That is, even if the driving transistor T1 receives the data signal Di of the same voltage level, it may generate a driving current of different levels in the current frame according to the operating state in the previous frame. Therefore, in the organic light emitting display device, even if the same corresponding data voltage is applied to a pixel that exhibits black in the previous frame and a pixel that exhibits white, the pixel will have different corresponding brightness in the current frame. In order to reduce or prevent the brightness non-uniformity caused by the hysteresis of the driving transistor, before the pixel emits light, the organic light emitting display device is initialized to the on bias state of the driving transistor T1. Therefore, since all the driving transistors included in the organic light emitting display device have the same response characteristic, the brightness non-uniformity caused by the hysteresis can be reduced. However, as described above, the voltage levels of the third node N3 and the driving gate node GN are changed by ΔV and Δa, respectively, so that the (Vgs) and (Vds) (source-drain voltage) of the first sub-transistor T3_1 are reduced. The reduction of (Vgs) and (Vds) of the first sub-transistor T3_1 causes a leakage current (i_leakage) through the source-drain terminals of the first sub-transistor T3_1, so that this may change the voltage level of the driving gate node GN and increase or degrade the hysteresis characteristic of the driving transistor T1.

[0145] In this embodiment, by increasing the capacity of the auxiliary capacitor Cdd, ΔV in Equation 1 and Δa in Equation 2 can be reduced. By stably maintaining the voltage level of the driving gate node GN at the level of the compensation voltage Di-|Vth|, degradation of the hysteresis characteristic of the driving transistor T1 can be reduced or prevented.

[0146] Figure 8 and Fig. 9 yes Figure 4 An enlarged plan view of the first sub-transistor and the second sub-transistor of the pixel shown in FIG.

[0147] Figure 8 An example is shown in which the width and length of the first sub-channel region of the first sub-transistor are the same as the width and length of the second sub-channel region of the second sub-transistor.

[0148] First, refer to Figure 8 , on a plane, a distance d1 from a boundary between the first sub-channel region 131c_1 and the first sub-source region 136c_1 of the first sub-transistor T3_1 to a left edge of the shielding pattern 158 should be maintained (e.g., maintained at a predetermined distance or greater). A distance d2 from a boundary between the second sub-channel region 131c_2 and the second sub-drain region 137c_2 of the second sub-transistor T3_2 to a lower edge of the shielding pattern 158 should be maintained at a predetermined distance or greater.

[0149] In an embodiment, a width W1 (i.e., a length in the second direction DR2) of the first sub-channel region 131c_1 of the first sub-transistor T3_1 may be substantially equal to a width W2 (e.g., W1=W2) of the second sub-channel region 131c_2 of the second sub-transistor T3_2. A length L1 (i.e., a length in the first direction DR1) of the first sub-channel region 131c_1 of the first sub-transistor T3_1 may be substantially equal to a length L2 (L1=L2) of the second sub-channel region 131c_2 of the second sub-transistor T3_2.

[0150] On a plane, for example, the shielding pattern 158 overlaps the first sub-source region 136c_1 of the first sub-transistor T3_1 and the second sub-drain region 137c_2 of the second sub-transistor T3_2 to form an auxiliary capacitor Cdd (see Figure 5 ). It should be noted that in the embodiment of the present disclosure, the shielding pattern 158 does not overlap with the first sub-channel region 131c_1. In addition, in the embodiment of the present disclosure, the shielding pattern 158 does not overlap with the second sub-channel region 131c_2.

[0151] As mentioned above Figure 6 and Figure 7 As described above, the capacitance of the auxiliary capacitor Cdd may be sufficiently large, and one method for increasing the capacitance of the auxiliary capacitor Cdd is to increase the area where the shielding pattern 158 overlaps the first sub-source region 136c_1 and the second sub-drain region 137c_2. However, the area of ​​the shielding pattern 158 is within a limited pixel area.

[0152] Fig. 9 An example is shown in which the width of the first sub-channel region of the first sub-transistor is greater than the width of the second sub-channel region of the second sub-transistor.

[0153] Reference Fig. 9 , a width W1a (i.e., a length in the second direction DR2) of the first sub-channel region 131c_1 of the first sub-transistor T3_1 is greater than a width W2 of the second sub-channel region 131c_2 of the second sub-transistor T3_2 (e.g., W1a>W2). For example, the width W1a of the first sub-channel region 131c_1 may be about 0.5 μm greater than the width W2 of the second sub-channel region 131c_2 of the second sub-transistor T3_2. As the width W1a of the first sub-channel region 131c_1 of the first sub-transistor T3_1 increases, the capacitance of the auxiliary capacitor Cdd increases because the overlapping area between the first sub-source region 136c_1 and the shielding pattern 158 increases.

[0154] exist Fig. 9 In the example shown in , although (for example, with Figure 8Compared with the example shown in [reference], the width W1a of the first sub-channel region 131c_1 of the first sub-transistor T3_1 increases. However, in another embodiment, the width W2 of the second sub-channel region 131c_2 of the second sub-transistor T3_2 may increase. In another example, both the width W1a of the first sub-channel region 131c_1 and the width W2 of the second sub-channel region 131c_2 may increase.

[0155] Fig.10 An example is shown in which the length of the first sub-channel region of the first sub-transistor is shorter than the length of the second sub-channel region of the second sub-transistor.

[0156] Referring to Fig.10 , the length L1a of the first sub-channel region 131c_1 of the first sub-transistor T3_1 (e.g., the length in the first direction DR1) is shorter than the length L2 of the second sub-channel region 131c_2 of the second sub-transistor T3_2 (e.g., L1a < L2). As the length L1a of the first sub-channel region 131c_1 becomes shorter, the shielding pattern 158 can extend longer in the first direction DR1. That is, as the area of the shielding pattern 158 increases, since the overlapping area between the first source region 136c_1 and the shielding pattern 158 increases, the capacitance of the auxiliary capacitor Cdd increases.

[0157] According to Fig. 9 and Fig.10 the embodiments shown in [reference], it is possible to improve the space utilization efficiency and form an auxiliary capacitor Cdd having a sufficient capacitance.

[0158] An organic light-emitting display device according to various embodiments will be described with reference to Figure 11 to Figure 12 the above-described drawings. The same description of the components identical to those of the above embodiments will be omitted.

[0159] Fig.11 is a plan view of a part of a pixel according to an embodiment of the present disclosure. Fig.12 is Fig.11 a cross-sectional view taken along line VII-VII' of the organic light-emitting display device shown in [reference].

[0160] Fig.11 and Fig.12 the pixel shown in [reference] further includes an upper shielding pattern 210. The upper shielding pattern 210 may be disposed on the third insulating layer 160. In some embodiments, the upper shielding pattern 210 may be connected to Figure 3. The upper shield pattern 210 may be located on a layer different from that of the shield pattern 158, with the third insulating layer 160 located between the upper shield pattern 210 and the shield pattern 158. The upper shield pattern 210 may be located on the same layer as that of the connection member 174 (e.g., in the third conductive layer).

[0161] The upper shielding pattern 210 overlaps the first sub source region 136 c_1 of the first sub transistor T3_1 and the second sub drain region 137 c_2 of the second sub transistor T3_2 to form a second auxiliary capacitor Cdd2 .

[0162] The total capacitance may be increased by the parallel connection structure of the first auxiliary capacitor Cdd1 between the shielding pattern 158 and the first and second sub-source regions 136c_1 and 137c_2 and the second auxiliary capacitor Cdd2 between the upper shielding pattern 210 and the first and second sub-drain regions 136c_1 and 137c_2.

[0163] Fig.13 is a plan view of a portion of a pixel according to an embodiment of the present disclosure. Fig.14 yes Fig.13 0 is a cross-sectional view of the organic light emitting display device shown in taken along line VIII-VIII′.

[0164] Fig.13 and Fig.14 The pixel shown in FIG. 1 includes an upper shielding pattern 310. The upper shielding pattern 310 may be disposed on the fourth insulating layer 165. The fourth insulating layer 165 may be formed on the third insulating layer 160. In some embodiments, the upper shielding pattern 310 may be connected to the third insulating layer 160 through a contact hole. Figure 3 . The upper shield pattern 310 may be located on a layer different from that of the shield pattern 158, and the third insulating layer 160 and the fourth insulating layer 165 are located between the upper shield pattern 310 and the shield pattern 158. The fourth insulating layer 165 has an opening portion 166 overlapping the first sub-source region 136c_1 of the first sub-transistor T3_1 and the second sub-drain region 137c_2 of the second sub-transistor T3_2.

[0165] The upper shield pattern 310 overlaps the first sub-source region 136c_1 of the first sub-transistor T3_1 and the second sub-drain region 137c_2 of the second sub-transistor T3_2 to form a third auxiliary capacitor Cdd3. In this embodiment, the distance between the upper shield pattern 310 and the first sub-source region 136c_1 and the second sub-drain region 137c_2 is reduced by the opening portion 166 of the upper shield pattern 310, so that the capacity of the third auxiliary capacitor Cdd3 can be increased.

[0166] The total capacitance may be increased by the parallel connection structure of the first auxiliary capacitor Cdd1 between the shielding pattern 158 and the first and second sub-source regions 136c_1 and 137c_2 and the third auxiliary capacitor Cdd3 between the upper shielding pattern 310 and the first and second sub-drain regions 136c_1 and 137c_2.

[0167] The organic light emitting display device having such a configuration can reduce leakage current through the third transistor by increasing capacitance between a connection node of the third transistor having a double gate electrode and a power supply voltage wiring, thereby improving display quality of the organic light emitting display device.

[0168] Although embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these embodiments, but rather various changes and modifications may be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as claimed herein.

Claims

1. A pixel, comprising: A light emitting diode, comprising an anode and a cathode; a first transistor including a first drain region electrically connected to the anode of the light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region facing the first drain region, wherein the first channel region is located between the first drain region and the first source region; a first sub-transistor comprising a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode in a plan view, a first sub-drain region connected to the first gate electrode, and a first sub-source region facing the first sub-drain region, and the first sub-channel region is located between the first sub-drain region and the first sub-source region; a second sub-transistor comprising a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode in a plan view, a second sub-drain region connected to the first sub-source region, and a second sub-source region facing the second sub-drain region, and the second sub-channel region is located between the second sub-drain region and the second sub-source region; a shielding pattern overlapping the first sub-source region and the second sub-drain region in a plan view and not overlapping the first sub-channel region; as well as an upper shielding pattern, which is located at a different layer from the shielding pattern and overlaps the first sub-source region and the second sub-drain region in a plan view, Wherein, the width of the first sub-channel region is greater than the width of the second sub-channel region.

2. The pixel according to claim 1, wherein: The pixel also includes a fourth transistor, which includes a fourth gate electrode, a fourth channel region overlapping the fourth gate electrode in a plan view, a fourth drain region connected to the first gate electrode, and a fourth source region facing the fourth drain region, and the fourth channel region is located between the fourth drain region and the fourth source region.

3. The pixel according to claim 1, wherein: Each of the shielding pattern and the upper shielding pattern is configured to receive a driving voltage.

4. The pixel according to claim 3, wherein: The shielding pattern overlaps the first sub-source region and the second sub-drain region to form an auxiliary capacitor, and The upper shielding pattern overlaps the first sub-source region and the second sub-drain region to form a second auxiliary capacitor.

5. The pixel according to claim 1, further comprising an extension portion, wherein the extension portion and the first gate electrode are located in a different layer, in, The extension portion overlaps the first gate electrode to form a capacitor.

6. The pixel according to claim 5, wherein: The shielding pattern and the extending portion are located at the same layer.

Images