Display device

Abstract

A display device is provided. The display device includes a substrate including an emission region and a non-emission region, an anode on the emission region of the substrate, a pixel defining layer on the anode and overlapping the non-emission region while a first opening is defined by the pixel defining layer, a first bank structure, a second bank structure, and a first encapsulation layer encapsulating the first opening and the non-emission region. A first opening is defined by the first bank structure, a second opening is defined by the first bank structure, a second bank structure is defined by the first bank structure and comprises at least two materials, a first encapsulation layer is defined by the second bank structure, and the first bank structure comprises a first bank layer and a second bank layer, the second bank layer includes a first tip protruding toward a center of the first opening, the second bank structure includes a third bank layer and a fourth bank layer, the fourth bank layer includes a second tip protruding toward a center of the second opening, and the first encapsulation layer covers the first tip and the second tip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0095892, filed on Jul. 24, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As the information society develops, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. In such a flat panel display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight unit for providing light to the display panel. Summary of the invention

[0005] Recently, it may be desired that a display device has a high pixel integration to achieve high resolution. When a display device has a high pixel integration, the area of ​​the emission region where the light emitting element is arranged is reduced, and therefore, it may be difficult to separate the light emitting elements from each emission region through a mask process.

[0006] Embodiments of the present disclosure provide a display device capable of forming light emitting elements separated from each other for each emission region without a mask process.

[0007] Embodiments of the present disclosure also provide a display device that improves reliability of a display panel by preventing moisture and oxygen from penetrating through a bank structure during a manufacturing process.

[0008] However, the embodiments of the present disclosure are not limited to those set forth herein.The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] In an embodiment of the present disclosure, a display device includes a substrate, an anode, a pixel defining layer, a first dam structure, a second dam structure and a first encapsulation layer, the substrate includes an emission area and a non-emission area, the anode is positioned on the emission area of ​​the substrate, the pixel defining layer is positioned on the anode and overlaps with the non-emission area, wherein a first opening is defined by the pixel defining layer, the first dam structure is positioned on the pixel defining layer and includes at least two different conductive materials, wherein a second opening is defined by the first dam structure, the second dam structure is positioned on the first dam structure and includes at least two different materials, the first encapsulation layer is positioned on the second dam structure, wherein the first dam structure includes a first dam layer and a second dam layer, the second dam layer includes a first tip protruding toward the center of the first opening than the side surface of the first dam layer, the second dam structure includes a third dam layer and a fourth dam layer, the fourth dam layer includes a second tip protruding toward the center of the second opening than the side surface of the third dam layer, and the first encapsulation layer covers the first tip and the second tip.

[0010] In an embodiment, the display device may also include a first light-emitting layer positioned on the anode to overlap with the first opening, a cathode positioned on the first light-emitting layer, a first organic pattern positioned on the second embankment layer while surrounding the first opening and including the same material as the first light-emitting layer, and a first electrode pattern positioned on the first organic pattern while surrounding the first opening and including the same material as the cathode.

[0011] In embodiments, the first light emitting layer and the cathode may contact side surfaces of the first bank layer.

[0012] In an embodiment, the first organic pattern may be spaced apart from the first light emitting layer, and the first electrode pattern may be spaced apart from the cathode, and the first organic pattern and the first electrode pattern may overlap the first tip.

[0013] In an embodiment, the first bank layer may include aluminum, and the second bank layer may include titanium.

[0014] In embodiments, the first encapsulation layer may contact a side surface of the first bank layer and a first tip end of the second bank layer.

[0015] In embodiments, the second bank layer may include a first surface opposite to the third bank layer, and the first surface may include a first portion contacting the first organic pattern, a second portion contacting the first encapsulation layer, and a third portion that may contact the third bank layer.

[0016] In an embodiment, the second portion may be positioned between the first portion and the third portion, and the first portion, the second portion and the third portion are integrally formed as a single and indivisible part.

[0017] In embodiments, the first encapsulation layer may be in contact with a side surface of the third bank layer.

[0018] In embodiments, a cavity overlapping the second tip may be defined between the fourth bank layer and the first encapsulation layer.

[0019] In an embodiment, the display device may further include a second encapsulation layer positioned on the first encapsulation layer, wherein the cavity may be filled with the second encapsulation layer.

[0020] In an embodiment, in a direction perpendicular to the substrate, a space completely surrounded by the first encapsulation layer may be defined between the second bank layer and the fourth bank layer.

[0021] In an embodiment, the third bank layer may include an inorganic film including about 33% or more of oxygen, and the fourth bank layer may include an inorganic film including about 33% or more of nitrogen.

[0022] In an embodiment, the third bank layer may include an organic material or an inorganic material, and the fourth bank layer may include an organic material.

[0023] In an embodiment, a width of the third bank layer may be smaller than a width of the fourth bank layer.

[0024] In an embodiment, the first and second bank layers may overlap the emission region, and the third and fourth bank layers may not overlap the emission region.

[0025] In an embodiment of the present disclosure, a display device includes a substrate, a first anode, a second anode, a pixel defining layer, a first dam structure, a second dam structure and a first encapsulation layer, wherein the substrate includes a first emission region, a second emission region and a non-emission region positioned between the first emission region and the second emission region, the first anode is positioned on the first emission region of the substrate, the second anode is positioned on the second emission region of the substrate, the pixel defining layer is positioned on the non-emission region of the substrate between the first anode and the second anode, wherein a plurality of openings are defined by the pixel defining layer, the first dam structure is positioned on the pixel defining layer and includes at least two different conductive materials, the second dam structure is positioned on the first dam structure and includes at least two different inorganic films, the first encapsulation layer is positioned on the second dam structure, wherein the first dam structure includes a first dam layer and a second dam layer including a plurality of first tips, each of the plurality of first tips protruding from a corresponding one of a plurality of side surfaces of the first dam layer toward a center of a corresponding one of a plurality of openings, the second dam structure includes a third dam layer and a fourth dam layer including a plurality of second tips, each of the plurality of second tips protruding from a corresponding one of a plurality of side surfaces of the third dam layer toward a center of a corresponding one of a plurality of openings, and the first encapsulation layer covers the plurality of first tips and the plurality of second tips.

[0026] In an embodiment, the first encapsulation layer may include a first inorganic layer overlapping the first emission region and a second inorganic layer overlapping the second emission region, and a portion of the first inorganic layer overlapping the fourth bank layer and a portion of the second inorganic layer overlapping the fourth bank layer may be spaced apart from each other.

[0027] In an embodiment, the display device may also include: a first light-emitting layer positioned on the first anode; a second light-emitting layer positioned on the second anode; a first organic pattern positioned on the second embankment layer to overlap with the first emission region, including the same material as the first light-emitting layer and separated from the first light-emitting layer; and a second organic pattern positioned on the second embankment layer to overlap with the second emission region, including the same material as the second light-emitting layer and separated from the second light-emitting layer, wherein a third embankment layer may be positioned between the first organic pattern and the second organic pattern.

[0028] In an embodiment, the display device may further include a first light-emitting element including a first anode and a first light-emitting layer, and a second light-emitting element including a second anode and a second light-emitting layer, wherein in a plan view, the first light-emitting element and the second light-emitting element are completely surrounded by a pixel defining layer, and in a plan view, the pixel defining layer may be completely surrounded by the first embankment structure.

[0029] In a display device according to an embodiment of the present disclosure, the display device includes a first embankment structure, and thus it is possible to form light-emitting elements separated from each other for each emission region without using a mask process. In such an embodiment, the display device includes a second embankment structure arranged on the first embankment structure, and thus it is possible to prevent moisture penetration introduced through the first embankment structure. Therefore, the display device can be formed with high resolution, and the reliability of the display device against moisture penetration can be improved.

[0030] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing a display device according to an embodiment;

[0033] Figure 2 yes Figure 1 A schematic cross-sectional view of a display device;

[0034] Figure 3 yes Figure 2 A cross-sectional view of a display device having a curved bending area;

[0035] Figure 4is a plan view showing an arrangement of emission areas in a display area of ​​a display device according to an embodiment;

[0036] Figure 5 is along Figure 4 A cross-sectional view of the display device taken along line X1-X1';

[0037] Figure 6 yes Figure 5 an enlarged cross-sectional view of a portion “T1”;

[0038] Figure 7 yes Figure 6 an enlarged cross-sectional view of a portion “T3”;

[0039] Figure 8 yes Figure 7 an enlarged cross-sectional view of a portion “T5”;

[0040] Fig. 9 According to another embodiment Figure 7 an enlarged cross-sectional view of a portion “T5”;

[0041] Fig.10 According to another embodiment Figure 5 an enlarged cross-sectional view of a portion “T1”;

[0042] Fig.11 yes Fig.10 an enlarged cross-sectional view of portion “Q5” of FIG.

[0043] Fig.12 According to another embodiment Fig.10 An enlarged cross-sectional view of portion “Q5”. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully below with reference to the accompanying drawings showing various embodiments. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the specification, similar reference numerals refer to similar elements.

[0045] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0046] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part without departing from the teachings herein.

[0047] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. Unless the content clearly states otherwise, the singular forms "a", "an" and "the" as used herein are intended to include plural forms, including "at least one". Therefore, the "one" element mentioned in a claim that subsequently mentions the "said" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (at least one)" will not be interpreted as limiting "a" or "an". "Or (or)" means "and / or (and / or)". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprises” and / or “comprising” or “includes” and / or “including” are used in the present specification, it specifies the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or clusters thereof.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that, in addition to the orientations shown in the figures, relative terms are also intended to include different orientations of the device. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, the term "lower" can include both the "lower" and "upper" orientations according to the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "beneath" of the other element will then be oriented "above" of the other element. Therefore, the term "lower" or "below" can include both the orientations of the upper and lower sides.

[0049] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0051] Embodiments are described herein with reference to schematically illustrated cross-sectional illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the shapes of specific zones as shown herein, but will include deviations in shapes due to, for example, manufacturing. For example, zones shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0052] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a perspective view showing a display device 10 according to the embodiment.

[0054] Reference Figure 1 The display device 10 according to the embodiment may be included in an electronic device to provide a picture displayed on the electronic device. The electronic device may refer to any electronic device that provides a display picture, for example, a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, or the like.

[0055] The shape of the display device 10 may be modified in various ways. For example, the display device 10 may have a rectangular shape with a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction in a plan view (or when viewed in a third direction (Z-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded with a curvature, but is not limited thereto, and may also be a right angle. Here, the third direction (Z-axis direction) may be the thickness direction of the display device 10. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0056] The display device 10 may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0057] The display panel 100 may include a main area MA and a sub area SBA.

[0058] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA arranged around the display area DA. The display area DA may emit light from a plurality of emission areas. In an embodiment, for example, the display panel 100 may include a pixel circuit, a pixel defining layer defining an emission area, and a self-luminous element.

[0059] In an embodiment, for example, the self-luminous element may include at least one selected from an organic light emitting diode (organic LED, OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0060] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be arranged in the display area DA. Each of the plurality of pixels may be defined as a minimum unit of emitting light, and each of the pixels may be one of the self-luminous elements described above. The plurality of scan lines may supply a scan signal received from a scan driver to the plurality of pixels. The plurality of data lines may supply a data voltage received from a display driver 200 to the plurality of pixels. The plurality of power lines may supply a source voltage received from the display driver 200 to the plurality of pixels.

[0061] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver for supplying a scan signal to a scan line and a fan-out line connecting the display driver 200 and the display area DA to each other.

[0062] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a bending area BA and a pad area PDA.

[0063] The bending area BA may be arranged between the main area MA and the pad area PDA in the second direction (Y-axis direction). The bending area BA may extend in the first direction (X-axis direction). The bending area BA may be an area bent under the display panel 100 (for example, the bending area BA may be an area bent so that a portion of the sub-area SBA is positioned under the main area MA).

[0064] The pad area PDA may be a lower edge area of ​​the display panel 100. The pad area PDA may include a display driver 200, a display pad, and a circuit board 300.

[0065] A plurality of display drivers 200 may be arranged in the pad area PDA. Each of the display drivers 200 may be attached to the non-display area NDA of the display panel 100 in a chip on glass (COG) manner. In another embodiment, each of the display drivers 200 may also be attached to the circuit board 300 in a chip on plastic (COP) manner.

[0066] The circuit board 300 may be attached to the display pad using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Thus, the circuit board 300 may be electrically connected to the signal line of the display panel 100. Each of the circuit boards 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0067] Although not shown in the drawings, a plurality of display pads may be arranged at one end of the pad area PDA and may contact the circuit board 300. The display pads may be connected to a graphics system through the circuit board 300. The plurality of display pads may be connected to the circuit board 300 to receive digital video data, and the digital video data may be supplied to the display driver 200.

[0068] Figure 2 Observed from the side Figure 1 1 is a cross-sectional view of a display device 10. Figure 3 yes Figure 2 A cross-sectional view of a display device having a curved bending area.

[0069] Reference Figure 2 , an embodiment of the display device 10 may include a display panel 100, a color filter layer 190, a display driver 200, and a circuit board 300. The display panel 100 may include a substrate 110, a thin film transistor layer 130, a display element layer 150, a thin film encapsulation layer 170, and a touch sensor layer 180.

[0070] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, and rolled. In an embodiment, for example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, for example, the substrate 110 may include a glass material or a metal material.

[0071] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors TFT (see Figure 5 ). The thin film transistor layer 130 may be arranged in the main area MA, the bending area BA, and the pad area PDA. The thin film transistors, gate lines, data lines, and power lines of the thin film transistor layer 130 may be arranged in the display area DA of the main area MA, and the gate control lines and fan-out lines of the thin film transistor layer 130 may be arranged in the non-display area NDA of the main area MA. In addition, the leads of the thin film transistor layer 130 may be arranged in the bending area BA and the pad area PDA.

[0072] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include a plurality of light emitting elements each including an anode, a light emitting layer, and a cathode to emit light, a pixel defining layer, a bank structure, or the like.

[0073] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the anode receives a voltage through the thin film transistor of the thin film transistor layer 130 and the cathode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may combine with each other in the organic light-emitting layer to emit light. In another embodiment, the light-emitting element may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0074] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150, and may protect the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0075] The touch sensor layer 180 may be arranged on the thin film encapsulation layer 170. The touch sensor layer 180 may include a plurality of touch electrodes and a plurality of touch lines for sensing the touch of a user in a capacitive manner. In an embodiment, for example, the touch sensor layer 180 may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner. The plurality of touch electrodes of the touch sensor layer 180 may be arranged in a touch sensor area overlapping the display area DA. The touch lines of the touch sensor layer 180 may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0076] The color filter layer 190 may be arranged on the touch sensor layer 180. The color filter layer 190 may include various color filters corresponding to the plurality of emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength therethrough and block or absorb light of other wavelengths. The color filter layer 190 may absorb some of the light introduced from the outside of the display device 10 to reduce reflected light of the external light. Therefore, the color filter layer 190 may prevent color distortion due to reflection of external light.

[0077] Since the color filter layer 190 is directly disposed on the touch sensor layer 180 , the display device 10 may not include a separate substrate for the color filter layer 190 .

[0078] Reference Figure 3 , the pad area PDA of the display device 10 may be bent due to the bending area BA. When the pad area PDA is bent due to the bending area BA, the display driver 200 and the circuit board 300 arranged or positioned in the pad area PDA may overlap the main area MA in the third direction (Z-axis direction).

[0079] Figure 4 is a plan view showing the arrangement of emission areas EA1 , EA2 , and EA3 in a display area DA of a display device according to an embodiment.

[0080] Reference Figure 4 In an embodiment, the display area DA may include a plurality of emission areas EA1, EA2, and EA3 and a non-emission area NLA. The non-emission area NLA may be defined or positioned around the emission areas EA1, EA2, and EA3. An inorganic pixel defining layer 151, a dam structure 160, and a light blocking layer BM may be arranged or positioned in the non-emission area NLA.

[0081] The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors, respectively. The plurality of emission areas EA1, EA2, and EA3 may emit red light, green light, and blue light, respectively, and the colors of the light emitted from the corresponding emission areas EA1, EA2, and EA3 may be different from each other according to the types of the light emitting elements ED1, ED2, and ED3. In an embodiment, the first emission area EA1 may emit a first light that is red light, the second emission area EA2 may emit a second light that is green light, and the third emission area EA3 may emit a third light that is blue light. However, the present disclosure is not limited thereto.

[0082] In a plan view (or when viewed in a third direction or the Z-axis direction), the light emitting elements ED1, ED2, and ED3 overlapping the corresponding emission areas EA1, EA2, and EA3 may be surrounded by the inorganic pixel defining layer 151 defining the first opening OP1. In addition, the inorganic pixel defining layer 151 may be surrounded by the embankment structure 160. The embankment structure 160 may define the second opening OP2. In other words, the light emitting elements ED1, ED2, and ED3 overlapping the corresponding emission areas EA1, EA2, and EA3 may be arranged or positioned within the first opening OP1 and the second opening OP2.

[0083] Figure 5 is along Figure 4 A cross-sectional view of the display device 10 taken along line X1 - X1 ′.

[0084] Reference Figure 5 , an embodiment of the display panel 100 may include a substrate 110 , a thin film transistor layer 130 , a display element layer 150 , a thin film encapsulation layer 170 , and a touch sensor layer 180 .

[0085] The substrate 110 is substantially the same as the substrate described above, and any repeated detailed description thereof will be omitted.

[0086] The thin film transistor layer 130 may include a first buffer layer 111, a bottom metal layer BML, a second buffer layer 113, a thin film transistor TFT, a gate insulating layer 131, a first interlayer insulating layer 133, a capacitor electrode CPE, a second interlayer insulating layer 135, a first connection electrode CNE1, a first passivation layer 137, a second connection electrode CNE2 and a second passivation layer 139.

[0087] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing air or moisture from penetrating. In an embodiment, for example, the first buffer layer 111 may include a plurality of inorganic films alternately stacked.

[0088] The bottom metal layer BML may be disposed on the first buffer layer 111. In an embodiment, for example, the bottom metal layer BML may be formed as a single layer or a multilayer, wherein each layer herein includes at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or a combination thereof (e.g., alloy), or is made thereof.

[0089] The second buffer layer 113 may cover the first buffer layer 111 and the bottom metal layer BML. The second buffer layer 113 may include an inorganic film capable of preventing air or moisture from penetrating. In an embodiment, for example, the second buffer layer 113 may include a plurality of inorganic films alternately stacked.

[0090] The thin film transistor TFT may be arranged on the second buffer layer 113. The thin film transistor TFT may constitute a pixel circuit of each of the plurality of pixels. In an embodiment, for example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0091] The semiconductor layer ACT may be disposed on the second buffer layer 113. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the third direction (Z-axis direction), and may be insulated from the gate electrode GE by the gate insulating layer 131. The material of the semiconductor layer ACT in the portion of the semiconductor layer ACT may become a conductor to form the source electrode SE and the drain electrode DE.

[0092] The gate electrode GE may be disposed on the gate insulating layer 131. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer 131 interposed therebetween.

[0093] The gate insulating layer 131 may be disposed on the semiconductor layer ACT. For example, the gate insulating layer 131 may cover the semiconductor layer ACT and the second buffer layer 113 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer 131 may be provided with a contact hole through which the first connection electrode CNE1 extends.

[0094] The first interlayer insulating layer 133 may cover the gate electrode GE and the gate insulating layer 131. The first interlayer insulating layer 133 may be provided with a contact hole through which the first connection electrode CNE1 extends. The contact hole of the first interlayer insulating layer 133 may be connected to the contact hole of the gate insulating layer 131 and the contact hole of the second interlayer insulating layer 135.

[0095] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 133. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction or the third direction (Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0096] The second interlayer insulating layer 135 may cover the capacitor electrode CPE and the first interlayer insulating layer 133. The second interlayer insulating layer 135 may be provided with a contact hole through which the first connection electrode CNE1 extends. The contact hole of the second interlayer insulating layer 135 may be connected to the contact hole of the first interlayer insulating layer 133 and the contact hole of the gate insulating layer 131.

[0097] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 135. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer 135, the first interlayer insulating layer 133, and the gate insulating layer 131 to contact the drain electrode DE of the thin film transistor TFT.

[0098] The first passivation layer 137 may cover the first connection electrode CNE1 and the second interlayer insulating layer 135. The first passivation layer 137 may protect the thin film transistor TFT. The first passivation layer 137 may be provided with a contact hole through which the second connection electrode CNE2 extends.

[0099] The second connection electrode CNE2 may be disposed on the first passivation layer 137. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the anodes AE1, AE2, and AE3 of the light emitting element ED1, ED2, and ED3 to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer 137 to contact the first connection electrode CNE1.

[0100] The second passivation layer 139 may cover the second connection electrode CNE2 and the first passivation layer 137. The second passivation layer 139 may be provided with contact holes through which the anodes AE1 of the light emitting element ED1, AE2 of the light emitting element ED2, and AE3 of the light emitting element ED3 extend.

[0101] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may include light emitting elements ED1, ED2, and ED3, an inorganic pixel defining layer 151, and a bank structure 160.

[0102] The light emitting elements ED1, ED2, and ED3 may be disposed on the second passivation layer 139. The light emitting elements ED1, ED2, and ED3 may include anodes AE1, AE2, and AE3, respectively, light emitting layers EL1, EL2, and EL3, respectively, and cathodes CE1, CE2, and CE3, respectively.

[0103] The anodes AE1, AE2, and AE3 may be arranged in a plurality of emission areas EA1, EA2, and EA3, respectively. The anodes AE1, AE2, and AE3 may include a first anode AE1 arranged in a first emission area EA1, a second anode AE2 arranged in a second emission area EA2, and a third anode AE3 arranged in a third emission area EA3. The anodes AE1, AE2, and AE3 may be arranged to be spaced apart from each other on the second passivation layer 139. The anodes AE1, AE2, and AE3 may be arranged in different emission areas EA1, EA2, and EA3, respectively, to constitute light emitting elements ED1, ED2, and ED3 that emit light of different colors, respectively.

[0104] The first anode AE1, the second anode AE2, and the third anode AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. The first anode AE1, the second anode AE2, and the third anode AE3 may include or be made of a metal having high conductivity. In an embodiment, for example, the first anode AE1, the second anode AE2, and the third anode AE3 may have a material including a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3)) or a layer made of it and a stacked film structure of a layer made of a reflective material (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). The layer including a material having a high work function or made of it may be arranged at a layer above the layer made of the reflective material, and thus arranged to be close to the light-emitting layers EL1, EL2 and EL3. In an embodiment, for example, the first anode AE1, the second anode AE2 and the third anode AE3 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO, but are not limited thereto.

[0105] The inorganic pixel defining layer 151 may be arranged or positioned on the second passivation layer 139 and the first anode AE1, the second anode AE2, and the third anode AE3. The inorganic pixel defining layer 151 may define a plurality of first openings OP1 overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3. The inorganic pixel defining layer 151 may be completely arranged on the second passivation layer 139 to overlap the non-emission area NLA, and may overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3 to partially overlap the first anode AE1, the second anode AE2, and the third anode AE3. The inorganic pixel defining layer 151 may expose a portion of the upper surface of the first anode AE1, the second anode AE2, and the third anode AE3 that overlaps with the first opening OP1.

[0106] The inorganic pixel defining layer 151 may include an inorganic insulating material. In an embodiment, for example, the inorganic pixel defining layer 151 may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0107] A residual pattern 157 (eg, referring to FIG. 1 ) may be disposed or positioned between the inorganic pixel defining layer 151 and the first, second, and third anodes AE1, AE2, and AE3. Figure 6 ). Its detailed features will be described later.

[0108] The bank structure 160 may be arranged or positioned in the non-emission area NLA, and may be arranged or positioned on the inorganic pixel defining layer 151. The bank structure 160 may include a first bank structure 160A and a second bank structure 160B.

[0109] The first embankment structure 160A may be arranged or positioned on the inorganic pixel defining layer 151. The first embankment structure 160A may help the display device 10 to individually form light emitting elements ED1, ED2, and ED3 overlapping the corresponding emission areas EA1, EA2, and EA3. In addition, the first embankment structure 160A may define a second opening OP2, which defines the first emission area EA1, the second emission area EA2, and the third emission area EA3. The second opening OP2 may overlap with the first opening OP1 and may have a greater width than the first opening OP1. In other words, the first opening OP1 may be positioned within the second opening OP2.

[0110] The first bank structure 160A may include a first bank layer 161 and a second bank layer 163 including conductive materials different from each other and respectively performing different roles.

[0111] The first bank layer 161 may be arranged or positioned on the inorganic pixel defining layer 151. The first bank layer 161 may include a metal having high conductivity. As an example, the first bank layer 161 may include aluminum (Al). In the display device 10 according to the embodiment, the cathodes CE1, CE2, and CE3 arranged in different emission areas EA1, EA2, and EA3 are not directly connected to each other, and may be electrically connected to each other through the first bank layer 161. Therefore, the cathodes CE1, CE2, and CE3 arranged in different emission areas EA1, EA2, and EA3 may be spaced apart from each other by the first bank layer 161 interposed therebetween, and may be in contact with the first bank layer 161.

[0112] The second bank layer 163 may be arranged or positioned on the first bank layer 161. The second bank layer 163 may include a material having an etching rate lower than that of the first bank layer 161. In an embodiment, for example, the second bank layer 163 may include titanium (Ti). The second bank layer 163 may have both side surfaces 161c (see FIG. 1 ) of the first bank layer 161. Figure 6 ) protrudes toward the first opening OP1. Therefore, the second bank layer 163 may include a tip TIP1 protruding toward the first opening OP1. Therefore, an undercut structure may be defined or formed between a lower portion of the protruding tip TIP1 of the second bank layer 163 and the first bank layer 161. In the display device 10 according to the embodiment, the second bank layer 163 includes the protruding tip TIP1, and therefore, the light emitting elements ED1, ED2, and ED3 may be individually formed in the corresponding emission areas EA1, EA2, and EA3.

[0113] The second bank structure 160B may be arranged or positioned on the first bank structure 160A to overlap the non-emission area NLA. The second bank structure 160B may block a permeation path of oxygen and moisture introduced through the first bank structure 160A. The second bank structure 160B may include a third bank layer 165 and a fourth bank layer 167 including materials different from each other and performing different roles, respectively.

[0114] The third bank layer 165 may be arranged or positioned on the second bank layer 163. The third bank layer 165 may overlap the non-emission area NLA and be positioned between a plurality of patterns ELP, CEP, and CLP that are spaced apart from each other and will be described later. The third bank layer 165 may be an inorganic film. Therefore, the third bank layer 165 may block moisture and oxygen that may penetrate into the upper surface of the second bank layer 163.

[0115] The fourth bank layer 167 may be arranged or positioned on the third bank layer 165. The fourth bank layer 167 may include a tip TIP2 protruding from the side toward the center of the first opening OP1 more than the third bank layer 165. Therefore, an undercut structure may be formed between the lower portion of the protruding tip TIP2 of the fourth bank layer 167 and the third bank layer 165. The fourth bank layer 167 may include an inorganic film having an etching rate lower than that of the third bank layer 165. Detailed features thereof will be described later.

[0116] The light-emitting layers EL1, EL2, and EL3 may be disposed on the anodes AE1, AE2, and AE3, respectively. The light-emitting layers EL1, EL2, and EL3 may be formed after forming the embankment structure 160 in the manufacturing process. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers including or made of an organic material, and may be formed on the anodes AE1, AE2, and AE3, respectively, by a deposition process. When the thin film transistor TFT applies a predetermined anode voltage to the anodes AE1, AE2, and AE3 and the cathodes CE1, CE2, and CE3 receive a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and may be combined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0117] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be arranged on the first anode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be arranged on the second anode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be arranged on the third anode AE3 in the third emission area EA3. In an embodiment, for example, the first light-emitting layer EL1 may be a light-emitting layer that emits red light as light of a first color, the second light-emitting layer EL2 may be a light-emitting layer that emits green light as light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer that emits blue light as light of a third color.

[0118] The cathodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The cathodes CE1, CE2, and CE3 may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2, and EL3. The cathodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. When the anodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the cathodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference is formed between the anodes AE1, AE2, and AE3 and the cathodes CE1, CE2, and CE3, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0119] In an embodiment, for example, cathodes CE1, CE2, and CE3 may include silver (Ag), but are not limited thereto. The cathodes CE1, CE2, and CE3 may include a layer made of a material having a small work function (such as Li, Ca, Al, Mg, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba, or a compound thereof (e.g., BaF) or a mixture (e.g., a mixture of Ag and Mg, etc.)), and may have a single-layer structure or a multi-layer structure (e.g., LiF / Ca, LiF / Al). The cathodes CE1, CE2, and CE3 may also include a transparent metal oxide layer arranged on a layer including or made of a material having a small work function.

[0120] As described above, in the embodiment of the display device 10, through the tip TIP1 of the first bank structure 160A, the cathodes CE1, CE2, and CE3 can be formed separately in different regions even in a deposition process without using a mask. The cathodes CE1, CE2, and CE3 may include a first cathode CE1, a second cathode CE2, and a third cathode CE3 arranged in different emission regions EA1, EA2, and EA3, respectively. The first cathode CE1 may be arranged on the first light-emitting layer EL1 in the first emission region EA1, the second cathode CE2 may be arranged on the second light-emitting layer EL2 in the second emission region EA2, and the third cathode CE3 may be arranged on the third light-emitting layer EL3 in the third emission region EA3. The first cathode CE1, the second cathode CE2, and the third cathode CE3 formed separately may be electrically connected to each other through the first bank layer 161.

[0121] In some embodiments, the first embankment structure 160A includes a protruding tip TIP1, and accordingly, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be formed separately, but the material may not be smoothly deposited under the protruding tip TIP1. Therefore, the materials of the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be deposited in a direction inclined relative to the upper surface of the substrate 110 (rather than in a third direction (Z-axis direction) perpendicular to the upper surface of the substrate 110). Specifically, the deposition process for forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be performed so that the materials of the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 are deposited in a direction that is not perpendicular to the upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3 (for example, in a direction inclined between the first direction (X-axis direction) and the third direction (Z-axis direction)).

[0122] In an embodiment, when the angle of the deposition process for forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 is defined as the first angle, the deposition process for forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be performed at an inclination angle in the range of about 45° to about 50° from the upper surface of the first anode AE1, the second anode AE2, and the third anode AE3. That is, the first angle may be in the range of about 45° to about 50°. Therefore, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 may be formed even on a partial area hidden by the protruding tip TIP1 of the embankment structure 160 and the side surface 161c of the first embankment layer 161.

[0123] In some embodiments, the deposition process for forming the first cathode CE1, the second cathode CE2, and the third cathode CE3 may also be performed so that the materials of the first cathode CE1, the second cathode CE2, and the third cathode CE3 are deposited in a direction that is not perpendicular to the upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3 (for example, in a direction inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). In an embodiment, when the angle of the deposition process for forming the first cathode CE1, the second cathode CE2, and the third cathode CE3 is defined as the second angle, the deposition process for forming the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be performed at an inclined angle within a range of about 30° or less from the upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3.

[0124] In other words, the deposition process for forming the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be performed in an inclined direction relatively closer to the horizontal direction than the deposition process for forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. Therefore, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be deposited to contact the side surface 161c of the first bank layer 161 with a larger area than the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. Therefore, the deposition process for forming the first cathode CE1, the second cathode CE2, and the third cathode CE3 may have a higher step coverage characteristic than the deposition process for forming the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3. That is, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be deposited on the side surface 161c of the first bank layer 161 to a position higher than the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3.

[0125] Covering layers CPL1, CPL2, and CPL3 may be disposed on cathodes CE1, CE2, and CE3, respectively. Covering layers CPL1, CPL2, and CPL3 may include an inorganic insulating material and cover light emitting elements ED1, ED2, and ED3, respectively. Covering layers CPL1, CPL2, and CPL3 may prevent light emitting elements ED1, ED2, and ED3 from being damaged by external air, and may protect first cathode CE1, second cathode CE2, and third cathode CE3 so that first cathode CE1, second cathode CE2, and third cathode CE3 are not separated.

[0126] The cover layers CPL1, CPL2, and CPL3 may include a first cover layer CPL1 overlapping the first emission area EA1, a second cover layer CPL2 overlapping the second emission area EA2, and a third cover layer CPL3 overlapping the third emission area EA3.

[0127] The cover layers CPL1, CPL2, and CPL3 overlapping the corresponding emission areas EA1, EA2, and EA3 may completely cover the cathodes CE1, CE2, and CE3, respectively. However, the present disclosure is not limited thereto, and the cover layers CPL1, CPL2, and CPL3 overlapping the corresponding emission areas EA1, EA2, and EA3 may expose portions of the cathodes CE1, CE2, and CE3, respectively.

[0128] The cover layers CPL1, CPL2 and CPL3 may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiON).

[0129] Reference Figure 5 , a plurality of organic patterns ELP1, ELP2, and ELP3, a plurality of electrode patterns CEP1, CEP2, and CEP3, and a plurality of capping patterns CLP1, CLP2, and CLP3 may be arranged on the second bank layer 163 to surround the first opening OP1 in a plan view. Portions of the plurality of organic patterns ELP1, ELP2, and ELP3, the plurality of electrode patterns CEP1, CEP2, and CEP3, and the plurality of capping patterns CLP1, CLP2, and CLP3 may be partially etched in a manufacturing process of the display device 10. Therefore, the plurality of organic patterns ELP1, ELP2, and ELP3, the plurality of electrode patterns CEP1, CEP2, and CEP3, and the plurality of capping patterns CLP1, CLP2, and CLP3 may be arranged to be spaced apart from each other in a portion overlapping the non-emission area NLA.

[0130] A plurality of organic patterns ELP1, ELP2, and ELP3 may be arranged or positioned on the second bank layer 163. The organic patterns ELP1, ELP2, and ELP3 may include the same material as the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3, respectively. The first organic pattern ELP1 may include the same material as the first light emitting layer EL1 of the first light emitting element ED1, the second organic pattern ELP2 may include the same material as the second light emitting layer EL2 of the second light emitting element ED2, and the third organic pattern ELP3 may include the same material as the third light emitting layer EL3 of the third light emitting element ED3. The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be traces formed when the deposited material is disconnected from the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 by the tip TIP1 of the first bank structure 160A instead of being connected to the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3.

[0131] A plurality of electrode patterns CEP1, CEP2, and CEP3 may be arranged on a plurality of organic patterns ELP1, ELP2, and ELP3, respectively. In an embodiment, for example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly arranged on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 and the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may be the same as the arrangement relationship between the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may include the same material as the first cathode CE1, the second cathode CE2, and the third cathode CE3, respectively. Such first, second and third electrode patterns CEP1, CEP2 and CEP3 may be traces formed when deposited materials are disconnected from, rather than connected to, the first, second and third cathodes CE1, CE2 and CE3 by the tip TIP1 of the first bank structure 160A.

[0132] A plurality of covering patterns CLP1, CLP2, and CLP3 may be arranged or positioned on the plurality of electrode patterns CEP1, CEP2, and CEP3, respectively. The plurality of covering patterns CLP1, CLP2, and CLP3 may include the same material as the covering layers CPL1, CPL2, and CPL3, respectively. The arrangement relationship between the covering patterns CLP1, CLP2, and CLP3 and the plurality of electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship between the covering layers CPL1, CPL2, and CPL3 and the cathodes CE1, CE2, and CE3. Such covering patterns CLP1, CLP2, and CLP3 may be traces formed when the deposited material is disconnected from the covering layers CPL1, CPL2, and CPL3 by the tip TIP1 of the first embankment structure 160A. The covering patterns CLP1, CLP2, and CLP3 may prevent the lower pattern from being peeled off during the manufacturing process.

[0133] The thin film encapsulation layer 170 may be disposed on the cover layers CPL1, CPL2, and CPL3, the cover patterns CLP1, CLP2, and CLP3, and the embankment structure 160, and may cover the cover layers CPL1, CPL2, and CPL3, the cover patterns CLP1, CLP2, and CLP3, and the embankment structure 160. The thin film encapsulation layer 170 may include at least one inorganic film to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic film to protect the lower structure from foreign matter such as dust. In an embodiment, the thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 sequentially stacked. The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 disposed between the first encapsulation layer 171 and the third encapsulation layer 175 may be an organic encapsulation layer.

[0134] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include at least one selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0135] The second encapsulation layer 173 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, a polyethylene, and the like. In an embodiment, for example, the second encapsulation layer 173 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer 173 may be formed by curing a monomer or applying a polymer.

[0136] The first encapsulation layer 171 may include a first inorganic layer 171 - 1 , a second inorganic layer 171 - 2 , and a third inorganic layer 171 - 3 arranged to correspond to different emission areas EA1 , EA2 , and EA3 , respectively.

[0137] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be arranged to cover the capping layers CPL1, CPL2, and CPL3, the capping patterns CLP1, CLP2, and CLP3, and the embankment structure 160. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed by chemical vapor deposition (CVD), and thus may be formed with a uniform thickness along the contour of the lower structure. In an embodiment, for example, even under the conditions of the undercut structure of the tip TIP1 of the first embankment structure 160A and the undercut structure of the tip TIP2 of the second embankment structure 160B, the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed as a thin film.

[0138] In an embodiment, Figure 5 As shown in , the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in the same layer, but the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes, respectively. In an embodiment, for example, the first inorganic layer 171-1 may be formed after forming the first cathode CE1, the second inorganic layer 171-2 may be formed after forming the second cathode CE2, and the third inorganic layer 171-3 may be formed after forming the third cathode CE3.

[0139] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be arranged to be spaced apart from each other in a portion overlapping the non-emission area NLA. Therefore, a portion of the fourth bank layer 167 included in the second bank structure 160B may be exposed. Therefore, a portion of the fourth bank layer 167 may contact the second encapsulation layer 173.

[0140] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include a touch buffer layer 181, a touch insulating layer 183, touch electrodes TE, and a touch protection layer 185.

[0141] The touch buffer layer 181 may be arranged on the thin film encapsulation layer 170. The touch buffer layer 181 may have insulating and optical functions. The touch buffer layer 181 may include at least one inorganic film. Alternatively, the touch buffer layer 181 may be omitted. Although not shown in the drawings, a connection electrode that electrically connects the touch electrodes TE to each other may be arranged on the touch buffer layer 181. The connection electrode may be formed as a single layer including or made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0142] The touch insulating layer 183 may cover the touch buffer layer 181. The touch insulating layer 183 may have an insulating function. In an embodiment, for example, the touch insulating layer 183 may be an inorganic film including at least one selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0143] The touch electrodes TE may be arranged on the touch insulating layer 183 to overlap the non-emission area NLA. Each of the touch electrodes TE may not overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3. Each of the touch electrodes TE may be formed as a single layer including or made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0144] The touch protection layer 185 may cover the touch electrode TE and the touch insulating layer 183. The touch protection layer 185 may have insulating and optical functions. The touch protection layer 185 may include or be made of the materials listed above with respect to the touch insulating layer 183.

[0145] The light blocking layer BM may be arranged or positioned in the non-emission area NLA, and may be arranged on the touch sensor layer 180. The light blocking layer BM may be arranged to overlap with the inorganic pixel defining layer 151, the embankment structure 160, and the touch electrode TE. The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing caused by penetration of visible light between the first emission area EA1, the second emission area EA2, and the third emission area EA3 to improve the color gamut of the display device 10.

[0146] The color filter layer 190 may be disposed on each of the touch protection layer 185 and the light blocking layer BM to overlap the first, second, and third emission regions EA1, EA2, and EA3.

[0147] The color filter layer 190 may include a first color filter 191, a second color filter 193, and a third color filter 195 arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. A plurality of color filters 191, 193, and 195 may include a colorant (such as a dye or a pigment) that absorbs light of a wavelength band other than light of a specific wavelength band, and may be arranged to correspond to the color of light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3. In an embodiment, for example, the first color filter 191 may be a red color filter arranged to overlap with the first emission area EA1 and transmit only a first light which is red light therethrough. The second color filter 193 may be a green color filter arranged to overlap with the second emission area EA2 and transmit only a second light which is green light therethrough, and the third color filter 195 may be a blue color filter arranged to overlap with the third emission area EA3 and transmit only a third light which is blue light therethrough.

[0148] Figure 5 , a structure in which the plurality of color filters 191, 193, and 195 do not overlap with other adjacent color filters on the light blocking layer BM has been shown, but the present disclosure is not limited thereto. In other words, the plurality of color filters 191, 193, and 195 may be arranged to partially overlap with other adjacent color filters.

[0149] An overcoat layer OC may be disposed on the color filter layer 190 and the light blocking layer BM to planarize the upper ends of the plurality of color filters 191, 193, and 195. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. In an embodiment, for example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0150] Figure 6 yes Figure 5 An enlarged cross-sectional view of portion “T1”. Figure 7 yes Figure 6 An enlarged cross-sectional view of portion “T3”. Figure 8 yes Figure 7 An enlarged cross-sectional view of portion “T5”.

[0151] Reference Figure 6In an embodiment, the inorganic pixel defining layer 151 may be arranged or positioned on the second passivation layer 139 and the first anode AE1. A portion of the inorganic pixel defining layer 151 overlapping the second opening OP2 may be arranged or positioned to be spaced apart from the first anode AE1 in the third direction (Z-axis direction). The residual pattern 157 may be arranged or positioned between the inorganic pixel defining layer 151 and the first anode AE1.

[0152] During the manufacturing process, the display device 10 may include a temporary protective layer between the inorganic pixel defining layer 151 and the first anode AE1. The temporary protective layer may be arranged between the inorganic pixel defining layer 151 and the first anode AE1, and then removed by a subsequent wet etching process. The portion of the temporary protective layer that is not removed may remain as a residual pattern 157 between the inorganic pixel defining layer 151 and the first anode AE1. In other words, since the residual pattern 157 is arranged or positioned between the inorganic pixel defining layer 151 and the first anode AE1 of the display device 10, it will be understood that the display device 10 includes the temporary protective layer during the manufacturing process.

[0153] The first light emitting layer EL1 may be arranged at a portion between the inorganic pixel defining layer 151 and the first anode AE1 spaced apart from each other in the third direction (Z-axis direction). In an embodiment, as described above, the deposition process for forming the first light emitting layer EL1 may be performed so that the material of the first light emitting layer EL1 is deposited in a direction inclined between the first direction (X-axis direction) and the third direction (Z-axis direction). Therefore, the first light emitting layer EL1 may be deposited while partially filling the portion between the first anode AE1 and the inorganic pixel defining layer 151 spaced apart from each other. Therefore, the residual pattern 157 and the first light emitting layer EL1 may be arranged or positioned to contact each other in the portion between the first anode AE1 and the inorganic pixel defining layer 151 spaced apart from each other. For the convenience of description, the first anode AE1 and the first light emitting layer EL1 have been described by way of example, but the first anode AE1, the second anode AE2 and the third anode AE3 and the first light emitting layer EL1, the second light emitting layer EL2 and the third light emitting layer EL3 may all have the same structure and characteristics as each other.

[0154] The first bank structure 160A may be disposed or positioned on the inorganic pixel defining layer 151. The first bank structure 160A may include a first bank layer 161 and a second bank layer 163 including different conductive materials, respectively.

[0155] The first bank layer 161 may be arranged or positioned to contact the inorganic pixel defining layer 151. The first bank layer 161 may cover the inorganic pixel defining layer 151 with the same thickness along the contour of the inorganic pixel defining layer 151. Therefore, the first bank layer 161 may include a stepped structure.

[0156] The first bank layer 161 may include a side surface 161c arranged or positioned toward the first opening OP1. The side surface 161c of the first bank layer 161 may be arranged or positioned in the form of an inclined surface inclined in a direction between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 161c of the first bank layer 161 may be arranged or positioned to be recessed toward one side in the first direction (X-axis direction) than the corresponding side surface of the inorganic pixel defining layer 151. Therefore, the side surface 161c of the first bank layer 161 may partially expose the inorganic pixel defining layer 151 in a portion overlapping with the second opening OP2.

[0157] In an embodiment, as described above, the first cathode CE1, the second cathode CE2, and the third cathode CE3 of the display device 10 may be deposited in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, and may be electrically connected to each other through the first bank layer 161. Therefore, the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be in contact with the side surface 161c of the first bank layer 161. In an embodiment, for example, as the area in which the first cathode CE1, the second cathode CE2, and the third cathode CE3 are in contact with the side surface 161c of the first bank layer 161 increases, the resistance of the display device 10 may be reduced. In addition, the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 and the cover layers CPL1, CPL2, and CPL3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be in contact with the side surface 161c of the first bank layer 161.

[0158] The second bank layer 163 may be disposed or positioned on the first bank layer 161. The second bank layer 163 may be disposed or positioned to be in contact with the first bank layer 161.

[0159] Reference Figure 6 and Figure 7 , the second bank layer 163 may include an upper surface 163b, a lower surface 163a, and a side surface 163c. The lower surface 163a of the second bank layer 163 may be a surface in contact with the first bank layer 161. In addition, the upper surface 163b of the second bank layer 163 may be a surface opposite to the lower surface 163a of the second bank layer 163. Like the first bank layer 161, the second bank layer 163 may cover the first bank layer 161 with the same thickness along the contour of the first bank layer 161. Therefore, the upper surface 163b and the lower surface 163a of the second bank layer 163 may include a step structure.

[0160] The side surface 163 c of the second bank layer 163 may be arranged or positioned toward the first opening OP1 , and may connect the upper surface 163 b and the lower surface 163 a of the second bank layer 163 to each other.

[0161] In some embodiments, the first bank layer 161 and the second bank layer 163 may be formed by a wet etching process during a manufacturing process. Specifically, the first bank layer 161 and the second bank layer 163 included in the first bank structure 160A may be formed to cover the entirety of the first emission region EA1, the second emission region EA2, and the third emission region EA3 during a manufacturing process, and then formed to overlap only the non-emission region NLA included in the structure in the embodiment by a subsequent photolithography process and a wet etching process. In such a process, the second bank layer 163 includes a material that is relatively stable to the wet etching process compared to the first bank layer 161, and therefore, the side surfaces 163c of the second bank layer 163 have a shape in which they protrude toward the center of the first opening OP1 toward the opposite side than the side surfaces 161c of the first bank layer 161. In other words, the side surfaces 161c of the first bank layer 161 may have a shape that is recessed toward the center of the first bank structure 160A than the corresponding side surfaces 163c of the second bank layer 163. Thus, the second bank 163 may include a tip TIP1 protruding toward the center of the first opening OP1 from the side surface 161c of the first bank 161. An undercut structure may be formed between a lower portion of the tip TIP1 of the second bank 163 and the side surface 161c of the first bank 161.

[0162] Reference Figure 7 , the upper surface 163 b of the second bank layer 163 may include a first portion b1 , a second portion b2 , and a third portion b3 defined based on the structures in contact therewith.

[0163] In some embodiments, the first portion b1 of the upper surface 163b of the second bank layer 163 may be a portion in contact with the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3. Figure 7 As shown in , the first portion b1 positioned (or defined) in the other side of the upper surface 163b in the first direction (X-axis direction) may contact the first organic pattern ELP1, and the first portion b1 positioned in one side of the upper surface 163b in the first direction (X-axis direction) may contact the second organic pattern ELP2, but the present disclosure is not limited thereto. That is, the first portion b1 positioned in the other side of the upper surface 163b in the first direction (X-axis direction) may contact one of the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, and the first portion b1 positioned in one side of the upper surface 163b in the first direction (X-axis direction) may contact another one of the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 that is different from one of the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 positioned in the other side of the upper surface 163b.

[0164] The second portion b2 of the upper surface 163b of the second bank layer 163 may be a portion in contact with the first encapsulation layer 171. The third portion b3 of the upper surface 163b may be a portion in contact with the third bank layer 165 of the second bank structure 160B. The third portion b3 of the upper surface 163b of the second bank layer 163 may be positioned between the second portions b2 positioned on opposite sides of the third portion b3.

[0165] Typically, in the case where the second bank structure 160B is not formed on the first bank structure 160A, the upper surface 163b of the second bank layer 163 may include only the first portion b1 and the second portion b2. In other words, a portion of the upper surface 163b of the second bank layer 163 is in a state covered only by the first encapsulation layer 171 and may be exposed to subsequent photolithography and etching processes. Therefore, a portion of the upper surface 163b may be easily damaged and may become a permeation path for moisture and oxygen.

[0166] In an embodiment of the present invention, as disclosed herein, the display device 10 includes the second bank structure 160B on the first bank structure 160A, and thus, the upper surface 163 b of the second bank layer 163 may be protected to be exposed as little as possible during the manufacturing process.

[0167] In some embodiments, a width W163 of the second bank layer 163 may be greater than a width W165 of the third bank layer 165 included in the second bank structure 160B and a width W167 of the fourth bank layer 167 included in the second bank structure 160B.

[0168] The second bank structure 160B may be arranged or positioned to contact the upper surface 163b of the second bank layer 163. In addition, the second bank structure 160B may be arranged or positioned in the first direction (X-axis direction) between a plurality of first patterns ELP1, CEP1, and CLP1 (which may be referred to as the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1 herein) overlapping the first emission area EA1 and a plurality of second patterns ELP2, CEP2, and CLP2 (which may be referred to as the second organic pattern ELP2, the second electrode pattern CEP2, and the second cover pattern CLP2 herein) overlapping the second emission area EA2. The second bank structure 160B may include a third bank layer 165 and a fourth bank layer 167 including different inorganic films, respectively.

[0169] Reference Figure 6 and Figure 7 , the third bank layer 165 may be arranged or positioned to contact the upper surface 163b of the second bank layer 163. The third bank layer 165 may include a side surface 165c arranged or positioned toward the second opening OP2. Figure 6 and Figure 7As shown in FIG. 1 , the side surface 165 c of the third bank layer 165 may be perpendicular to the second bank layer 163 , but the present disclosure is not limited thereto. In another embodiment, the side surface 165 c of the third bank layer 165 may be an inclined surface having an inclined shape.

[0170] The third bank layer 165 may include a silicon-based inorganic film containing oxygen. In an embodiment, for example, the third bank layer 165 may include silicon oxynitride (SiON) and silicon oxide (SiO 2 In an embodiment, for example, the oxygen content in the third bank layer 165 may be about 33% or more.

[0171] In some embodiments, the third bank layer 165 may be arranged to cover the first bank structure 160A and the first, second and third anodes AE1, AE2 and AE3 during the manufacturing process, and then formed into the shape of the third bank layer 165 shown in the drawings through a photolithography process and a dry etching process included in subsequent processes.

[0172] In an embodiment, Figure 7 As shown in , the fourth bank layer 167 may be positioned on the third bank layer 165. The fourth bank layer 167 may include an upper surface 167b and a side surface 167c. The upper surface 167b of the fourth bank layer 167 may be a surface opposite to the second encapsulation layer 173. The side surface 167c of the fourth bank layer 167 may be arranged or positioned to protrude toward the center of the first opening OP1 more than the side surface 165c of the third bank layer 165. In an embodiment, as shown in FIG. Figure 6 and Figure 7 As shown in FIG. 1 , the side surface 167c of the fourth bank layer 167 may be perpendicular to the second bank layer 163 in the third direction (Z-axis direction), but the present disclosure is not limited thereto. In another embodiment, the side surface 167c of the fourth bank layer 167 may be an inclined surface having an inclined shape.

[0173] The fourth bank layer 167 may include a silicon-based inorganic film including nitrogen. In an embodiment, for example, the fourth bank layer 167 may include silicon nitride (Si 3 N 4 ) and silicon oxynitride (SiON). In an embodiment, for example, the nitrogen content in the fourth bank layer 167 may be about 33% or more. The fourth bank layer 167 may have an etch rate relatively lower than that of the third bank layer 165.

[0174] In some embodiments, the fourth bank layer 167 may be arranged to cover the entirety of the third bank layer 165 and the first anode AE1, the second anode AE2, and the third anode AE3 during a manufacturing process, and then formed into the shape of the fourth bank layer 167 shown in the drawings by a photolithography process and a dry etching process included in a subsequent process. The third bank layer 165 and the fourth bank layer 167 may be formed in the same manufacturing process, but the etching rates of the third bank layer 165 and the fourth bank layer 167 may be different from each other according to the physical properties of the materials of the third bank layer 165 and the fourth bank layer 167. Specifically, the etching rate of the third bank layer 165 including the inorganic film having a high oxygen content may be greater than the etching rate of the fourth bank layer 167 including the inorganic film having a high nitrogen content.

[0175] In an embodiment, as described above, the fourth bank layer 167 includes a material that is relatively stable to the dry etching process compared to the third bank layer 165, and therefore, the side surface 167c of the fourth bank layer 167 may have a shape that protrudes toward the center of the first opening OP1 and the second opening OP2 than the side surface 165c of the third bank layer 165. In other words, the side surface 165c of the third bank layer 165 may have a shape that is recessed toward the center of the second bank structure 160B than the side surface 167c of the fourth bank layer 167. Therefore, the fourth bank layer 167 may include a tip TIP2 that protrudes toward the center of the first opening OP1 and the second opening OP2 than the side surface 165c of the third bank layer 165. An undercut structure may be formed between the lower portion of the tip TIP2 of the fourth bank layer 167 and the side surface 165c of the third bank layer 165. The width W165 of the third bank layer 165 may be smaller than the width W167 of the fourth bank layer 167.

[0176] In an embodiment, as described above, the first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be formed in different processes, respectively. Specifically, the first inorganic layer 171-1 may be formed to also cover the second emission area EA2 and the third emission area EA3 after forming the first cover layer CPL1, and then be removed in a portion other than the portion overlapping with the first emission area EA1 by a subsequent photolithography process and a dry etching process. In addition, the second inorganic layer 171-2 may be formed to also cover the first emission area EA1 and the third emission area EA3 after forming the second cover layer CPL2, and then be removed in a portion other than the portion overlapping with the second emission area EA2 by a subsequent photolithography process and a dry etching process. In addition, the third inorganic layer 171 - 3 may be formed to also cover the first and second emission regions EA1 and EA2 after forming the third capping layer CPL3 , and then removed in portions other than a portion overlapping the third emission region EA3 by subsequent photolithography and dry etching processes.

[0177] Therefore, the first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other in the first direction (X-axis direction) in the portion overlapping the non-emission area NLA. Specifically, the first inorganic layer 171-1 and the second inorganic layer 171-2 may be spaced apart from each other in the first direction (X-axis direction) on the upper surface 167b of the fourth bank layer 167. For the convenience of description, only the first inorganic layer 171-1 and the second inorganic layer 171-2 are described, but the third inorganic layer 171-3 may also have the same structure and characteristics as those of the first inorganic layer 171-1 and the second inorganic layer 171-2.

[0178] The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may cover the lower structure along the contour of the lower structure. Figure 6As shown in , the first inorganic layer 171-1 may cover the lower structure along the contour of the lower structure in the portion overlapping with the first emission area EA1, and the second inorganic layer 171-2 may cover the lower structure along the contour of the lower structure in the portion overlapping with the second emission area EA2. Specifically, the first inorganic layer 171-1 may contact and cover the first cover layer CPL1, the side surface 161c of the first bank layer 161, the lower surface 163a of the second bank layer 163, and the plurality of first patterns ELP1, CEP1, and CLP1 in the portion overlapping with the first emission area EA1, and the second inorganic layer 171-2 may contact and cover the second cover layer CPL2, the side surface 161c of the first bank layer 161, the lower surface 163a of the second bank layer 163, and the plurality of second patterns ELP2, CEP2, and CLP2 in the portion overlapping with the second emission area EA2.

[0179] In addition, the first inorganic layer 171-1 may cover a plurality of first patterns ELP1, CEP1 and CLP1, a side surface 165c of the third embankment layer 165, and a protruding tip TIP2 of the fourth embankment layer 167 in a portion overlapping with the non-emission area NLA, and the second inorganic layer 171-2 may cover a plurality of second patterns ELP2, CEP2 and CLP2, a side surface 165c of the third embankment layer 165, and a protruding tip TIP2 of the fourth embankment layer 167 in a portion overlapping with the non-emission area NLA.

[0180] Reference Figure 7 , the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be arranged or positioned to be spaced apart from the upper surface 167b of the fourth bank layer 167 in the third direction (Z-axis direction). Therefore, a cavity may be defined or formed between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 and the upper surface 167b of the fourth bank layer 167.

[0181] In some embodiments, in the manufacturing process of the display device 10, after forming the first bank structure 160A, the second bank structure 160B may be formed, and then, the first light emitting layer EL1, the first cathode CE1, and the first capping layer CPL1 may be sequentially formed. In such a process, the plurality of patterns ELP, CEP, and CLP may be formed not only on the upper surface 163b of the second bank layer 163, but also on the upper surface 167b of the fourth bank layer 167. However, the plurality of patterns ELP, CEP, and CLP formed on the upper surface 167b of the fourth bank layer 167 may be removed by a subsequent photolithography process and a dry etching process performed after forming the first encapsulation layer 171. Therefore, a cavity may be formed between the first encapsulation layer 171 and the upper surface 167b of the fourth bank layer 167. In other words, since the cavity is defined between the first encapsulation layer 171 and the upper surface 167 b of the fourth bank layer 167 , it will be understood that the plurality of patterns ELP, CEP, and CLP were provided or positioned on the upper surface 167 b of the fourth bank layer 167 .

[0182] The second encapsulation layer 173 may be arranged or positioned on the first encapsulation layer 171. The second encapsulation layer 173 may cover the first encapsulation layer 171 along the contour of the first encapsulation layer 171. Specifically, the second encapsulation layer 173 may cover the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 in the portion overlapping the first emission area EA1, the second emission area EA2, and the third emission area EA3, and may be arranged or positioned between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 spaced apart from each other in the portion overlapping the non-emission area NLA. In addition, the second encapsulation layer 173 may fill the cavity in the portion overlapping the non-emission area NLA.

[0183] In some embodiments, the first encapsulation layer 171 may form a space SA in a portion overlapping the non-emission area NLA. Specifically, the first encapsulation layer 171 may form a space SA below the tip TIP2 of the fourth bank layer 167. In an embodiment, for example, the space SA may be formed as the first encapsulation layer 171 covers the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167 along the contours of the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167. In an embodiment, as Figure 8 As shown in , the space SA may be completely surrounded by the first encapsulation layer 171. In an embodiment, for example, according to the manufacturing environment of the display device 10, the space SA may be filled with nitrogen or air, but is not limited thereto.

[0184] Fig. 9 According to another embodiment Figure 7 An enlarged cross-sectional view of portion “T5”.

[0185] Reference Fig. 9 , except that the first encapsulation layer 171 does not form a space SA in a portion overlapping the non-emission area NLA, the display device 30 of another embodiment is substantially the same as the display device 10 according to the above embodiment. Specifically, Fig. 9 The display device 30 is the same as the display device 10 according to the above-described embodiment in that the first encapsulation layer 171 covers the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167 along the contours of the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167, but is different from the display device 10 according to the above-described embodiment in that the first encapsulation layer 171 forms a narrow gap instead of the space SA while covering the lower structure along the contour of the lower structure. The narrow gap formed by the first encapsulation layer 171 of the display device 30 may be filled with the second encapsulation layer 173. This may be adjusted during the manufacturing process according to the contour of the lower structure to be covered by the first encapsulation layer 171.

[0186] Fig.10 According to another embodiment Figure 5 An enlarged cross-sectional view of portion “T1”. Fig.11 yes Fig.10 An enlarged cross-sectional view of portion “Q5”. Fig.12 According to another embodiment Fig.10 An enlarged cross-sectional view of portion “Q5”.

[0187] Reference Fig.10 The display device 50 of another embodiment is substantially the same as the display device according to the above embodiment, except that the second bank structure 160B includes a third bank layer 165 and a fourth bank layer 167 including materials different from those described above.

[0188] According to the embodiment, the third bank layer 165 may include an organic material or an inorganic material. In the embodiment, for example, the organic material of the third bank layer 165 may include acrylic resin, silicon-based resin or silicon acrylic resin, and the inorganic material of the third bank layer 165 may include silicon oxide, silicon nitride or silicon oxynitride.

[0189] In some embodiments, the third bank layer 165 of the display device 50 may be arranged to cover the first bank structure 160A and the first anode AE1, the second anode AE2, and the third anode AE3 during the manufacturing process, and then formed into a Fig.10 The shape of the third bank layer 165 is shown in FIG. Other features thereof are substantially the same as those described above, and any repeated detailed description thereof will be omitted.

[0190] The fourth bank layer 167 of the display device 50 may include an organic material. The organic material of the fourth bank layer 167 may include acrylic resin, silicon-based resin, or silicon acrylic resin.

[0191] In some embodiments, the fourth bank layer 167 may be arranged to cover the third bank layer 165 and the entirety of the first anode AE1, the second anode AE2, and the third anode AE3 during the manufacturing process, and then formed into Fig.10 The shape of the fourth bank layer 167 is shown in FIG. The third bank layer 165 and the fourth bank layer 167 may be formed in the same manufacturing process as each other, but the etching rate of the third bank layer 165 and the etching rate of the fourth bank layer 167 may be different from each other according to the physical properties of the materials of the third bank layer 165 and the fourth bank layer 167. In an embodiment, the etching rate of the third bank layer 165 may be greater than the etching rate of the fourth bank layer 167.

[0192] In some embodiments, the thickness H167 of the fourth bank layer 167 may decrease in the first direction (X-axis direction) toward the first encapsulation layer 171. This may be caused by the fourth bank layer 167 including an organic material. However, the present disclosure is not limited thereto, and the thickness H167 of the fourth bank layer 167 may also become uniform through subsequent processes.

[0193] Reference Fig.11 , the first encapsulation layer 171 of the display device 50 may form a space SA in a portion overlapping the non-emission area NLA. Specifically, the first encapsulation layer 171 may form a space SA below the tip TIP2 of the fourth bank layer 167 .

[0194] In some embodiments, the space SA may be formed as the first encapsulation layer 171 covers the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167 along the contours of the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167. In an embodiment, as Fig.11As shown in , the space SA may be completely surrounded by the first encapsulation layer 171. In an embodiment, for example, according to the manufacturing environment of the display device 50, the space SA may be filled with nitrogen or air, but is not limited thereto. Other features thereof are substantially the same as those described above, and any repeated detailed description thereof will be omitted.

[0195] Reference Fig.12 , the display device 70 is different from the display device 50 according to the above-described embodiment in that the first encapsulation layer 171 does not form the space SA in the portion overlapping the non-emission area NLA. Specifically, the display device 70 is the same as the display device 50 according to the above-described embodiment in that the first encapsulation layer 171 covers the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167 along the contours of the plurality of patterns ELP, CEP, and CLP, the upper surface 163b of the second bank layer 163, the side surface 165c of the third bank layer 165, and the protruding tip TIP2 of the fourth bank layer 167, but is different from the display device 50 according to the above-described embodiment in that the first encapsulation layer 171 forms a narrow gap instead of the space SA while covering the lower structure along the contour of the lower structure. The narrow gap formed by the first encapsulation layer 171 of the display device 70 may be filled with the second encapsulation layer 173. This may be adjusted during the manufacturing process according to the contour of the lower structure of the display device 70 to be covered by the first encapsulation layer 171 .

[0196] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0197] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising an emitting region and a non-emitting region; an anode positioned on the emitting region of the substrate; a pixel defining layer positioned on the anode and overlapping the non-emitting region, wherein a first opening is defined through the pixel defining layer; a first bank structure, the first bank structure being positioned on the pixel defining layer and comprising at least two different conductive materials, wherein a second opening is defined by the first bank structure; a second bank structure positioned on the first bank structure and comprising at least two different materials; as well as a first encapsulation layer, the first encapsulation layer being positioned on the second bank structure, wherein the first bank structure includes a first bank layer and a second bank layer, the second bank layer includes a first tip protruding toward the center of the first opening from a side surface of the first bank layer, The second bank structure includes a third bank layer and a fourth bank layer, the fourth bank layer includes a second tip protruding toward the center of the second opening from a side surface of the third bank layer, and The first encapsulation layer covers the first tip and the second tip.

2. The display device according to claim 1, further comprising: a first light emitting layer, the first light emitting layer being positioned on the anode to overlap the first opening; a cathode positioned on the first light-emitting layer; a first organic pattern, the first organic pattern being positioned on the second bank layer while surrounding the first opening and including the same material as the first light emitting layer; as well as A first electrode pattern is positioned on the first organic pattern while surrounding the first opening and includes the same material as the cathode.

3. The display device according to claim 2, wherein: The first light emitting layer and the cathode are in contact with the side surface of the first bank layer.

4. The display device according to claim 3, wherein: The first organic pattern is spaced apart from the first light emitting layer, The first electrode pattern is spaced apart from the cathode, and The first organic pattern and the first electrode pattern overlap the first tip.

5. The display device according to claim 4, wherein: The first bank layer includes aluminum, and The second bank layer includes titanium.

6. The display device according to claim 1, wherein: The first encapsulation layer contacts the side surface of the first bank layer and the first tip end of the second bank layer.

7. The display device according to claim 2, wherein: The second bank layer includes a first surface opposite to the third bank layer, and The first surface comprises: a first portion, the first portion being in contact with the first organic pattern; a second portion, the second portion being in contact with the first encapsulation layer; and A third portion is in contact with the third bank layer.

8. The display device according to claim 7, wherein: The second portion is positioned between the first portion and the third portion, and The first portion, the second portion and the third portion are integrally formed as a single and indivisible part.

9. The display device according to claim 8, wherein: The first encapsulation layer contacts the side surface of the third bank layer.

10. The display device according to claim 1, wherein: A cavity overlapping the second tip is defined between the fourth bank layer and the first encapsulation layer.

11. The display device according to claim 10, further comprising: a second encapsulation layer, the second encapsulation layer being positioned on the first encapsulation layer, Wherein, the cavity is filled with the second encapsulation layer.

12. The display device according to claim 1, wherein: In a direction perpendicular to the substrate, a space completely surrounded by the first encapsulation layer is defined between the second bank layer and the fourth bank layer.

13. The display device according to claim 1, wherein: The third bank layer includes an inorganic film containing 33% or more of oxygen, The fourth bank layer includes an inorganic film including 33% or more of nitrogen.

14. The display device according to claim 1, wherein: The third bank layer includes an organic material or an inorganic material, and The fourth bank layer includes an organic material.

15. The display device according to claim 1, wherein: The width of the third bank layer is smaller than the width of the fourth bank layer.

16. The display device according to claim 15, wherein: The first bank layer and the second bank layer overlap the emission region, and The third bank layer and the fourth bank layer do not overlap the emission region.

17. A display device, comprising: a substrate comprising a first emission region, a second emission region, and a non-emitting region positioned between the first emission region and the second emission region; a first anode positioned on the first emitting region of the substrate; a second anode positioned on the second emitting region of the substrate; a pixel defining layer positioned on the non-emitting region of the substrate between the first anode and the second anode, wherein a plurality of openings are defined through the pixel defining layer; a first bank structure positioned on the pixel defining layer and comprising at least two different conductive materials; a second bank structure positioned on the first bank structure and comprising at least two different inorganic films; as well as a first encapsulation layer, the first encapsulation layer being positioned on the second bank structure, wherein the first bank structure includes a first bank layer and a second bank layer including a plurality of first tips, each of the plurality of first tips protruding from a corresponding one of the plurality of side surfaces of the first bank layer toward a center of a corresponding one of the plurality of openings, The second bank structure includes a third bank layer and a fourth bank layer including a plurality of second tips, each of the plurality of second tips protruding toward a center of a corresponding one of the plurality of openings from a corresponding one of the plurality of side surfaces of the third bank layer, and The first encapsulation layer covers the plurality of first tips and the plurality of second tips.

18. The display device according to claim 17, wherein: The first encapsulation layer comprises: a first inorganic layer, the first inorganic layer overlapping the first emission region; and a second inorganic layer, the second inorganic layer overlapping the second emission region, and A portion of the first inorganic layer overlapping the fourth bank layer and a portion of the second inorganic layer overlapping the fourth bank layer are spaced apart from each other.

19. The display device according to claim 18, further comprising: a first light-emitting layer, the first light-emitting layer being positioned on the first anode; a second light-emitting layer, the second light-emitting layer being positioned on the second anode; a first organic pattern, the first organic pattern being positioned on the second bank layer to overlap the first emission region, including the same material as the first light emitting layer, and being spaced apart from the first light emitting layer; as well as a second organic pattern, the second organic pattern being positioned on the second bank layer to overlap the second emission region, including the same material as the second light emitting layer, and being spaced apart from the second light emitting layer, The third bank layer is located between the first organic pattern and the second organic pattern.

20. The display device according to claim 19, further comprising: a first light-emitting element, the first light-emitting element comprising the first anode and the first light-emitting layer; as well as a second light-emitting element, the second light-emitting element comprising the second anode and the second light-emitting layer, wherein, in a plan view, the first light emitting element and the second light emitting element are completely surrounded by the pixel defining layer, and In the plan view, the pixel defining layer is completely surrounded by the first bank structure.

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