A silk screen binding method, device and system for a server add-in card

Abstract

The application relates to the technical field of servers and discloses a silk printing binding method, device and system of a server external plug-in card equipment, the method is applied to a processing module on a mainboard, the method comprises the following steps: obtaining a PCIe expansion card position in a server, reading burning information through an I2C switch of the PCIe expansion card, obtaining physical slot silk printing of a server where a PCIe device is located on each slot, and obtaining an I2C address bound by each PCIe device; determining at least one PCIe device address according to a preset processor address, slot bandwidth information and at least one mapping relationship and in-place information of the PCIe device on each slot; establishing a binding relationship among the physical slot silk printing of the PCIe device on each slot, the PCIe device address and the I2C address, and managing the PCIe device by using the binding relationship. The method enables BIOS or BMC to freely access the same device through an I2C path, and solves the problem that a specified device cannot be managed.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a silk screen binding method, device and system for server external card equipment. Background Art

[0002] With the rapid development of information technology and the deepening of digital transformation, the rise and rapid development of new technologies such as artificial intelligence, edge computing, cloud computing, and virtual reality, coupled with the explosion of processed data volume, has led to a continuous increase in the scale of servers in large data centers. As an important component of server information infrastructure, PCIe (Peripheral Component Interconnect Express)-compliant devices in servers play a vital role in networking, storage, and GPU (Graphics Processing Unit) computing scenarios.

[0003] Currently, PCIe devices are typically designed with access paths such as the PCIe bus and I2C bus. Therefore, the BMC (Baseboard Management Controller) and BIOS (Basic Input Output System) must be able to bind their PCIe addresses, I2C addresses, and the physical silkscreen address of the server they are located in. This allows for asset management, fault diagnosis and location, and temperature information sources for cooling strategies. Failure to determine the address mapping of PCIe devices can impact data center server operations and maintenance, and may even cause server downtime due to improper PCIe device management. Summary of the Invention

[0004] In view of this, the present invention provides a silk screen binding method, device and equipment for server external card devices, the purpose of which is to realize the binding between the server physical silk screen of the PCIe device and the PCIe address and I2C address.

[0005] In a first aspect, the present invention provides a silkscreen binding method for a server plug-in card device. The method can be applied to a processing module on a mainboard, wherein the processing module is connected to a PCIe expansion card via an I2C bus. The method comprises:

[0006] Obtaining the location of a PCIe expansion card in a server through I2C bus access, and reading programming information through an I2C switch of the PCIe expansion card, wherein the programming information includes: I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information, and at least one mapping relationship;

[0007] According to the PCIe slot information and its mapping relationship, obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot, and scan to obtain the I2C address bound to each PCIe device;

[0008] Determining at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and information about a PCIe device in each of the PCIe slots;

[0009] A binding relationship is established between the physical slot silk screen of the PCIe device on each PCIe slot, at least one PCIe device address and the I2C address, and at least one PCIe device is managed using the binding relationship.

[0010] The silkscreen binding method provided by the present invention obtains the location of a PCIe expansion card in a server via I2C bus access, reads the burned-in information of the hardware device, and determines the physical slot silkscreen of the server where the PCIe device is located, the I2C address bound to each PCIe device, and the PCIe device address based on the burned-in information. A binding relationship is then established between the server silkscreen address of the PCIe device and the PCIe address and I2C address. This allows the BIOS or BMC to freely access the same device via the I2C path, solving the problem of being unable to manage a specified device. This method manages by establishing a binding relationship, more effectively monitoring and maintaining the status of PCIe devices, promptly identifying and resolving problems, and improving the reliability and maintainability of the entire system.

[0011] In combination with the first aspect, in an optional implementation, the PCIe slot information includes: a PCIe slot sequence and a relative position of the slot on the PCIe expansion card.

[0012] The obtaining, based on the PCIe slot information, a physical slot silkscreen of the server where the PCIe device is located on each PCIe slot includes: obtaining, based on the PCIe slot sequence, PCIe slot bandwidth information, and the relative position of the slot on the PCIe expansion card, in combination with the position of the PCIe expansion card, the physical slot silkscreen of the PCIe device on each PCIe slot.

[0013] In combination with the first aspect, in another optional implementation, the at least one mapping relationship includes: a mapping relationship between the at least one expansion chip and at least one PCIe slot.

[0014] The determining of at least one PCIe device address according to the preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and the presence information of the PCIe device in each of the PCIe slots includes:

[0015] Accessing at least one expansion chip corresponding to the at least one PCIe slot according to the mapping relationship, and obtaining presence information, processor address information, and PCIe port address information of each PCIe device based on a preset processor address, a relationship between pins on a high-speed connector of a motherboard and the processor address, a presence signal of the at least one PCIe device, and PCIe slot bandwidth information;

[0016] If the processing module is a basic input and output system BIOS, scanning at least one PCIe device according to the processor address information and the PCIe port address information, and binding a unique identifier to each of the PCIe devices;

[0017] The BIOS sends a binding relationship between at least one PCIe device and the unique identifier to a baseboard management controller BMC.

[0018] In combination with the first aspect, in yet another optional implementation, scanning at least one PCIe device according to the processor address information and the PCIe port address information, and binding a unique identifier to each PCIe device, includes:

[0019] The BIOS assigns a unique identifier to the PCIe device on each PCIe slot according to the PCIe port of the processor address information; and establishes a binding relationship between the unique identifier and the PCIe port.

[0020] In combination with the first aspect, in yet another optional implementation, the method further includes:

[0021] If the processing module is a BMC, the BMC receives a binding relationship between at least one PCIe device and a unique identifier sent by the BIOS;

[0022] The establishing of a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, the at least one PCIe device address, and the I2C address includes:

[0023] The BMC establishes a binding relationship between the physical slot silkscreen, the at least one PCIe device address, and the I2C address according to the physical slot silkscreen, the binding relationship between the at least one PCIe device address and the I2C address, and the binding relationship between the at least one PCIe device and the I2C address.

[0024] In combination with the first aspect, in another optional embodiment, obtaining the I2C address bound to each of the PCIe devices includes: scanning PCIe plug-in devices according to the channel mapping relationship of the I2C switch, binding an I2C address for each of the PCIe devices, and obtaining the I2C address.

[0025] In combination with the first aspect, in another optional embodiment, before obtaining the location of the PCIe expansion card in the server through I2C bus access, it also includes: adding a first pin representing the processor CPU address on the high-speed connector of the motherboard, and adding a second pin representing the PCIe port address; storing the information of the first pin and the second pin through at least one expansion chip.

[0026] In a second aspect, the present invention further provides a silk screen binding device for a server external card device, the device comprising:

[0027] A reading module is configured to obtain the location of a PCIe expansion card in a server through an I2C bus access and read programming information through an I2C switch of the PCIe expansion card, wherein the programming information includes: I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information, and at least one mapping relationship;

[0028] An acquisition module is used to obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot based on the PCIe slot information and its mapping relationship, and to scan and obtain the I2C address bound to each PCIe device;

[0029] a determination module, configured to determine at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and information about a PCIe device in each PCIe slot;

[0030] An establishment module is used to establish a binding relationship between the physical slot silk screen of the PCIe device on each PCIe slot, the at least one PCIe device address and the I2C address, and use the binding relationship to manage the at least one PCIe device address.

[0031] In a third aspect, the present invention provides a silk screen binding system, comprising a mainboard and at least one PCIe expansion card; wherein the mainboard comprises at least one processing module, at least one arbitration chip, and at least one high-speed connector; each of the PCIe expansion cards comprises an I2C switch, a storage unit, at least one expansion chip, and at least one PCIe slot;

[0032] The at least one processing module is connected to the at least one expansion chip of the PCIe expansion card through the at least one arbitration chip and the at least one high-speed connector;

[0033] The I2C switch is connected to the storage unit and the at least one PCIe slot through different channels, and the storage unit is used to store burning information, and the burning information includes: I2C address information of the at least one expansion chip, PCIe slot information and at least one mapping relationship;

[0034] Each of the processing modules stores computer instructions, and by executing the computer instructions, the silk screen binding method for the server external card device described in the first aspect or any corresponding embodiment thereof is executed.

[0035] Optionally, in an optional implementation manner, if the number of the processing module is one, the processing module is a baseboard management controller BMC or a basic input and output system BIOS.

[0036] If the number of the processing modules is two, the two processing modules are respectively a BMC and a BIOS.

[0037] In a fourth aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the silk screen binding method of a server external card device according to the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0038] In a fifth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the silk screen binding method for a server external card device according to the first aspect or any corresponding embodiment thereof.

[0039] In addition, the present invention provides a computer program product including computer instructions, which are used to enable a computer to execute the silk screen binding method for a server external card device according to the first aspect or any corresponding embodiment thereof.

[0040] The present invention provides a silkscreen binding method, device, and system for server plug-in card devices. These methods obtain the location of a PCIe expansion card in a server via I2C bus access, read the hardware device's burn-in information and the GPIO expansion chip's stored information, and determine the physical slot silkscreen of the server where the PCIe device resides, the I2C address bound to each PCIe device, and the PCIe device address based on the burn-in information. These methods then establish a binding relationship between the server silkscreen address of the PCIe device and the PCIe and I2C addresses. This allows the BIOS or BMC to freely access the same device via the I2C path, resolving the issue of being unable to manage a specified device. By establishing this binding relationship for management, the status of PCIe devices can be more effectively monitored and maintained, problems can be promptly discovered and resolved, and the reliability and maintainability of the entire system can be improved.

[0041] In addition, this method fully automates the binding of the PCIe address, I2C address, and server slot silkscreen address of the PCIe device, avoiding the need to adapt the BIOS or BMC firmware for newly developed PCIe expansion cards or for reuse in new product models, thus reducing the workload of hardware R&D and BIOS / BMC firmware development. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 This is a schematic diagram of a structure for binding a PCIe address and a silk screen according to an embodiment of the present invention;

[0044] Figure 2 This is a structural diagram of a system for connecting a motherboard and a PCIe expansion card according to an embodiment of the present invention;

[0045] Figure 3 This is a flow chart of a silk screen binding method for a server external card device according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of a physical silk screen of a server PCIe add-in card device according to an embodiment of the present invention;

[0047] Figure 5 1 is a flow chart of another method for silk screen binding of a server external card device according to an embodiment of the present invention;

[0048] Figure 6This is a flow chart of another method for silk screen binding of a server external card device according to an embodiment of the present invention;

[0049] Figure 7 This is a structural block diagram of a silk screen binding device according to an embodiment of the present invention;

[0050] Figure 8 FIG. 4 is a schematic diagram of the hardware structure of a processing module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0052] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0053] In addition, the terms “first” and “second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0054] The technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0055] First, the application scenarios and related technical terms of the technical solutions provided by the embodiments of the present invention are introduced.

[0056] like Figure 1 The figure shows a schematic diagram of a PCIe address and silkscreen binding scenario provided by an embodiment of the present invention. The scenario includes a motherboard and a PCIe expansion card, and the motherboard and the PCIe expansion card are connected via an I2C bus.

[0057] Figure 1 In the present invention, a hard code programming method of semi-automatic identification of PCIe device addresses is used to implement the PCIe address allocation of PCIe devices and the binding of server silk screen addresses. However, this method cannot implement the binding of PCIe addresses of PCIe devices and I2C addresses.

[0058] Specifically, in one embodiment, the central processing unit (CPU) address and the CPU's PCIe port address are encoded, and the encoded content is saved through a GPIO (General Purpose Input Output) expansion chip (Expander) device. The BIOS or BMC reads and parses the PCIe device address to implement PCIe address allocation. At the same time, the BIOS or BMC writes the mapping relationship between the physical silkscreen address in the server system configuration and the PCIe address into the BIOS or BMC code in advance through a hard-coded method, thereby implementing the binding of the PCIe address allocation of the PCIe device and the physical silkscreen address of the server. This method cannot achieve the binding of the PCIe address and the I2C address, making it impossible for the BIOS or BMC to manage the same device through the PCIe path and the I2C path when accessing the PCIe device.

[0059] In addition, when using this hard-coding method to bind the PCIe address of the PCIe device to the server silkscreen address, every time a PCIe expansion card is developed, the BIOS and / or BMC of the PCIe device card needs to be adapted, including BIOS and BMC version upgrades, which increases the workload of hardware R&D and BIOS / BMC firmware development.

[0060] In order to solve the above problems, an embodiment of the present invention provides a silk screen binding method for a server external card device, which can be applied to a motherboard and PCIe expansion card connection system.

[0061] like Figure 2 As shown, the system includes a motherboard and a PCIe expansion card. The motherboard and the PCIe expansion card can be connected via an I2C bus. Furthermore, the motherboard includes: a BMC, a BIOS, at least one I2C arbitration chip, at least one high-speed connector (also known as a high-speed connector MCIO) and an I2C bus. In addition, the motherboard also includes at least one CPU, Figure 2 The CPU is not shown.

[0062] The high-speed MCIO connector, short for Multi-Channel Input / Output, is an interface technology that combines multiple physical channels into a single high-speed data stream. MCIO interfaces are classified into various types based on application requirements, with MCIO16 and MCIO8 being the most common. Figure 2 There are four high-speed connectors shown in the figure: MCIO16_0, MCIO8_0, MCIO16_1 and MCIO8_0.

[0063] Among them, a pin representing the CPU address can be added to each high-speed connector MCIO, namely CPU_Addr0 / 1 / 2, indicating three CPU addresses, which can represent CPU0, CPU1, ..., CPU7, etc. through CPU coding.

[0064] The I2C arbitration chip is used to switch the I2C bus. Figure 2 The figure shows two I2C buses, I2C0 and I2C1, connected to I2C Arbitration Chip 0 and I2C Arbitration Chip 1, respectively. Arbitration Chip 0 and I2C Arbitration Chip 1 are used to connect or disconnect the high-speed MCIO connector, thereby connecting or disconnecting a PCIe expansion card. In this embodiment, Arbitration Chip 0 controls bus I2C0 to connect to GPIO Expansion Chip 0; Arbitration Chip 1 controls bus I2C1 to connect to GPIO Expansion Chip 1.

[0065] It should be understood that in this embodiment, the number of high-speed connector MCIO and I2C arbitration chips can be freely set according to actual needs and is not limited in this embodiment. Similarly, the number of PCIe expansion cards can be one or more, and can be set according to actual needs and is not limited in this embodiment.

[0066] The BIOS is a program embedded in the motherboard of a computer system. It performs hardware initialization and self-tests during computer startup, and provides basic input and output functions to ensure the normal startup and operation of the operating system. Specifically, BIOS functions include hardware initialization, self-tests, boot sequence settings, and basic input and output functions.

[0067] BMC is a controller specifically used to manage server hardware, which can provide functions such as remote management, monitoring, fault diagnosis, etc. In this embodiment, BMC can be used to implement a remote management method and monitoring system for the server.

[0068] In this embodiment, both the BIOS and the BMC may serve as a processing module or a processing circuit to execute the method provided in this embodiment.

[0069] exist Figure 2 In the example, a PCIe expansion card includes: a storage unit, a cable, at least one GPIO expansion chip, an I2C switch chip, at least one PCIe slot and other components or modules.

[0070] The I2C switch chip, also known as an I2C switch, connects to the storage unit and PCIe slots via multiple channels (CHs). In this embodiment, the IC2 switch connects to the storage unit via channel 0 (CH0), PCIe slot 0 via channel 1 (CH1), and PCIe slot 1 via channel 2 (CH2).

[0071] In addition, in the PCIe expansion card, GPIO expansion chip 0 and GPIO expansion chip 1 include multiple pins, for example, each includes 8 pins from P00 to P07, and are connected to the PCIe slot through a set pin, such as P00.

[0072] An embodiment of the present invention provides an embodiment of a silk screen binding method for a server external card device. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0073] In this embodiment, a silk screen binding method for a server plug-in card device is provided, which can be used for the above-mentioned processing modules, such as BIOS and / or BMC. Before executing this method, the hardware device provided in this embodiment needs to be configured first.

[0074] Combine Figure 2 , the hardware design of the embodiment is performed on the device side of the motherboard and PCIe expansion card. The specific hardware design execution process is as follows:

[0075] First, configure the motherboard hardware. Add pins representing the CPU address (collectively referred to as the first pins) to the MCIO high-speed connector. These pins, CPU_ADDR0 / 1 / 2, represent CPU0, CPU1, ..., CPU7, respectively, using CPU encoding. Also, add pins representing the PCIe port address (collectively referred to as the second pins), PE0 / 1 / 2 / 3, to the MCIO high-speed connector. These pins represent different PCIe port descriptors.

[0076] In addition, after the high-speed MCIO connector is connected to the PCIe expansion card via a cable, the CPU_ADDR0 / 1 / 2 pin information and PE0 / 1 / 2 / 3 information are stored via the GPIO expansion chip / expansion card. There is a preset mapping relationship between the GPIO expansion chip and the PCIe slot number. For example, the preset mapping relationship includes: GPIO expansion chip 0 corresponds to PCIe slot 0, and GPIO expansion chip 1 corresponds to PCIe slot 1. Configuration on the motherboard side can store the CPU address information and PCIe port address information corresponding to the PCIe slot in the GPIO expansion chip corresponding to the slot.

[0077] Optionally, the pin information of the above address CPU_ADDR0 / 1 / 2 is stored in the GPIO expansion chip / expansion card and occupies 3 available bits, and the storage of PE0 / 1 / 2 / 3 information can occupy 4 bits.

[0078] In this embodiment, on the motherboard, either BMC or BIOS can be used as an I2C host, and multiple I2C arbitration chips can be connected to different I2C connectors. Figure 2 In the application structure, I2C arbitration chip 0 is located in I2C Bus 0, I2C0_0 / I2C1_0, and I2C arbitration chip 1 is located in I2C Bus 1, I2C0_1 / I2C1_1.

[0079] The I2C connector can be a separate connector or added to the high-speed MCIO connector. The BMC or BIOS can control the I2C arbitration chip to set the sole I2C master control to itself, so that only one I2C master can access the corresponding I2C bus at a time.

[0080] In addition, different I2C arbitration chips are connected to I2C connectors representing the locations of PCIe expansion cards in different servers. The correspondence between the locations and connectors is pre-defined / configured in the design. Therefore, when the BMC or BIOS accesses different I2C arbitration chips, it means that the PCIe expansion cards being accessed are from different server system locations.

[0081] The I2C connector is connected to the PCIe expansion card via a cable. The I2C switch chip switches between different channels. Accessing Channel 0 allows access to a storage unit, such as a FRU module / unit or GPIO expansion chip. Furthermore, the I2C switch chip can access PCIe slots 0, 1, 5, and so on, by accessing Channel 1 (CH1), Channel 2 (CH2), and so on.

[0082] The BMC and BIOS can access the GPIO expansion chip through the I2C path to obtain the CPU address information and PCIe port address information of the PCIe device on the specified PCIe slot, and then know the PCIe device address.

[0083] On the PCIe expansion card side, the relative physical locations of the PCIe slots are described. For example, from top to bottom, they are PCIe slot 0, PCIe slot 1, ..., PCIe slot 5, and so on. Therefore, the BMC and BIOS can access PCIe devices using the I2C path and I2C address to obtain the system location of the PCIe expansion card and the relative location of the PCIe device slot on the PCIe expansion card, thereby obtaining the physical silkscreen location of the PCIe device on the server.

[0084] For PCIe expansion cards, their hardware feature information is planned in advance and filled into the FRU (Field Replaceable Unit). FRU burning information means writing specific data or information into the FRU's memory chip so that these FRUs can be identified and managed during system or device operation.

[0085] like Figure 2 As shown, the FRU burned-in information records the hardware characteristics of the motherboard and / or GPIO expansion card and PCIe device. Furthermore, the FRU burned-in information includes information such as the I2C switch of the PCIe expansion card, the I2C address of the GPIO expansion chip, the channel mapping relationship of the I2C switch, the PCIe slot sequence, PCIe slot bandwidth information, and the relative position of the slot on the PCIe expansion card. This FRU burned-in information paves the way for the BMC and BIOS to fully automatically bind the I2C path of the specified PCIe slot, the physical silkscreen address of the server where it is located, and the PCIe device address.

[0086] In addition, the above-mentioned FRU burning information may be located in a ROM (Read-Only Memory), such as an EEPROM (Electrically Erasable Programmable ROM).

[0087] The following combination Figure 2 and Figure 3 , a silk screen binding method for a server external card device provided in this embodiment is described. Figure 3 1 is a flowchart of a silk screen binding method according to an embodiment of the present invention. The method can be applied to a processing module, which can be the aforementioned BIOS or BMC. The method flow includes:

[0088] Step S101: obtaining the location of the PCIe expansion card in the server through the I2C bus access, and reading the burning information through the I2C switch of the PCIe expansion card.

[0089] The burning information includes: I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information and at least one mapping relationship.

[0090] Specifically, the processing module sequentially accesses the I2C arbitration chip via I2C to gain control of PCIe expansion card positions 0, 1, ..., and n in the server, thereby sequentially obtaining the connected PCIe expansion cards inserted in positions 0, 1, ..., and n. Using these positions, the processing module then determines the system position of the PCIe expansion card and the relative position of the PCIe device slot on the PCIe expansion card, thereby determining the physical silkscreen location of the server where the PCIe device resides, such as which slots (Slot 1, Slot 2, ..., Slot 8) contain the PCIe device.

[0091] Step S102: According to the PCIe slot information and its mapping relationship, the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot is obtained, and the I2C address bound to each PCIe device is scanned and obtained.

[0092] The PCIe slot information includes: PCIe slot sequence, PCIe slot bandwidth information. The mapping relationship includes the relative position of each PCIe slot on the PCIe expansion card. This step S102: Based on the PCIe slot information and its mapping relationship, obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot, specifically including:

[0093] Obtain the physical slot location silkscreen of the PCIe device in each PCIe slot based on the PCIe slot sequence, the relative positions of the slots on the PCIe expansion card, and the location of the PCIe expansion card.

[0094] like Figure 4 As shown in the figure, slot 1 (Slot 1), Slot 2, Slot 3, ..., Slot 8 are the physical structures on the server backplane. When the PCIe expansion card is inserted in different positions, the corresponding physical silk screen is different.

[0095] The backplane also includes OCP NIC 0 and OCP NIC 1. OCP NICs are network interface cards that comply with the Open Compute Project (OCP) Network Interface Card (NIC) specifications and are used to support scenarios such as data centers, cloud computing, and large Internet service providers to meet the network requirements of high performance, low latency, and low power consumption.

[0096] In addition, in this step, obtaining the I2C address bound to each of the PCIe devices specifically includes: scanning PCIe external devices according to the channel mapping relationship of the I2C switch, binding an I2C address to each PCIe device, and obtaining the I2C address.

[0097] Step S103: determining at least one PCIe device address according to a preset processor address, PCIe slot bandwidth information, at least one mapping relationship, and information about a PCIe device in each PCIe slot.

[0098] In the above FRU burning information, at least one mapping relationship includes: a mapping relationship between at least one expansion chip and at least one PCIe slot. The preset processor address and at least one mapping relationship are the software and hardware configurations made on the motherboard and PCIe expansion card before step S101 of the above method.

[0099] This step S103, determining at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, at least one mapping relationship, and information about the PCIe device in each PCIe slot, specifically includes:

[0100] First, according to the mapping relationship, at least one PCIe slot corresponding to at least one expansion chip is accessed, and the presence information, processor address information and PCIe port address information of each PCIe device are obtained based on the preset processor address, the relationship between each pin on the high-speed connector of the motherboard and the processor address, the presence signal of at least one PCIe device and the PCIe slot bandwidth information.

[0101] Then, it is determined whether the current processing module is the basic input and output system BIOS.

[0102] Next, if the processing module is a BIOS, the BIOS scans at least one PCIe device based on the processor address information, the PCIe slot bandwidth information, and the PCIe port address information, and binds a unique identifier to each PCIe device. Furthermore, the BIOS sends the binding relationship between the at least one PCIe device and the unique identifier to the BMC.

[0103] Furthermore, the above-mentioned BIOS scans at least one PCIe device according to the processor address information and the PCIe port address information, and binds a unique identifier to each of the PCIe devices, specifically including: the BIOS assigns a unique identifier, such as BDF (Bus Device Function), to the PCIe device on each PCIe slot according to the PCIe port of the processor address information; and then the BIOS establishes a binding relationship between each unique identifier and the PCIe port.

[0104] The PCIe slot bandwidth information includes the maximum bandwidth information supported by each PCIe slot.

[0105] In this embodiment, the above-mentioned determination of whether the current processing module is a BIOS further includes:

[0106] If the processing module is a BMC, the BMC receives the binding relationship between the at least one PCIe device and the unique identifier sent by the BIOS; the above-mentioned step S104 specifically includes: the BMC establishes the binding relationship between the physical slot silkscreen, the at least one PCIe device address and the I2C address based on the physical slot silkscreen, the binding relationship between the at least one PCIe device address and the I2C address, and the binding relationship between the at least one PCIe device and the I2C address.

[0107] Step S104: establishing a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, at least one PCIe device address, and the I2C address, and managing the at least one PCIe device using the binding relationship.

[0108] By combining the physical silkscreen addresses of the servers where the PCIe devices on all PCIe slots are located, the binding relationship between the PCIe devices and PCIe identifiers, and the binding relationship between the PCIe devices and I2C addresses, we can form a binding relationship between the physical silkscreen addresses of the PCIe devices, the PCIe device addresses (referred to as PCIe addresses), and the I2C addresses.

[0109] Other functions related to the PCIe device address are enabled, such as asset information management, fault diagnosis and location, and heat dissipation strategy, which are not limited in this embodiment.

[0110] This embodiment provides a silkscreen binding method for server plug-in card devices. The method obtains the location of the PCIe expansion card in the server through I2C bus access, reads the burn information of the hardware device, and determines the physical slot silkscreen of the server where the PCIe device is located, the I2C address bound to each PCIe device, and the PCIe device address based on the burn information and the GPIO expansion chip storage information. The method then establishes a binding relationship between the server silkscreen address of the PCIe device and the PCIe address and I2C address. This allows the BIOS or BMC to freely access the same device through the I2C path, solving the problem of being unable to manage a specified device. By establishing a binding relationship for management, the status of the PCIe device can be more effectively monitored and maintained, problems can be discovered and resolved in a timely manner, and the reliability and maintainability of the entire system can be improved.

[0111] In addition, this method fully automates the binding of the PCIe address, I2C address, and server slot silkscreen address of the PCIe device, eliminating the need for BIOS or BMC firmware adaptation for newly developed PCIe expansion cards or for reuse in new product models, reducing the workload of hardware R&D and BIOS / BMC firmware development.

[0112] The following combination Figure 5 and Figure 6, the method provided in this embodiment is described in detail. It should be noted that, Figure 5 and Figure 6 A silk screen binding method for server plug-in card devices is provided respectively. The difference lies in the execution subjects of the two methods are different. Figure 5 The execution subject of the method is BIOS, Figure 6 The execution subject in the two methods is BMC, but the overall process of the two methods is mostly the same, with only individual steps being different.

[0113] See also Figure 5 , is a flow chart of a silk screen binding method for a server external card device using BIOS as the execution body, the method comprising:

[0114] Step S0: The BIOS sequentially accesses and controls the I2C arbitration chip at position i through the I2C.

[0115] Where i = 0, 1, ..., n, where n is a positive integer. Specifically, the BIOS obtains control of PCIe expansion card slots 0, 1, ..., and n in the server, i.e., it obtains control of the PCIe expansion card connected to slots 0, 1, ..., or n. When the I2C arbitration chip is turned on, it allows access to the I2C bus and obtains control of the connected slots.

[0116] Step S1: BIOS controls to turn on the I2C switch, and sequentially accesses the I2C switches of the PCIe expansion card, such as turning on channel 0 and reading the Riser FRU information of the downstream storage unit.

[0117] Among them, the FRU information includes the pre-filled hardware information of the PCIe expansion card. The FRU information specifically includes: ① the I2C address of at least one expansion chip, ② the mapping relationship between the expansion chip and the PCIe slot, ③ the mapping relationship between at least one channel CH of the I2C switch, ④ the PCIe slot sequence and ⑤ the relative position of the slot on the PCIe expansion card.

[0118] Combine Figure 2 In the structure example, the FRU information specifically includes the following:

[0119] ①The I2C address of GPIO expansion chip 0 and the I2C address of GPIO expansion chip 1.

[0120] ②GPIO expansion chip 0 has a one-to-one mapping relationship with PCIe slot 0, and GPIO expansion chip 1 has a one-to-one mapping relationship with PCIe slot 1.

[0121] ③I2C switch channel mapping relationship: Channel 1 (CH1) has a one-to-one mapping relationship with PCIe slot 0, and Channel 2 (CH2) has a one-to-one mapping relationship with PCIe slot 1.

[0122] ④ The corresponding positions of the PCIe expansion card are in the following order from top to bottom: PCIe slot 0, PCIe slot 1.

[0123] ⑤ The relative position of the slot on the PCIe expansion card, combined with Figure 3 The backplane structure includes the following two cases:

[0124] Case 1: When a PCIe expansion card is inserted in position 0, the corresponding physical silkscreen on PCIe slot 0 is Slot 1, and the corresponding physical silkscreen on PCIe slot 1 is Slot 2.

[0125] Case 2: When a PCIe expansion card is inserted in position 1, the corresponding physical silkscreen on PCIe slot 0 is Slot 4, and the corresponding physical silkscreen on PCIe slot 1 is Slot 5.

[0126] Steps S0 and S1 of this embodiment correspond to step S101 of the aforementioned embodiment.

[0127] Step S2: The BIOS uses the above-mentioned PCIe slot sequence (4) and the relative position of slot (5) on the PCIe expansion card, combined with the location of the PCIe expansion card, to obtain the physical silkscreen addresses of the servers where the PCIe devices in all PCIe slots are located. This step corresponds to step S102 in the previous embodiment.

[0128] Step S3: The BIOS uses the mapping relationship between GPIO expansion chips and PCIe slots (②) to sequentially access the GPIO expansion chips corresponding to the PCIe slots. Based on the PRSNT signals from CPU0 / 1 / 2, PE0 / 1 / 2 / 3, and the PCIe devices, it obtains the PCIe device presence information, CPU address information, and PCIe port address information for each PCIe slot. This step corresponds to step S103 in the previous embodiment.

[0129] The PRSNT signal is a position indicator signal, such as PRSNT1# and PRSNT2#, corresponding to the hot-plug detection pins of a PCIe (PCI Express) card. On a PCIe card, the PRSNT1# and PRSNT2# signals are short-circuited. The PRSNT1# pin of a PCIe slot is permanently connected to ground, while PRSNT2# is pulled up. In this embodiment, the PRSNT signal indicates whether a PCIe device is inserted into a PCIe slot.

[0130] Step S4: The BIOS scans PCIe devices and generates PCIe identifiers (Bus Device Function) according to the specified order of the PCIe slot bandwidth information, CPU address information, and PCIe port address information. This is done by binding a unique PCIe identifier to each PCIe device. The BIOS transmits the binding relationship between the PCIe device and the unique PCIe identifier to the BMC. This step corresponds to step S103 in the previous embodiment.

[0131] In a specific example, the BIOS uses PCIe Port 0 of CPU 0 to assign a BDF value, such as BDF1, to the PCI device in PCIe slot 0. The BIOS establishes a binding relationship between BDF1 and PCIe Port 0 (or PCIe slot 0). The binding relationships for other PCIe ports are similar and will not be detailed here.

[0132] Step S5: BIOS scans the PCIe add-in card according to the channel mapping relationship of ③I2C Switch and assigns an I2C address, that is, binds an I2C address to each PCIe device ⑦.

[0133] Step S6: BIOS combines the physical silkscreen addresses of the servers where the PCIe devices on all PCIe slots are located, the binding relationship between the PCIe device and the PCIe unique identifier, and the binding relationship between the PCIe device and the I2C address output in step S5 to establish a binding relationship between the physical silkscreen addresses of the PCIe devices, the PCIe device addresses, and the I2C addresses.

[0134] The BIOS uses the binding relationship between the physical silkscreen address, PCIe device address, and I2C address of the PCIe device to enable other functions related to the PCIe device address, such as asset information management, fault diagnosis and location, and cooling strategy.

[0135] In addition, the method of this embodiment further includes: the BIOS displays the binding relationship between the device PCIe device address, device slot silkscreen, and I2C address on a display interface such as a BIOS interface and a BMC management website.

[0136] See also Figure 6 , is another embodiment of the present invention provides a silk screen binding method, the execution subject of the method steps is BMC, wherein the steps S0 to S2, step S3, step S5 and step S6 executed by BMC are all the same as Figure 5 The method flow shown is the same and will not be repeated here.

[0137] The different steps are S4, such as Figure 6 As shown, step S4': BMC receives the BDF unique identifier sent from BIOS. This step follows the above Figure 5Step S4 is shown. After the BMC receives the BDF unique identifier, or receives the binding relationship between the PCIe device and the PCIe unique identifier sent by the BIOS, step S5 is executed.

[0138] Step S5: The BMC controls channels 1 to 6 of the I2C Switch in sequence to scan and obtain the I2C address of the PCIe device.

[0139] Step S6: The BMC establishes a binding relationship between the server system slot number, physical slot silkscreen, PCIe address, and I2C address.

[0140] It should be noted that the method provided in this embodiment can be executed by one processing module, such as BIOS or BMC, or by two or more processing modules simultaneously, such as BIOS and BMC synchronously executing the aforementioned Figure 3 、 Figure 5 and Figure 6 The method shown in the figure. However, the method flow executed by BIOS is as follows Figure 3 and Figure 5 As shown, the method flow executed by BMC is as follows Figure 3 and Figure 6 It should be understood that if there are more processing modules, such as two or more BMCs, each BMC can be Figure 3 and Figure 6 The method flow shown is executed, and this embodiment takes two processing modules as an example.

[0141] The method provided in this embodiment has the following beneficial effects:

[0142] 1. The hardware is pre-configured on the I2C path of the motherboard riser, so that the riser card can indicate its different positions in the server system by connecting to different I2C buses. In terms of hardware design, the BMC and BIOS can have I2C access to the riser card.

[0143] 2. Hardware: Decouple software and hardware from each other in the riser card design. The I2C topology is designed according to the pre-determined hardware and software positional relationships, and the channel binding slots are bound according to fixed rules. The CPU_Addr and VPP_Addr representing the PCIe address information are used in the GPIO expansion chip IO design according to fixed rules.

[0144] 3. The BIOS develops code for identifying physical silkscreen information and binding addresses. This includes accessing different I2C channels to obtain riser information at different locations, accessing the GPIO expansion chip and obtaining PCIe address information through the PCIe scan sequence, and accessing the riser FRU to obtain the physical slot silkscreen for each riser slot. The BIOS combines this information to determine the binding relationship between the PCIe address information and the physical slot silkscreen, and sends this binding relationship to the BMC.

[0145] 4. After receiving the information, the BMC accesses different I2C channels to obtain information about risers in different locations. For example, it accesses the GPIO expansion chip and obtains PCIe address information, accesses FRU burning information to obtain the physical slot silkscreen of each slot on the riser card, accesses different I2C channels on the riser card and performs device address scanning to obtain the I2C address information of devices connected to different slots, and receives the binding relationship between the PCIe address information and the physical slot silkscreen information transmitted by the BIOS. The BMC combines this information to obtain the binding relationship between the device PCIe address information, the device slot silkscreen information, and the device I2C address information.

[0146] The following combines the above Figure 3 、 Figure 5 and Figure 6 The method flow, and Figure 2 and Figure 4 The method provided in this embodiment is described with examples of the software and hardware structure. The details are as follows:

[0147] First, the BMC chip on the server motherboard features extensive GPIO and I2C resources. The BMC and BIOS can access the same riser card (such as a PCIe expansion card) in a time-sharing manner by accessing the I2C arbitration chip. I2C arbitration chip 0 corresponds to insertion position 0, and I2C arbitration chip 1 corresponds to insertion position 1.

[0148] Then, the BMC and / or BIOS can access the riser cards located at "position 0" and "position 1" of the server by accessing two I2C arbitration chips 0 and I2C arbitration chips 0 with different addresses. All I2C devices on the riser card are hung on different channels of the I2C switch.

[0149] I2C switch channel 0 on the riser card is connected to storage units such as an EEPROM (FRU), an optional temperature sensor, and a GPIO expansion chip. I2C switch channels 1 to 6 on the riser card connect to the I2C ports on the PCIe CEM in PCIe slots 0 to 5, respectively.

[0150] To obtain riser data for server position 1, the BIOS enables I2C arbitration chip 1 and I2CSwitch channel 0. It then retrieves the upstream and downstream connector data stored in the EEPROM (FRU), along with the physical slot location information for position 1. After obtaining the total number of downstream connector slots, it reads the physical slot location information for each slot, the IO status of the corresponding GPIO expansion chip, and the maximum bandwidth supported by each PCIe slot. The same process is used to obtain the location information for other server slots.

[0151] The BIOS uses the CPU_Addr, VPP_Addr, and mapping table for PCIe slots 0 through 5 to determine the CPU and PCIe port number of the device in that slot. During a PCIe scan, the BIOS binds the server system slot number and slot silkscreen to each PCIe port for each CPU serial number. Table 1 shows the VPP_Addr and PCIe port mapping table.

[0152] Table 1. Mapping table of VPP_Addr and PCIe Port

[0153]

[0154] In Table 1, the PCIe port address information is VPP Addr, for example, VPP Addr: 0011. The VPP addr is converted into PCIe Port PE0 according to the relationship in Table 1. PE0 represents PCIe Port 0 (ie, PCIe port 0).

[0155] The BIOS sends the server system slot number, physical slot silkscreen, and PCIe address binding data to the BMC through the communication interface. The BMC receives, parses, and saves the data. The binding data is the BDF unique identifier established in step S4, which binds the PCIe address to the physical slot number, such as slot 0.

[0156] The BIOS sequentially turns on I2C channels 1 through 6, scanning the I2C addresses of PCIe devices. Combining the server's system slot number, physical slot silkscreen, and PCIe address binding data, it generates a binding relationship between the server's system slot number, physical slot silkscreen, PCIe address, and I2C address. This binding relationship is then used for subsequent location information display and fault diagnosis functions.

[0157] Similarly, to obtain the riser data of server position 1, the BMC controls the opening of I2C arbitration chip 1 and I2C switch channel 0, obtains the upstream connector data, downstream connector data, position 1 silk screen scheme data and other information stored in the EEPROM (FRU), and after obtaining the total number of downstream connector slots, reads the slot silk screen information corresponding to each slot, the IO status of the corresponding GPIO expansion chip and the maximum bandwidth information supported by the PCIe slot, etc.

[0158] The BMC uses the CPU_Addr, VPP_Addr, and mapping table for PCIe slots 0 to 5 to determine the CPU and PCIe port number of the device in that slot. It then uses the server system slot number, slot silkscreen, and PCIe address binding data sent by the BIOS to perform the analysis and save the data.

[0159] BMC sequentially controls channels 1 to 6 of the I2C switches to scan the I2C addresses of PCIe devices. Combined with the server system slot number, physical slot silkscreen, and PCIe address binding data, it generates binding data information of the server system slot number, physical slot silkscreen, PCIe address, and I2C address, such as Figure 4 and as shown in Table 2 below. It is used for functions such as location information display, fault diagnosis, and slot-oriented cooling strategy control.

[0160] Table 2. Binding relationship between physical slot silkscreen, PCIe address, and I2C address

[0161]

[0162] The method provided in this embodiment establishes a binding relationship between the server physical slot silkscreen of the PCIe device and the PCIe address and I2C address, allowing the BIOS and / or BMC to freely access the same device through the PCIe address or I2C path, solving the problem of a specified device being unable to be managed.

[0163] This method also eliminates the need for BIOS / BMC firmware adaptation for newly developed PCIe expansion cards or for reuse in new product models, reducing both hardware R&D workload and the BIOS and BMC firmware development workload. Furthermore, in scenarios such as PCIe device asset management and machine failures, remote monitoring eliminates the need for on-site measurement and analysis by engineers, enabling direct access to effective information and improving monitoring and operational efficiency.

[0164] This embodiment also provides a silkscreen binding device for a server plug-in card device. This device is used to implement the above-mentioned embodiments and preferred implementations. Details already described will not be repeated here. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0165] This embodiment provides a silk screen binding device, such as Figure 7 As shown, the silk screen binding device includes: a reading module 710, an acquisition module 720, a determination module 730 and an establishment module 740. In addition, the device can also include other more or fewer units or modules, such as a storage unit / storage module, a sending module, etc., which is not limited in this embodiment.

[0166] Among them, the reading module 710 is used to obtain the location of the PCIe expansion card in the server through the I2C bus access, and read the burning information through the I2C switch of the PCIe expansion card. The burning information includes: the I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information and at least one mapping relationship.

[0167] The acquisition module 720 is used to obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot according to the PCIe slot information and its mapping relationship, and scan to obtain the I2C address bound to each PCIe device.

[0168] The determination module 730 is configured to determine at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, at least one mapping relationship, and information about a PCIe device in each PCIe slot.

[0169] The establishment module 740 is used to establish a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, at least one PCIe device address and the I2C address, and use the binding relationship to manage at least one PCIe device address.

[0170] The storage module is used to store various information, addresses, mapping relationships, etc.

[0171] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0172] The silk screen binding device in this embodiment is presented in the form of a functional unit, which refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0173] This embodiment also provides a silk screen binding system. The structure of the system can be as described above. Figure 2 As shown, it includes a mainboard and at least one PCIe expansion card.

[0174] The motherboard includes at least one processing module, at least one arbitration chip, and at least one high-speed connector; each PCIe expansion card includes an I2C switch, a storage unit, at least one expansion chip, and at least one PCIe slot. The at least one processing module is connected to the at least one expansion chip of the PCIe expansion card via the at least one arbitration chip and at least one high-speed connector;

[0175] The I2C switch connects a storage unit and at least one PCIe slot through different channels. The storage unit is used to store programming information, which includes: I2C address information of at least one expansion chip, PCIe slot information, and at least one mapping relationship.

[0176] Each processing module stores computer instructions, and executes the computer instructions to perform the above-mentioned Figure 3 、 Figure 5 and Figure 6 The following figure shows the silkscreen binding method for server external card devices.

[0177] Furthermore, the number of processing modules can be one or more. If the number of processing modules is one, the processing module is one of the BMC and the BIOS. If the number of processing modules is two, the two processing modules are the BMC and the BIOS respectively. Figure 2 The system structure shows two processing modules, one is BIOS and the other is BMC.

[0178] It should be understood that the silk screen binding system of this embodiment may further include more than two processing modules, such as more than two BMCs.

[0179] The present invention provides a silkscreen binding device and system for server plug-in card devices. This device obtains the location of a PCIe expansion card in a server via I2C bus access, reads the burned-in information of the hardware device, and uses this burned-in information to determine the physical slot silkscreen of the server where the PCIe device resides, the I2C address bound to each PCIe device, and the PCIe device address. This device then establishes a binding relationship between the server silkscreen address of the PCIe device and the PCIe and I2C addresses. This allows the BIOS or BMC to freely access the same device via the I2C path, resolving the issue of being unable to manage a specific device. By establishing this binding relationship for management, the status of PCIe devices can be more effectively monitored and maintained, problems can be promptly identified and resolved, and the reliability and maintainability of the entire system can be improved.

[0180] In addition, this embodiment also realizes the fully automated binding of the PCIe address, I2C address and server slot silkscreen address of the PCIe device, avoiding the need to adapt the BIOS or BMC firmware for newly developed PCIe expansion cards or for reuse in new product models, thereby reducing the workload of hardware research and development and BIOS / BMC firmware development.

[0181] The embodiment of the present invention further provides a processing module having the above Figure 7 Silkscreen binding shown.

[0182] See also Figure 8 , is a schematic structural diagram of a processing module provided by an optional embodiment of the present invention, the processing module comprising: one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected using different buses and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the processing module, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface).

[0183] In some alternative embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple storages if desired. Similarly, multiple units / modules can be connected, with each device providing a portion of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0184] The processor 10 may be a central processing unit. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0185] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable the at least one processor 10 to execute the silk screen binding method for the server external card device shown in the above embodiment.

[0186] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the processing module, etc. In addition, the memory 20 may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may include a memory remotely located relative to the processor 10, and these remote memories may be connected to the processing module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0187] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0188] The processing module further includes a communication interface 30 for the computer device to communicate with other devices or a communication network, wherein the number of the communication interface 30 can be one or more.

[0189] In this example, the processing module is a manager, such as a BMC. Alternatively, the processing module may be a hardware or software module integrated with BIOS functions, for executing the silkscreen binding method in the aforementioned embodiment.

[0190] In addition, Figure 2 In addition to the application scenarios shown, the technical solution provided in this embodiment can also be used in servers, storage devices, and switch products that bind the slot silkscreen and device addresses of other multi-protocol devices.

[0191] An embodiment of the present invention also provides a computer-readable storage medium, and the above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded on a storage medium, or downloaded via a network and originally stored in a remote storage medium, or a non-temporary machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.

[0192] The storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium may include a combination of the aforementioned types of memory. It is understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0193] The embodiments of the present application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the above method. The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present disclosure, wherein the programming languages ​​include object-oriented programming languages ​​such as Java, C++, etc., and also include conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0194] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silk screen binding method for a server external card device, characterized in that: A processing module applied to a mainboard, the processing module being connected to a PCIe expansion card via an I2C bus, the method comprising: Obtaining the location of a PCIe expansion card in a server through I2C bus access, and reading programming information through an I2C switch of the PCIe expansion card, wherein the programming information includes: I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information, and at least one mapping relationship; According to the PCIe slot information and its mapping relationship, obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot, and scan to obtain the I2C address bound to each PCIe device; Determining at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and information about a PCIe device in each of the PCIe slots; Establishing a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, the at least one PCIe device address, and the I2C address, and managing the at least one PCIe device using the binding relationship; Before obtaining the location of the PCIe expansion card in the server through the I2C bus access, the method further includes: Add a first pin representing the processor address and a second pin representing the PCIe port address to the high-speed connector of the motherboard; The information of the first pin and the second pin is stored through at least one expansion chip.

2. The method according to claim 1, characterized in that The PCIe slot information includes: PCIe slot sequence and relative position of the slot on the PCIe expansion card; The step of obtaining a physical slot silkscreen of a server where a PCIe device is located on each PCIe slot according to the PCIe slot information includes: According to the PCIe slot sequence and the relative positions of the slots on the PCIe expansion card, combined with the position of the PCIe expansion card, the physical slot silk screen of the PCIe device on each PCIe slot is obtained.

3. The method according to claim 1, characterized in that The at least one mapping relationship includes: a mapping relationship between the at least one expansion chip and at least one PCIe slot; The determining of at least one PCIe device address according to the preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and the presence information of the PCIe device in each of the PCIe slots includes: Accessing at least one expansion chip corresponding to the at least one PCIe slot according to the mapping relationship, and obtaining presence information, processor address information, and PCIe port address information of each PCIe device according to a preset processor address, a relationship between pins on a high-speed connector of a motherboard and the processor address, a presence signal of the at least one PCIe device, and PCIe slot bandwidth information; If the processing module is a basic input and output system BIOS, scanning at least one PCIe device according to the processor address information and the PCIe port address information, and binding a unique identifier to each of the PCIe devices; The BIOS sends the binding relationship between the at least one PCIe device and the unique identifier to a baseboard management controller (BMC); and At least one PCIe device address is determined according to the PCIe device presence information, the processor address information, and the PCIe port address information.

4. The method according to claim 3, characterized in that The step of scanning at least one PCIe device according to the processor address information and the PCIe port address information and binding a unique identifier to each PCIe device includes: The BIOS assigns a unique identifier to the PCIe device on each PCIe slot according to the PCIe port of the processor address information; The BIOS establishes a binding relationship between the unique identifier and the PCIe port.

5. The method according to claim 3, characterized in that The method further comprises: If the processing module is a BMC, the BMC receives the binding relationship between the at least one PCIe device and the unique identifier sent by the BIOS; The establishing of a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, the at least one PCIe device address, and the I2C address includes: The BMC establishes a binding relationship between the physical slot silkscreen, the at least one PCIe device address, and the I2C address according to the physical slot silkscreen, the binding relationship between the at least one PCIe device address and the I2C address, and the binding relationship between the at least one PCIe device and the I2C address.

6. The method according to claim 1, characterized in that The obtaining of the I2C address bound to each of the PCIe devices includes: Scan PCIe external devices according to the channel mapping relationship of the I2C switch, bind an I2C address to each PCIe device, and obtain the I2C address.

7. A silk screen binding device for a server external card device, characterized in that: The device comprises: A reading module is configured to obtain the location of a PCIe expansion card in a server through an I2C bus access and read programming information through an I2C switch of the PCIe expansion card, wherein the programming information includes: I2C address information of at least one expansion chip in the PCIe expansion card, PCIe slot information, and at least one mapping relationship; An acquisition module is used to obtain the physical slot silkscreen of the server where the PCIe device is located on each PCIe slot based on the PCIe slot information and its mapping relationship, and to scan and obtain the I2C address bound to each PCIe device; a determination module, configured to determine at least one PCIe device address based on a preset processor address, PCIe slot bandwidth information, the at least one mapping relationship, and information about a PCIe device in each PCIe slot; an establishing module, configured to establish a binding relationship between the physical slot silkscreen of the PCIe device on each PCIe slot, the at least one PCIe device address, and the I2C address, and manage the at least one PCIe device address using the binding relationship; Among them, the reading module is also used to add a first pin representing the processor address and a second pin representing the PCIe port address on the high-speed connector of the motherboard before obtaining the location of the PCIe expansion card in the server through the I2C bus access; and store the information of the first pin and the second pin through at least one expansion chip.

8. A silk screen binding system, characterized in that: Includes a motherboard and at least one PCIe expansion card; The mainboard includes at least one processing module, at least one arbitration chip and at least one high-speed connector; each of the PCIe expansion cards includes an I2C switch, a storage unit, at least one expansion chip and at least one PCIe slot; The at least one processing module is connected to the at least one expansion chip of the PCIe expansion card through the at least one arbitration chip and the at least one high-speed connector; The I2C switch is connected to the storage unit and the at least one PCIe slot through different channels, and the storage unit is used to store burning information, and the burning information includes: I2C address information of the at least one expansion chip, PCIe slot information and at least one mapping relationship; Each of the processing modules stores computer instructions, and the silk screen binding method for a server external card device according to any one of claims 1 to 6 is executed by executing the computer instructions.

9. The system according to claim 8, characterized in that If the number of the processing module is one, the processing module is a baseboard management controller BMC or a basic input and output system BIOS; If the number of the processing modules is two, the two processing modules are respectively a BMC and a BIOS.

Images