SRAM type FPGA online fault injection test system and test method
By combining code mutation technology and online data loading technology, the existing online fault injection testing system has solved the problem of scale limitation and slow testing speed when dealing with large-scale FPGA design, large data volume and large-scale test scenarios, and achieved efficient Online fault injection test.
Patent Information
- Application Number
- CN202411343611.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-02-07
AI Technical Summary
The existing online fault injection testing system has problems such as scale limitation and slow testing speed when dealing with large-scale FPGA designs, large data volumes and large-scale test scenarios.
Using code mutation technology and online data loading technology, test scene source data is loaded online from the upper computer through the serial port, and data is cached in the large-capacity memory DDR outside the FPGA, and the single-bit flip of the injected signal is controlled in real time to realize time-sharing operation and Results comparison.
Online fault injection testing that adapts to large-scale FPGA design, large data volume, and large-scale test scenarios is realized, and the testing speed and efficiency are improved.
Smart Images
Figure CN119400230A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of system testing, and in particular relates to an SRAM type FPGA online fault injection testing system and a testing method. Background Art
[0002] SRAM-based FPGA chips have been increasingly widely used in recent decades due to their high density, high performance, low development cost, and flexible configuration. SRAM-based FPGA chips are inherently sensitive to single-particle effects in space, which greatly limits their application in space environments. When using SRAM-based FPGA chips in space environments, it is necessary to adopt reinforcement measures such as triple-mode redundancy to improve the radiation resistance of FPGA chips, and use verification technology to verify the effectiveness of the reinforcement measures.
[0003] Fault injection testing refers to a testing method that simulates spatial single-particle effects by injecting faults into the design under test. It is an effective means to verify the single-particle effect reinforcement of SRAM-type FPGA chips. Fault injection test systems are generally divided into two types: test systems based on software simulation and online test systems based on hardware platforms. The test speed based on software simulation is much lower than the online test speed based on hardware platforms. Since the fault injection test uses a single-bit flip in the FPGA to simulate the spatial single-particle effect, and the number of bits in the FPGA design is as high as tens of thousands, the test of a single bit flip requires dozens or even hundreds of test scenarios to verify the effectiveness of the reinforcement measures. Therefore, the entire FPGA design requires a large number of tests, and generally an online fault injection test system is required to maximize the test speed.
[0004] Previous online fault injection test systems (such as Figure 1 ) Usually, the original module without fault injection (called golden reference module) and the module under test after fault injection are placed in the FPGA at the same time, and the source data required for the test is stored in the ROM inside the FPGA. After the test is started, the golden reference module and the module under test run at the same time, and the result data output by the golden reference module (called golden result data) and the result data output by the module under test (called injection test result data) are each stored in a RAM, and finally a result comparison module compares the two. If the two are consistent, the injection test result is correct, indicating that the reinforcement measures are effective. If the two are consistent, the injection test result is wrong, indicating that the reinforcement measures are ineffective.
[0005] This fault injection system architecture limits the size of the module under test because the golden reference module and the module under test must be placed in the FPGA at the same time. In addition, the storage space of the ROM or RAM inside the FPGA is limited. When the amount of source data and result data is relatively large, it will not be able to be stored. The method of pre-storing the source data in the ROM also means that the injection test can only complete one or a few test scenarios. Changing the source data requires recompiling the FPGA, which greatly limits the speed of the fault injection test. Summary of the invention
[0006] In order to overcome the deficiencies in the prior art, the present invention proposes an SRAM-type FPGA online fault injection test system and test method, which, combined with code mutation technology and online data loading technology, can realize online fault injection testing that is suitable for large-scale FPGA design, large data volume, and large-batch testing scenarios.
[0007] The SRAM type FPGA online fault injection system of the present invention comprises a host computer, an FPGA board card, and a serial port cable; the host computer comprises: a serial port A, a host computer fault injection module, and a source data module; the metadata module is connected to the host computer fault injection module, and the host computer fault injection module is connected to the serial port cable via the serial port A.
[0008] The FPGA board includes: serial port B, FPGA, DDR; the host computer and the FPGA board are connected through a serial port cable. The FPGA includes: a serial port B sending module, a serial port B receiving module, a source data storage and writing module, an injection control module, a result comparison module, a module under test, a source data driver module, and a result data storage and writing module; one end of the serial port B sending module and the serial port B receiving module are connected to the serial port cable through the serial port B, the other end of the serial port B receiving module is connected to the source data storage and writing module and one end of the injection control module, and the other end of the serial port B sending module is connected to one end of the result comparison module; the source data storage and writing module is connected to the DDR; the other end of the injection control module is connected to the source data driver module, the module under test, and one end of the result comparison module; the other end of the data source driver module and the result data storage and writing module are both connected to the DDR and the module under test; the other end of the result comparison module is connected to the DDR.
[0009] Module under test: A signal to be injected with a single-bit fault is selected from the original module under test, the signal is modified by a code mutation method, and a single-bit fault injection control signal is inserted to form a module under test after the code mutation.
[0010] The upper computer fault injection module includes: a serial port A sending module, a serial port A receiving module, a source data loading module, and a test result display module; the source data module sends data to the source data loading module, and the source data loading module processes and loads the data and then sends it to serial port A through the serial port A sending module; the serial port A receiving module receives the data transmitted by serial port A and sends it to the test result display module.
[0011] The testing method of the SRAM type FPGA online fault injection system of the present invention specifically comprises the following steps:
[0012] Step 1: Select a signal to be injected with a single-bit fault in the original module under test, modify the signal by code mutation, insert a single-bit fault injection control signal, and form a module under test after code mutation.
[0013] Step 2: The module code under test is embedded in the FPGA board, compiled to generate a bit stream file, and then loaded into the FPGA on the FPGA board for execution. Meanwhile, the host computer fault injection module is run on the host computer.
[0014] Step 3: The source data loading module of the fault injection module of the host computer reads the source data in the source data module and sends it to serial port A through the serial port A sending module.
[0015] Step 4: Serial port A sends the source data to serial port B via the serial cable.
[0016] Step 5: Serial port B sends the source data to the serial port B receiving module of the FPGA.
[0017] Step 6: The serial port B receiving module stores the source data into the address space 1 in the DDR through the source data storage and writing module, and notifies the injection control module that the source data has been received.
[0018] Step 7: The injection control module controls the single-bit fault injection control signal in the module under test to be 0, that is, the injected signal is the original value.
[0019] Step 8: The injection control module sends a start signal to the source data driver module for the first time and starts timing at the same time.
[0020] Step 9: The source data driver module reads the source data from address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test.
[0021] Step 10: After receiving the source data, the module under test runs and generates golden result data, and sends it to the result data storage and writing module. The result data storage and writing module stores the golden result data in address space 2 in the DDR.
[0022] Step 11: When the injection control module timing reaches the preset running time, it is determined that the first running of the module under test has ended.
[0023] Step 12: The injection control module controls the single-bit fault injection control signal in the module under test to be 1, that is, the injected signal is a single-bit flipped fault value.
[0024] Step 13: The injection control module sends a start signal to the source data driving module for the second time and starts timing at the same time.
[0025] Step 14: The source data driver module reads the source data from address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test.
[0026] Step 15: After receiving the source data, the module under test runs and generates injection test result data, and sends it to the result data storage and writing module. The result data storage and writing module stores the injection test result data in address space 3 in the DDR.
[0027] Step 16: When the injection control module reaches the preset running time, it determines that the second running of the module under test has ended, and sends a start signal to the result comparison module.
[0028] Step 17: The result comparison module reads the golden result data from address space 2 in the DDR, reads the injection test result data from address space 3 in the DDR, and compares the golden result data and the injection test result data word by word; if the comparison is consistent, the test result is correct, if the comparison is inconsistent, the test result is wrong.
[0029] Step 18: The result comparison module sends the test result to the serial port B sending module, and the serial port B sending module sends the test result to the serial port B.
[0030] Step 19: Serial port B sends the test result to serial port A via the serial port cable, and serial port A sends the test result to the test result display module via the serial port A receiving module.
[0031] Step 20: The test result display module displays the test result.
[0032] The beneficial effects of the present invention are
[0033] 1. Use code mutation technology to insert a single-bit fault injection control signal into the injected signal, and control in real time whether the injected signal has a single-bit flip. The tested module runs in time-sharing mode to generate golden result data and injection test result data. It can adapt to online fault injection testing of large-scale FPGA designs.
[0034] 2. The test scenario source data is loaded online from the host computer through the serial port, which can adapt to the online fault injection test of large-scale test scenarios.
[0035] 3. The source data, golden result and injection test result data are cached in the large-capacity memory DDR outside the FPGA, and are equipped with a control module, a drive module and a storage and writing module inside the FPGA, which can adapt to online fault injection testing of large amounts of data. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 This is the architecture diagram of the traditional FPGA online fault injection test system.
[0037] Figure 2 This is the architecture diagram of the FPGA online fault injection test system of the present invention.
[0038] Figure 3 This is the original FPGA module example.
[0039] Figure 4 This is an example of the module under test after the code is mutated. DETAILED DESCRIPTION
[0040] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0041] The present invention proposes an SRAM type FPGA online fault injection system, such as Figure 2 As shown, the system consists of: a host computer, an FPGA target board, and a serial cable. The host computer includes: serial port A, host computer fault injection software, and source data files. The FPGA board includes: serial port B, FPGA, and DDR. The host computer and the FPGA board are connected via a serial cable. The host computer fault injection software includes: serial port A sending module, serial port A receiving module, source data loading module, and test result display module. FPGA includes: serial port B sending module, serial port B receiving module, source data storage and writing module, injection control module, result comparison module, module under test, source data driving module, and result data storage and writing module. Module under test: Select the signal that needs to be injected with a single-bit fault injection in the original module under test, modify the signal using code mutation technology, insert a single-bit fault injection control signal, and form a module under test after code mutation.
[0042] The present invention provides a method for performing a fault injection test on the fault injection system, comprising the following steps:
[0043] Step 1: Select the signal that needs to be injected with a single-bit fault in the original module under test, modify the signal using code mutation technology, insert a single-bit fault injection control signal, and form a module under test after code mutation. The original FPGA module example is as follows Figure 3 As shown, in this example, a simple FPGA module written in Verilog language is shown, named MulAdd.
[0044] An example of a module under test after code mutation is as follows Figure 4 As shown in the figure, in this example, the 0th bit of signal d is selected as the single-bit flip fault bit, and the input signal inject_en is added to the module MulAdd, which is the single-bit fault injection control signal. A copy d_inject is created for signal d, and the 0th bit of signal d is XORed with the inject_en signal, and the other bits remain unchanged, and assigned to the signal d_inject using the assign statement. Then, all places where signal d is used in the module are replaced with signal d_inject.
[0045] In this way, whether the 0th bit of signal d has a single-bit flip is controlled in real time by the signal inject_en. When the input inject_en signal is equal to 0, the value of the signal d_inject is the same as that of the signal d, that is, no single-bit flip occurs. When the input inject_en signal is equal to 1, the 0th bit of the signal d_inject is opposite to the 0th bit of the signal d, and the other bits remain the same, that is, a single-bit flip fault occurs in the 0th bit of the signal d, which is simulated.
[0046] Step 2: Embed the module code under test into the FPGA target board FPGA project, compile and generate the bitstream file, and then load it into the FPGA on the FPGA target board for execution. Meanwhile, run the host computer fault injection software on the host computer.
[0047] like Figure 2 As shown, the FPGA target board FPGA project includes, in addition to the module under test, a serial port B sending module, a serial port B receiving module, a source data storage and writing module, an injection control module, a result comparison module source data driver module, and a result data storage and writing module.
[0048] Step 3: The source data loading module of the fault injection software of the host computer reads the source data file and sends it to serial port A through the serial port A sending module.
[0049] Step 4: Serial port A sends the source data to serial port B via the serial cable.
[0050] Step 5: Serial port B sends the source data to the serial port B receiving module of the FPGA.
[0051] Step 6: The serial port B receiving module stores the source data in address space 1 in the DDR, and notifies the injection control module that the source data has been received.
[0052] Step 7: The injection control module controls the single-bit fault injection control signal inject_en in the module under test to be 0, so that the value of the injected signal d_inject is the same as the signal d, that is, no single-bit flip occurs.
[0053] Under this condition, the operation of the module under test will produce golden result data.
[0054] Step 8: The injection control module sends a start signal to the source data driver module for the first time and starts timing at the same time.
[0055] Step 9: The source data driver module reads the source data from address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test.
[0056] Step 10: After receiving the source data, the module under test generates golden result data and sends it to the result data storage module. The result data storage module stores the golden result data in address space 2 in the DDR.
[0057] Step 11: When the injection control module timing reaches the preset running time, it is determined that the first running of the module under test has ended.
[0058] Step 12: The injection control module controls the single-bit fault injection control signal inject_en in the module under test to be 1, so that the 0th bit of the signal d_inject is opposite to the 0th bit of the signal d, and the other bits remain the same, that is, a single-bit flip fault of the 0th bit of the signal d is simulated.
[0059] Under this condition, the operation of the module under test will generate injection test result data.
[0060] Step 13: The injection control module sends a start signal to the source data driving module for the second time and starts timing at the same time.
[0061] Step 14: The source data driver module reads the source data from address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test.
[0062] Step 15: After receiving the source data, the module under test generates injection test result data and sends it to the result data storage module. The result data storage module stores the injection test result data in address space 3 in the DDR.
[0063] Step 16: When the injection control module reaches the preset running time, it determines that the second running of the module under test has ended, and sends a start signal to the result comparison module.
[0064] Step 17: The result comparison module reads the golden result data from address space 2 in the DDR, reads the injection test result data from address space 3 in the DDR, and compares the golden result data and the injection test result data word by word. If the comparison is consistent, the test result is correct. If the comparison is inconsistent, the test result is wrong.
[0065] Step 18: The result comparison module sends the test result to the serial port B sending module, and the serial port B sending module sends the test result to the serial port B.
[0066] Step 19: Serial port B sends the test result to serial port A via the serial port cable, and serial port A sends the test result to the test result display module via the serial port A receiving module.
[0067] Step 20: The test result display module displays the test result.
[0068] The present invention is not limited to the above specific implementations, and the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made to the above implementations based on the technical essence of the present invention shall be included in the protection scope of the present invention.
Claims
1. An SRAM-type FPGA online fault injection system, characterized in that: include: Host computer, FPGA board, serial port cable; The host computer comprises: a serial port A, a host computer fault injection module, and a source data module; the metadata module is connected to the host computer fault injection module, and the host computer fault injection module is connected to the serial port cable via the serial port A; The FPGA board includes: serial port B, FPGA, DDR; the host computer and the FPGA board are connected via a serial port cable; The FPGA comprises: a serial port B sending module, a serial port B receiving module, a source data storage and writing module, an injection control module, a result comparison module, a module under test, a source data driving module, and a result data storage and writing module; one end of the serial port B sending module and the serial port B receiving module are connected to the serial port cable through the serial port B, the other end of the serial port B receiving module is connected to the source data storage and writing module and one end of the injection control module, and the other end of the serial port B sending module is connected to one end of the result comparison module; the source data storage and writing module is connected to the DDR; the other end of the injection control module is connected to the source data driving module, the module under test, and one end of the result comparison module; the other end of the data source driving module and the result data storage and writing module are both connected to the DDR and the module under test; the other end of the result comparison module is connected to the DDR; The module under test: selects a signal that needs to be injected with a single-bit fault injection in the original module under test, modifies the signal in a code mutation manner, inserts a single-bit fault injection control signal, and forms a module under test after code mutation.
2. The SRAM-type FPGA online fault injection system according to claim 1, characterized in that: The host computer fault injection module includes: a serial port A sending module, a serial port A receiving module, a source data loading module, and a test result display module; the source data module sends data to the source data loading module, and after the source data loading module processes and loads the data, it sends it to serial port A through the serial port A sending module; after the serial port A receiving module receives the data transmitted by serial port A, it sends it to the test result display module.
3. A test method for an SRAM-type FPGA online fault injection system according to claim 1 or 2, characterized in that: The specific steps include: Step 1: Select a signal to be injected with a single-bit fault in the original module under test, modify the signal by code mutation, insert a single-bit fault injection control signal, and form a module under test after code mutation; Step 2: Embed the tested module code into the FPGA board, compile and generate a bitstream file, then load it into the FPGA on the FPGA board for execution, and run the host computer fault injection module on the host computer at the same time; Step 3: The source data loading module of the fault injection module of the host computer reads the source data in the source data module and sends it to the serial port A through the serial port A sending module; Step 4: Serial port A sends the source data to serial port B via the serial cable; Step 5: Serial port B sends the source data to the serial port B receiving module of FPGA; Step 6: The serial port B receiving module stores the source data into the address space 1 in the DDR through the source data storage and writing module, and notifies the injection control module that the source data has been received; Step 7: The injection control module controls the single-bit fault injection control signal in the module under test to be 0, that is, the injected signal is the original value; Step 8: The injection control module sends a start signal to the source data driver module for the first time, and starts timing at the same time; Step 9: The source data driver module reads the source data from address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test; Step 10: After receiving the source data, the module under test runs and generates golden result data, and sends it to the result data storage and writing module. The result data storage and writing module stores the golden result data in address space 2 in the DDR; Step 11: When the injection control module reaches the preset running time, it is determined that the first running of the module under test has ended; Step 12: the injection control module controls the single-bit fault injection control signal in the module under test to be 1, that is, the injected signal is a single-bit flipped fault value; Step 13: The injection control module sends a start signal to the source data driving module for the second time, and starts timing at the same time; Step 14: The source data driver module reads the source data from the address space 1 in the DDR and drives it to the module under test according to the input format required by the module under test; Step 15: After receiving the source data, the module under test runs and generates the injection test result data, and sends it to the result data storage and writing module. The result data storage and writing module stores the injection test result data in the address space 3 in the DDR; Step 16: When the injection control module reaches the preset running time, it is determined that the second running of the tested module has ended, and a start signal is sent to the result comparison module; Step 17: The result comparison module reads the golden result data from address space 2 in the DDR, reads the injection test result data from address space 3 in the DDR, and compares the golden result data and the injection test result data word by word; If the comparison is consistent, the test result is correct; if the comparison is inconsistent, the test result is wrong; Step 18: The result comparison module sends the test result to the serial port B sending module, and the serial port B sending module sends the test result to the serial port B; Step 19: Serial port B sends the test result to serial port A through the serial port cable, and serial port A sends the test result to the test result display module through the serial port A receiving module; Step 20: The test result display module displays the test result.