A media access control layer PONMAC chip supporting resource reallocation

Abstract

The present application proposes a media access control layer PONMAC chip that supports resource reallocation, including a central processing unit CPU unit and a logic unit, wherein: the CPU unit communicates with the management CPU in the optical line terminal / main device through the management network port, and is used to manage the logic unit based on the system configuration file / configuration file sent by the management CPU, and the management includes the configuration of software and hardware resources and business logic management of the passive optical network PON port; the uplink port of the logic unit is connected to the switching chip, and the downlink port is the PON port, which is connected to the CPU unit through a bus, and is used to perform business logic of data stream forwarding between the uplink switching port and the configured software and hardware resources of the PON port according to the management of the CPU unit. Using the chip in the FTTR networking can realize the flexible adjustment of the relevant resources of the PON port and resource sharing and reallocation, and make full use of the computing power of the CPU.

Description

Technical Field

[0001] The present invention relates to the field of PON (Passive Optical Network) and FTTR (Fiber to The Room), and in particular to a media access control layer PON MAC (Passive Optical Network Media Access Control Chip) chip supporting reallocation of resources. The present invention relates to the field of PON (Passive Optical Network) and FTTR (Fiber to The Room), and in particular to a media access control layer PON MAC (Passive Optical Network Media Access Control Chip) chip supporting reallocation of resources. Background Art

[0002] As an advanced network deployment method, FTTR networking extends optical fiber directly to every room in the user's home to provide high-bandwidth, low-latency network connections. It is the core technology of the new generation of home networking. The FTTR networking architecture mainly consists of an MFU device (Main FTTR Unit, master device) and one or more SFU devices (Single FTTR Unit, slave devices), as well as an indoor optical distribution network connecting the master and slave devices. The MFU integrates the functions of ONU (Optical Network Unit) and OLT (Optical Line Termination).

[0003] In the prior art, the PONMAC chip in the OLT device or MFU device generally adopts an ASIC (Application-Specific Integrated Circuit) integrated chip. The hardware structure of the ASIC integrated chip is fixed, and it supports a specific number of PON ports. The software and hardware resources are bound to the fixed PON port, which lacks flexibility. When the PON port is idle, its corresponding resources cannot be released, resulting in performance waste. On the other hand, once the ASIC chip is designed, its function is fixed, and its adaptability to changes in the environment or demand is poor. Different functional requirements need to be redesigned and produced, and frequent design updates result in high production cycles and labor costs. In the actual deployment process of the existing network, due to the limitations of the number of ONU deployments and the existing wiring environment, some of the downstream PON ports of the OLT device or MFU device cannot be fully utilized and have been idle, resulting in a waste of related resources. Summary of the invention

[0004] The embodiment of the present invention provides a PONMAC chip supporting resource reallocation and a resource reallocation method based on the PONMAC chip. The number of supported PON ports and corresponding software and hardware resources can be reconfigured through a system configuration file to achieve flexible adjustment of related resources of the PON port, support resource sharing and reallocation of the PON port, and make full use of the computing power of the CPU.

[0005] In a first aspect, an embodiment of the present application provides a PONMAC chip supporting resource reallocation, including a CPU unit and a logic unit, wherein the logic unit is programmed by a field programmable gate array FPGA to implement hardware logic functions, wherein:

[0006] The CPU unit communicates with the management CPU in the optical line terminal OLT / main device MFU device through the management network port, and is used to manage the logic unit based on the system configuration file / configuration file sent by the management CPU, and the management includes software and hardware resource configuration and business logic management of the passive optical network PON port;

[0007] The logic unit has an uplink port connected to a switching chip and a downlink port as a PON port, which is connected to the CPU unit via a bus and is used to implement business logic of data stream forwarding between the uplink switching port and the configured software and hardware resources of the PON port according to the management of the CPU unit.

[0008] In some possible embodiments, the logic unit includes a plurality of PON units corresponding to each PON port, each PON unit includes a service logic module and a configuration logic module, wherein:

[0009] The business logic module is used to utilize the software and hardware resources of the configured PON port to perform business logic for data stream forwarding between the uplink switching port;

[0010] The configuration logic module is used to implement the service logic management function of the CPU unit on each PON port.

[0011] In some possible embodiments, the configuration logic module includes:

[0012] Physical layer operation management and maintenance PLOAM message buffer module, used for receiving and buffering PLOAM messages in the downstream and upstream directions of the PON port;

[0013] The optical network unit manages and controls the OMCI message buffer module, which is used for receiving and buffering the downstream and upstream OMCI messages of the PON port;

[0014] Configuration and status register module, used to implement the configuration and status query functions of the business logic functions of the PON port;

[0015] An interrupt status module, configured to send an interrupt message to the CPU unit when determining that an interrupt event occurs in a service logic module of the corresponding PON port based on the value of the register corresponding to the PON port in the configuration and status register module;

[0016] A dynamic bandwidth allocation DBA upstream traffic statistics module is used to implement a statistical function of the upstream traffic of each transmission container TCONT of the PON port in each DBA cycle, and provide the statistical results to the CPU unit;

[0017] A DBA downstream data buffer module is used to receive downstream DBA data from the CPU unit to the PON port, and forward the data to the optical network unit ONU by the PON port;

[0018] The upstream direction is from the PON port to the CPU unit, and the downstream direction is from the PON port to the ONU.

[0019] In some possible embodiments, the logic unit further includes a shared storage resource pool;

[0020] The shared storage resource pool is used to store at least one of the following resources shared by all the multiple PON units: ONU resources, bandwidth scheduling AllocID resources and GEMPort resources, the minimum unit of data flow.

[0021] In some possible embodiments, the CPU unit includes a first CPU core and at least one second CPU core, and the system configuration file includes a first configuration file for managing the logic unit and a second configuration file for configuring the second CPU core, wherein:

[0022] The first CPU core is used to manage the logic unit and each second CPU core based on the first configuration file in the system configuration file / the configuration file sent by the management CPU;

[0023] Each second CPU core is used to determine the allocated PON port based on the second configuration file in the system configuration file, and perform DBA calculation on each allocated PON port based on the management of the first CPU core.

[0024] In some possible embodiments, the first CPU core includes:

[0025] The network port driver module is used to forward the configuration management message carrying the configuration file received from the management CPU through the management network port to the configuration management thread;

[0026] A configuration management thread is used to receive the configuration management message, analyze the configuration management message to obtain a configuration file, wherein the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, send the local configuration information to the corresponding PON port module, and forward the overall configuration information to the device configuration thread;

[0027] A plurality of PON port modules corresponding to each PON port, each of the PON port modules being used to receive the local configuration information and configure the corresponding PON unit in the logic unit according to the local configuration information;

[0028] The device configuration thread is used to install the corresponding PON port module according to the first configuration file, initialize the configuration of the PON port module and the logic unit, create a DBA control data table in the second configuration file and send bandwidth configuration parameters to the corresponding second CPU cores, receive the overall configuration information, and update the system configuration file based on the overall configuration information, update the configuration of the corresponding PON port module and the logic unit and the DBA control data table and send bandwidth configuration parameters to the corresponding second CPU cores.

[0029] In some possible embodiments, the first CPU core further includes:

[0030] The register read and write interface module is used to implement the reading and writing of the configuration and status register modules in the corresponding PON unit by the PON port module and the device configuration thread.

[0031] In some possible embodiments, the first CPU core further includes:

[0032] An interrupt processing module, used for receiving an interrupt message of the corresponding PON port sent by the logic unit, calling the register read-write interface module, reading the value of the register of the corresponding PON port in the configuration and status register module, and determining event information based on the value of the register, and sending the event information to the interrupt message distribution thread;

[0033] The interrupt message distribution thread is used to forward the event information to a PON port module corresponding to the target PON port based on the target PON port corresponding to the event information.

[0034] In some possible embodiments, the PON port module includes:

[0035] The PON port configuration thread is used to receive and process the local configuration information sent by the configuration management thread;

[0036] OMCI protocol stack management thread, for building the OMCI business model of ONU, receiving and processing the OMCI event information sent by the interrupt message distribution thread, and processing the OMCI business configuration information for ONU in the local configuration information;

[0037] An uplink port configuration thread, used for processing the uplink port configuration information in the local configuration information sent by the configuration management thread;

[0038] The alarm processing thread is used to receive and process the alarm event information sent by the interrupt message distribution thread;

[0039] The PLOAM message processing thread is used to receive and process the PLOAM event information sent by the interrupt message distribution thread.

[0040] In some possible embodiments, the PON port module further includes:

[0041] The encryption key exchange thread is used to process the exchange and switching of the downstream encryption key of the corresponding PON port;

[0042] PON port timer task module, used to complete the timing task of the PON port;

[0043] The ONU timer task module is used to complete the corresponding ONU timing task according to the respective configuration of each ONU.

[0044] In a second aspect, the embodiment of the present application further proposes a resource reallocation method based on a PONMAC chip, the method comprising:

[0045] Initialize the configuration of the logic unit through the CPU unit based on the parameters preset in the system configuration file;

[0046] A configuration management message carrying a configuration file for resource reallocation sent by a management CPU in an OLT device or an MFU device is received through a CPU unit, and the logic unit is reconfigured based on the configuration file.

[0047] In some possible embodiments, the CPU unit includes a first CPU core and at least one second CPU core, and the initializing and configuring the logic unit includes at least one of the following steps:

[0048] Calling the register read-write interface module through the device configuration thread in the first CPU core, initializing the configuration and status register module of the PON unit in the logic unit based on the first configuration file preset in the system configuration file;

[0049] Installing a corresponding PON port module based on the first configuration file through the device configuration thread, and initializing the configuration of the PON port module;

[0050] The device configuration thread creates a DBA control data table in the second configuration file based on the second configuration file preset in the system configuration file, and sends bandwidth configuration parameters to the corresponding second CPU cores.

[0051] In some possible embodiments, the reconfiguring and managing the logic unit includes:

[0052] Forwarding the configuration management message carrying the configuration file received from the management CPU to the configuration management thread through the network port driver module in the first CPU core;

[0053] Receiving the configuration management message through the configuration management thread in the first CPU core, analyzing the configuration management message to obtain a configuration file, wherein the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, sending the local configuration information to a target PON port module corresponding to the some PON ports, and forwarding the overall configuration information to the device configuration thread;

[0054] Receiving the local configuration information through the target PON port module in the first CPU core, and reconfiguring the corresponding PON unit in the logic unit according to the local configuration information;

[0055] The overall configuration information is received through the device configuration thread in the first CPU core, and the system configuration file is updated based on the overall configuration information, the corresponding PON port module and logic unit are configured, and the DBA control data table in the second configuration file of the system configuration file is updated and the bandwidth configuration parameters are sent to the corresponding second CPU cores.

[0056] In some possible embodiments, the method further includes:

[0057] The second CPU core starts DBA calculation of the PON port based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the DBA control data table.

[0058] In some possible embodiments, the method further includes:

[0059] The second CPU core performs DBA calculation of the PON port based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file updated in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the updated DBA control data table.

[0060] The media access control layer PONMAC chip supporting resource reallocation and the resource reallocation method based on the PONMAC chip provided in the embodiments of the present application can realize the configuration and flexible adjustment of relevant resources of the PON port, support resource sharing and reallocation of the PON port, and make full use of the computing power of the CPU.

[0061] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0063] Figure 1 A schematic diagram of a common hardware architecture of an OLT device in an embodiment of the present application;

[0064] Figure 2 A schematic diagram of a common hardware architecture of an MFU device in an embodiment of the present application;

[0065] Figure 3 A schematic diagram of a PONMAC chip architecture supporting resource reallocation in an embodiment of the present application;

[0066] Figure 4 This is a schematic diagram of the logic unit architecture in an embodiment of the present application;

[0067] Figure 5 This is a schematic diagram of the configuration logic module architecture in an embodiment of the present application;

[0068] Figure 6 This is a schematic diagram of the CPU unit architecture in an embodiment of the present application;

[0069] Figure 7 A schematic diagram of a resource reallocation method based on a PONMAC chip in an embodiment of the present application;

[0070] Figure 8 A schematic diagram of a process of reconfiguring a logic unit in an embodiment of the present application;

[0071] Fig. 9This is an exemplary flow chart of initializing and configuring a PON port in an embodiment of the present application;

[0072] Fig.10 This is an exemplary flow chart of reallocating resources of a PON port in an overall configuration manner in an embodiment of the present application. DETAILED DESCRIPTION

[0073] To further illustrate the technical solution provided by the embodiments of the present application, a detailed description is given below in conjunction with the accompanying drawings and specific implementation methods.

[0074] PON technology is a P2MP (Point 2 Multiple point) fiber access technology with the advantages of low cost, easy maintenance, and high bandwidth. It is the mainstream technology of access network, and has gradually developed from FTTB (Fiber TO The Building), FTTH (Fiber TO The Home) to FTTO (Fiber TO The Office), FTTR, and the rate has been upgraded from Gigabit to 10 Gigabit PON technology. The entire PON system consists of OLT, ONU and ODN (Optical Distribution Network). The downstream uses broadcast to transmit data, and the upstream uses TDMA (Time Division Multiple Access) to achieve shared access of multiple ONUs. GPON (Gigabit Passive Optical Network) technology is a PON technology defined by ITU-T (International Telecommunication Union-Telecommunication Standardization Sector, the telecommunication standardization department of the International Telecommunication Union). It has comprehensive and standardized management characteristics and is more widely used in existing networks. XG(S)PON (10 Gigabit Passive Optical Network) technology is an upgraded version of GPON technology, supporting asymmetric or symmetric 10 Gigabit rates for upstream and downstream.

[0075] In PON equipment, the chip responsible for implementing the PON protocol stack functions defined in the ITU-T standard is generally called a PONMAC chip. In an ONU, it generally contains one or more TCONTs (Transmission CONTs, service transmission containers), which are identified by bandwidth scheduling AllocID. The PONMAC chip of the OLT allocates upstream time slots, that is, corresponding upstream bandwidths, to multiple TCONTs of different ONUs through the DBA (Dynamic Bandwidth Assignment) mechanism, and implements upstream access control of multiple ONUs to improve the upstream bandwidth utilization of the system.

[0076] Common hardware architecture of OLT equipment, such as Figure 1 As shown: the switching chip is connected to the upper-layer network device through the uplink Ethernet interface and is responsible for the storage and forwarding of Ethernet data services; the PONMAC chip generally has multiple PON ports, each of which is connected to a large number of ONU devices in a P2MP manner through a passive optical fiber network, and is responsible for the conversion between PON link data and Ethernet service data, the dynamic allocation of each ONU's upstream bandwidth and access control; the management CPU is responsible for the configuration management of the service functions on the switching chip and the PONMAC chip.

[0077] The FTTR network architecture mainly consists of an MFU device and one or more SFU devices, as well as an indoor optical distribution network connecting the master device and the slave device, where the MFU integrates the ONU and OLT functions. The general hardware architecture of the MFU device is as follows: Figure 2 As shown: Upward, it is connected to the central office OLT device through the ONU PONMAC chip to provide fiber-to-the-home, realizing the conversion between Ethernet services and PON link data in the upstream direction; downward, as the main OLT device, it connects multiple slave devices through the OLT PONMAC chip and the indoor optical network to realize the conversion between PON link data and Ethernet service data in the downstream direction, and the dynamic allocation and access control of the upstream bandwidth of each slave device; the internal switching chip is responsible for the storage and forwarding of upstream and downstream Ethernet services; the management CPU is responsible for the configuration management of the switching chip and the service functions on the ONU / OLT PONMAC chip.

[0078] In the prior art, the PONMAC chip in the OLT device or MFU device generally adopts an ASIC integrated chip. The hardware structure of the ASIC integrated chip is fixed, and it supports a specific number of PON ports. The software and hardware resources are bound to the fixed PON port, which lacks flexibility. When the PON port is idle, its corresponding resources cannot be released, resulting in performance waste. On the other hand, once the ASIC chip is designed, its function is fixed, and its adaptability to changes in the environment or demand is poor. Different functional requirements need to be redesigned and produced, and frequent design updates result in high production cycles and labor costs. In the actual deployment process of the existing network, due to the limitations of the number of ONU deployments and the existing wiring environment, some of the downstream PON ports of the OLT device or MFU device cannot be fully utilized and have been in an idle state, resulting in a waste of related resources.

[0079] In view of the above problem that some downlink PON ports may not be fully utilized due to restrictions in the actual deployment process of the existing network, and are in an idle state, resulting in waste of related resources, the embodiment of the present application provides a PONMAC chip that supports reallocation of resources, such as Figure 3 As shown, it includes a CPU unit 301 and a logic unit 302, and the logic unit is programmed by a field programmable gate array FPGA to implement hardware logic functions, wherein:

[0080] The CPU unit communicates with the management CPU in the optical line terminal OLT / main device MFU device through the management network port, and is used to manage the logic unit based on the system configuration file / configuration file sent by the management CPU, and the management includes software and hardware resource configuration and business logic management of the passive optical network PON port;

[0081] The logic unit has an uplink port connected to a switching chip and a downlink port as a PON port, which is connected to the CPU unit via a bus and is used to implement business logic of data stream forwarding between the uplink switching port and the configured software and hardware resources of the PON port according to the management of the CPU unit.

[0082] In the embodiment of the present application, the flexible configuration of the PON port in the logic unit and the flexible configuration of the resources in the CPU unit between the PON ports are realized through FPGA programming. Through the CPU unit, based on the system configuration file / configuration file sent by the management CPU, the software and hardware resources corresponding to the supported PON ports can be configured, and the flexible adjustment of the resources related to the PON port is realized. At the same time, it also supports multiple PON ports to share the computing power of the CPU unit, making full use of the computing power of the CPU unit. On the other hand, the use of FPGA programming to realize its hardware functions avoids the disadvantages of redesigning and producing ASIC chips for different functional requirements, which can reduce the production cycle and labor costs.

[0083] In some possible embodiments, the logic unit includes a plurality of PON units corresponding to each PON port, and is used to implement the service logic functions related to each PON port, such as Figure 4 As shown, each PON unit includes a service logic module 401 and a configuration logic module 402, wherein:

[0084] The service logic module 401 is used to utilize the software and hardware resources of the configured PON port to perform service logic for data stream forwarding between the uplink switching port;

[0085] The configuration logic module 402 is used to implement the service logic management function of the CPU unit on each PON port.

[0086] In an embodiment of the present application, the business logic module is used to utilize the software and hardware resources of the configured PON port to perform business logic for data stream forwarding between the upstream switching port, and is specifically responsible for realizing the conversion between PON services and Ethernet services in the upstream and downstream directions, wherein the upstream direction is the PON port to the CPU unit, and the downstream direction is the PON port to the ONU.

[0087] In some possible embodiments, the logic unit further includes a shared storage resource pool, which is used to store at least one of the following resources shared by all multiple PON units: ONU resources, AllocID resources and GEMPort (GPON Encapsulation Method Port, Gigabit Passive Optical Network Encapsulation Port) resources.

[0088] The logic unit obtains corresponding resources from the shared resource pool according to the configuration of the service logic management function of each PON port in the configuration logic module, and implements the service logic of the corresponding PON port in the logic unit.

[0089] In some possible embodiments, the configuration logic module implements the service logic management function of the CPU unit for each PON port through each submodule, such as Figure 5 As shown, including:

[0090] A PLOAM (Physical Layer Operations, Administration and Maintenance) message buffer module 501 is used for receiving and buffering PLOAM messages in the downstream direction and upstream direction of the PON port, wherein: the downstream direction is to receive PLOAM messages from the CPU unit and forward them from the PON port to the ONU; the upstream direction is to receive PLOAM messages from the ONU and send them to the CPU unit;

[0091] OMCI (ONU Management and Control Interface, optical network unit management and control) message buffer module 502, used for receiving and caching downstream and upstream OMCI messages of the PON port, wherein: the downstream direction is to receive the OMCI message from the CPU unit and forward it from the PON port to the ONU; the upstream direction is to receive the OMCI message from the ONU and send it to the CPU unit;

[0092] Configuration and status register module 503, used to implement the configuration and status query functions of the service logic functions of the PON port, and to implement the control of the service logic functions by the CPU unit;

[0093] The interrupt status module 504 is used to send an interrupt message to the CPU unit when determining that an interrupt event occurs in the service logic module of the corresponding PON port based on the value of the register corresponding to the PON port in the configuration and status register module, so as to report the interrupt event detected by the service logic module of the PON unit to the CPU unit in the form of an interrupt message;

[0094] The DBA upstream traffic statistics module 505 is used to implement the statistics function of the upstream traffic of each transmission container TCONT of the PON port in each DBA cycle, and provide the statistical results to the CPU unit;

[0095] DBA downstream data buffer module 506, used to receive downstream DBA data from the CPU unit to the PON port, and forwarded by the PON port to the optical network unit ONU, the downstream DBA data including BWmap (Bandwidth Map, upstream bandwidth permission) data of each AllocID and related control data;

[0096] The upstream direction is from the PON port to the CPU unit, and the downstream direction is from the PON port to the ONU.

[0097] In some possible embodiments, the above-mentioned interrupt status module determines that there is an interrupt event in the service logic module of the corresponding PON port, and the interrupt event includes at least one of the following: discovery of a new ONU device, completion of ONU ranging, receipt of an uplink PLOAM message, and receipt of an uplink OMCI message.

[0098] In some possible embodiments, the interruption event also includes an alarm event, which is detected by a business logic module related to the PON port or the ONU, and includes at least one of the following: LOS (Loss Of Signal) alarm of the PON port, LOSi (Loss Of Signal) alarm related to the ONU, LOFi (Loss Of Frame) alarm, LOAMi (Loss of PLOAM) alarm, DOWi (Drift of window) alarm and TIWI (Transmission interfere warming) alarm.

[0099] In some possible embodiments, Figure 6 As shown, the CPU unit includes a first CPU core and at least one second CPU core, and the system configuration file includes a first configuration file for managing the logic unit and a second configuration file for configuring the second CPU core, wherein:

[0100] The first CPU core is used to manage the logic unit and each second CPU core based on the first configuration file in the system configuration file / the configuration file sent by the management CPU;

[0101] Each second CPU core is used to determine the allocated PON port based on the second configuration file in the system configuration file, and perform DBA calculation on each allocated PON port based on the management of the first CPU core.

[0102] In the embodiment of the present application, the first CPU core is mainly responsible for the configuration management of the PON protocol stack and the device configuration management function, and the second CPU core is only responsible for the DBA calculation of the AllocID of each PON port. When the number of PON ports is large, the PON ports can be assigned to different second CPU cores for calculation to reduce the calculation burden on a single core. The PONMAC chip of the embodiment of the present application, through the collaboration of the first CPU core and multiple second CPU cores, jointly completes all business management and calculation functions on the PONMAC chip, and the DBA calculation of all PON ports is the responsibility of the dedicated second CPU core. On each second CPU core, the DBA calculation of multiple PON ports can be completed within one DBA cycle, which can make full use of the CPU's computing resources.

[0103] In some possible embodiments, the first configuration file for managing the logical unit in the system configuration file specifically includes at least one of the following:

[0104] The enabling status of each PON port, the ONU information supported by the enabled PON port, the AllocID information supported by each PON port, and the GEMPort information supported by each PON port.

[0105] The second configuration file for configuring the second CPU cores specifically includes at least one of the following: the number of PON ports and the PON port ID range for which each second CPU core is responsible for DBA calculation.

[0106] In some possible embodiments, each second CPU core is used to complete the calculation of several PON ports in sequence according to the order of PON port IDs. For each PON port, the DBA calculation process is performed on each AllocID under the PON port, and the second CPU core is specifically used to:

[0107] Obtain the upstream traffic statistics result of the AllocID of each PON port from the DBA upstream traffic statistics module in the configuration logic module of the PON unit in the logic unit;

[0108] According to the bandwidth configuration parameters of each AllocID and the statistical data of the upstream traffic, the DBA calculation of the AllocID is performed to obtain the upstream bandwidth allocation data of the AllocID;

[0109] Construct the downstream BWmap data of the PON port, and send the upstream bandwidth allocation data of each AllocID to the DBA downstream data cache module in the configuration logic module of the PON unit in the logic unit.

[0110] On each second CPU core responsible for DBA calculation, after completing the DBA calculation process of the first PON port, continue to complete the DBA calculation process of the second PON port, and so on. After completing all the DBA calculation processes of the last PON port that the second CPU core is responsible for, the bandwidth configuration parameters of all AllocIDs of each PON port are updated from the configuration parameter buffer area of ​​the second CPU core. After that, continue to re-perform the DBA calculation process of each PON port starting from the first PON port.

[0111] In some possible embodiments, the first CPU core, such as Figure 6 As shown, including:

[0112] The network port driver module is used to forward the configuration management message carrying the configuration file received from the management CPU through the management network port to the configuration management thread, so as to realize the sending and receiving function of the CPU on the external management network port;

[0113] The configuration management thread is used to receive and process messages from the lower-layer network port driver module, the upper-layer device configuration thread, and each PON port module, including:

[0114] Receive the configuration management message, analyze the configuration management message to obtain a configuration file, the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, send the local configuration information to the corresponding PON port module, and forward the overall configuration information to the device configuration thread;

[0115] Receive messages from the upper-layer device configuration thread and each PON port module, cache the message content, and fragment the messages that exceed the maximum limit of the network port MTU, add message headers to the fragmented messages, and call the network port driver module to send the fragmented messages through the network port;

[0116] In some possible embodiments, the configuration management thread may be implemented by two threads, including a network polling thread and a configuration management thread:

[0117] The network polling thread is responsible for polling and waiting for messages from the network port driver module, and forwarding the received messages to the configuration management thread;

[0118] The configuration management thread is used to receive and process messages from the lower layer network port driver module, the upper layer device configuration thread and each PON port module, wherein:

[0119] In the uplink direction, receiving the configuration management message from the network polling thread, caching the message content and reorganizing it according to the identifier of the message header, parsing the reorganized configuration management message content, sending the local configuration information to the corresponding PON port module according to the configuration file in the configuration management message content, and forwarding the overall configuration information to the device configuration thread;

[0120] In the downstream direction, it receives messages from the upper-layer device configuration thread or threads in each PON port module (such as: PON port configuration thread, uplink port configuration thread), caches the message content, and fragments the messages that exceed the maximum limit of the network port MTU, adds message headers to the fragmented messages, and calls the network port driver sending interface to send the fragmented messages through the network port.

[0121] A plurality of PON port modules corresponding to each PON port, each of which corresponds to one PON port, and is used to complete the PON port management, uplink port management, ONU management, GEMPort management, TCONT management, interrupt processing, PLOAM protocol stack, OMCI protocol stack, encryption and key exchange and other functions related to the PON port, wherein:

[0122] When configuring the PON port, the PON port module is used to receive the local configuration information and configure the corresponding PON unit in the logic unit according to the local configuration information;

[0123] The device configuration thread is used to complete the overall configuration of the device, including device configuration management, uplink port overall configuration management, PON port module overall configuration management and system configuration file management, including:

[0124] Specifically used for installing the corresponding PON port module according to the first configuration file, initializing the configuration of the PON port module and the logic unit, creating a DBA control data table in the second configuration file and sending bandwidth configuration parameters to the corresponding second CPU cores, and receiving the overall configuration information, and updating the system configuration file based on the overall configuration information, updating the configuration of the corresponding PON port module and the logic unit and the DBA control data table and sending bandwidth configuration parameters to the corresponding second CPU cores.

[0125] The device configuration thread may update the first configuration file and the second configuration file in the system configuration file according to the content of the configuration management message. When the first configuration file and the second configuration file are updated, the device configuration thread reinitializes the PON port module and reallocates the PON ports participating in the DBA calculation and the resources in the CPU unit occupied by them according to the configuration management message.

[0126] In some possible embodiments, the first CPU core further includes:

[0127] The register read and write interface module is used to implement the reading and writing of the configuration and status register modules in the corresponding PON unit by the PON port module and the device configuration thread.

[0128] In the embodiment of the present application, when the device is configured, the device configuration thread and the corresponding PON port module are used to call the register read and write interface module to update the configuration register value in the corresponding logic unit according to the content of the configuration management message.

[0129] In some possible embodiments, the first CPU core further includes:

[0130] The interrupt processing module is used to receive the interrupt message of the corresponding PON port sent by the logic unit, call the register read and write interface module, read the value of the register corresponding to the PON port in the configuration and status register module, and determine the event information based on the value of the register, and send the event information to the interrupt message distribution thread, wherein the event information includes the type and attribute parameters of the event source.

[0131] The interrupt message distribution thread is used to forward the event information to a PON port module corresponding to the target PON port based on the target PON port corresponding to the event information.

[0132] In an embodiment of the present application, the interrupt processing module is specifically implemented using an interrupt processing interface function, and the interrupt events correspond to their own independent interrupt functions. The interrupt function reads the value of the register corresponding to the PON port in the configuration and status register module, and determines the corresponding interrupt event type, source and attributes based on the register value.

[0133] In some possible embodiments, the event source of the event information is mainly PON port ID and ONU ID. The attribute parameters of the event information include: new ONU serial number (SN), ONU equalization delay bit number, ONU upstream drift direction indication, and ONU upstream drift bit number.

[0134] In the embodiment of the present application, the event information includes alarm information and interrupt event information, wherein:

[0135] The alarm information includes at least one of the following: LOS alarm of the PON port, LOSi alarm related to the ONU, LOFi alarm, LOAMi alarm, DOWi alarm and TIWI alarm;

[0136] The interruption event information includes at least one of the following: a new ONU SN discovery message, an ONU ranging completion message, an uplink PLOAM message, and an uplink OMCI message.

[0137] In some possible embodiments, the PON port module is used to complete the PON port management, uplink port management, ONU management, GEMPort management, TCONT management, interrupt processing, PLOAM protocol stack, OMCI protocol stack, encryption and key exchange and other functions related to the PON port, which are implemented through corresponding threads, such as Figure 6 As shown, the PON port module includes:

[0138] The PON port configuration thread is responsible for processing the local configuration information of the PON port reported by the configuration management thread, including: PON port related configuration management messages, ONU related configuration management messages, GEM Port related configuration management messages and TCONT related configuration management messages, and configuring related parameters based on the configuration management messages;

[0139] At the same time, the PON port configuration thread is also responsible for processing the ONU related event messages of the PON port reported by the interrupt message distribution thread, including: new ONU SN discovery message, ONU ranging completion message.

[0140] OMCI protocol stack management thread, responsible for the functional management of the PON port OMCI protocol stack, specifically used for: building the OMCI business model of the ONU, processing the OMCI business configuration message of the ONU of the PON port reported by the configuration management thread, receiving and processing the OMCI event information sent by the interrupt message distribution thread, and building and issuing OMCI messages;

[0141] An uplink port configuration thread, used for processing the uplink port configuration information in the local configuration information sent by the configuration management thread, and configuring uplink port related parameters based on the uplink port configuration information;

[0142] An alarm processing thread is used to receive and process the alarm event information sent by the interrupt message distribution thread, wherein the alarm event information includes the LOS alarm of the PON port, the ONU-related LOSi alarm, LOFi alarm, LOAMi alarm, DOWi alarm and TIWI alarm;

[0143] The PLOAM message processing thread is used to receive and process the PLOAM event information sent by the interrupt message distribution thread.

[0144] Correspondingly, in the embodiment of the present application, the interrupt message distribution thread is used to forward the event information to the PON port module corresponding to the target PON port based on the target PON port corresponding to the event information, specifically for:

[0145] Forwarding the alarm information to the alarm processing thread of the PON port module;

[0146] Forward new ONU SN discovery message and ONU ranging completion message to the PON port configuration thread;

[0147] Forward the uplink PLOAM message to the PLOAM message processing thread;

[0148] Forward the upstream OMCI message to the PON OMCI protocol stack management thread.

[0149] In some possible embodiments, the PON port module further includes:

[0150] The encryption key exchange thread is used to process the exchange and switching of the downstream encryption key of the corresponding PON port;

[0151] PON port timer task module, used to complete the timing task of the PON port;

[0152] The ONU timer task module is used to complete the corresponding ONU timing task according to the respective configuration of each ONU, wherein each ONU corresponds to its own independent timer.

[0153] Through the PON port configuration thread, OMCI protocol stack management thread, uplink port configuration thread, alarm processing thread, PLOAM message processing thread, encryption key exchange thread, PON port timer task module and ONU timer task module included in the above-mentioned PON port module, the PON port management, uplink port management, ONU management, GEMPort management, TCONT management, alarm processing, PLOAM protocol stack, OMCI protocol stack, encryption and key exchange and other functions related to the PON port can be collaboratively completed.

[0154] In the embodiment of the present application, a media access control layer PONMAC chip supporting resource reallocation is proposed, including a CPU unit and a logic unit, wherein: the CPU unit communicates with the management CPU in the optical line terminal OLT / main device MFU device through the management network port, and is used to manage the logic unit based on the system configuration file / configuration file sent by the management CPU, and the management includes the configuration of software and hardware resources and business logic management of the passive optical network PON port; the uplink port of the logic unit is connected to the switching chip, and the downlink port is a PON port, which is connected to the CPU unit through a bus, and is used to perform business logic of data stream forwarding between the uplink switching port and the configured software and hardware resources of the PON port according to the management of the CPU unit. In the logic unit and the CPU unit, the logical functions and resources between the PON ports are independent of each other, and the system configuration file in the CPU unit can determine whether its function is loaded and initialized, and the number of PON ports supported by the PONMAC chip can be flexibly adjusted, so that the configuration and flexible adjustment of the relevant resources of the PON port can be realized, and the resource sharing and reallocation of the PON port can be supported, and the computing power of the CPU can be fully utilized.

[0155] Based on the same inventive concept, the embodiment of the present application also proposes a resource reallocation method based on a PONMAC chip, which can realize the configuration and flexible adjustment of related resources of the PON port, support resource sharing and reallocation of the PON port, and make full use of the computing power of the CPU, such as Figure 7 As shown, the method includes:

[0156] Step 701, initializing and configuring the logic unit based on the parameters preset in the system configuration file by the CPU unit;

[0157] Step 702: A configuration management message carrying a configuration file for resource reallocation sent by a management CPU in an OLT device or an MFU device is received through a CPU unit, and the logic unit is reconfigured based on the configuration file.

[0158] In some possible embodiments, the CPU unit includes a first CPU core and at least one second CPU core, the parameters preset in the above system configuration file include a first configuration file for managing the logic unit and a second configuration file for configuring the second CPU core, and the initialization configuration of the logic unit includes at least one of the following steps:

[0159] Calling the register read-write interface module through the device configuration thread in the first CPU core, initializing the configuration and status register module of the PON unit in the logic unit based on the first configuration file preset in the system configuration file;

[0160] Installing a corresponding PON port module based on the first configuration file through the device configuration thread, and initializing the configuration of the PON port module;

[0161] The device configuration thread creates a DBA control data table in the second configuration file based on the second configuration file preset in the system configuration file, and sends bandwidth configuration parameters to the corresponding second CPU cores.

[0162] Before performing initialization configuration, it is necessary to initialize the basic modules on the first CPU core in the CPU unit, which include: registering an interrupt processing module, installing a network port driver module, starting a network polling thread, a configuration management thread, an interrupt message distribution thread, and a device configuration thread.

[0163] In an embodiment of the present application, the first CPU core determines the PON port modules that need to be initialized and installed according to the first configuration file preset in the system configuration file through the device configuration thread, and initializes the installed PON port modules according to the number of ONU / AllocID / GEMPort resources in each PON port module in the first configuration file.

[0164] In an embodiment of the present application, the initialization configuration of the installed PON port module includes at least one of the following:

[0165] In each PON port module, the configuration management data table, ONU resource list, AllocID resource list, and GEMPort resource list of each PON port are initialized;

[0166] Create each ONU timer task module and register the ONU timer processing interface;

[0167] Create a PON port timer task module and register the PON port timer processing interface;

[0168] Create and start the PON port configuration thread, alarm processing thread, PLOAM message processing thread, encryption key exchange thread, uplink port configuration thread and OMCI protocol stack management thread in each PON port module.

[0169] In an embodiment of the present application, the PON port configuration thread, alarm processing thread, PLOAM message processing thread, encryption key exchange thread, uplink port configuration thread and OMCI protocol stack management thread in each of the above-mentioned PON port modules are specifically used to implement functions. Please refer to the corresponding part of the content in a PONMAC chip that supports resource reallocation in the above-mentioned embodiment of the present application, and will not be repeated here.

[0170] After initializing the configuration of the installed PON port module, the device configuration thread is further used to create a DBA control data table in the second configuration file of the system configuration file based on the first configuration file, and send bandwidth configuration parameters to the corresponding second CPU cores. The DBA control data table can indicate the ID range of the PON port for which each second CPU core is responsible for DBA calculation and the number of PON port subunits enabled in the logic unit, and instruct each second CPU core to start DBA calculation based on the DBA control data table.

[0171] Correspondingly, the second CPU core starts DBA calculation based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file in the system configuration file, and stores the calculation results in the DBA control data table. The calculation process of each second CPU core can refer to the corresponding part of the PONMAC chip supporting resource reallocation in the above-mentioned embodiment of the present application, which will not be repeated here.

[0172] In some possible embodiments, each second CPU core receives the bandwidth configuration parameters of AllocID on each PON port from the first CPU core and caches them in the configuration parameter cache area of ​​each second CPU core. After the second CPU core completes the DBA calculation of all PON ports, the calculation results are sent to the logic unit corresponding to the PON port and stored in the DBA control data table. At the same time, the bandwidth configuration parameters of AllocID on each PON port are read from the configuration parameter cache area and updated in the DBA control data table of each PON port.

[0173] In some possible embodiments, when the logic unit is reconfigured and managed, the logic unit is mainly reconfigured through the functional module of the first CPU core, such as Figure 8 As shown, the method includes:

[0174] Step 801: forwarding a configuration management message carrying a configuration file received from a management CPU to a configuration management thread through a network port driver module in a first CPU core.

[0175] Step 802: receive the configuration management message through the configuration management thread in the first CPU core, analyze the configuration management message to obtain a configuration file, the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, send the local configuration information to the target PON port module corresponding to the some PON ports, and forward the overall configuration information to the device configuration thread.

[0176] Step 803: Receive the local configuration information through the target PON port module in the first CPU core, and reconfigure the corresponding PON unit in the logic unit according to the local configuration information.

[0177] The reconfiguring of the corresponding PON unit in the logic unit according to the local configuration information, in an embodiment of the present application, the method includes at least one of the following:

[0178] Updating the first configuration file corresponding to the PON port in the system configuration file;

[0179] Install / uninstall the PON port module corresponding to the PON port;

[0180] By calling the register read-write interface module, the value of the final register of the configuration and status register module corresponding to the PON port is updated;

[0181] The DBA control data table corresponding to the PON port in the second configuration file in the system configuration file is updated.

[0182] Step 804: receive the overall configuration information through the device configuration thread in the first CPU core, update the system configuration file based on the overall configuration information, configure the corresponding PON port module and logic unit, and update the DBA control data table in the second configuration file of the system configuration file and send bandwidth configuration parameters to the corresponding second CPU cores.

[0183] The system configuration file is updated based on the overall configuration information to configure the corresponding PON port module and logic unit. In the embodiment of the present application, based on the overall configuration information, all configurations corresponding to all PON ports are updated. The specific updating method is the same as the above-mentioned methods for reconfiguring the corresponding PON unit in the logic unit according to the local configuration information, and will not be repeated here.

[0184] In some possible embodiments, the method further includes:

[0185] The second CPU core performs DBA calculation of the PON port based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file updated in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the updated DBA control data table.

[0186] The second CPU core starts DBA calculation based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file updated in the system configuration file, and stores the calculation results in the DBA control data table. At the same time, the bandwidth configuration parameters of AllocID on each PON port are read from the configuration parameter buffer area and updated to the DBA control data table of each PON port. The calculation process of each second CPU core can refer to the corresponding part of the PONMAC chip supporting resource reallocation in the above-mentioned embodiment of the present application, which will not be repeated here.

[0187] The following is an exemplary process of initializing and configuring a PON port using a resource reallocation method based on a PONMAC chip in an embodiment of the present application, taking the PONMAC chip supporting 4 PON ports, the first CPU core being Core0, the second CPU core being Core1, and a preset system configuration file for example, wherein the first configuration file in the preset system configuration file includes:

[0188] a) PON1 port enable: support 64 ONUs, 512 AllocIDs, 1024 GEMPorts;

[0189] b) PON2 port enablement: supports 64 ONUs, 512 AllocIDs, and 1024 GEMPorts;

[0190] c) PON3 port enablement: support 64 ONUs, 512 AllocIDs, 1024 GEMPorts;

[0191] d) PON4 port enablement: supports 64 ONUs, 512 AllocIDs, and 1024 GEMPorts.

[0192] The second configuration file includes: Core1 completes the DBA calculation of the PON1, PON2, PON3, and PON4 ports.

[0193] The exemplary process of initializing the configuration of the PON port is as follows: Fig. 9 As shown, including:

[0194] Step 901, start each module of Core0 and Core1 of the CPU unit, wherein each module of Core0 includes: registering an interrupt processing module, installing a network port driver module, starting a network polling thread, a configuration management thread, an interrupt message distribution thread and a device configuration thread;

[0195] Step 902, calling the register read / write interface module through the device configuration thread in Core0, based on the first configuration file preset in the system configuration file, the configuration and status register modules of the four PON units in the logical unit are initialized, and the initialization content includes configuring the number of ONUs, the number of AllocIDs, and the number of GEMPorts supported by each of PON1~PON4;

[0196] Step 903: installing the PON port modules corresponding to PON1 to PON4 respectively based on the first configuration file through the device configuration thread, and initializing the configuration of the PON port modules;

[0197] The specific method steps of installing the PON port modules corresponding to PON1 to PON4 respectively and initializing the configuration of the PON port modules can be referred to the corresponding specific contents in the above embodiments, which will not be repeated here.

[0198] Step 904: Create a DBA control data table in the second configuration file preset in the system configuration file through the device configuration thread, wherein the DBA control data table can instruct Core0 to be responsible for the DBA calculation of PON1 to PON4, and issue bandwidth configuration parameters of each AllocID to instruct each Core1 to start DBA calculation;

[0199] Step 905: Core1 starts DBA calculation based on the instruction of Core0, the bandwidth configuration parameters and the DBA control data table in the second configuration file in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the DBA control data table. At the same time, the bandwidth configuration parameters of AllocID on each PON port are read from the configuration parameter buffer area and updated to the DBA control data table of each PON port.

[0200] The following is an exemplary process for reallocating resources of PON ports in an overall configuration manner using a resource reallocation method based on a PONMAC chip in an embodiment of the present application. In an existing network environment, after the PONMAC chip completes the above-mentioned exemplary process of initialization configuration, it is restricted by changes in the network topology environment and can only use PON1 and PON2 ports, while the resources of PON3 and PON4 ports are idle. In order not to waste the resources of PON3 and PON4 ports, the resources of PON3 and PON4 ports are reallocated to PON1 and PON2 ports.

[0201] The exemplary process of reallocating resources of PON ports in an overall configuration manner is as follows: Fig.10 As shown, including:

[0202] Step 1001: forwarding a configuration management message carrying a configuration file received from a management CPU to a configuration management thread through a network port driver module in Core0.

[0203] Step 1002: Receive the configuration management message through the configuration management thread in Core0, analyze the configuration management message to obtain a configuration file, the configuration file includes overall configuration information for all PON port configurations, and forward the overall configuration information to the device configuration thread.

[0204] The overall configuration information includes first overall configuration information and second overall configuration information, and the first overall configuration information includes:

[0205] a) PON1 port enable: supports 128 ONUs, 1024 AllocIDs, and 2048 GEMPorts; b) PON2 port enable: supports 128 ONUs, 1024 AllocIDs, and 2048 GEMPorts;

[0206] c) PON3 port is prohibited;

[0207] d) PON4 port is disabled.

[0208] The second overall configuration information includes: Core1 completes DBA calculation of the PON1 and PON2 ports.

[0209] The configuration management message disables the functions of the PON3 and PON4 ports, reallocates the resources originally allocated to the PON3 and PON4 ports to the PON1 and PON2 ports, and adjusts the ID range of the PON ports participating in the DBA calculation on Core1.

[0210] Step 1003, receiving the overall configuration information through the device configuration thread in Core0, and updating the system configuration file based on the overall configuration information, configuring the corresponding PON port module and logic unit, and updating the DBA control data table in the second configuration file of the system configuration file to issue the bandwidth configuration parameters of each AllocID.

[0211] The first configuration file of the updated system configuration file is as follows:

[0212] a) PON1 port enable: support 128 ONUs, 1024 AllocIDs, 2048 GEMPorts;

[0213] b) PON2 port enable: support 128 ONUs, 1024 AllocIDs, 2048 GEMPorts;

[0214] c) PON3 port disabled: supports 0 ONU, 0 AllocID, 0 GEMPort;

[0215] d) PON4 port disabled: supports 0 ONU, 0 AllocID, 0 GEMPort;

[0216] The second configuration file of the updated system configuration file includes: DBA calculation of PON1 and PON2 ports is completed by Core1;

[0217] The new configuration file stipulates that the resources that the entire PONMAC chip can support are only allocated to PON1 and PON2, and do not need to be allocated to PON3 and PON4 ports. It can achieve the above-mentioned changes limited by the network topology environment. Only PON1 and PON2 ports can be used, and PON3 and PON4 port resources are idle. In order not to waste the resources of PON3 and PON4 ports, the resources of PON3 and PON4 ports are reallocated to the resource reallocation function of PON1 and PON2 ports.

[0218] Specifically, the device configuration thread in the Core0 uninstalls the PON3 and PON4 port software modules according to the parameters of the updated system configuration file, and stops each thread in the two PON port modules, including: a PON port configuration thread, an OMCI protocol stack management thread, an uplink port configuration thread, an alarm processing thread, a PLOAM message processing thread, an encryption key exchange thread, a PON port timer task module and an ONU timer task module, as well as a configuration management data table related to the PON port, an ONU resource list, an AllocID resource list, and a GEMPort resource list.

[0219] After the PON3 and PON4 port modules are uninstalled, all resources related to the two PON ports are released, and any configuration management messages and interrupt messages forwarded to the two PON port modules are no longer processed.

[0220] The device configuration thread in the Core0 deletes the DBA control data table of the PON3 and PON4 ports in the corresponding second configuration file according to the parameters of the updated system configuration file. Thereafter, the DBA processing thread on Core1 only processes the DBA calculation process of the PON1 and PON2 ports, and after the DBA processing of the PON1 and PON2 ports is completed, only the AllocID bandwidth configuration parameter of the PON1 and PON2 ports is updated. The DBA thread no longer processes the DBA calculation process of the PON3 and PON4 ports, and no longer updates the AllocID bandwidth configuration parameters of the PON3 and PON4 ports.

[0221] The device configuration thread configures the corresponding configuration and status register module in the logic unit through the register read and write interface module according to the parameters of the updated system configuration file: enables the PON1 and PON2 port logic unit modules, disables the PON3 and PON4 port logic unit modules, and reconfigures the number of ONUs, AllocIDs and GEMPorts supported in the PON1 and PON2 port logic units, and allocates the storage resources related to the PON3 and PON4 ports to the PON1 and PON2 ports.

[0222] At the same time, the number of ONUs, AllocIDs and GEMPorts supported by the PON1 and PON2 ports in the updated system configuration file are sent to the corresponding PON1 and PON2 port modules: in the PON1 and PON2 port modules, the number of their respective ONU resource lists, AllocID resource lists and GEMPort resource lists are increased, a timer is created for the newly added ONU and the ONU timer processing interface is registered.

[0223] Step 1004: Core 1 performs DBA calculation according to the bandwidth configuration parameters of each AllocID issued and the DBA control data table in the updated second configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the updated DBA control data table. At the same time, the bandwidth configuration parameters of the AllocID on each PON port are read from the configuration parameter buffer area and updated to the DBA control data table of each PON port.

[0224] The Core0 device configuration thread increases the AllocID quantity in the DBA control data table of the PON1 and PON2 ports according to the AllocID quantity supported by the PON1 and PON2 ports in the new system configuration file. Thereafter, the DBA processing thread completes the DBA calculation process of PON1 and PON2 according to the increased AllocID quantity of the PON1 and PON2 ports, and after the DBA processing of the PON1 and PON2 ports is completed, the AllocID bandwidth configuration parameters of the PON1 and PON2 ports are updated according to the increased AllocID quantity.

[0225] The above method completes the reallocation of related resources of each PON port on the PONMAC chip, that is, the related resource occupation of the PON3 and PON4 ports is released, the waste of resources on the PON3 and PON4 ports is avoided, the resources on the PON1 and PON2 ports are increased, and the service access capacity of PON1 and PON2 is improved.

[0226] A resource reallocation method based on the PONMAC chip is proposed in an embodiment of the present application. The method initializes the configuration of the logic unit based on the parameters preset in the system configuration file through the CPU unit; the CPU unit receives the configuration management message carrying the configuration file for resource reallocation sent by the management CPU in the OLT device or the MFU device, and reconfigures the logic unit based on the configuration file. The method proposed in the present application can realize the configuration and flexible adjustment of the relevant resources of the PON port, support the resource sharing and reallocation of the PON port, and make full use of the computing power of the CPU.

[0227] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0228] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0229] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0230] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0231] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A media access control layer PONMAC chip supporting resource reallocation, characterized in that: It includes a central processing unit (CPU) and a logic unit. The logic unit is programmed by a field programmable gate array (FPGA) to implement hardware logic functions, wherein: The CPU unit communicates with the management CPU in the optical line terminal OLT / main device MFU device through the management network port, and is used to manage the logic unit based on the system configuration file / configuration file sent by the management CPU, and the management includes software and hardware resource configuration and business logic management of the passive optical network PON port; The logic unit has an uplink port connected to a switching chip and a downlink port as a PON port, which is connected to the CPU unit via a bus and is used for performing business logic of data stream forwarding between the uplink switching port and the configured software and hardware resources of the PON port according to the management of the CPU unit; The CPU unit includes a first CPU core and at least one second CPU core, and the system configuration file includes a first configuration file for managing the logic unit and a second configuration file for configuring the second CPU core, wherein: The first CPU core is used to manage the logic unit and each second CPU core based on the first configuration file in the system configuration file / the configuration file sent by the management CPU; Each second CPU core is used to determine the allocated PON port based on the second configuration file in the system configuration file, and perform DBA calculation on each allocated PON port based on the management of the first CPU core.

2. The PONMAC chip according to claim 1, characterized in that: The logic unit includes a plurality of PON units corresponding to each PON port, each PON unit includes a service logic module and a configuration logic module, wherein: The business logic module is used to utilize the software and hardware resources of the configured PON port to perform business logic for data stream forwarding between the uplink switching port; The configuration logic module is used to implement the service logic management function of the CPU unit on each PON port.

3. The PONMAC chip according to claim 2, characterized in that: The configuration logic module includes: Physical layer operation management and maintenance PLOAM message buffer module, used for receiving and buffering PLOAM messages in the downstream and upstream directions of the PON port; The optical network unit manages and controls the OMCI message buffer module, which is used for receiving and buffering the downstream and upstream OMCI messages of the PON port; Configuration and status register module, used to implement the configuration and status query functions of the business logic functions of the PON port; An interrupt status module, configured to send an interrupt message to the CPU unit when determining that an interrupt event occurs in a service logic module of the corresponding PON port based on the value of the register corresponding to the PON port in the configuration and status register module; A dynamic bandwidth allocation DBA upstream traffic statistics module is used to implement a statistical function of the upstream traffic of each transmission container TCONT of the PON port in each DBA cycle, and provide the statistical results to the CPU unit; A DBA downstream data buffer module is used to receive downstream DBA data from the CPU unit to the PON port, and forward the data to the optical network unit ONU by the PON port; The upstream direction is from the PON port to the CPU unit, and the downstream direction is from the PON port to the ONU.

4. The PONMAC chip according to claim 2, characterized in that: The logical unit also includes a shared storage resource pool; The shared storage resource pool is used to store at least one of the following resources shared by all the multiple PON units: ONU resources, bandwidth scheduling AllocID resources and GEMPort resources, the minimum unit of data flow.

5. The PONMAC chip according to claim 1, characterized in that: The first CPU core comprises: The network port driver module is used to forward the configuration management message carrying the configuration file received from the management CPU through the management network port to the configuration management thread; A configuration management thread is used to receive the configuration management message, analyze the configuration management message to obtain a configuration file, wherein the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, send the local configuration information to the corresponding PON port module, and forward the overall configuration information to the device configuration thread; A plurality of PON port modules corresponding to each PON port, each of the PON port modules being used to receive the local configuration information and configure the corresponding PON unit in the logic unit according to the local configuration information; The device configuration thread is used to install the corresponding PON port module according to the first configuration file, initialize the configuration of the PON port module and the logic unit, create a DBA control data table in the second configuration file and send bandwidth configuration parameters to the corresponding second CPU cores, receive the overall configuration information, and update the system configuration file based on the overall configuration information, update the configuration of the corresponding PON port module and the logic unit and the DBA control data table, and send bandwidth configuration parameters to the corresponding second CPU cores.

6. The PONMAC chip according to claim 5, characterized in that: The first CPU core also includes: The register read and write interface module is used to implement the reading and writing of the configuration and status register modules in the corresponding PON unit by the PON port module and the device configuration thread.

7. The PONMAC chip according to claim 6, characterized in that: The first CPU core further includes: An interrupt processing module, used for receiving an interrupt message of the corresponding PON port sent by the logic unit, calling the register read-write interface module, reading the value of the register of the corresponding PON port in the configuration and status register module, and determining event information based on the value of the register, and sending the event information to the interrupt message distribution thread; The interrupt message distribution thread is used to forward the event information to a PON port module corresponding to the target PON port based on the target PON port corresponding to the event information.

8. The PONMAC chip according to any one of claims 5 to 7, characterized in that: The PON port module comprises: The PON port configuration thread is used to receive and process the local configuration information sent by the configuration management thread; OMCI protocol stack management thread, for building the OMCI business model of ONU, receiving and processing the OMCI event information sent by the interrupt message distribution thread, and processing the OMCI business configuration information for ONU in the local configuration information; An uplink port configuration thread, used for processing the uplink port configuration information in the local configuration information sent by the configuration management thread; The alarm processing thread is used to receive and process the alarm event information sent by the interrupt message distribution thread; The PLOAM message processing thread is used to receive and process the PLOAM event information sent by the interrupt message distribution thread.

9. The PONMAC chip according to claim 8, characterized in that: The PON port module also includes: The encryption key exchange thread is used to process the exchange and switching of the downstream encryption key of the corresponding PON port; PON port timer task module, used to complete the timing task of the PON port; The ONU timer task module is used to complete the corresponding ONU timing task according to the respective configuration of each ONU.

10. A resource reallocation method based on a PONMAC chip, characterized in that: include: Initialize and configure the logic unit through the CPU unit based on the configuration file preset in the system configuration file; Receiving, by the CPU unit, a configuration management message carrying a configuration file for resource reallocation sent by a management CPU in an OLT device or an MFU device, and reconfiguring the logical unit based on the configuration file; The CPU unit includes a first CPU core and at least one second CPU core, and the initialization configuration of the logic unit includes at least one of the following steps: Calling the register read-write interface module through the device configuration thread in the first CPU core, initializing the configuration and status register module of the PON unit in the logic unit based on the first configuration file preset in the system configuration file; Installing a corresponding PON port module based on the first configuration file through the device configuration thread, and initializing the configuration of the PON port module; The device configuration thread creates a DBA control data table in the second configuration file based on the second configuration file preset in the system configuration file, and sends bandwidth configuration parameters to the corresponding second CPU cores.

11. The method according to claim 10, characterized in that The CPU unit includes a first CPU core and at least one second CPU core, and the reconfiguring of the logic unit includes: Forwarding the configuration management message carrying the configuration file received from the management CPU to the configuration management thread through the network port driver module in the first CPU core; Receiving the configuration management message through the configuration management thread in the first CPU core, analyzing the configuration management message to obtain a configuration file, wherein the configuration file includes overall configuration information for all PON ports and local configuration information for some PON ports, sending the local configuration information to a target PON port module corresponding to the some PON ports, and forwarding the overall configuration information to the device configuration thread; Receiving the local configuration information through the target PON port module in the first CPU core, and reconfiguring the corresponding PON unit in the logic unit according to the local configuration information; The overall configuration information is received through the device configuration thread in the first CPU core, and the system configuration file is updated based on the overall configuration information, the corresponding PON port module and logic unit are configured, and the DBA control data table in the second configuration file of the system configuration file is updated and the bandwidth configuration parameters are sent to the corresponding second CPU cores.

12. The method according to claim 10, characterized in that The CPU unit includes a first CPU core and at least one second CPU core, and the method further includes: The second CPU core starts DBA calculation of the PON port based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the DBA control data table.

13. The method according to claim 12, characterized in that Also includes: The second CPU core performs DBA calculation of the PON port based on the bandwidth configuration parameters issued by the first CPU core and the DBA control data table in the second configuration file updated in the system configuration file, and sends the calculation result to the logic unit corresponding to the PON port and stores it in the updated DBA control data table.

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