Semiconductor device, power module, power conversion circuit, vehicle and method for manufacturing semiconductor device

Abstract

The present invention discloses a semiconductor device, a power module, a power conversion circuit, a vehicle and a method for preparing a semiconductor device. The semiconductor device comprises: a semiconductor body, a gate structure, located in the gate groove; a source structure, located in the source groove; a drain, located on the second surface; a source, located on the first surface, wherein a third surface of the source away from the drain is provided with a first groove, and the first groove extends from the third surface to the source; a passivation layer, located on the side of the source away from the drain, wherein at least part of the passivation layer is located in the first groove. The present invention provides a semiconductor device, a power module, a power conversion circuit, a vehicle and a method for preparing a semiconductor device, which improves the bonding force between the passivation layer and the source, avoids cracking, and improves the stability of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a power module, a power conversion circuit, a vehicle, and a method for manufacturing a semiconductor device. Background Art

[0002] Silicon carbide (SiC) has excellent physical and electrical properties. Currently, semiconductor devices made of SiC materials have the advantages of high current density and small cell pitch, and are widely used. However, in the packaging structure of semiconductor devices, due to the different thermal expansion coefficients between the passivation layer of the semiconductor device and the contacting metal layer, the stress at the contact position between the passivation layer and the contacting metal layer is different in an environment with repeated temperature changes, so the connection position is prone to cracking, causing water and oxygen intrusion, affecting the application reliability of semiconductor devices. Summary of the invention

[0003] The present invention provides a semiconductor device, a power module, a power conversion circuit, a vehicle and a method for preparing a semiconductor device, which improves the bonding force between a passivation layer and a source electrode, avoids cracking and improves the stability of the device.

[0004] An embodiment of the present invention provides a semiconductor device, including:

[0005] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench and the source trench both extending from the first surface into the semiconductor body;

[0006] A gate structure, located in the gate trench;

[0007] A source structure, located in the source trench;

[0008] a drain electrode, located on the second surface;

[0009] A source electrode is located on the first surface, wherein a first groove is provided on a third surface of the source electrode away from the drain electrode, and the first groove extends from the third surface to the source electrode;

[0010] A passivation layer is located on a side of the source electrode away from the drain electrode, wherein at least a portion of the passivation layer is located in the first trench.

[0011] Optionally, the source structure includes:

[0012] A first insulating layer, disposed on the bottom and sidewalls of the source trench;

[0013] At least a portion of the source is located in the source trench on a side of the first insulating layer away from the drain; an orthographic projection of the first trench on the drain overlaps with an orthographic projection of the source trench on the drain.

[0014] Optionally, the source structure further includes:

[0015] A trench source, located in the source trench between the first insulating layer and the source, a fourth surface of the trench source away from the drain is provided with a second trench, and the second trench extends from the fourth surface to the trench source;

[0016] At least a portion of the source is located in the second trench.

[0017] Optionally, the semiconductor device further includes:

[0018] An encapsulation layer, located on a side of the passivation layer away from the drain electrode;

[0019] A third groove is disposed on a surface of the passivation layer away from the drain electrode. The third groove extends from the surface of the passivation layer away from the drain electrode into the passivation layer. At least a portion of the encapsulation layer is located in the third groove.

[0020] In a second aspect, an embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0021] In a third aspect, an embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0022] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0023] In a fourth aspect, an embodiment of the present invention provides a vehicle, comprising a load and the power conversion circuit described in the embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0024] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0025] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench and the source trench both extending from the first surface into the semiconductor body;

[0026] forming a gate structure in the gate trench;

[0027] forming a source structure in the source trench;

[0028] forming a drain electrode on the second surface;

[0029] A source electrode is formed on the first surface, wherein a first groove is provided on a third surface of the source electrode away from the drain electrode, and the first groove extends from the third surface to the source electrode;

[0030] A passivation layer is formed on a side of the source electrode away from the drain electrode, wherein at least a portion of the passivation layer is located in the first trench.

[0031] Optionally, forming a source structure in the source trench includes:

[0032] forming a first insulating layer at the bottom and sidewalls of the source trench;

[0033] When the source is formed on the first surface, at least part of the source is formed in the source trench on the first insulating layer away from the drain; the orthographic projection of the first trench on the drain overlaps with the orthographic projection of the source trench on the drain.

[0034] Optionally, forming a source structure in the source trench includes:

[0035] forming a first insulating layer at the bottom and sidewalls of the source trench;

[0036] A trench source is formed in the source trench on the side of the first insulating layer away from the drain, a second trench is provided on the fourth surface of the trench source on the side away from the drain, and the second trench extends from the fourth surface to the trench source;

[0037] When the source is formed on the first surface, at least a portion of the source is formed in the second trench.

[0038] Optionally, the method for preparing a semiconductor device further includes:

[0039] When a passivation layer is formed on a side of the source electrode away from the drain electrode, a third groove is provided on a surface of the passivation layer away from the drain electrode, and the third groove extends from the surface of the passivation layer away from the drain electrode into the passivation layer;

[0040] A packaging layer is formed on a side of the passivation layer away from the drain electrode, and at least a portion of the packaging layer is located in the third trench.

[0041] The semiconductor device provided by the technical solution provided in the embodiment of the present invention includes: a semiconductor body, the semiconductor body includes a first surface and a second surface arranged oppositely, the semiconductor body also includes a well region and a first region, the first region is arranged on the first surface, and the well region is arranged on the side of the first region away from the first surface; the first surface is also provided with a gate groove and a source groove, and the gate groove and the source groove both extend from the first surface to the semiconductor body; the gate structure is located in the gate groove; the source structure is located in the source groove; the drain is located on the second surface; the source is located on the first surface, wherein the third surface on the side of the source away from the drain is provided with a first groove, and the first groove extends from the third surface to the source; the passivation layer is located on the side of the source away from the drain, wherein at least part of the passivation layer is located in the first groove, the passivation layer material contacts the source through the first groove, and the contact area between the passivation layer and the source is increased by using the first groove, thereby improving the bonding force between the passivation layer and the source material. And the space provided by the first groove is used to disperse and release the residual stress generated internally during the deposition process of the passivation layer, further improving the bonding stability and reliability between the passivation layer and the source. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment more quickly, thereby reducing local temperature rise and the occurrence of high-temperature deformation, thereby improving overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;

[0043] Figure 2 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0045] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 5 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0047] Figures 6 to 12Schematic diagram of the intermediate structure of the preparation process provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Figure 1 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 1 ,include:

[0050] The semiconductor body 100 includes a first surface and a second surface that are arranged opposite to each other. The semiconductor body 100 also includes a well region 10 and a first region 20. The first region 20 is arranged on the first surface, and the well region 10 is arranged on a side of the first region 20 away from the first surface. The first surface is also provided with a gate trench 40 and a source trench 30. Both the gate trench 40 and the source trench 30 extend from the first surface into the semiconductor body 100.

[0051] A gate structure, located in the gate trench 40;

[0052] A source structure, located in the source trench 30;

[0053] A drain electrode 110, located on the second surface;

[0054] The source electrode 120 is located on the first surface, wherein a first groove 121 is provided on a third surface of the source electrode 120 away from the drain electrode 110, and the first groove 121 extends from the third surface to the source electrode 120;

[0055] The passivation layer 130 is located on a side of the source electrode 120 away from the drain electrode 110 , wherein at least a portion of the passivation layer 130 is located in the first trench 121 .

[0056] Specifically, the semiconductor device in the embodiment of the present invention may be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET), and the semiconductor body 100 may include a substrate 50, an epitaxial layer 70, a well region 10, and a first region 20. The materials of the substrate 50 and the epitaxial layer 70 may be silicon carbide. The epitaxial layer 70 is formed on one side of the substrate 50. Exemplarily, the epitaxial layer 70 may be formed on the surface of the substrate 50 by epitaxial growth. A well region 10 is provided on the side of the epitaxial layer 70 away from the substrate 50, and a first region 20 is provided on the side of the well region 10 away from the substrate 50. The well region 10 and the first region 20 may be formed by epitaxial growth, ion implantation, or vapor deposition. The well region 10 and the first region 20 are used to form a conductive channel of the semiconductor device, wherein the first region 20 is of the first doping type, and the well region 10 is of the second doping type.

[0057] The first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the accompanying drawings indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, in the embodiment of the present invention, the first doping type is N-type doping, and the second doping type is P-type doping as an example. When the semiconductor device is an N-type device, the substrate is N+ type doped, for example, it may be an N+ silicon carbide substrate; the epitaxial layer 70 is N-type doped, for example, it may be an N-silicon carbide epitaxial layer 70; when the semiconductor device is a P-type device, the substrate is P+ type doped, and the epitaxial layer 70 is P-type doped.

[0058] A side surface of the first region 20 away from the substrate 50 is used as a first surface, and a gate trench 40 and a source trench 30 are formed on the first surface by an etching process, wherein the gate trench 40 and the source trench 30 can be formed by simultaneous etching in the same preparation process. In some other embodiments, the gate trench 40 and the source trench 30 can be set to different depths and shapes, and the gate trench 40 and the source trench 30 can be formed by etching separately. The gate trench 40 and the source trench 30 pass through the first region 20 and the well region 10, and extend from the first surface to the epitaxial layer 70. The source trench 30 is located on one side of the gate trench 40, and the source trench 30 can be an annular trench, which is set to a structure surrounding the gate trench 40. The source trench 30 can also be an independent trench, and a plurality of source trenches 30 are distributed on both sides of the gate trench 40. For example, Figure 1Source trenches 30 are arranged on both sides of the middle gate trench 40, and the two source trenches 30 can be arranged symmetrically or asymmetrically. In some embodiments, the semiconductor body 100 is further provided with a second region 60, and the second region 60 is arranged in the region extending into the semiconductor body 100 from the sidewall and / or bottom of the source trench 30. Exemplarily, the second region 60 can be formed by ion implantation. The doping type of the second region 60 is the same as the doping type of the well region 10, so a depletion region can be formed between the second region 60 and the epitaxial layer 70, which can play a role in shielding the electric field of the gate structure, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of device operation.

[0059] A gate structure is arranged in the gate trench 40. Exemplarily, the gate structure may include a second insulating layer 41 and a trench gate 42. The second insulating layer 41 is arranged on the inner wall and the bottom of the gate trench 40. The second insulating layer 41 may be a gate oxide layer. The gate oxide layer may be a high dielectric constant (K) material. The trench gate 42 may be polysilicon. The gate structure is arranged in the gate trench 40. The well regions 10 on both sides of the gate structure may form a vertical conductive channel, which may eliminate the junction field-effect transistor (JFET) region, thereby lowering the on-resistance of the semiconductor device.

[0060] A source structure is disposed in the source trench 30. Exemplarily, the source structure may include a first insulating layer 31 and a trench source 32. The first insulating layer 31 is disposed on the inner wall and bottom of the source trench 30. The trench source 32 may be polysilicon. The first insulating layer 31 in the source structure may be the same as the second insulating layer 41 in the gate structure. Therefore, during preparation, the first insulating layer 31 in the source structure and the second insulating layer 41 in the gate structure may be formed simultaneously. In some other embodiments, the trench source 32 may not be disposed in the source trench 30 or a portion of the trench source 32 may be disposed in the source trench 30.

[0061] A source electrode 120 is disposed on the first surface of the semiconductor body 100. Exemplarily, a third insulating layer 140 is further included between the source electrode 120 and the gate structure. The third insulating layer 140 may be an interlayer dielectric layer (ILD). The third insulating layer 140 covers the surface of the gate structure. The third insulating layer 140 isolates the gate structure from the source electrode 120. An ohmic contact metal layer 150 is disposed on the side of the third insulating layer 140 away from the gate structure. The ohmic contact metal layer 150 can significantly reduce the contact resistance of the source electrode 120, thereby improving the conductive efficiency of the device. The ohmic contact metal layer 150 may include metals such as nickel (Ni) or titanium (Ti).

[0062] Exemplarily, the source 120 can be formed by sputtering and the like, and the source 120 is a metal conductive layer, and the metal conductive layer can be titanium (Ti), nickel (Ni) or silver (Ag). The third surface of the source 120 away from the drain 110 is provided with a first groove 121, and the first groove 121 can be formed by an etching process. The passivation layer 130 is formed on the surface of the source 120, and at least part of the passivation layer 130 is located in the first groove 121. The passivation layer 130 material contacts the source 120 through the first groove 121, and the contact area between the passivation layer 130 and the source 120 is increased by the first groove 121, thereby improving the bonding force between the passivation layer 130 and the source 120 material. And the space provided by the first groove 121 is used to disperse and release the residual stress generated inside the passivation layer 130 during the deposition process, further improving the bonding stability and reliability between the passivation layer 130 and the source 120. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment more quickly, thereby reducing local temperature rise and the occurrence of high-temperature deformation, thereby improving the overall structural stability.

[0063] The semiconductor device provided by the technical solution provided in the embodiment of the present invention includes: a semiconductor body 100, the semiconductor body 100 includes a first surface and a second surface arranged opposite to each other, the semiconductor body 100 also includes a well region 10 and a first region 20, the first region 20 is arranged on the first surface, and the well region 10 is arranged on a side of the first region 20 away from the first surface; the first surface is also provided with a gate trench 40 and a source trench 30, the gate trench 40 and the source trench 30 both extend from the first surface to the semiconductor body 100; the gate structure is located in the gate trench 40; the source structure is located in the source trench 30; the drain 110 The source 120 is located on the first surface, wherein the third surface of the source 120 away from the drain 110 is provided with a first groove 121, and the first groove 121 extends from the third surface to the source 120; the passivation layer 130 is located on the side of the source 120 away from the drain 110, wherein at least part of the passivation layer 130 is located in the first groove 121, and the passivation layer 130 material contacts the source 120 through the first groove 121, and the contact area between the passivation layer 130 and the source 120 is increased by using the first groove 121, thereby improving the bonding force between the passivation layer 130 and the source 120 material. And the space provided by the first groove 121 is used to disperse and release the residual stress generated inside the passivation layer 130 during the deposition process, further improving the bonding stability and reliability between the passivation layer 130 and the source 120. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment more quickly, thereby reducing local temperature rise and the occurrence of high-temperature deformation, thereby improving overall performance.

[0064] As an optional embodiment, Figure 2 A schematic diagram of a semiconductor device is provided for an embodiment of the present invention. Figure 2 , the source structure includes: a first insulating layer 31, arranged on the bottom and sidewalls of the source trench 30;

[0065] At least part of the source 120 is located in the source trench 30 on the side of the first insulating layer 31 away from the drain 110 ; the orthographic projection of the first trench 121 on the drain 110 overlaps with the orthographic projection of the source trench 30 on the drain 110 .

[0066] Specifically, a source structure is provided in the source trench 30, and the source structure includes a first insulating layer 31, and the first insulating layer 31 is provided on the inner wall and the bottom of the source trench 30, and no trench source 32 is provided in the source trench 30. Exemplarily, in the preparation process, after the source trench 30 and the gate trench 40 are formed on the first surface, and the first insulating layer 31 is prepared, polysilicon can be deposited, and then the entire surface of the polysilicon is etched back to fill the gate trench 40 with polysilicon to form a trench gate, and a third insulating layer 140 is formed on the surface of the gate structure, and the third insulating layer 140 is used to protect the polysilicon in the gate trench 40, and then the etching is continued to remove the polysilicon in the source trench 30.

[0067] When the source electrode 120 is deposited on the first surface, at least part of the source electrode 120 is formed in the source groove 30 on the side of the first insulating layer 31 away from the drain electrode 110, that is, the source groove 30 on the side of the first insulating layer 31 away from the drain electrode 110 is used as a receiving space, and the source electrode 120 will collapse with a groove morphology at a position corresponding to the surface away from the drain electrode 110, and the first groove 121 is naturally formed. In other words, the orthographic projection of the first groove 121 on the drain electrode 110 overlaps with the orthographic projection of the source groove 30 on the drain electrode 110, so in the preparation process, there is no need to form the first groove 121 separately, and the first groove 121 can be obtained by using the structure of the source groove 30 itself, thereby simplifying the process.

[0068] It should be noted that the first groove 121 may be a U-shaped groove, a V-shaped groove or a groove of other shapes, and the first groove 121 may be used to increase the contact area between the passivation layer 130 and the source 120. The source groove 30 may also be a U-shaped groove, a V-shaped groove or a groove of other shapes. Figure 1 , illustratively, the source trench 30 is a U-shaped trench, and the gate trench 40 can also be a U-shaped trench. Figure 2 For example, the source groove 30 adopts a V-shaped groove, and the gate groove 40 can be etched separately as a U-shaped groove according to product requirements or adopt the same V-shaped groove as the source groove 30, or grooves of other shapes, without specific limitation herein.

[0069] As an optional embodiment, Figure 3 A schematic diagram of a semiconductor device is provided for an embodiment of the present invention. Figure 3 , the source structure also includes:

[0070] The trench source 32 is located in the source trench 30 between the first insulating layer 31 and the source 120 . A second trench 33 is provided on the fourth surface of the trench source 32 away from the drain 110 . The second trench 33 extends from the fourth surface to the trench source 32 . At least part of the source 120 is located in the second trench 33 .

[0071] Specifically, compared with Figure 2 , the difference of the embodiment of the present invention is that the first insulating layer 31 and the trench source 32 are provided in the trench source 32, and the fourth surface of the trench source 32 has a second trench 33, so part of the source 120 will be formed in the second trench 33. Exemplarily, in the preparation process, after the source trench 30 and the gate trench 40 are formed on the first surface, and the first insulating layer 31 is prepared, polysilicon can be deposited, and then the entire surface of the polysilicon is etched back to fill the gate trench 40 with polysilicon to form a trench gate 42, and a third insulating layer 140 is formed on the surface of the gate structure, and the third insulating layer 140 is used to protect the polysilicon in the gate trench 40, and then the etching is continued to form the second trench 33 on the fourth surface of the source trench 30, that is, the polysilicon in the source trench 30 is partially removed to form the second trench 33.

[0072] When the source electrode 120 is deposited on the first surface, at least part of the source electrode 120 is formed in the second groove 33, and the corresponding position of the surface of the source electrode 120 away from the drain electrode 110 will have a groove morphology to naturally form the first groove 121. In other words, the orthographic projection of the first groove 121 on the drain electrode 110 overlaps with the orthographic projection of the source groove 30 on the drain electrode 110, so in the preparation process, there is no need to form the first groove 121 separately, and the first groove 121 can be obtained by using the structure of the source groove 30 itself, thereby simplifying the process.

[0073] Combination Figure 1-Figure 3 , the semiconductor device further includes: an encapsulation layer 160 , located on a side of the passivation layer 130 away from the drain 110 ;

[0074] A third trench 131 is disposed on a surface of the passivation layer 130 away from the drain 110 . The third trench 131 extends from the surface of the passivation layer 130 away from the drain 110 into the passivation layer 130 . At least a portion of the encapsulation layer 160 is located in the third trench 131 .

[0075] Specifically, the passivation layer 130 is formed on the surface of the source electrode 120, at least part of the passivation layer 130 is located in the first groove 121, and the position of the passivation layer 130 corresponding to the surface away from the drain electrode 110 will have a groove morphology to naturally form the third groove 131. Similarly, part of the encapsulation layer 160 is located in the third groove 131, and the encapsulation layer 160 material contacts the passivation layer 130 through the third groove 131. The third groove 131 is used to increase the contact area between the encapsulation layer 160 and the passivation layer 130, thereby improving the bonding force between the encapsulation layer 160 and the passivation layer 130. In addition, the space provided by the third groove 131 is used to disperse and release the residual stress generated internally during the formation of the encapsulation layer 160, further improving the bonding stability and reliability between the encapsulation layer 160 and the passivation layer 130. The orthographic projection of the third groove 131 on the drain 110 overlaps with the orthographic projection of the source groove 30 on the drain 110. That is to say, the upper structure of the source 120 away from the drain 110 can form corresponding grooves through morphology without separate setting, thereby simplifying the process.

[0076] An embodiment of the present invention provides a power module based on the above embodiment, including a substrate and a semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0077] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0078] An embodiment of the present invention provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0079] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0080] An embodiment of the present invention provides a vehicle based on the above embodiment, including a load and a power conversion circuit as in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0081] An embodiment of the present invention provides a method for preparing a semiconductor device based on the above embodiment. Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, combined with Figure 1-3 ,refer to Figure 4 , the preparation method comprises:

[0082] S110, providing a semiconductor body 100, the semiconductor body 100 comprising a first surface and a second surface arranged opposite to each other, the semiconductor body 100 further comprising a well region 10 and a first region 20, the first region 20 being arranged on the first surface, the well region 10 being arranged on a side of the first region 20 away from the first surface; the first surface is further provided with a gate trench 40 and a source trench 30, both of which extend from the first surface into the semiconductor body 100;

[0083] Among them, the semiconductor device in the embodiment of the present invention may be a silicon carbide trench metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), and the first doping type in the embodiment of the present invention may be N-type doping, and the second doping type may be P-type doping, or the first doping type may be P-type doping, and the second doping type may be N-type doping. P+ and N+ shown in the figure indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doping ions may be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions may be Al (aluminum) ions or B (boron) ions. Exemplarily, the embodiment of the present invention takes the first doping type as N-type doping and the second doping type as P-type doping as an example. When the semiconductor device is an N-type device, the substrate 50 is N+ type doped, for example, it may be an N+ silicon carbide substrate 50; the epitaxial layer 70 is N-type doped, for example, it may be an N-silicon carbide epitaxial layer 70; when the semiconductor device is a P-type device, the substrate 50 is P+ type doped, and the epitaxial layer 70 is P-type doped.

[0084] Specifically, the semiconductor body 100 may include a substrate 50, an epitaxial layer 70, a well region 10 and a first region 20. The materials of the substrate 50 and the epitaxial layer 70 may be silicon carbide. The epitaxial layer 70 is formed on one side of the substrate 50. Exemplarily, the epitaxial layer 70 may be formed on the surface of the substrate 50 by epitaxial growth. A well region 10 is provided on the side of the epitaxial layer 70 away from the substrate 50. A first region 20 is provided on the side of the well region 10 away from the substrate 50. The well region 10 and the first region 20 may be formed by epitaxial growth, ion implantation or vapor deposition. The well region 10 and the first region 20 are used to form a conductive channel of a semiconductor device, wherein the first region 20 is of a first doping type and the well region 10 is of a second doping type.

[0085] A side surface of the first region 20 away from the substrate 50 is used as a first surface, and a gate trench 40 and a source trench 30 are formed on the first surface by an etching process, wherein the gate trench 40 and the source trench 30 can be formed by simultaneous etching in the same preparation process. In some other embodiments, the gate trench 40 and the source trench 30 can be set to different depths and shapes, so the gate trench 40 and the source trench 30 can be formed by etching separately. The gate trench 40 and the source trench 30 pass through the first region 20 and the well region 10, and extend from the first surface to the epitaxial layer 70. The source trench 30 is located on one side of the gate trench 40, and the source trench 30 can be an annular trench, which is set to a structure surrounding the gate trench 40. The source trench 30 can also be an independent trench, and a plurality of source trenches 30 are distributed on both sides of the gate trench 40. For example, see Figure 1 , source trenches 30 are arranged on both sides of the gate trench 40, and the two source trenches 30 can be arranged symmetrically or asymmetrically. In some embodiments, the semiconductor body 100 is further provided with a second region 60, and the second region 60 is arranged in the region extending into the semiconductor body 100 from the sidewall and / or bottom of the source trench 30. Exemplarily, the second region 60 can be formed by ion implantation. The doping type of the second region 60 is the same as the doping type of the well region 10, so a depletion region can be formed between the second region 60 and the epitaxial layer 70, which can play a role in shielding the electric field of the gate structure, thereby improving the problem of gate oxide layer breakdown and ensuring the reliability of device operation.

[0086] S120, forming a gate structure in the gate trench 40;

[0087] A gate structure is provided in the gate trench 40. Exemplarily, the gate structure may include a second insulating layer 41 and a trench gate 42. The trench gate 42 may be polysilicon. The second insulating layer 41 is deposited on the inner wall and bottom of the gate trench 40 by atomic layer deposition (ALD) or the like. The second insulating layer 41 in the gate trench 40 may be a gate oxide layer. The gate oxide layer may be a high-K material, which may improve the electron mobility at the interface of the trench gate 42 and reduce the on-resistance of the device. The trench gate 42 is deposited by low pressure chemical vapor deposition (LPCVD) or the like. The material of the trench gate 42 may be polysilicon.

[0088] S130, forming a source structure in the source trench 30;

[0089] Specifically, a source structure is provided in the source trench 30. Exemplarily, the source structure may include a first insulating layer 31 and a trench source 32. While forming the second insulating layer 41, the first insulating layer 31 may be deposited on the inner wall and bottom of the source trench 30 by the same process. That is, the first insulating layer 31 and the second insulating layer 41 are formed in the same layer. The trench source 32 may be formed simultaneously with the trench gate 42 by the deposition process. In some other embodiments, the source structure may include only the first insulating layer 31, that is, the trench source 32 may not be provided in the source trench 30.

[0090] S140, forming a drain electrode 110 on the second surface;

[0091] Specifically, the drain electrode 110 may be formed on the side of the substrate 50 away from the epitaxial layer 70 by sputtering or the like, wherein the surface of the substrate 50 away from the epitaxial layer 70 is first thinned, and then the drain electrode 110 is formed by sputtering or the like. The drain electrode 110 is a metal conductive layer, and illustratively, the metal conductive layer may be titanium (Ti), nickel (Ni) or silver (Ag).

[0092] S150, forming a source electrode 120 on the first surface, wherein a first trench 121 is provided on a third surface of the source electrode 120 away from the drain electrode 110, and the first trench 121 extends from the third surface into the source electrode 120;

[0093] Specifically, a source electrode 120 is formed on the first surface of the semiconductor body 100. For example, the source electrode 120 can be formed by sputtering or the like. The source electrode 120 is a metal conductive layer, and the metal conductive layer can be titanium (Ti), nickel (Ni) or silver (Ag). A first groove 121 is provided on the third surface of the source electrode 120 away from the drain electrode 110. For example, the first groove 121 can be formed by an etching process.

[0094] S160 , forming a passivation layer 130 on a side of the source electrode 120 away from the drain electrode 110 , wherein at least a portion of the passivation layer 130 is located in the first trench 121 .

[0095] Specifically, the passivation layer 130 is formed on the surface of the source 120, and at least part of the passivation layer 130 is located in the first groove 121. The material of the passivation layer 130 contacts the source 120 through the first groove 121. The contact area between the passivation layer 130 and the source 120 is increased by using the first groove 121, thereby improving the bonding force between the passivation layer 130 and the source 120 material. And the space provided by the first groove 121 is used to disperse and release the residual stress generated internally during the deposition process of the passivation layer 130, further improving the bonding stability and reliability between the passivation layer 130 and the source 120. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment faster, thereby reducing local temperature rise and reducing the occurrence of high-temperature deformation, thereby improving the overall performance.

[0096] The technical solution provided in the embodiment of the present invention includes providing a semiconductor body 100, the semiconductor body 100 includes a first surface and a second surface arranged opposite to each other, the semiconductor body 100 also includes a well region 10 and a first region 20, the first region 20 is arranged on the first surface, and the well region 10 is arranged on the side of the first region 20 away from the first surface; the first surface is also provided with a gate trench 40 and a source trench 30, and the gate trench 40 and the source trench 30 both extend from the first surface to the semiconductor body 100; a gate structure is formed in the gate trench 40; a source structure is formed in the source trench 30; a drain 110 is formed on the second surface; a source 120 is formed on the first surface, wherein a first trench 121 is provided on the third surface of the source 120 away from the drain 110, and the first trench 121 extends from the third surface to the source 120; a passivation layer 130 is formed on the side of the source 120 away from the drain 110, wherein at least part of the passivation layer 130 is located in the first trench 121. The material of the passivation layer 130 contacts the source electrode 120 through the first groove 121, and the contact area between the passivation layer 130 and the source electrode 120 is increased by using the first groove 121, thereby improving the bonding force between the passivation layer 130 and the source electrode 120 material. In addition, the space provided by the first groove 121 is used to disperse and release the residual stress generated internally during the deposition process of the passivation layer 130, further improving the bonding stability and reliability between the passivation layer 130 and the source electrode 120. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment faster, thereby reducing local temperature rise and reducing the occurrence of high-temperature deformation, thereby improving the overall performance.

[0097] As an optional embodiment, when forming the source structure in the source trench 30 , the first insulating layer 31 is formed only on the bottom and sidewalls of the source trench 30 ;

[0098] Specifically, the first insulating layer 31 of the source structure and the second insulating layer 41 of the gate structure can be formed in the same layer by the same process, and the first insulating layer 31 is deposited on the inner wall and bottom of the source trench 30. After the first insulating layer 31 is formed, polysilicon can be deposited and then the entire surface of the polysilicon is etched back to fill the gate trench 40 with polysilicon to form a trench gate 42. At this time, the source trench 30 is also filled with polysilicon. A third insulating layer 140 is formed on the surface of the gate structure, and the third insulating layer 140 is used to protect the polysilicon in the gate trench 40, and then the etching is continued to remove all the polysilicon in the source trench 30.

[0099] When the source 120 is formed on the first surface by sputtering or other methods, at least part of the source 120 is formed in the source groove 30 on the side of the first insulating layer 31 away from the drain 110, and the corresponding position of the surface of the source 120 away from the drain 110 will have a groove morphology to naturally form the first groove 121. In other words, the orthographic projection of the first groove 121 on the drain 110 overlaps with the orthographic projection of the source groove 30 on the drain 110, so in the preparation process, there is no need to form the first groove 121 separately, and the first groove 121 can be obtained by using the structure of the source groove 30 itself, thereby simplifying the process.

[0100] As an optional embodiment, after forming the first insulating layer 31, polysilicon can be deposited and then the entire surface of the polysilicon is etched back to fill the gate trench 40 with polysilicon to form a trench gate 42, and at this time, the source trench 30 is also filled with polysilicon. A third insulating layer 140 is formed on the surface of the gate structure, and the third insulating layer 140 is used to protect the polysilicon in the gate trench 40, and then the etching is continued to remove part of the polysilicon in the source trench 30, and a second trench 33 is formed on the fourth surface of the source trench 30 away from the drain 110.

[0101] When the source electrode 120 is deposited on the first surface, at least part of the source electrode 120 is formed in the second groove 33, and the corresponding position of the surface of the source electrode 120 away from the drain electrode 110 will have a groove morphology to naturally form the first groove 121. In other words, the orthographic projection of the first groove 121 on the drain electrode 110 overlaps with the orthographic projection of the second groove 33 on the drain electrode 110. Therefore, in the preparation process, there is no need to form the first groove 121 separately, and the first groove 121 can be obtained by using the structure of the source groove 30 itself, thereby simplifying the process.

[0102] Optionally, the method for preparing a semiconductor device further includes:

[0103] When the passivation layer 130 is formed on the side of the source electrode 120 away from the drain electrode 110, a third groove 131 is provided on the surface of the passivation layer 130 away from the drain electrode 110, and the third groove 131 extends from the surface of the passivation layer 130 away from the drain electrode 110 to the passivation layer 130;

[0104] An encapsulation layer 160 is formed on a side of the passivation layer 130 away from the drain electrode 110 , and at least a portion of the encapsulation layer 160 is located in the third trench 131 .

[0105] Specifically, the passivation layer 130 is formed on the surface of the source electrode 120, at least part of the passivation layer 130 is located in the first groove 121, and the position of the passivation layer 130 corresponding to the surface away from the drain electrode 110 will have a groove morphology to naturally form the third groove 131. Similarly, part of the encapsulation layer 160 is located in the third groove 131, and the encapsulation layer 160 material contacts the passivation layer 130 through the third groove 131. The third groove 131 is used to increase the contact area between the encapsulation layer 160 and the passivation layer 130, thereby improving the bonding force between the encapsulation layer 160 and the passivation layer 130. In addition, the space provided by the third groove 131 is used to disperse and release the residual stress generated internally during the formation of the encapsulation layer 160, further improving the bonding stability and reliability between the encapsulation layer 160 and the passivation layer 130. The orthographic projection of the third groove 131 on the drain 110 overlaps with the orthographic projection of the source groove 30 on the drain 110. That is to say, the upper structure of the source 120 away from the drain 110 can form corresponding grooves through morphology without separate setting, thereby simplifying the process.

[0106] The embodiment of the present invention is Figure 2 Taking the semiconductor device structure in as an example, a method for preparing a semiconductor device is introduced. Figure 5 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figures 6 to 12 is a schematic diagram of an intermediate structure of a preparation process provided by an embodiment of the present invention, and the preparation method comprises:

[0107] S210, forming an epitaxial layer 70 on one side of the substrate 50;

[0108] In the embodiment of the present invention, the first doping type is N-type doping and the second doping type is P-type doping. When the semiconductor device is an N-type device, the substrate 50 is N+ type doping, for example, it can be an N+ silicon carbide substrate 50; the epitaxial layer 70 is N-type doping, for example, it can be an N-silicon carbide epitaxial layer 70; when the semiconductor device is a P-type device, the substrate 50 is P+ type doping, and the epitaxial layer 70 is P-type doping. The structure is as follows: Figure 6 shown.

[0109] S220, forming a well region 10 on a side of the epitaxial layer 70 away from the substrate 50; forming a first region 20 on a side of the well region 10 away from the substrate 50;

[0110] The well region 10 and the first region 20 are used to form a conductive channel of the semiconductor device. The well region 10 and the first region 20 can be formed by epitaxial growth, ion implantation or vapor deposition, and the structure is as follows: Figure 7 shown.

[0111] S230 , the surface of the first region 20 away from the substrate 50 is used as the first surface, and a gate trench 40 and a source trench 30 are formed on the first surface respectively. The gate trench 40 and the source trench 30 both extend from the first surface into the epitaxial layer 70 .

[0112] Specifically, the gate trench 40 and the source trench 30 can be set to different depths and shapes. The gate trench 40 and the source trench 30 are formed by etching in different steps during different preparation processes. The gate trench 40 and the source trench 30 pass through the first region 20 and the well region 10 and extend from the first surface to the epitaxial layer 70. Its structure is as follows Figure 8 shown.

[0113] S240, forming a second region 60 on the sidewall and / or bottom of the source trench 30;

[0114] The second region 60 is formed on the sidewall and / or bottom of the source trench 30 by ion implantation. The first region 2040 is of the first doping type, and the well region 10 and the second region 60 are of the second doping type; the structure is as follows Fig. 9 shown.

[0115] S250, forming a gate structure in the gate trench 40, and forming a source structure in the source trench 30;

[0116] Specifically, the gate structure and the source structure are correspondingly arranged in the gate trench 40 and the source trench 30. The gate structure may include a second insulating layer 41 and a trench gate 42, and the second insulating layer 41 is arranged on the inner wall and the bottom of the gate trench 40. The source structure may include a first insulating layer 31 and a trench source 32, and the first insulating layer 31 is arranged on the inner wall and the bottom of the source trench 30. During preparation, the first insulating layer 31 in the source structure and the second insulating layer 41 in the gate structure may be formed simultaneously by a thermal oxidation process. After forming the first insulating layer 31, polysilicon may be deposited and then the entire surface of the polysilicon may be backetched to fill the gate trench 40 with polysilicon to form a trench gate 42. At this time, the source trench 30 is also filled with polysilicon. Its structure is as follows Fig.10 shown.

[0117] S260, forming a third insulating layer 140 on the surface of the gate structure, using the third insulating layer 140 to protect the polysilicon in the gate trench 40, and then continuing to etch back to completely remove the polysilicon in the source trench 30. Fig.11 shown.

[0118] S270, forming an ohmic contact metal layer 150 on a side of the third insulating layer 140 away from the gate structure, and forming a source electrode 120 on a side of the ohmic contact metal layer 150 away from the gate structure;

[0119] Specifically, the third insulating layer 140 covers the surface of the gate structure, exposing the ohmic contact area, and an ohmic contact metal layer 150 is formed by sputtering and other methods. A source 120 is formed on the surface of the ohmic contact metal layer 150. The source 120 is a metal conductive layer, and the metal conductive layer can be titanium (Ti), nickel (Ni) or silver (Ag). At least part of the source 120 is formed in the source groove. The surface of the source 120 away from the drain 110 corresponds to the position of the source groove, and will have a groove morphology to naturally form the first groove 121. In other words, the orthographic projection of the first groove 121 on the drain 110 overlaps with the orthographic projection of the source groove on the drain 110. Therefore, in the preparation process, there is no need to form the first groove 121 separately. The first groove 121 can be obtained on the basis of the source groove, thereby simplifying the process. Its structure is as follows Fig.12 shown.

[0120] S280, forming a passivation layer 130, an encapsulation layer 160 and a drain electrode 110 on the other side of the substrate 50. The structure is as follows Figure 2 shown.

[0121] Specifically, the passivation layer 130 is formed on the surface of the source 120, and at least part of the passivation layer 130 is located in the first groove 121. The material of the passivation layer 130 contacts the source 120 through the first groove 121. The contact area between the passivation layer 130 and the source 120 is increased by using the first groove 121, thereby improving the bonding force between the passivation layer 130 and the source 120 material. And the space provided by the first groove 121 is used to disperse and release the residual stress generated internally during the deposition process of the passivation layer 130, further improving the bonding stability and reliability between the passivation layer 130 and the source 120. Furthermore, by increasing the surface area, the efficiency of heat conduction and heat radiation is effectively improved. Heat can be transferred from the heat source to the surrounding environment faster, thereby reducing local temperature rise and reducing the occurrence of high-temperature deformation, thereby improving the overall performance.

[0122] Due to the existence of the first groove 121, at least part of the passivation layer 130 is located in the first groove 121, and the corresponding position of the surface of the passivation layer 130 away from the drain 110 will have a groove morphology to naturally form the third groove 131. Similarly, part of the encapsulation layer 160 is located in the third groove 131, and the material of the encapsulation layer 160 contacts the passivation layer 130 through the third groove 131. The contact area between the encapsulation layer 160 and the passivation layer 130 is increased by the third groove 131, thereby improving the bonding force between the encapsulation layer 160 and the passivation layer 130. In addition, the space provided by the third groove 131 is used to disperse and release the residual stress generated internally during the formation of the encapsulation layer 160, further improving the bonding stability and reliability between the encapsulation layer 160 and the passivation layer 130. The orthographic projection of the third groove 131 on the drain 110 overlaps with the orthographic projection of the source groove 30 on the drain 110. That is to say, the upper structure of the source 120 away from the drain 110 can form corresponding grooves through morphology without separate setting, thereby simplifying the process.

[0123] The drain electrode 110 may be formed on the side of the substrate 50 away from the epitaxial layer 70 by sputtering or the like, wherein the surface of the substrate 50 away from the epitaxial layer 70 is first thinned, and then the drain electrode 110 is formed by sputtering or the like. The drain electrode 110 is a metal conductive layer, and illustratively, the metal conductive layer may be titanium (Ti), nickel (Ni) or silver (Ag).

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench and the source trench both extending from the first surface into the semiconductor body; A gate structure, located in the gate trench; A source structure, located in the source trench; a drain electrode, located on the second surface; A source electrode is located on the first surface, wherein a first groove is provided on a third surface of the source electrode away from the drain electrode, and the first groove extends from the third surface to the source electrode; a passivation layer, located on a side of the source electrode away from the drain electrode, wherein at least a portion of the passivation layer is located in the first trench; Wherein, the source structure comprises: A first insulating layer, disposed on the bottom and sidewalls of the source trench; At least a portion of the source is located in the source trench on a side of the first insulating layer away from the drain; an orthographic projection of the first trench on the drain overlaps with an orthographic projection of the source trench on the drain.

2. The semiconductor device according to claim 1, wherein: The source structure further includes: A trench source, located in the source trench between the first insulating layer and the source, a fourth surface of the trench source away from the drain is provided with a second trench, and the second trench extends from the fourth surface to the trench source; At least a portion of the source is located in the second trench.

3. The semiconductor device according to any one of claims 1 to 2, characterized in that: Also includes: An encapsulation layer, located on a side of the passivation layer away from the drain electrode; A third groove is disposed on a surface of the passivation layer away from the drain electrode. The third groove extends from the surface of the passivation layer away from the drain electrode into the passivation layer. At least a portion of the encapsulation layer is located in the third groove.

4. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 3, wherein the substrate is used to carry the semiconductor device.

5. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is electrically connected to the circuit board.

6. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 5, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

7. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being arranged on the first surface, the well region being arranged on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench and the source trench both extending from the first surface into the semiconductor body; forming a gate structure in the gate trench; forming a source structure in the source trench; forming a drain electrode on the second surface; A source electrode is formed on the first surface, wherein a first groove is provided on a third surface of the source electrode away from the drain electrode, and the first groove extends from the third surface to the source electrode; forming a passivation layer on a side of the source electrode away from the drain electrode, wherein at least a portion of the passivation layer is located in the first trench; A source structure is formed in the source trench, comprising: forming a first insulating layer at the bottom and sidewalls of the source trench; When the source is formed on the first surface, at least part of the source is formed in the source trench on the first insulating layer away from the drain; the orthographic projection of the first trench on the drain overlaps with the orthographic projection of the source trench on the drain.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: A source structure is formed in the source trench, comprising: forming a first insulating layer at the bottom and sidewalls of the source trench; A trench source is formed in the source trench on the side of the first insulating layer away from the drain, a second trench is provided on the fourth surface of the trench source on the side away from the drain, and the second trench extends from the fourth surface to the trench source; When the source is formed on the first surface, at least a portion of the source is formed in the second trench.

9. The method for preparing a semiconductor device according to any one of claims 7 to 8, characterized in that: Also includes: When a passivation layer is formed on a side of the source electrode away from the drain electrode, a third groove is provided on a surface of the passivation layer away from the drain electrode, and the third groove extends from the surface of the passivation layer away from the drain electrode into the passivation layer; A packaging layer is formed on a side of the passivation layer away from the drain electrode, and at least a portion of the packaging layer is located in the third trench.

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