Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a substrate, the substrate comprises a display area and a non-display area at least partially surrounding the display area, and the non-display area on at least one side of the display area comprises a first frame area, a bending area and a bonding area which are sequentially away from the display area; the bending area comprises a middle area and arc angle areas located at the two ends of the middle area. The demultiplexing circuit is arranged in the first frame area; and the demultiplexing signal line is electrically connected with the demultiplexing circuit, and the orthographic projection of the demultiplexing signal line on the substrate is not overlapped with the arc angle area. According to the display panel provided by the invention, the demultiplexing signal line does not pass through the arc angle area, so that the frame width of the arc angle area is reduced, and a narrow frame of a product is realized; and meanwhile, other wires in the arc angle area do not need to be compressed, so that the yield and the performance of the product are ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with traditional LCD (Liquid Crystal Display) display technology, OLED (Organic Light-Emitting Diode) has the advantages of active luminescence, light weight, fast response speed, good stability, low driving voltage, and high contrast, so it is widely used in display panels.

[0003] However, the performance of existing display panels needs to be improved. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a display panel that achieves a narrow frame while ensuring performance.

[0005] Based on the above purpose, the present application provides a display panel, which includes:

[0006] A substrate, comprising a display area and a non-display area at least partially surrounding the display area, wherein the non-display area on at least one side of the display area comprises a first frame area, a bending area and a bonding area sequentially arranged away from the display area, and the bending area comprises a middle area and arc angle areas located at both ends of the middle area;

[0007] A demultiplexing circuit is arranged in the first border area;

[0008] A demultiplexing signal line has one end electrically connected to the driving module and the other end electrically connected to the demultiplexing circuit, and an orthographic projection of the demultiplexing signal line on the substrate does not overlap with the arc angle area.

[0009] In one embodiment, the demultiplexed signal line includes a first routing segment and a second routing segment, the first routing segment is located in the bonding area, and the second routing segment is located in the middle area.

[0010] In one embodiment, the display panel further includes:

[0011] a first power line, at least partially located in the bonding area;

[0012] In the bonding area, an orthographic projection of the first routing segment on the substrate does not overlap with an orthographic projection of the first power line on the substrate.

[0013] In one embodiment, the display panel further includes:

[0014] a second power line, wherein at least a portion of the second power line is located in the bending area;

[0015] The orthographic projection of the second wiring segment on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate;

[0016] Preferably, the second power line extends along a first direction, the second routing segment extends along a second direction, and the first direction intersects the second direction.

[0017] In one embodiment, the second power line and the second wiring segment are in different layers.

[0018] In one embodiment, the display panel further includes:

[0019] A first conductor layer, located on one side of the substrate;

[0020] A second conductor layer is located on a side of the first conductor layer away from the substrate;

[0021] The second routing segment is located in the first conductor layer and / or the second conductor layer;

[0022] Preferably, when the second routing segment is partially located in the first conductor layer and partially located in the second conductor layer, the second routing segment in the first conductor layer is connected in parallel with the second routing segment in the second conductor layer;

[0023] Preferably, the display panel further includes:

[0024] a third conductor layer, located on a side of the second conductor layer away from the substrate;

[0025] The second power line is located in the third conductor layer;

[0026] Preferably, the first routing segment is located in the third conductor layer.

[0027] In one embodiment, the display panel further includes:

[0028] A data line, wherein the data line and the first power line are at least partially located in the bending area;

[0029] In the bending area, the orthographic projection of the second routing segment on the substrate does not overlap with the orthographic projections of the data line and the first power line on the substrate, and the orthographic projection of the second routing segment on the substrate is located between the orthographic projections of the data line and the first power line on the substrate.

[0030] In one embodiment, the display panel further includes:

[0031] A first conductor layer, located on one side of the substrate;

[0032] A second conductor layer is located on a side of the first conductor layer away from the substrate;

[0033] a third conductor layer, located on a side of the second conductor layer away from the substrate;

[0034] In the bending area, the data line is at least partially located in the first conductor layer, at least partially located in the second conductor layer, and the first power line is located in the third conductor layer;

[0035] Preferably, in the bending area, the second routing segment is located in the third conductor layer.

[0036] In one embodiment, the display panel further includes:

[0037] a gate drive circuit, wherein the gate drive circuit is at least partially located in the arc angle region;

[0038] Preferably, the display panel further includes:

[0039] A data line, wherein the data line is at least partially located in the arc corner area.

[0040] Based on the same inventive concept, the present application also provides a display device, which includes the display panel as described above.

[0041] Compared with the prior art, the present application provides a display panel in which the orthographic projection of the demultiplexed signal line on the substrate does not overlap with the arc corner area, that is, the demultiplexed signal line does not pass through the arc corner area, which is beneficial to reducing the border width of the arc corner area, thereby achieving a narrow border of the product; at the same time, there is no need to compress other lines in the arc corner area, thereby ensuring the yield and performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic diagram of a related display panel;

[0044] Figure 2 is a schematic diagram of a partial structure of an existing display panel;

[0045] Figure 3 is a schematic diagram of a display panel in an embodiment of the present application;

[0046] Figure 4is a schematic diagram of the layer structure of a display panel in an embodiment of the present application;

[0047] Figure 5 is a schematic diagram of a partial structure of a display panel in an embodiment of the present application;

[0048] Figure 6 It is a schematic structural diagram of a bending area and a first frame area of ​​a display panel in an embodiment of the present application;

[0049] Figure 7 is a schematic diagram of a layer structure of a display panel in another embodiment of the present application;

[0050] Figure 8 is a schematic diagram of a partial structure of a display panel in another embodiment of the present application;

[0051] Fig. 9 Schematic diagram of the structure of the bending area and the first border area of ​​the display panel in another embodiment of the present application.

[0052] Marking Description:

[0053] 10. Display panel; 11. Display area; 12. Non-display area; 121. First frame area; 122. Second frame area; 123. Third frame area; 124. Fourth frame area; 125. Bending area; 1251. Middle area; 1252. Arc angle area; 126. Bonding area; 13. L-shaped cutout;

[0054] 21. substrate; 22. dielectric layer;

[0055] 30. Driver module;

[0056] 40. demultiplexing circuit; 41. demultiplexing signal line; 411. first routing segment; 412. second routing segment;

[0057] 51. a first power line; 52. a second power line;

[0058] 61. Data line; 62. Gate drive circuit; 64. Touch signal line;

[0059] 71, first via hole; 72, second via hole; 73, third via hole. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0061] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] In the process of implementing the present invention, the inventors found that the related art has the following problems: Figure 1 As shown, a related display panel 10 includes a display area 11 and a non-display area 12. The non-display area 12 is arranged around the display area 11. The non-display area 12 includes a first frame area 121, a second frame area 122, a third frame area 123 and a fourth frame area 124. The first frame area 121 (usually the lower frame) is also provided with a bending area 125 and a bonding area 126 on the side away from the display area 11. The bonding area 126 will be provided with a driving module, and the bending area 125 will be bent toward the back of the display panel 10. In order to facilitate the bending of the bending area 125 and reduce the space of the whole machine, it is necessary to perform arc cutting on both ends of the bending area 125 along the first direction (X direction in the figure), so that the bending area 125 forms an L-shaped incision 13 (also called L-Cut), and arc angle areas 1252 are formed at both ends of the bending area 125.

[0063] In the current display panel 10, the gate drive circuit, data line and demultiplexing signal line all run in the arc angle area 1252. When the first frame area 121 is too narrow, the lines in the arc angle area 1252 will be compressed, which may easily lead to the lines in the arc angle area 1252 being broken or short-circuited. Therefore, it is difficult to meet the demand for narrow frame of the product. Based on this, the purpose of this application is to provide a display panel solution to solve the above problem.

[0064] Reference Figure 3-6 As shown, in view of the discovery of the above problems, an embodiment of the present application provides a display panel 10 , which includes a substrate 21 , a demultiplexing circuit 40 , and a demultiplexing signal line 41 .

[0065] The substrate 21 includes a display area 11 and a non-display area 12, and the non-display area 12 is arranged around the display area 11. The non-display area 12 on at least one side of the display area 11 includes a first border area 121, a bending area 125 and a bonding area 126 which are arranged away from the display area 11 in sequence, and the bending area 125 includes a middle area 1251 and arc angle areas 1252 located at both ends of the middle area 1251; the demultiplexing circuit 40 is arranged in the first border area 121, the demultiplexing signal line 41 is electrically connected to the demultiplexing circuit 40, and the orthographic projection of the demultiplexing signal line 41 on the substrate 21 does not overlap with the arc angle area 1252.

[0066] The present embodiment provides a display panel 10, in which the orthographic projection of the demultiplexing signal line 41 on the substrate 21 does not overlap with the arc angle area 1252, that is, the demultiplexing signal line 41 does not run through the arc angle area 1252, which is beneficial for reducing the width of the border (first border area 121) of the arc angle area 1252, thereby achieving a narrow border of the product; at the same time, there is no need to compress other lines in the arc angle area, thereby ensuring the yield and performance of the display panel.

[0067] The first frame area 121 is usually the lower frame of the display panel 10. Furthermore, the non-display area 12 also includes a second frame area 122, a third frame area 123 and a fourth frame area 124.

[0068] Furthermore, the display panel 10 further includes a driving module 30 , which is disposed on one side of the substrate 21 and located in the bonding area 126 ; one end of the demultiplexing signal line 41 is electrically connected to the driving module 30 , and the other end is electrically connected to the demultiplexing circuit 40 .

[0069] Reference Figure 5 and 6 As shown, in one embodiment, the demultiplexed signal line 41 includes a first routing segment 411 and a second routing segment 412, the first routing segment 411 is located in the bonding area 126, and the second routing segment 412 is located in the middle area 1251. The demultiplexed signal line 41 is to be connected from the bonding area 126 to the first border area 121, and must pass through the bending area 125. In this embodiment, the demultiplexed signal line 41 (i.e., the second routing segment 412) passing through the bending area 125 is routed in the middle area 1251 to avoid occupying the arc corner area 1252, so as to facilitate the realization of a narrow border of the product.

[0070] Reference Figure 5 As shown, in one embodiment, the display panel 10 further includes a first power line 51, and the first power line 51 is at least partially located in the bonding area 126; in the bonding area 126, the orthographic projection of the first routing segment 411 on the substrate 21 does not overlap with the orthographic projection of the first power line 51 on the substrate 21. Figure 2In a related display panel, the demultiplexed signal line 41 of the bonding area 126 needs to cross the first power line 51, while in this embodiment, the demultiplexed signal line 41 of the bonding area 126 (i.e., the second routing segment 412) does not need to cross the first power line 51, which is beneficial to improve the charging and discharging time (RC loading), greatly reduce the resistance of the demultiplexed signal, and thus achieve performance advantages such as reduced charging time. Further, the first power line 51 is an ELVSS power line.

[0071] Reference Figure 6 As shown, in one embodiment, the display panel 10 further includes a second power line 52, and the second power line 52 is at least partially located in the bending area 125; the orthographic projection of the second routing segment 412 on the substrate 21 overlaps at least partially with the orthographic projection of the second power line 52 on the substrate 21. That is, the demultiplexing signal line 41 enters the first border area 121 from the bonding area 126 through the area where the second power line 52 is located, thereby avoiding occupying the arc corner area 1252. Further, the second power line 52 is an ELVDD power line.

[0072] Please continue to refer to Figure 6 As shown, in one embodiment, the second power line 52 extends along the first direction (such as the X direction in the figure), and the second routing segment 412 extends along the second direction (such as the Y direction in the figure), and the first direction intersects the second direction. It can be understood that the second routing segment 412 crosses the second power line 52, or the second power line 52 crosses the second routing segment 412, so that the second routing segment 412 reaches the first border area 121 from the bonding area 126. Further, the first direction is perpendicular to the second direction.

[0073] Please continue to refer to Figure 6 As shown, in one embodiment, the second power line 52 and the second routing segment 412 are in different layers. Specifically, a first via 71 is formed on the side of the middle area 1251 close to the bonding area, and a second via 72 is formed on the side of the middle area 1251 close to the first border area 121. The two ends of the second routing segment 412 are respectively connected through the first via 71 and the second via 72 to achieve line switching. Further, the demultiplexing circuit 40 is located in the first conductor layer M1 and the second conductor layer M2.

[0074] Reference Figure 4 As shown, in one embodiment, the display panel 10 further includes a first conductor layer M1 and a second conductor layer M2, the first conductor layer M1 is located on one side of the substrate 21, the second conductor layer M2 is located on a side of the first conductor layer M1 away from the substrate 21, and the second wiring segment 412 is located on the first conductor layer M1 and / or the second conductor layer M2. That is, the second wiring segment 412 can be a single-layer wiring or a double-layer wiring.

[0075] Preferably, when the second routing segment 412 is partially located in the first conductor layer M1 and partially located in the second conductor layer M2, the second routing segment 412 in the first conductor layer M1 is connected in parallel with the second routing segment 412 in the second conductor layer M2, which is beneficial to reducing the resistance of the second routing segment 412. Furthermore, the first conductor layer M1 and the second conductor layer M2 are usually Mo (molybdenum).

[0076] In one embodiment, the display panel 10 further includes a third conductor layer M3, which is located on a side of the second conductor layer M2 away from the substrate 21, and the second power line 52 is located on the third conductor layer M3, so that the second routing segment 412 and the second power line 52 are in different layers. Furthermore, the first routing segment 411 is located on the third conductor layer M3, because the first routing segment 411 is usually longer, and the third conductor layer M3 is usually TAT (titanium aluminum titanium), and routing on the third conductor layer M3 can effectively reduce resistance.

[0077] Referring to Figures 7-9, in another embodiment, the display panel 10 also includes a data line 61, and the data line 61 and the first power line 51 are at least partially located in the bending area 125; in the bending area 125, the orthographic projection of the second routing segment 412 on the substrate 1 has no overlap with the orthographic projections of the data line 61 and the first power line 51 on the substrate 1, and the orthographic projection of the second routing segment 412 on the substrate 21 is located between the orthographic projections of the data line 61 and the first power line 51 on the substrate 21, that is, the gap between the data line 61 and the first power line 51 is utilized to realize the demultiplexing signal line 41 from the bonding area 126 to the first border area 121, avoiding occupying the arc angle area 1252, thereby facilitating the realization of a narrow border of the product.

[0078] Reference Figure 7As shown, in one embodiment, the display panel 10 includes a first conductor layer M1, a second conductor layer M2 and a third conductor layer M3, the first conductor layer M1 is located on one side of the substrate 21, the second conductor layer M2 is located on the side of the first conductor layer M1 away from the substrate 21, and the third conductor layer M3 is located on the side of the second conductor layer M2 away from the substrate 21; in the bending area 125, the data line 61 is at least partially located in the first conductor layer M1, at least partially located in the second conductor layer M2, and the first power line 51 is located in the third conductor layer M3; wherein, the data line 61 in the first conductor layer M1 and the second conductor layer M2 can respectively carry different data signals, and the first power line 51 and the data line 61 are in different layers. Further, in the bending area 125, the second routing segment 412 is located in the third conductor layer M3, and the first routing segment 411 is located in the third conductor layer M3; that is, between the bonding area 126 and the middle area 1251, the first routing segment 411 and the second routing segment 412 do not need to be replaced by vias. Furthermore, the demultiplexing circuit 40 is located in the first conductor layer M1 and the second conductor layer M2 , a third via hole 73 is formed on one side of the middle area 1251 close to the first frame area 121 , and the second wiring segment 412 is connected to the demultiplexing circuit 40 through the third via hole 73 .

[0079] Further, refer to Figure 4 and 7 As shown, a dielectric layer 22 is disposed between the first conductor layer M1 and the second conductor layer M2, and between the second conductor layer M2 and the third conductor layer M3 to achieve insulation. In another embodiment, the second conductor layer M2 and the third conductor layer M3 further have a fourth conductor layer M4, which can be used for line switching.

[0080] Furthermore, the display panel 10 further includes a gate driving circuit 62, which is at least partially located in the arc corner area 1252; wherein the main function of the gate driving circuit is to provide appropriate gate driving signals for the pixels in the display panel 10 to control the on and off sequence of the pixels. Further, the gate driving circuit 62 generally includes an emission control circuit (EM circuit) and a scanning circuit (SCAN circuit).

[0081] Furthermore, the display panel 10 further includes a data line, which is at least partially located in the arc angle area 1252. The data line is used to write a driving signal into the pixel driving circuit. That is, the gate driving circuit and the data line are routed through the arc angle area 1252, but the demultiplexing signal line 41 does not route through the arc angle area 1252, which is conducive to achieving a narrow frame.

[0082] Furthermore, the display panel 10 further includes a touch signal line 64 . In the middle area 1251 , the touch signal line 64 is located between the data line 61 and the first power line 51 .

[0083] Another embodiment of the present application discloses a display device, which includes the display panel in the above embodiment. Further, the display device includes a mobile phone, a VR device, a computer, a television, a car display device, etc.

[0084] A display device provided by this embodiment has a display panel 10 in which the orthographic projection of the demultiplexing signal line 41 on the substrate 21 does not overlap with the arc angle area 1252, that is, the demultiplexing signal line 41 does not run through the arc angle area 1252, which is beneficial to reducing the width of the border (first border area 121) of the arc angle area 1252, thereby achieving a narrow border of the product; at the same time, there is no need to compress other lines in the arc angle area, thereby ensuring the yield and performance of the display panel, thereby improving the performance of the display device.

[0085] Although the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.

[0086] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0087] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A substrate, comprising a display area and a non-display area at least partially surrounding the display area, wherein the non-display area located at least on one side of the display area comprises a first frame area, a bending area and a bonding area which are sequentially arranged away from the display area, and the bending area comprises a middle area and arc angle areas located at both ends of the middle area; A demultiplexing circuit is arranged in the first border area; A demultiplexing signal line is electrically connected to the demultiplexing circuit, and an orthographic projection of the demultiplexing signal line on the substrate does not overlap with the arc angle area.

2. The display panel according to claim 1, wherein: The demultiplexed signal line includes a first routing segment and a second routing segment, the first routing segment is located in the bonding area, and the second routing segment is located in the middle area.

3. The display panel according to claim 2, wherein: The display panel further includes: a first power line, at least partially located in the bonding area; In the bonding area, an orthographic projection of the first routing segment on the substrate does not overlap with an orthographic projection of the first power line on the substrate.

4. The display panel according to claim 2 or 3, characterized in that: The display panel further includes: a second power line, wherein the second power line is at least partially located in the bending area; an orthographic projection of the second routing segment on the substrate at least partially overlaps with an orthographic projection of the second power line on the substrate; Preferably, the second power line extends along a first direction, the second routing segment extends along a second direction, and the first direction intersects the second direction.

5. The display panel according to claim 4, wherein: The second power line and the second wiring segment are in different layers.

6. The display panel according to claim 5, wherein: The display panel further includes: A first conductor layer, located on one side of the substrate; A second conductor layer is located on a side of the first conductor layer away from the substrate; The second routing segment is located in the first conductor layer and / or the second conductor layer; Preferably, when the second routing segment is partially located in the first conductor layer and partially located in the second conductor layer, the second routing segment in the first conductor layer is connected in parallel with the second routing segment in the second conductor layer; Preferably, the display panel further includes: a third conductor layer, located on a side of the second conductor layer away from the substrate; The second power line is located in the third conductor layer; Preferably, the first routing segment is located in the third conductor layer.

7. The display panel according to claim 3, wherein: The display panel further includes: A data line, wherein the data line and the first power line are at least partially located in the bending area; In the bending area, the orthographic projection of the second routing segment on the substrate does not overlap with the orthographic projections of the data line and the first power line on the substrate, and the orthographic projection of the second routing segment on the substrate is located between the orthographic projections of the data line and the first power line on the substrate.

8. The display panel according to claim 7, wherein: The display panel further includes: A first conductor layer, located on one side of the substrate; A second conductor layer is located on a side of the first conductor layer away from the substrate; a third conductor layer, located on a side of the second conductor layer away from the substrate; In the bending area, the data line is at least partially located in the first conductor layer, at least partially located in the second conductor layer, and the first power line is located in the third conductor layer; Preferably, in the bending area, the second routing segment is located in the third conductor layer.

9. The display panel according to claim 1, wherein: The display panel further includes: a gate drive circuit, wherein the gate drive circuit is at least partially located in the arc angle region; Preferably, the display panel further includes: A data line, wherein the data line is at least partially located in the arc corner area.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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