Adapter for quantization

Abstract

A processor-implemented method for adaptive quantization in an artificial neural network (ANN) includes receiving an ANN model. The ANN model has a plurality of channels of target activation. A quantization module is incorporated between the first linear layer of the ANN and the second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 18 / 330,990, filed on June 7, 2023, entitled “ADAPTERS FOR QUANTIZATION,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 355,472, filed on June 24, 2022, entitled “ADAPTERS FOR QUANTIZATION,” the disclosures of which are expressly incorporated by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure generally relate to quantization in artificial neural networks. Background Art

[0004] An artificial neural network may include an interconnected group of artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method to be performed by a computing device. A convolutional neural network (CNN) is a feedforward artificial neural network. A convolutional neural network may include a collection of neurons, each of which has a receptive field and collectively spells out an input space. Convolutional neural networks (CNNs), such as deep convolutional neural networks (DCNs), have numerous applications. Specifically, these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword detection, autonomous driving, and other classification tasks.

[0005] Edge devices, such as smartphones, are widely used. Given the many useful applications of neural networks, the use of edge devices and the demand for personalized services for such edge devices are increasing. However, edge devices have limited computing resources, and generalized models can utilize more complex networks and computing resources.

[0006] Transformer-based architectures have become the de facto standard model for various natural language processing tasks. However, their memory footprint and high latency hinder efficient deployment and inference on resource-limited devices. Summary of the invention

[0007] The present disclosure is set out in the independent claims respectively. Some aspects of the present disclosure are described in the dependent claims.

[0008] In one aspect of the present disclosure, a processor-implemented method includes receiving an artificial neural network (ANN) model having multiple channels of target activations. The method also includes combining a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. The method may further include operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0009] Another aspect of the present disclosure relates to an apparatus comprising a component for receiving an artificial neural network (ANN) model having multiple channels of target activation. The apparatus also comprises a component for combining a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. The apparatus may further comprise a component for operating the adapted ANN model to generate an inference based on the learnable quantization module parameters.

[0010] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for receiving an artificial neural network (ANN) model having multiple channels of target activation. The program code also includes program code for combining a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. The program code may further include program code for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0011] Another aspect of the present disclosure relates to an apparatus having a memory and one or more processors coupled to the memory. The processor is configured to receive an artificial neural network (ANN) model having multiple channels of target activation. The processor is also configured to combine a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. The processor may also be further configured to operate the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0012] Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the drawings is provided for illustration and description purposes only and is not intended as a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0014] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0015] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0016] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0017] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0018] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to aspects of the present disclosure.

[0019] Figure 5 is a block diagram illustrating an example implementation of a quantization adapter module in an artificial neural network (ANN) according to aspects of the present disclosure.

[0020] Figure 6 is a diagram illustrating example pseudo code for training a quantization adapter module according to aspects of the present disclosure.

[0021] Figure 7 is a flow chart illustrating a processor-implemented method for adaptive quantization in an artificial neural network (ANN) according to aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the described concepts can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, known structures and components are shown in block diagram form.

[0023] Based on the teachings, those skilled in the art will recognize that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device or a method can be implemented using any number of aspects described. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality that are supplementary to or different from the various aspects of the present disclosure described. It should be understood that any aspect of the present disclosure disclosed can be embodied by one or more elements of the claims.

[0024] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Although specific aspects are described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or purposes. On the contrary, various aspects of the present disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated as examples in the accompanying drawings and the following description of preferred aspects. The specific embodiments and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0026] Recently, transformer architectures have shown improvements in language modeling and natural language processing (NLP) tasks. Based on conventional transformer architectures, such as (but not limited to) Bidirectional Encoder Representations from Transformers (BERT), Robust Optimized BERT Method (RoBERTa), XLNet, Transformer-XL, and Generative Pre-Trained Transformers (GPT) series of transformers (e.g., GPT-2, GPT-3, GPT-4, etc.), language models can be pre-trained from large corpora of unlabeled text. As a result, such transformer architectures have become a common building block in conventional NLP pipelines and in other fields such as computer vision and audio processing.

[0027] Despite providing performance improvements in many applications, pre-trained transformer-based models can be extremely large, e.g., sometimes exceeding billions of parameters. Therefore, it is challenging to efficiently deploy such transformer-based models on resource-constrained embedded systems including mobile devices (e.g., smartphones) and Internet of Things (IoT) devices, and even some systems in data centers due to increased latency, energy consumption, and excessive memory footprint.

[0028] An effective way to solve this problem is neural network quantization. Neural network quantization reduces memory consumption by using low-bit precision for weights and activation tensors. In addition, neural network quantization can reduce inference time and improve energy efficiency by adopting low-bit fixed-point operations instead of floating-point operations.

[0029] However, quantization may introduce additional noise in the neural network, which may lead to a reduction in model accuracy and an increase in computational complexity. For example, transformer models may have numerous outliers in their activations. These activation outliers may lead to large quantization errors. Some conventional methods attempt to solve large quantization errors by applying quantization-aware training (QAT). QAT involves a fine-tuning process based on the same training data set and training pipeline as the original model. However, the QAT process may lead to overfitting because QAT changes the parameters of the pre-trained model when adapting to unfamiliar distributions or domains. In addition, many pre-trained language models may not grant access to training data sets and pipelines, forcing users to rely on arbitrary data sets and training pipelines for fine-tuning, which may also cause the model to overfit to the fine-tuning data.

[0030] To address these and other issues, aspects of the present disclosure relate to adapters for improved quantization in neural network models. The quantization adapter module can adapt to domain shifts caused by quantization while retaining initial model parameters. In some aspects, quantization-aware training and / or post-training quantization can also be applied. Therefore, aspects of the present disclosure can beneficially reduce and in some aspects prevent overfitting when fine-tuning data for QAT, and improve quantization performance in data-scarce environments and in distributed settings.

[0031] Figure 1 An example implementation of a system on a chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for adaptive quantization in an artificial neural network. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with CPU 102, a memory block associated with a graphics processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at CPU 102 may be loaded from a program memory associated with CPU 102, or may be loaded from memory block 118.

[0032] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0033] The SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general purpose processor 102 may include code for receiving an artificial neural network (ANN) model having multiple channels of target activation. The general purpose processor 102 may also include code for combining a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. The general purpose processor 102 may also include code for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0034] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning solves the main bottleneck of traditional machine learning. Before the advent of deep learning, machine learning methods for object recognition problems may rely heavily on human-designed features, possibly in conjunction with shallow classifiers. A shallow classifier can be a two-class linear classifier, for example, in which the weighted sum of feature vector components can be compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, they require training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0035] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0036] Deep learning architectures can perform particularly well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0037] Neural networks can be designed to have a variety of connection patterns. In a feedforward network, information is passed from a lower layer to a higher layer, where each neuron in a given layer communicates with a neuron in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have loops or feedback (also known as top-down) connections. In a loop connection, the output from a neuron in a given layer can be communicated to another neuron in the same layer. The loop architecture can help identify patterns that span more than one input data block in the input data blocks that are sequentially delivered to the neural network. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. When the recognition of a high-level concept can assist in discerning specific low-level features of the input, a network with many feedback connections may be helpful.

[0038] The connections between neural network layers can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In a fully connected neural network 202, a neuron in a first layer may communicate its output to each neuron in a second layer, such that each neuron in the second layer will receive input from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connection patterns may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive inputs that are tuned through training to the characteristics of a limited portion of the total input to the network.

[0039] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0040] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2DA detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as a vehicle-mounted camera) is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0041] The DCN 200 may be trained by supervised learning. During training, an image (such as an image 226 of a speed limit sign) may be presented to the DCN 200, and a forward pass may then be calculated to produce an output 222. The DCN 200 may include a feature extraction portion and a classification portion. Upon receiving the image 226, a convolutional layer 232 may apply a convolutional kernel (not shown) to the image 226 to generate a first set 218 of feature maps. As an example, the convolutional kernel of the convolutional layer 232 may be a 5×5 kernel that generates a 28×28 feature map. In this example, because four different feature maps are generated in the first set 218 of feature maps, four different convolutional kernels are applied to the image 226 at the convolutional layer 232. A convolutional kernel may also be referred to as a filter or a convolution filter.

[0042] The first set 218 of feature maps may be subsampled by a max pooling layer (not shown) to generate a second set 220 of feature maps. The max pooling layer reduces the size of the first set 218 of feature maps. That is, the size of the second set 220 of feature maps (such as 14×14) is smaller than the size of the first set 218 of feature maps (such as 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set 220 of feature maps may also be convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0043] exist Figure 2D In the example of , the second set 220 of feature maps is convolved to generate a first feature vector 224. In addition, the first feature vector 224 is also convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign", "60", and "100". A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Therefore, the output 222 of the DCN 200 may be a probability that the image 226 includes one or more features.

[0044] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers (such as "30", "40", "50", "70", "80", "90", and "100") in output 222. Before training, the output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the ground truth value of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that the output 222 of DCN 200 is closer to the target output.

[0045] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient may indicate the amount by which the error will increase or decrease when the weights are adjusted. At the top layer, the gradient may correspond directly to the value of the weights connecting the activated neurons in the penultimate layer and the neurons in the output layer. In lower layers, the gradient may depend on the value of the weights and the calculated error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting weights may be referred to as "backward propagation" because it involves a "backward pass" through the neural network.

[0046] In practice, the error gradient of the weights may be calculated over a small number of examples so that the calculated gradient is close to the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, the DCN 200 may be presented with new images, and a forward pass through the DCN 200 may produce an output 222 that may be considered an inference or prediction of the DCN 200.

[0047] A Deep Belief Network (DBN) is a probabilistic model that includes multiple layers of hidden nodes. A DBN can be used to extract a hierarchical representation of a training data set. A DBN can be obtained by stacking layers of Restricted Boltzmann Machines (RBMs). RBMs are a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn probability distributions without information about the category to which each input should be classified, RBMs are often used for unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBM of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0048] A DCN is a network of convolutional networks, configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the weights of the network using a gradient descent method.

[0049] The DCN may be a feed-forward network. In addition, as described above, the connections from a neuron in the first layer of the DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of the DCN can be used for fast processing. For example, the computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes loops or feedback connections.

[0050] The processing of each layer of the convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on the input can be thought of as three-dimensional, where two spatial dimensions are along the axes of the image and the third dimension captures color information. The output of the convolutional connection can be thought of as forming a feature map in a subsequent layer, each element in which receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, max(0,x)). The values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0051] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms can further improve the performance of deep learning. Rectified linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce overfitting, allowing larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0052] Figure 3 is a block diagram illustrating a deep convolutional network (DCN) 350. Based on connectivity and weight sharing, the deep convolutional network 350 may include multiple different types of layers. Figure 3As shown, the deep convolutional network 350 includes convolutional blocks 354A, 354B. Each of the convolutional blocks 354A, 354B may be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAX POOL) 360. Although only two convolutional blocks 354A, 354B are shown, the present disclosure is not limited thereto, but instead, any number of convolutional blocks 354A, 354B may be included in the deep convolutional network 350 according to design preferences.

[0053] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0054] For example, a parallel filter bank of a deep convolutional network may be loaded on SOC 100 (e.g., Figure 1 ) on the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0055] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may also include a logistic regression (LR) layer 364. There are weights (not shown) to be updated between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350. The output of each of these layers (e.g., 356, 358, 360, 362, 364) can be used as an input to a subsequent layer of these layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) supplied at the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is a probability that the input data includes a feature from a set of features.

[0056] Figure 4 400 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functions. According to aspects of the present disclosure, by using the architecture 400, a system on a chip (SoC) 420 (which can be similar to Figure 1 Various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of SoC 100 support the application of adaptive quantization for AI application 402. Architecture 400 may be included in a computing device such as a smart phone, for example.

[0057] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and recognition of scenes indicating the location where the computing device (including the architecture 400) is currently operating. For example, the AI ​​application 402 may configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0058] The runtime engine 408, which may be compiled code of a runtime framework, may further be accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inference, for example, at specific time intervals or triggered by an event detected by a user interface of the AI ​​application 402. When the runtime engine 408 is caused to provide an inference response, the runtime engine may in turn transmit a signal to an operating system in an operating system (OS) space (such as a Linux kernel 412) running on the SoC 420. The operating system may then cause continuous quantization relaxation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers (such as drivers 414, 416, or 418 for the DSP 424, GPU 426, or NPU 428, respectively). In an illustrative example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422 , DSP 424 , and GPU 426 , or may run on NPU 428 .

[0059] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and identification of a scene indicating the location at which the computing device (including the architecture 400) is currently operating. For example, the AI ​​application 402 may configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request to a compiled program code associated with a library defined in a scene detection application programming interface (API) 406 to provide an estimate of the current scene. The request may ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0060] The runtime engine 408, which may be compiled code of the runtime framework, may further be accessible by the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request scene estimation, for example, at specific time intervals or triggered by an event detected by a user interface of the AI ​​application 402. When causing the runtime engine 408 to estimate the scene, the runtime engine may in turn transmit a signal to an operating system 410 (such as a kernel 412) running on the SoC 420. The operating system 410 may then cause the calculation to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, and other processing blocks may be accessed through drivers (such as drivers 414-418 for the DSP 424, for the GPU 426, or for the NPU 428). In an exemplary example, the differential neural network may be configured to run on a combination of processing blocks (such as the CPU 422 and the GPU 426), or may run on the NPU 428.

[0061] As described, aspects of the present disclosure relate to an adapter for improved quantization in a neural network model. According to aspects of the present disclosure, an artificial neural network (ANN) can be adapted by incorporating a quantization adapter module (the quantization adapter module can be referred to as a "quantization adapter"). The quantization adapter can linearly scale the input channels of the ANN and restore after quantization. Thus, identity relationships can be maintained to enable retention of model parameters.

[0062] A quantization adapter may include a set of learnable parameters and may be configured to Linear scaling is performed before or after for the target activation. That is, the quantization adapter can linearly scale the input channels of the ANN and restore the input channels after quantization. In doing so, the identity relationship between the quantization parameters can enable the model parameters to be maintained. Instead, only the set of learnable quantization parameters is adapted. The scaling and inverse scaling of activations can be folded into the weights and biases of the previous layer and into the weights of the next layer. For example, given a forward pass of two linear layers,

[0063] y = W2(W1x + b1) + b2, (1) where x represents the input, y represents the output, W1 and b1 represent the weight and bias of the first linear layer, and W2 and b2 represent the weight and bias of the second linear layer, respectively. Quantized adapter module output It can be defined as follows:

[0064]

[0065]

[0066] Where A = diag(α) is a diagonal matrix, where A ii =α i ,in is a learnable quantization (quantization adapter) parameter, and d is the intermediate activation dimension. and is a weight quantizer, and is the activation quantizer. Each quantizer The input value (eg, the value in the input channel of the quantizer, which may be referred to as the “target activated channel”) may be quantized based on the quantization range parameter θ=(θ min ,θ max ). The quantization (quantization adapter) parameter α may be trained during the training phase and fused (eg, fixed) during the inference phase. ′ 1 and b ′ 1 represents the fused weight and bias of the first linear layer. ′ 2 represents the fusion weight of the second layer at inference time (e.g., as in Equation 3).

[0067] As in Equation 2, forward scaling and inverse scaling may correspond across three nested quantizers, which may be strongly nonlinear operations. Therefore, the quantization adapter parameter α should be learned rather than set analytically, as a single analytical solution may not be sufficient to balance the quantization burden between the two layers.

[0068] Figure 5 is a block diagram illustrating an example implementation 500 of a quantization adapter module 502 in an artificial neural network (ANN) according to aspects of the present disclosure. Figure 5 , the quantization adapter module 502 is configured as described to apply the quantization adapter parameter α to the weights and biases of the previous linear layer (e.g., a layer normalization (LN) layer). The quantization adapter module 502 may also apply the inverse of the quantization adapter parameter α to the weights of the next layer (e.g., a fully connected (FC) layer). The quantizer parameter Q may apply the quantization process to the weights and activations of each layer of the ANN.

[0069] exist Figure 5 In the specific implementation example 500, the quantization adapter module 502 is inserted in the ANN 504. In the example implementation, the ANN 504 has a transformer architecture. Of course, this is just an example, and the quantization adapter module 502 can be included in other types of ANNs. For ease of illustration, Figure 5 A single transformer block is shown in FIG. 504. However, it should be understood that ANN 504 may include multiple transformer blocks.

[0070] One or more instances of the quantization adapter module 502 may be incorporated into the ANN 504. For example, the first quantization adapter module 502a may be inserted between the first LN layer 506a and the attention layer 508. The second quantization adapter module 502b may be inserted between the second LN layer 506b and the multi-layer perceptron (MLP) layer 510. In some aspects, the quantization adapter module 502 may also be included between the final LN layer and the final logit projection.

[0071] Figure 6 is a diagram illustrating an example pseudo code 600 for training a quantization adapter module according to aspects of the present disclosure. Figure 6 , quantization adapter modules (e.g., Figure 5 The learning of 502) can be performed in two stages: a block-by-block calibration stage 602 and an end-to-end fine-tuning stage 604. In the block-by-block calibration stage 602, each of the quantization adapter module instances (e.g., 502a, 502b) can be initialized to And trained using a set of calibration data for quantization. Each quantization adapter module (e.g., 502a, 502b) can be trained independently on a per-quantization adapter module basis. The local target of each block can be, for example, an L2 loss:

[0072]

[0073] The quantization adapter parameter α is learned by minimizing the block-wise quantization error using the calibration data for quantization. In some aspects, the quantization adapter module output α may be calculated in a dynamic quantization mode. The statistical data is obtained in batches, and the quantization parameter Q min / max can be dynamically calculated in each batch taking into account the influence of the quantization adapter parameters.

[0074] The quantization adapter modules (eg, 502 a , 502 b ) resulting from the block-wise calibration stage 602 are post-training quantization (PTQ) methods independent of the end-to-end fine-tuning stage 604 .

[0075] The end-to-end fine-tuning stage 604 may start with more adaptive quantization parameters (e.g., less extreme min / max statistics) because more modest values ​​may be generated compared to more extreme outliers during the block-by-block calibration stage 602. As a result, the fine-tuning process may converge faster.

[0076] Statistics for quantization may be calculated based on the same calibration data as in the block-by-block calibration phase 602, just as in static quantization. The quantization adapter module (e.g., 502a, 502b) may then be trained using the training data set to minimize the end-to-end task loss. In some aspects, the quantization parameters may be jointly learned, while the ANN model parameters (e.g., weights) may be fixed.

[0077] Figure 7 7 is a flowchart illustrating a processor-implemented method 700 for adaptive quantization in an artificial neural network according to aspects of the present disclosure. For example, the processor-implemented method 700 may be executed by a processor such as a CPU 102, a GPU 104, or a NPU 108.

[0078] like Figure 7 As shown, at block 702, a processor receives an artificial neural network (ANN) model. The ANN model has multiple channels of target activation. For example, the ANN may include a transformer neural network, such as (but not limited to) a bidirectional encoder representation from a transformer (BERT), a transformer based on a robustly optimized BERT method (RoBERTa), a transformer based on XLNet, a transformer based on transformer-XL, or a generative pre-trained transformer (GPT). In some aspects, the ANN model may include a pre-trained model.

[0079] At block 704, the processor combines a quantization module between a first linear layer of the ANN and a second linear layer of the ANN to generate an adapted ANN. The quantization module scales a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scales a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters. For example, as described in reference Figure 5 As described, the quantization adapter module 502a can be inserted between the first LN layer 506a and the attention layer 508 of the ANN 504.

[0080] At block 706, the processor may optionally operate the adapted ANN model to generate inferences based on the learnable quantization module parameters. In some aspects, the adapted ANN model may be operable to generate inferences based on the learnable quantization parameters. The quantization parameters may be determined based on the task loss of the adapted ANN model.

[0081] Specific implementation examples are described in the following numbered clauses:

[0082] 1. A processor-implemented method, the method comprising:

[0083] receiving an artificial neural network (ANN) model having a plurality of channels activated by a target; and

[0084] A quantization module is incorporated between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

[0085] 2. The processor-implemented method of clause 1 , further comprising scaling the target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

[0086] 3. The processor-implemented method of clause 1 or 2, further comprising determining the learnable quantization parameter based on a task loss of the adapted ANN model.

[0087] 4. A processor-implemented method according to any of clauses 1 to 3, wherein the learnable quantization parameters and the learnable quantization module parameters are jointly determined.

[0088] 5. A processor-implemented method according to any one of clauses 1 to 4, further comprising retraining the adapted ANN model using a quantization-aware training process.

[0089] 6. A processor-implemented method according to any one of clauses 1 to 5, wherein the ANN model comprises a transformer neural network model.

[0090] 7. A processor-implemented method according to any one of clauses 1 to 6, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformer (BERT), a Transformer based on the Robust Optimization of BERT method (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

[0091] 8. A processor-implemented method according to any of clauses 1 to 7, further comprising operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0092] 9. A device, comprising:

[0093] Memory; and

[0094] at least one processor, the at least one processor coupled to the memory, the at least one processor configured to:

[0095] receiving an artificial neural network (ANN) model having a plurality of channels activated by a target; and

[0096] A quantization module is incorporated between a first linear layer of the ANN and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

[0097] 10. The apparatus of clause 9, wherein the at least one processor is further configured to scale the target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

[0098] 11. An apparatus according to clause 9 or 10, wherein the at least one processor is further configured to determine the learnable quantization parameter based on a task loss of the adapted ANN model.

[0099] 12. The apparatus of any of clauses 9 to 11, wherein the at least one processor is further configured to jointly determine the learnable quantization parameter and the learnable quantization module parameter.

[0100] 13. An apparatus according to any of clauses 9 to 12, wherein the at least one processor is further configured to retrain the adapted ANN model using a quantization-aware training process.

[0101] 14. An apparatus according to any one of clauses 9 to 13, wherein the ANN model comprises a transformer neural network model.

[0102] 15. An apparatus according to any one of clauses 9 to 14, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformer (BERT), a Transformer based on the Robust Optimization of BERT method (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

[0103] 16. An apparatus according to any of clauses 9 to 15, wherein the at least one processor is further configured to operate the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0104] 17. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0105] Program code for receiving an artificial neural network (ANN) model having a plurality of channels of target activation; and

[0106] Program code for incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

[0107] 18. The non-transitory computer-readable medium of clause 17, wherein the program code further comprises program code for scaling a target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

[0108] 19. The non-transitory computer-readable medium of clause 17 or 18, wherein the program code further comprises program code for determining the learnable quantization parameter based on a task loss of the adapted ANN model.

[0109] 20. The non-transitory computer readable medium of any of clauses 17 to 19, wherein the program code further comprises program code for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0110] 21. A device, comprising:

[0111] means for receiving an artificial neural network (ANN) model having a plurality of channels of target activations; and

[0112] A component for incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

[0113] 22. The apparatus of clause 21, further comprising means for scaling a target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

[0114] 23. The apparatus according to clause 21 or 22, further comprising means for determining the learnable quantization parameter based on a task loss of the adapted ANN model.

[0115] 24. The apparatus of any of clauses 21 to 23, further comprising means for jointly determining the learnable quantization parameter and the learnable quantization module parameter.

[0116] 25. An apparatus according to any of clauses 21 to 24, further comprising means for retraining the adapted ANN model using a quantization-aware training procedure.

[0117] 26. An apparatus according to any one of clauses 21 to 25, wherein the ANN model comprises a transformer neural network model.

[0118] 27. An apparatus according to any one of clauses 21 to 26, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformer (BERT), a Transformer based on the Robust Optimization of BERT method (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

[0119] 28. An apparatus according to any of clauses 21 to 27, further comprising means for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

[0120] In some aspects, the receiving means, combining means, operating means, determining means, scaling means and / or training means may be the GPU 104, a program memory associated with the GPU 104, the fully connected layer 362, the NPU 428 and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0121] The various operations of the above methods may be performed by any suitable components capable of performing the corresponding functions. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components plus function components with similar numbers.

[0122] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0123] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0124] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0125] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. The software module may be located in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. The storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral with the processor.

[0126] The disclosed methods include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0127] The functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0128] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, a machine-readable medium may include a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a disk, an optical disk, a hard disk drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging material.

[0129] In hardware implementation, machine-readable media can be a part of a processing system separated from a processor. However, as will be readily appreciated by those skilled in the art, machine-readable media or any part thereof can be outside a processing system. By way of example, machine-readable media can include a transmission line, a carrier wave modulated by data, and / or a computer product separated from a device, all of which can be accessed by a processor through a bus interface. Alternatively or in addition thereto, machine-readable media or any part thereof can be integrated into a processor, such as with a cache and / or a general register stack. Although the various components discussed can be described as having specific locations, such as local components, they can also be configured in various ways, such as certain components being configured as a part of a distributed computing system.

[0130] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and an external memory providing at least a portion of a machine-readable medium, all of which are linked together with other supporting circuit systems through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) having at least a portion of a processor, a bus interface, a user interface, a support circuit, and a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuits, or circuits capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how to best implement the functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0131] The machine-readable medium may include multiple software modules. These software modules include instructions that cause the processing system to perform various functions when executed by the processor. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, the software module may be loaded from a hard drive into a RAM. During the execution of the software module, the processor may load some of the instructions into a cache to increase access speed. Then one or more cache lines may be loaded into a general register stack for execution by the processor. When the functionality of a software module is mentioned below, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. In addition, it should be understood that various aspects of the present disclosure produce improvements in the functionality of a processor, a computer, a machine, or other systems that implement such aspects.

[0132] If implemented in software, each function can be stored on a computer-readable medium or sent by it as one or more instructions or codes.Computer-readable media includes both computer storage media and communication media, including any medium that facilitates a computer program to be transmitted from one place to another.Storage media can be any available medium that can be accessed by a computer.Exemplarily and not restrictively, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, and can also be used to carry or store desired program codes in the form of instructions or data structures and any other medium that can be accessed by a computer.In addition, any connection is also appropriately referred to as computer-readable media.For example, if software is sent from a website, server or other remote source using a coaxial cable, optical cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared (IR), radio and microwaves, then the coaxial cable, optical cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray Optical disks, where magnetic disks typically reproduce data magnetically, and optical disks reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0133] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions that can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0134] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station when applicable. For example, such a device can be coupled to a server to facilitate the transfer of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk, etc.) so that once the storage device is coupled to or provided to the user terminal and / or base station, the device can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to the device can be used.

[0135] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, the method comprising: receiving an artificial neural network (ANN) model having a plurality of channels activated by a target; as well as A quantization module is incorporated between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

2. The processor-implemented method of claim 1 , further comprising scaling a target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

3. The processor-implemented method of claim 2, further comprising determining the learnable quantization parameter based on a task loss of the adapted ANN model. 4 . The processor-implemented method of claim 2 , wherein the learnable quantization parameter and the learnable quantization module parameter are jointly determined.

5. The processor-implemented method of claim 1 , further comprising retraining the adapted ANN model using a quantization-aware training process.

6. The processor-implemented method of claim 1, wherein the ANN model comprises a Transformer Neural Network model.

7. The processor-implemented method of claim 6, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformers (BERT), a Transformer based on a Robust Optimization of BERT approach (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

8. The processor-implemented method of claim 1, further comprising operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

9. A device, comprising: Memory; and at least one processor, the at least one processor coupled to the memory, the at least one processor configured to: receiving an artificial neural network (ANN) model having a plurality of channels activated by a target; as well as A quantization module is incorporated between a first linear layer of the ANN and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

10. The apparatus of claim 9, wherein the at least one processor is further configured to scale the target activation in each of the plurality of channels of target activation based on a learnable quantization parameter. 11 . The apparatus of claim 10 , wherein the at least one processor is further configured to determine the learnable quantization parameter based on a task loss of the adapted ANN model. 12 . The apparatus of claim 10 , wherein the at least one processor is further configured to jointly determine the learnable quantization parameter and the learnable quantization module parameter.

13. The apparatus of claim 9, wherein the at least one processor is further configured to retrain the adapted ANN model using a quantization-aware training process.

14. The apparatus of claim 9, wherein the ANN model comprises a transformer neural network model.

15. The apparatus of claim 14, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformers (BERT), a Transformer based on a Robust Optimization of BERT approach (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

16. The apparatus of claim 9, wherein the at least one processor is further configured to operate the adapted ANN model to generate inferences based on the learnable quantization module parameters.

17. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving an artificial neural network (ANN) model having a plurality of channels of target activation; and Program code for incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

18. The non-transitory computer readable medium of claim 17, wherein the program code further comprises program code for scaling a target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

19. The non-transitory computer readable medium of claim 18, wherein the program code further comprises program code for determining the learnable quantization parameter based on a task loss of the adapted ANN model.

20. The non-transitory computer readable medium of claim 17, wherein the program code further comprises program code for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

21. A device, comprising: means for receiving an artificial neural network (ANN) model having a plurality of channels of target activations; and A component for incorporating a quantization module between a first linear layer of the ANN model and a second linear layer of the ANN model to generate an adapted ANN model, the quantization module scaling a first set of weights and biases of the first linear layer based on learnable quantization module parameters and scaling a second set of weights of the second linear layer based on an inverse of the learnable quantization module parameters.

22. The apparatus of claim 21, further comprising means for scaling a target activation in each of the plurality of channels of target activation based on a learnable quantization parameter.

23. The apparatus of claim 22, further comprising means for determining the learnable quantization parameter based on a task loss of the adapted ANN model.

24. The apparatus of claim 22, further comprising means for jointly determining the learnable quantization parameter and the learnable quantization module parameter.

25. The apparatus of claim 21, further comprising means for retraining the adapted ANN model using a quantization-aware training process.

26. The apparatus of claim 21, wherein the ANN model comprises a transformer neural network model.

27. An apparatus according to claim 26, wherein the transformer neural network model comprises one of a Bidirectional Encoder Representation from Transformers (BERT), a Transformer based on a Robust Optimization of BERT method (RoBERTa), an XLNet-based Transformer, a Transformer-XL-based Transformer, or a Generative Pre-Trained Transformer (GPT).

28. The apparatus of claim 21, further comprising means for operating the adapted ANN model to generate inferences based on the learnable quantization module parameters.

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