Generating synchronization signals

Abstract

Examples relate to generating a synchronization signal. An example apparatus includes an output, an input, and a circuit. The output provides a data valid signal to a video source that operates to provide video data to a video data processing pipeline. The input receives a delayed data valid signal from the video data processing pipeline. The circuitry is to generate a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least in part in response to a received delayed data valid signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the priority date of Indian Provisional Patent Application No. 202241036390 filed on June 24, 2022 and entitled “VIDEO-TIMING GENERATOR”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The description generally relates to generating timing signals. More specifically, some examples relate to video timing generators for generating data valid signals, horizontal sync signals, and vertical sync signals, but are not limited thereto. Background Art

[0004] The video timing generator may generate one or more timing signals, including a data valid signal, a horizontal sync signal, and a vertical sync signal, according to the timing specifications of a particular protocol (such as the Video Electronics Standards Association (VESA) and Industry Standards and Guidelines for Computer Display Monitor Timing (DMT) Version 1.0, Revision 11, published by the Video Electronics Standards Association of Milpitas, California on May 1, 2007. The video processing pipeline and / or the display may use the timing signals when displaying images and / or playing sounds. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] While the present disclosure concludes with claims that particularly point out and distinctly claim specific examples, the various features and advantages of examples within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0006] Figure 1 is a functional block diagram depicting a system according to one or more examples.

[0007] Figure 2 is a functional block diagram depicting another system according to one or more examples.

[0008] Figure 3 is a functional block diagram depicting an apparatus according to one or more examples.

[0009] Figure 4 is a flowchart of a method according to one or more examples.

[0010] Figure 5 is a flow chart of another method according to one or more examples.

[0011] Figure 6 Block diagrams illustrating devices that may be used to implement various functions, operations, acts, processes, or methods according to one or more examples. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of example specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0013] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0014] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "by way of example," and "for example" means that the relevant description is illustrative, and while the scope of the present disclosure is intended to encompass examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples of the present disclosure to the specified components, steps, features, functions, etc.

[0015] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0016] In addition, the specific embodiments shown and described are examples only, and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Components, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are examples only, and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between the block definitions and the individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure, and are within the capabilities of those of ordinary skill in the relevant art.

[0017] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and description, some of the accompanying drawings may illustrate signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal. Those of ordinary skill in the art will appreciate that the present disclosure encompasses the transmission of quantum information and qubits used to represent quantum information.

[0018] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer executes computing instructions (e.g., software code, but not limited thereto) associated with the examples disclosed herein.

[0019] Examples can be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts can describe operable actions as continuous processes, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions can be rearranged. A process can correspond to a method, a thread, a function, a procedure, a subroutine, or a subprogram, but is not limited thereto. In addition, the methods disclosed herein can be implemented by hardware, software, or both. If implemented in software, a function can be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that is conducive to transferring a computer program from one location to another.

[0020] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to or with another element, the element may be in direct physical or electrical contact, or there may be one or more intervening elements or layers. In contrast, when an element is described as being "directly coupled" to or with another element, there are no intervening elements or layers. It should be understood that when an element is referred to as being "coupled" to a first element and a second element, the element is coupled to the first element and the element is coupled to the second element.

[0021] Figure 1 is a functional block diagram depicting a system 100 according to one or more examples. The system 100 may include a video timing generator 102, a video data processing pipeline 138, and a display 150.

[0022] The video timing generator 102 may provide (e.g., generate, provide, or both, but not limited to) delayed synchronization signals, among other things, which include (as non-limiting examples) a delayed horizontal synchronization signal 134 (the delayed horizontal synchronization signal 134 may alternatively be referred to herein as “delayed h-sync 134”) and / or a delayed vertical synchronization signal 136 (the delayed vertical synchronization signal 136 may alternatively be referred to herein as “delayed v-sync 136”).

[0023] Video timing generator 102 may include output 104 , sync output 114 , delayed data valid output 128 , delayed sync output 132 , input 120 , and circuit 108 .

[0024] Circuit 108 may include a horizontal synchronization counter 110 (the horizontal synchronization counter 110 may be referred to alternatively herein as “h-sync counter 110”), a vertical synchronization counter 112 (the vertical synchronization counter 112 may be referred to alternatively herein as “v-sync counter 112”), a delayed horizontal synchronization counter 124 (the delayed horizontal synchronization counter 124 may be referred to alternatively herein as “delayed h-sync counter 124”), and a delayed vertical synchronization counter 126 (the delayed vertical synchronization counter 126 may be referred to alternatively herein as “delayed v-sync counter 126”).

[0025] The video timing generator 102 may provide (e.g., generate, provide, or both, but not limited to) a data valid signal 106 (the data valid signal 106 may be alternatively referred to herein as “data valid 106”), a horizontal synchronization signal 116 (the horizontal synchronization signal 116 may be alternatively referred to herein as “h-sync 116”), and a vertical synchronization signal 118 (the vertical synchronization signal 118 may be alternatively referred to herein as “v-sync 118”) to the video data processing pipeline 138 or, more specifically, to the video source 140 of the video data processing pipeline 138. The video source 140 receives the data valid signal 106, the h-sync signal 116, and the v-sync signal 118, and synchronizes the generation of the video data 144 with the timing information in the data valid signal 106.

[0026] The video data processing pipeline 138 may include, for example, a video source 140 at an input 152 of the video data processing pipeline 138, but is not limited thereto. The video data processing pipeline 138 (as a non-limiting example) may perform a set of operations on the video data 144 to (for another non-limiting example) change, analyze, or enhance the content of the video data 144. In one or more examples, the set of operations performed by the video data processing pipeline 138 may be used to display an image on a computer monitor, such as an image specified by the DMT, but is not limited thereto. The video data processing pipeline 138 may additionally include one or more video processors 146 (the video processors 146 may alternatively be referred to herein as "video processors 146"). The video source operates to provide (e.g., generate, provide, or both, but is not limited thereto) video data 144 to the video data processing pipeline 138, or more specifically to the video processors 146 of the video data processing pipeline 138. The video data processing pipeline 138 may provide the delayed data valid signal 122 (the delayed data valid signal 122 may be referred to herein alternatively as “delayed data valid 122”), for example, from an output 154 of the video data processing pipeline 138 to the video timing generator 102 (e.g., an input 120 of the video timing generator 102). The video data processing pipeline 138 may provide processed video data 148 (the processed video data 148 may be referred to herein alternatively as “video data 148”) to the display 150.

[0027] The video timing generator 102 may provide a delayed data valid signal 130 (which may be substantially the same as the delayed data valid signal 122 provided by the video data processing pipeline 138 and may be referred to herein alternatively as “delayed data valid 130”), a delayed horizontal synchronization signal 134, and a delayed vertical synchronization signal 136 to the display 150.

[0028] Video source 140 may be a source of or may include a source of video data 144 regarding system 100. Video source 140 may create, read, or receive video data 144. Video source 140 may be, as non-limiting examples, a camera, a hard drive including video data 144, a disk including video data 144, and a recipient of a data stream including video data 144.

[0029] The video data 144 may be image and / or sound information encoded into a signal in any suitable format, including (as non-limiting examples) RGB, YUV, RAW, Motion Picture Experts Group 4 (MPEG 4 or MP4), Windows Media Video (WMV), and Flash Video (FLV), or may include image and / or sound information encoded into a signal in any suitable format, including (as non-limiting examples) RGB, YUV, RAW, Motion Picture Experts Group 4 (MPEG 4 or MP4), Windows Media Video (WMV), and Flash Video (FLV).

[0030] The video processor 146 may be, or may include, one or more functional blocks that may perform corresponding operations on the video data 144. Non-limiting examples of operations include converting the video data 144 into processed video data 148 (i.e., a format suitable for reproduction by the display 150), image processing, edge detection, and / or image enhancement.

[0031] The video data processing pipeline 138 may be implemented by one or more of a field programmable gate array (FPGA) and / or an application specific integrated circuit (ASIC). In some non-limiting examples, each of the video source 140 and the video processor 146 may be implemented by a corresponding intellectual property block of an FPGA or an ASIC.

[0032] Processed video data 148 may be, or may include, video data 144 encoded into a signal for reproduction at display 150. Processed video data 148 may include blocks of data (e.g., composed of one or more bytes) for individual pixels of display 150. The blocks of data may be ordered in the signal according to the rows and grids of display 150. Processed video data 148 may additionally include audio data to be reproduced as sound.

[0033] Display 150 may be, or may include, a device or system for displaying images (e.g., sequentially, video) and / or playing sound. Display 150 may operate according to standards including, as non-limiting examples, High Definition Multimedia Interface (HDMI), 4K HDMI, and Video Graphics Array (VGA). In one or more examples, display 150 may be a computer display, a computer monitor, or a smart TV.

[0034] The video timing generator 102 may provide one or more timing signals (including the data valid signal 106, the horizontal synchronization signal 116, the vertical synchronization signal 118, the delayed data valid signal 130, the delayed horizontal synchronization signal 134, and the delayed vertical synchronization signal 136) to the video data processing pipeline 138 and / or the display 150 so that the image (and / or audio) displayed (and / or played) at the display 150 is properly displayed (and / or played). As a non-limiting example, the display 150 may convert a block of data (e.g., one or more bytes) of the processed video data 148 into an image and / or sound. More specifically, the display 150 may convert a first number of blocks of data of the processed video data 148 into a first number of pixels in a first row of the display 150, and convert a second number of blocks of data of the processed video data 148 into a second number of pixels in a second row of the display 150. The display 150 may use the delayed horizontal synchronization signal 134 to determine where the first number of blocks of data of the processed video data 148 ends and where the second number of blocks of data of the processed video data 148 begins. In other words, the display 150 may parse the processed video data 148 into rows according to the delayed horizontal synchronization signal 134. Additionally, the display 150 may begin refreshing the first row of the display 150 (e.g., after the last row has been filled) according to the delayed vertical synchronization signal 136. In other words, the display 150 may parse the processed video data 148 into a grid according to the delayed vertical synchronization signal 136. Additionally, the display 150 may use the delayed data valid signal 130 to determine when to convert the processed video data 148 into visual and / or audio information. As a non-limiting example, when the delayed data valid signal 130 is valid (e.g., high), the display 150 may display visual information.

[0035] It may be important that the delayed horizontal sync signal 134 and the delayed vertical sync signal 136 are synchronized with the processed video data 148. As a non-limiting example, any mismatch between the timing of the delayed horizontal sync signal 134, the delayed vertical sync signal 136, and the processed video data 148 may cause the display 150 to incorrectly reproduce the processed video data 148. As a non-limiting example, a mismatch between the delayed horizontal sync signal 134, the delayed vertical sync signal 136, and the processed video data 148 may cause a horizontally or vertically shifted video display or monitor to be unable to recognize the video signal.

[0036] exist Figure 1 In a conventional system not illustrated, a conventional video timing generator generates a data valid signal, a horizontal synchronization signal, and a vertical synchronization signal and provides the data valid signal, the horizontal synchronization signal, and the vertical synchronization signal to a video source. The video source provides video data and a data valid signal, a horizontal synchronization signal, and a vertical synchronization signal to a conventional video processor of a video data processing pipeline. Conventional video processors can each delay video data as a result of an operation performed on the video data. Conventional video processors can also delay the data valid signal, the horizontal synchronization signal, and the vertical synchronization signal by the same duration when the video data is delayed, so that the video data can be synchronized with the data valid signal, the horizontal synchronization signal, and the vertical synchronization signal. In order to delay the data valid signal, the horizontal synchronization signal, and the vertical synchronization signal, a conventional video processor (including each video processor in a conventional video data processing pipeline) includes corresponding logic for delaying the data valid signal, the horizontal synchronization signal, and the vertical synchronization signal.

[0037] Various examples include a video timing generator (e.g., video timing generator 102) that generates a delayed horizontal synchronization signal (e.g., delayed horizontal synchronization signal 134) and a delayed vertical synchronization signal (e.g., delayed vertical synchronization signal 136). In such examples, the video timing generator may provide the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display (e.g., display 150). By generating the delayed horizontal synchronization signal and the delayed vertical synchronization signal and providing the delayed horizontal synchronization signal and the delayed vertical synchronization signal to the display, the video timing generator no longer requires a video processor (e.g., video processor 146) for delaying the horizontal synchronization signal and the vertical synchronization signal. In the absence of the need to delay the horizontal synchronization signal and the vertical synchronization signal, the video processor may not need to include logic for delaying the horizontal synchronization signal and the vertical synchronization signal. Therefore, a system including a video timing generator that generates a delayed horizontal synchronization signal and a delayed vertical synchronization signal and provides the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display may include a simpler and / or less expensive video processor.

[0038] Thus, in some non-limiting examples, the video source 140 may not provide the horizontal synchronization signal 116 and the vertical synchronization signal 118 to the video processor 146 of the video data processing pipeline 138. Thus, the video processor 146 of the video data processing pipeline 138 may not receive any of the horizontal synchronization signal 116, the vertical synchronization signal 118, the delayed horizontal synchronization signal 134, and the delayed vertical synchronization signal 136. Furthermore, the video processor 146 of the video data processing pipeline 138 may not include circuitry for handling any of the horizontal synchronization signal 116, the vertical synchronization signal 118, the delayed horizontal synchronization signal 134, and the delayed vertical synchronization signal 136.

[0039] In some non-limiting examples, the video timing generator 102 may be implemented by a FPGA or an ASIC. In some non-limiting examples, the video timing generator 102 may be implemented by the same FPGA or ASIC as one or more of the video source 140 and the video processor 146. In other non-limiting examples, the video timing generator 102 may be implemented by any suitable device.

[0040] As an example of the contemplated operation of system 100, video timing generator 102 may generate data valid signal 106, horizontal sync signal 116, and vertical sync signal 118. Data valid signal 106 may indicate the timing of the start of video data.

[0041] The horizontal sync signal 116 may indicate the timing of the start of a new horizontal data line in the video data. The horizontal sync counter 110 may count clock cycles since the video timing generator 102 began outputting the terminal data valid signal 106. When the horizontal sync counter 110 has counted the number of clock cycles corresponding to the timing of the start of a new horizontal line, the video timing generator 102 may generate the horizontal sync signal 116.

[0042] The vertical sync signal 118 may indicate the timing of the start of a new data grid in the video data (i.e., returning to the top horizontal line to begin refreshing the grid). The vertical sync counter 112 may count clock cycles since the video timing generator 102 began outputting the terminal data valid signal 106. The video timing generator 102 may generate the vertical sync signal 118 when the vertical sync counter 112 has counted the number of clock cycles corresponding to the timing of starting a new grid.

[0043] The video timing generator 102 may provide a data valid signal 106 at an output 104 to the video data processing pipeline 138 (or more specifically to a video source 140, which may be located at an input 152 of the video data processing pipeline 138). The video timing generator 102 may provide a horizontal synchronization signal 116 and a vertical synchronization signal 118 at a synchronization output 114 to the video data processing pipeline 138 (or more specifically to a video source 140, which may be located at an input 152 of the video data processing pipeline 138).

[0044] After receiving the data valid signal 106, the video source 140 may provide the video data 144 and the data valid signal 142 to the video data processing pipeline 138 (e.g., to the video processor 146 of the video data processing pipeline 138). The data valid signal 142 indicates when valid pixel data (referred to herein as processed video data 148) is provided (e.g., sent, but not limited to) to the display 150. In one or more examples, the processed video data 148 may be provided at a timing and rate indicated at least in part by the data valid signal 106. Thus, in some examples, the data valid signal 142 may be the same as the data valid signal 106 (e.g., indicating the same timing, but not limited to this). Additionally or alternatively, the data valid signal 142 may be a delayed version of the data valid signal 106 delayed by the video source 140 (e.g., corresponding to the delay of the video source 140, but not limited to this). Video source 140 may delay data valid signal 106 according to the operation of video source 140 , ie, such that video data 144 is valid when data valid signal 142 arrives at video processor 146 , or in other words when video data 144 is synchronized with data valid signal 142 .

[0045] Video processors 146 may process video data 144 according to individual operations of each of video processors 146 to generate processed video data 148. Example operations of video processors 146 include converting video data 144 into processed video data 148, image processing, edge detection, and / or image enhancement.

[0046] Additionally, the video processors 146 may delay the data valid signal 142 for a duration associated with processing the video data 144. Specifically, the video processors 146 may delay the data valid signal 142 based on the individual operations of each of the video processors 146 used to generate the delayed data valid signal 122 so that the delayed data valid signal 122 is synchronized with the processed video data 148. As a non-limiting example, if a first of the video processors 146 takes 1 millisecond (ms) to perform an operation on the video data 144, the first of the video processors 146 may delay the data valid signal 142 by 1 ms. Additionally, if a second of the video processors 146 takes 2 ms to perform an operation on the video data 144, the second of the video processors 146 may delay the data valid signal 142 by an additional 2 ms. The video data processing pipeline 138 may provide the delayed data valid signal 122 from the output 154 to the video timing generator 102.

[0047] The video processor 146 may or may not receive the horizontal synchronization signal 116 and / or the vertical synchronization signal 118 from the video source 140. The video processor 146 may or may not include an input for receiving the horizontal synchronization signal 116 and / or the vertical synchronization signal 118. The video processor 146 may or may not include logic for processing or delaying the horizontal synchronization signal 116 and / or the vertical synchronization signal 118.

[0048] The video timing generator 102 may receive a delayed data valid signal 122 at an input 120. In response at least in part to receiving the delayed data valid signal 122, the video timing generator 102 may initialize a delayed horizontal sync counter 124 and a delayed vertical sync counter 126.

[0049] The video timing generator 102 may generate a delayed horizontal synchronization signal 134 at least in part in response to the delayed horizontal synchronization counter 124. As a non-limiting example, the delayed horizontal synchronization counter 124 may count clock cycles since the video timing generator 102 received the delayed data valid signal 122. When the delayed horizontal synchronization counter 124 has counted a number of clock cycles corresponding to the timing of starting a new horizontal line, the video timing generator 102 may generate the delayed horizontal synchronization signal 134. The delayed horizontal synchronization signal 134 may be substantially the same as the horizontal synchronization signal 116, however, the delayed horizontal synchronization signal 134 may be delayed by the duration it takes the video data processing pipeline 138 (including the video source 140 and the video processor 146) to generate the processed video data 148 from the video data 144, for example. Thus, the delayed horizontal synchronization signal 134 may be synchronized with the processed video data 148. It is not required that delayed horizontal sync signal 134 delay the exact duration it takes video data processing pipeline 138 (including video source 140 and video processor 146 ) to generate processed video data 148 , as long as the degree of synchronization is sufficient to enable proper operation of display 150 .

[0050] Similarly, the video timing generator 102 may generate a delayed vertical synchronization signal 136 at least in part in response to the delayed vertical synchronization counter 126. When the delayed vertical synchronization counter 126 has counted a number of clock cycles corresponding to the timing of starting a new grid, the video timing generator 102 may generate the delayed vertical synchronization signal 136. The delayed vertical synchronization signal 136 may be substantially the same as the vertical synchronization signal 118, however, the vertical synchronization signal 136 may be delayed by the duration it takes the delayed video data processing pipeline 138, for example, to generate the processed video data 148 from the video data 144. Thus, the delayed vertical synchronization signal 136 may be synchronized with the processed video data 148. It is not required that the delayed vertical synchronization signal 136 be delayed by the duration it takes the delayed video data processing pipeline 138 (including the video source 140 and the video processor 146) to generate the processed video data 148, as long as the degree of synchronization is sufficient to enable proper operation of the display 150.

[0051] The video timing generator 102 may provide a delayed horizontal sync signal 134 and a delayed vertical sync signal 136 to the display 150 at respective ones of the delayed sync outputs 132. Additionally, the video timing generator 102 may provide a delayed data valid signal 130 (which may be the same as the delayed data valid signal 122) to the display 150 at the delayed data valid output 128. In another example, the video data processing pipeline 138 may provide the delayed data valid signal 122 to the display 150, for example, from the output 154, and the delayed data valid signal 130 may not be required.

[0052] Figure 2 2 is a functional block diagram depicting a system 200 according to one or more examples. The system 200 includes a video timing generator 102, a video data processing pipeline 138, and a video source 140 at an input 152 of the video data processing pipeline 138.

[0053] The video timing generator 102 may generate a data valid signal 106 and provide the data valid signal 106 to a video source 140. The video source 140 may provide video data 144 to a video data processing pipeline 138 and provide a data valid signal 142 to the video data processing pipeline 138. The video data processing pipeline 138 may process the video data 144, provide the processed video data 148 to a display 150, delay the data valid signal 142 and provide a delayed data valid signal 122 to the video timing generator 102. The video timing generator 102 may generate a delayed horizontal sync signal 134 and a delayed vertical sync signal 136 in response, at least in part, to the delayed data valid signal 122 and provide the delayed horizontal sync signal 134 and the delayed vertical sync signal 136 to the display 150.

[0054] Figure 3 is a functional block diagram depicting an apparatus 300 according to one or more examples. The apparatus 300 may include an output 104 for providing a data valid signal 106 to a video source 140. The video source 140 provides video data 144 to a video data processing pipeline 138. The apparatus 300 may include an input 120 for receiving a delayed data valid signal 122 from the video data processing pipeline 138. The apparatus 300 may include a circuit 108 for generating a delayed horizontal sync signal 134 and a delayed vertical sync signal 136 at least in part in response to the received delayed data valid signal 122 (e.g., based on the timing of the delayed data valid signal 122, but not limited thereto).

[0055] In one or more examples, corresponding ones of the video data processing pipeline 138, the video source 140, the input 152, and the output 154 are optional, such as Figure 3 The video data processing pipeline 138, video source 140, input 152, and output 154 are indicated using dashed lines. In examples where the apparatus 300 does not include the video data processing pipeline 138, the apparatus 300 may be understood as the video timing generator 102.

[0056] Figure 4 400 according to one or more examples. One or more operations of process 400 may be performed by a device or system such as Figure 1 System 100, Figure 1 and / or Figure 2The video timing generator 102, Figure 1 and / or Figure 2 Video data processing pipeline 138, Figure 3 Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0057] At operation 402, process 400 provides a data valid signal to a video source to align the timing of video data provided by the video source with the timing of a display controller. The video source may provide video data to a video data processing pipeline. As a non-limiting example, the video source may provide a data valid signal to a display controller. Figure 1 , Figure 2 and / or Figure 3 The video source 140 provides Figure 1 , Figure 2 and / or Figure 3 The data valid signal 106 is provided.

[0058] At operation 404, process 400 receives a delayed data valid signal from the video data processing pipeline. As a non-limiting example, the delayed data valid signal may be received from the video data processing pipeline 138. Figure 1 , Figure 2 and / or Figure 3 The delayed data valid signal 122.

[0059] At operation 406, process 400 generates a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least in part in response to the received delayed data valid signal (e.g., in response to the timing indicated by the delayed data valid signal, but not limited thereto). As a non-limiting example, the delayed horizontal synchronization signal and the delayed vertical synchronization signal may be generated at least in part in response to the received delayed data valid signal. Figure 1 , Figure 2 and / or Figure 3 The received delayed data valid signal 122 is generated Figure 1 , Figure 2 and / or Figure 3 The delayed horizontal synchronization signal 134 and Figure 1 , Figure 2 and / or Figure 3 The delayed vertical synchronization signal 136.

[0060] Figure 5 5 is a flow chart of a process 500 according to one or more examples. In some examples, at least a portion of the process 500 may be performed by, for example, Figure 1 System 100, Figure 1 and / or Figure 2 The video timing generator 102, Figure 1 and / or Figure 2 Video data processing pipeline 138, Figure 3The device or system of the apparatus 300 or another device or system performs. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated depending on the desired implementation.

[0061] At operation 502, process 500 provides a data valid signal to a video source. The video source may provide video data to a video data processing pipeline. As a non-limiting example, the video source may provide a data valid signal to a video data processing pipeline. Figure 1 , Figure 2 and / or Figure 3 The video source 140 provides Figure 1 , Figure 2 and / or Figure 3 The data valid signal 106 is provided.

[0062] At operation 504, process 500 provides a horizontal synchronization signal and a vertical synchronization signal to the video source. As a non-limiting example, the video source 140 may be provided with a Figure 1 and / or Figure 2 The horizontal synchronization signal 116 and Figure 1 and / or Figure 2 The vertical synchronization signal 118 is provided.

[0063] At operation 506, process 500 provides video data from the video source to the video data processing pipeline. As a non-limiting example, the video data processing pipeline 138 may be provided with Figure 1 and / or Figure 2 The video data 144.

[0064] At operation 508, process 500 provides a data valid signal or a data valid signal delayed by the video source from the video source to the video data processing pipeline. As a non-limiting example, Figure 1 and / or Figure 2 The data valid signal 142 is provided from the video source 140 to the video data processing pipeline 138 (or more specifically, to the video data processing pipeline 138). Figure 1 and / or Figure 2 video processor 146).

[0065] At operation 510, process 500 processes video data at a video data processing pipeline. As a non-limiting example, video data 144 may be processed at video data processing pipeline 138 (or more specifically, at video processor 146 of video data processing pipeline 138).

[0066] At operation 512, process 500 provides the processed video data from the video data processing pipeline to a display. As a non-limiting example, Figure 1 and / or Figure 2 The processed video data 148 is provided from the video data processing pipeline 138 to Figure 1 and / or Figure 2 Display 150.

[0067] At operation 514, the process 500 delays the data valid signal by the video data processing pipeline (e.g., generates a version of the data valid signal having delayed timing compared to the data valid signal, but is not limited thereto). As a non-limiting example, the data valid signal 142 may be delayed by the video data processing pipeline 138 (or more specifically, delayed at the video processor 146 of the video data processing pipeline 138).

[0068] At operation 516, process 500 provides the delayed data valid signal from the video data processing pipeline to the video timing generator. As a non-limiting example, Figure 1 , Figure 2 and / or Figure 3 The delayed data valid signal 122 is provided from the video data processing pipeline 138 to Figure 1 and / or Figure 2 The video timing generator 102 or Figure 3 device 300.

[0069] At operation 518, process 500 receives a delayed data valid signal from the video data processing pipeline. As a non-limiting example, delayed data valid signal 122 may be received from video data processing pipeline 138 (eg, at input 120 of video timing generator 102).

[0070] At operation 520, process 500 generates a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least in part in response to the received delayed data valid signal. As a non-limiting example, the delayed horizontal synchronization signal and the delayed vertical synchronization signal may be generated at least in part in response to the received delayed data valid signal 122. Figure 1 , Figure 2 and / or Figure 3 The delayed horizontal synchronization signal 134 and Figure 1 , Figure 2 and / or Figure 3 The delayed vertical synchronization signal 136.

[0071] At operation 522, process 500 provides a delayed horizontal synchronization signal and a delayed vertical synchronization signal to a display. As a non-limiting example, delayed horizontal synchronization signal 134 and delayed vertical synchronization signal 136 may be provided to display 150.

[0072] At operation 524, process 500 provides a delayed data valid signal to the display. As a non-limiting example, the display 150 may be provided with a delayed data valid signal. Figure 1 and / or Figure 2 The delayed data valid signal 130.

[0073] Modifications, additions, or omissions may be made to process 400 and / or process 500 without departing from the scope of the present disclosure. For example, the operations of process 400 and / or process 500 may be implemented in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without departing from the essence of the disclosed examples.

[0074] Figure 6 600 is a block diagram of a device 600 that, in one or more examples, can be used to implement various functions, operations, actions, processes, or methods disclosed herein. Device 600 includes one or more processors 602 (sometimes referred to herein as "processor 602") that can be operatively coupled to one or more devices such as a data storage device (sometimes referred to herein as "storage device 604"), but is not limited to this. Storage device 604 includes machine executable code 606 stored thereon (e.g., stored on a computer readable memory, but is not limited to this), and processor 602 includes logic circuit system 608. Machine executable code 606 includes information describing functional elements that can be implemented by logic circuit system 608 (e.g., executed by the logic circuit system). Logic circuit system 608 implements (e.g., executes) the functional elements described by machine executable code 606. When the functional elements described by machine executable code 606 are executed, device 600 should be considered as dedicated hardware that can perform the functional elements disclosed herein. In one or more examples, processor 602 may execute the functional elements described by machine executable code 606 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0075] When implemented by the logic circuitry 608 of the processor 602, the machine executable code 606 may adapt the processor 602 to perform the operations of the examples disclosed herein. For example, the machine executable code 606 may adapt the processor 602 to perform Figure 4 Course 400 and / or Figure 5 For example, the machine executable code 606 may cause the processor 602 to execute at least a portion or all of the process 500. Figure 1 and / or Figure 2 The video timing generator 102, Figure 1 , Figure 2 and / or Figure 3 The video data processing pipeline 138 and / or Figure 3 The device 300 (but not limited to) may perform at least a portion or all of the operations discussed above.

[0076] Processor 602 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor executes computing instructions (e.g., software code, but not limited to this) related to the example, the general-purpose computer is considered to be a special-purpose computer. It should be noted that a general-purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, processor 602 may include any conventional processor, controller, microcontroller or state machine. Processor 602 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0077] In one or more examples, the storage device 604 includes a volatile data storage device (e.g., a random access memory (RAM), but not limited thereto), a non-volatile data storage device (e.g., a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), but not limited thereto). In one or more examples, the processor 602 and the storage device 604 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SOC), but not limited thereto). In one or more examples, the processor 602 and the storage device 604 may be implemented into separate devices.

[0078] In one or more examples, machine executable code 606 may include computer readable instructions (e.g., software code, firmware code, but not limited thereto). By way of non-limiting example, the computer readable instructions may be stored by storage device 604, directly accessed by processor 602, and executed by processor 602 using at least logic circuitry 608. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 604, sent to a memory device (not shown) for execution, and executed by processor 602 using at least logic circuitry 608. Thus, in one or more examples, logic circuitry 608 includes logic circuitry that may be configured electrically.

[0079] In one or more examples, machine executable code 606 may describe hardware (e.g., circuits, but not limited to) to be implemented in logic circuitry 608 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) may be used, such as, but not limited to, an Institute of Electrical and Electronics Engineers (IEEE) standard hardware description language (HDL). By way of non-limiting example, a Verilog TM 、SystemVerilog TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL TM ).

[0080] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, micro-operations to be performed by hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit system 608 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic component, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in one or more examples, the machine executable code 606 may include an HDL, RTL, GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0081] In examples where machine executable code 606 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 604) may implement the hardware description described by machine executable code 606. By way of non-limiting example, processor 602 may include a programmable logic device (e.g., an FPGA or PLC, but not limited thereto), and logic circuitry 608 may be electrically controlled to implement circuits corresponding to the hardware description into logic circuitry 608. Also by way of non-limiting example, logic circuitry 608 may include hard-wired logic manufactured by a manufacturing system (not shown, but including storage 604) according to the hardware description of machine executable code 606.

[0082] Regardless of whether the machine executable code 606 includes computer readable instructions or a hardware description, the logic circuit system 608, when implementing the functional elements of the machine executable code 606, performs the functional elements described by the machine executable code 606. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0083] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes to the extent that one skilled in the art would understand that the given parameter, property, or condition is satisfied with minor variations (such as within acceptable manufacturing tolerances). For example, a substantially satisfied parameter may be at least about 90% satisfied, at least about 95% satisfied, or even at least about 99% satisfied.

[0084] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that can perform the actions of a module or component or software object or software routine that can be stored on or executed by general hardware of a computing system (e.g., computer-readable media, processing devices, but not limited thereto). In one or more examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads, but not limited thereto). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on or executed by general hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0085] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements of the elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0086] Terms used in this disclosure, and especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", and the term "comprising" should be interpreted as "including but not limited to", but not limited to). As used herein, "each" means "some or all". As used herein, "each" means "all".

[0087] Additionally, if a specific number of introduced claim expressions is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim expressions. However, the use of such phrases should not be construed to imply that a claim expression introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim expression to an example containing only one such expression, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" or "an" means "at least one" or "one or more"); the same is true when a claim expression is introduced using a definite article.

[0088] Additionally, even if a specific number of introduced claim expressions is explicitly recited, those skilled in the art will recognize that such expressions should be interpreted to mean at least the number of expressions (e.g., the unmodified expression "two expressions" means at least two expressions, or two or more expressions, in the absence of other modifying elements). Furthermore, in those instances where conventional expressions like "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0089] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0090] Additional non-limiting embodiments of the present disclosure may include:

[0091] Embodiment 1: A device comprising: an output end, the output end being used to provide a data valid signal to a video source, the video source operating to provide video data to a video data processing pipeline; an input end, the input end being used to receive a delayed data valid signal from the video data processing pipeline; and a circuit, the circuit being used to generate a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least partially in response to the received delayed data valid signal.

[0092] Embodiment 2: According to the device described in Embodiment 1, the device includes a delayed synchronization output terminal, and the delayed synchronization output terminal is used to provide the delayed horizontal synchronization signal and the delayed vertical synchronization signal to the display respectively.

[0093] Embodiment 3: The device according to any one of Embodiments 1 and 2 comprises a delayed data valid output terminal, and the delayed data valid output terminal is used to provide the delayed data valid signal to the display.

[0094] Embodiment 4: An apparatus according to any one of Embodiments 1 to 3, wherein the circuit includes a delayed horizontal synchronization counter and a delayed vertical synchronization counter, the circuit is used to initialize the delayed horizontal synchronization counter and the delayed vertical synchronization counter at least partially in response to the received delayed data valid signal, the circuit is used to generate the delayed horizontal synchronization signal at least partially in response to the delayed horizontal synchronization counter, and the circuit is used to generate the delayed vertical synchronization signal at least partially in response to the delayed vertical synchronization counter.

[0095] Embodiment 5: According to the device described in any one of Embodiments 1 to 4, the device comprises a synchronization output terminal, and the synchronization output terminal is used to provide a horizontal synchronization signal and a vertical synchronization signal to the video source respectively.

[0096] Embodiment 6: A device according to any one of Embodiments 1 to 5, wherein the circuit includes a horizontal synchronization counter and a vertical synchronization counter, wherein the circuit is used to generate a horizontal synchronization signal at least partially in response to the horizontal synchronization counter, wherein the circuit is used to generate a vertical synchronization signal at least partially in response to the vertical synchronization counter, wherein the device also includes a synchronization output terminal, and the synchronization output terminal is used to provide the horizontal synchronization signal and the vertical synchronization signal to the video source respectively.

[0097] Embodiment 7: An apparatus according to any one of Embodiments 1 to 6, wherein the output terminal includes a data valid output terminal, wherein the circuit includes: a delayed horizontal synchronization counter, the delayed horizontal synchronization counter is used to count clock cycles, the circuit is used to generate the delayed horizontal synchronization signal at least partially in response to the clock cycle counted by the delayed horizontal synchronization counter, and the delayed horizontal synchronization counter is initialized at least partially in response to the received delayed data valid signal; and a delayed vertical synchronization counter, the delayed vertical synchronization counter is used to count clock cycles, the circuit is used to generate the delayed vertical synchronization signal at least partially in response to the clock cycle counted by the delayed vertical synchronization counter, and the delayed vertical synchronization counter is initialized at least partially in response to the received delayed data valid signal, and wherein the apparatus includes: a delayed synchronization output terminal, the delayed synchronization output terminal is used to provide the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display; and a delayed synchronization output terminal, the delayed synchronization output terminal is used to provide the delayed data valid signal to the display.

[0098] Embodiment 8: A device according to any one of Embodiments 1 to 7, wherein the circuit comprises: a horizontal synchronization counter, the horizontal synchronization counter being used to count clock cycles, the circuit being used to generate a horizontal synchronization signal at least partially in response to the clock cycles counted by the horizontal synchronization counter; and a vertical synchronization counter, the vertical synchronization counter being used to count clock cycles, the circuit being used to generate a vertical synchronization signal at least partially in response to the clock cycles counted by the vertical synchronization counter, and wherein the device comprises: a synchronization output terminal, the synchronization output terminal being used to provide the horizontal synchronization signal and the vertical synchronization signal to the video source.

[0099] Embodiment 9: A system, comprising: a video timing generator; a video data processing pipeline; and a video source; the video timing generator is used to: generate a data valid signal; and provide the data valid signal to the video source; the video source is used to: provide video data to the video data processing pipeline; and provide the data valid signal or the data valid signal delayed by the video source to the video data processing pipeline; the video data processing pipeline is used to: process the video data; provide the processed video data to a display; delay the data valid signal provided by the video source; and provide the delayed data valid signal to the video timing generator; the video timing generator is used to: generate a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least partially in response to the delayed data valid signal; and provide the delayed horizontal synchronization signal, the delayed vertical synchronization signal and the delayed data valid signal to the display.

[0100] Embodiment 10: The system of Embodiment 9, wherein the video timing generator is used to provide the delayed data valid signal to the display.

[0101] Embodiment 11: The system according to any one of embodiments 9 and 10, wherein the video timing generator is used to generate a horizontal synchronization signal and a vertical synchronization signal and provide the horizontal synchronization signal and the vertical synchronization signal to the video source respectively.

[0102] Embodiment 12: The system according to any one of embodiments 9 to 11, wherein the video source does not provide the horizontal synchronization signal and the vertical synchronization signal to the video processor of the video data processing pipeline respectively.

[0103] Embodiment 13: A system according to any one of Embodiments 9 to 12, wherein a video processor of the video data processing pipeline does not receive any of the horizontal synchronization signal, the vertical synchronization signal, the delayed horizontal synchronization signal, and the delayed vertical synchronization signal.

[0104] Embodiment 14: A system according to any one of Embodiments 9 to 13, wherein the video processor of the video data processing pipeline does not include circuitry for handling any of the horizontal synchronization signal, the vertical synchronization signal, the delayed horizontal synchronization signal, and the delayed vertical synchronization signal.

[0105] Embodiment 15: The system of any one of Embodiments 9 to 14, wherein the video data processing pipeline is configured to delay the data valid signal for a duration associated with the processing of the video data.

[0106] Embodiment 16: A method, comprising: providing a data valid signal to a video source, the video source being used to provide video data to a video data processing pipeline; receiving a delayed data valid signal from the video data processing pipeline; and generating a delayed horizontal synchronization signal and a delayed vertical synchronization signal at least partially in response to receiving the delayed data valid signal.

[0107] Embodiment 17: The method according to Embodiment 16 includes providing the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display.

[0108] Embodiment 18: The method of any one of Embodiments 16 and 17, comprising providing the delayed data valid signal to a display.

[0109] Embodiment 19: According to the method described in any one of Embodiments 16 to 18, the method comprises: providing a horizontal synchronization signal and a vertical synchronization signal to the video source.

[0110] Embodiment 20: According to the method described in any one of Embodiments 16 to 19, the method comprises: providing video data from the video source to the video processor of the video data processing pipeline; and providing the data valid signal or the data valid signal delayed by the video source from the video source to the video processor of the video data processing pipeline.

[0111] Embodiment 21: According to the method described in any one of Embodiments 16 to 20, the method comprises: processing the video data at the video data processing pipeline; providing the processed video data from the video data processing pipeline to a display; delaying the data valid signal through the video data processing pipeline; and providing the delayed data valid signal from the video data processing pipeline to a video timing generator, the video timing generator generating the delayed horizontal synchronization signal and the delayed vertical synchronization signal.

[0112] Although the present disclosure has been described with respect to certain illustrative examples, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features of another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: an output terminal for providing a data valid signal to a video source, the video source operating to provide video data to a video data processing pipeline; an input end, the input end being used to receive a delayed data valid signal from the video data processing pipeline; and Circuitry is provided for generating a delayed horizontal sync signal and a delayed vertical sync signal in response, at least in part, to a received delayed data valid signal. 2 . The device according to claim 1 , comprising a delayed synchronization output terminal, wherein the delayed synchronization output terminal is used to provide the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display respectively. 3 . The apparatus according to claim 1 , comprising a delayed data valid output terminal, wherein the delayed data valid output terminal is used to provide the delayed data valid signal to a display.

4. The device according to claim 1, wherein the circuit comprises a delayed horizontal synchronization counter and a delayed vertical synchronization counter, The circuit is configured to initialize the delayed horizontal sync counter and the delayed vertical sync counter at least in part in response to the received delayed data valid signal, The circuit is configured to generate the delayed horizontal synchronization signal responsive at least in part to the delayed horizontal synchronization counter, and The circuit is configured to generate the delayed vertical synchronization signal responsive at least in part to the delayed vertical synchronization counter.

5. The apparatus according to claim 1, comprising a synchronization output terminal, wherein the synchronization output terminal is used to provide a horizontal synchronization signal and a vertical synchronization signal to the video source respectively.

6. The device according to claim 1, The circuit includes a horizontal synchronization counter and a vertical synchronization counter. wherein the circuit is configured to generate a horizontal synchronization signal responsive at least in part to the horizontal synchronization counter, wherein the circuit is configured to generate a vertical synchronization signal at least in part in response to the vertical synchronization counter, The device further comprises a synchronization output terminal, and the synchronization output terminal is used to provide the horizontal synchronization signal and the vertical synchronization signal to the video source respectively.

7. The apparatus of claim 1, wherein the output terminal comprises a data valid output terminal, wherein the circuit comprises: a delayed horizontal synchronization counter for counting clock cycles, the circuit for generating the delayed horizontal synchronization signal responsive at least in part to counted clock cycles of the delayed horizontal synchronization counter, the delayed horizontal synchronization counter being initialized at least in part responsive to a received delayed data valid signal; and a delayed vertical synchronization counter for counting clock cycles, the circuit for generating the delayed vertical synchronization signal at least in part in response to the counted clock cycles of the delayed vertical synchronization counter, the delayed vertical synchronization counter being initialized at least in part in response to the received delayed data valid signal, and The device comprises: A delayed synchronization output terminal, the delayed synchronization output terminal is used to provide the delayed horizontal synchronization signal and the delayed vertical synchronization signal to the display; and A delayed synchronization output terminal is used to provide the delayed data valid signal to the display.

8. The apparatus of claim 7, wherein the circuit comprises: a horizontal synchronization counter for counting clock cycles, the circuit for generating a horizontal synchronization signal responsive at least in part to the counted clock cycles of the horizontal synchronization counter; and a vertical synchronization counter for counting clock cycles, the circuit for generating a vertical synchronization signal at least in part in response to the counted clock cycles of the vertical synchronization counter, and The device comprises: A synchronization output terminal, wherein the synchronization output terminal is used to provide the horizontal synchronization signal and the vertical synchronization signal to the video source.

9. A system, comprising: Video timing generator; Video data processing pipeline; and Video source; The video timing generator is used to: Generate a data valid signal; as well as providing the data valid signal to the video source; The video source is used to: Providing video data to the video data processing pipeline; as well as providing the data valid signal or the data valid signal delayed by the video source to the video data processing pipeline; The video data processing pipeline is used to: processing the video data; providing processed video data to a display; delaying the data valid signal provided by the video source; and providing a delayed data valid signal to the video timing generator; The video timing generator is used to: generating a delayed horizontal synchronization signal and a delayed vertical synchronization signal responsive at least in part to the delayed data valid signal; and The delayed horizontal sync signal, the delayed vertical sync signal, and the delayed data valid signal are provided to the display.

10. The system of claim 9, wherein the video timing generator is used to provide the delayed data valid signal to the display.

11. The system of claim 9, wherein the video timing generator is used to generate a horizontal synchronization signal and a vertical synchronization signal and provide the horizontal synchronization signal and the vertical synchronization signal to the video source, respectively.

12. The system of claim 11, wherein the video source does not provide the horizontal synchronization signal and the vertical synchronization signal, respectively, to a video processor of the video data processing pipeline.

13. The system of claim 11, wherein a video processor of the video data processing pipeline does not receive any of the horizontal synchronization signal, the vertical synchronization signal, the delayed horizontal synchronization signal, and the delayed vertical synchronization signal.

14. The system of claim 9, wherein a video processor of the video data processing pipeline does not include circuitry for handling any of a horizontal synchronization signal, a vertical synchronization signal, the delayed horizontal synchronization signal, and the delayed vertical synchronization signal.

15. The system of claim 9, wherein the video data processing pipeline is to delay the data valid signal for a duration associated with the processing of the video data.

16. A method comprising: providing a data valid signal to a video source, wherein the video source is used to provide video data to a video data processing pipeline; receiving a delayed data valid signal from the video data processing pipeline; as well as A delayed horizontal synchronization signal and a delayed vertical synchronization signal are generated at least in part in response to receiving the delayed data valid signal.

17. The method of claim 16, comprising providing the delayed horizontal synchronization signal and the delayed vertical synchronization signal to a display.

18. The method of claim 16, comprising providing the delayed data valid signal to a display.

19. The method according to claim 16, comprising: A horizontal synchronization signal and a vertical synchronization signal are provided to the video source.

20. The method according to claim 16, comprising: a video processor that provides video data from the video source to the video data processing pipeline; as well as The data valid signal or the data valid signal delayed by the video source is provided from the video source to a video processor of the video data processing pipeline.

21. The method according to claim 16, comprising: processing the video data at the video data processing pipeline; providing processed video data from the video data processing pipeline to a display; delaying the data valid signal through the video data processing pipeline; as well as The delayed data valid signal is provided from the video data processing pipeline to a video timing generator, which generates the delayed horizontal sync signal and the delayed vertical sync signal.

Images