Gate drive circuit, power conversion device, and control method for gate drive circuit

Abstract

The gate drive circuit includes modulation circuits 2 and 3, a turn-on rectifier circuit 4, and a turn-off rectifier circuit 5. Modulation circuits 2 and 3 make the frequencies of the first modulation signal vTr1 and the second modulation signal vTr2 variable according to the turn-on command width and turn-off command width of the gate control instruction. The turn-on command width is the same as the duration of one positive pulse of the first modulation signal vTr1, and the turn-on command width is the same as the duration of one negative pulse of the first modulation signal vTr1. Whenever a turn-on command is received, positive and negative pulses of the first modulation signal vTr1 are output alternately. When the pulse transformer is driven by a DC / AC modulation circuit, the minimum turn-on pulse width limitation is relaxed while suppressing bias magnetization.

Description

Technical Field

[0001] This invention relates to a modulation method for the gate drive circuit of a series-driven power converter. Background Technology

[0002] In circuits that drive semiconductor devices in series, pulse transformers are used for gate driving to ensure simultaneous switching.

[0003] However, when using a DC / AC modulation circuit to drive a pulse transformer, in order to deal with the bias magnetism, the duration of the output positive pulse and negative pulse must be the same.

[0004] Figure 17 This refers to the operating waveform in a DC / AC modulation circuit where the minimum on-pulse width is limited due to the influence of hardware such as the driver IC. Because both positive and negative pulses are restricted, the minimum on-pulse width is twice the time. For example, when the minimum pulse width is set to 100ns, the modulation circuit cannot output pulses shorter than 200ns, thus limiting the command value.

[0005] This leads to an increase in the error between the gating command and the actual switching action of the semiconductor device, meaning that the output voltage accuracy of the inverter deteriorates.

[0006] Based on the above situation, providing the following gate drive circuit has become a technical issue, in which the minimum turn-on pulse width limitation is relaxed while the bias magnetization is suppressed when the pulse transformer is driven by the DC / AC modulation circuit.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2006-271041 Summary of the Invention

[0010] The present invention addresses the aforementioned problems and provides one embodiment of a gate driving circuit, characterized in that the gate driving circuit comprises: a modulation circuit that outputs a first modulation signal and a second modulation signal based on a gate control instruction for turning on and off; a turn-on rectifier circuit comprising: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting a voltage applied to the turn-on primary winding, and a turn-on tertiary winding; a first diode circuit for rectifying the output of the turn-on secondary winding; and a second diode circuit for rectifying the output of the turn-on tertiary winding; and a turn-off rectifier circuit comprising: a second pulse transformer having a turn-off primary winding to which the second modulation signal is applied, and a second pulse transformer for transforming and outputting a voltage applied to the turn-off primary winding. The circuit includes a voltage-transformed secondary winding and a tertiary winding on the disconnected side; a third diode circuit that rectifies the output of the secondary winding on the disconnected side; and a fourth diode circuit that rectifies the output of the tertiary winding on the disconnected side. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gate command's on and off commands. The width of the on command is the same as the duration of one positive pulse of the first modulation signal, and the width of the on command is the same as the duration of one negative pulse of the first modulation signal. Whenever the on command is received, the positive pulse and the negative pulse of the first modulation signal are output alternately.

[0011] Additionally, another approach is a gate driving circuit, characterized in that the gate driving circuit comprises: a modulation circuit that outputs a first modulation signal and a second modulation signal based on a gate control instruction's on and off instructions; an on-side rectifier circuit comprising: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding that transform and outputs the voltage applied to the on-side primary winding; a first diode circuit that rectifies the output of the on-side secondary winding; and a second diode circuit that rectifies the output of the on-side tertiary winding; and an off-side rectifier circuit comprising: a second pulse transformer having an off-side primary winding to which the second modulation signal is applied, and a voltage transformation circuit that transforms the voltage applied to the off-side primary winding. The circuit outputs a disconnected secondary winding and a disconnected tertiary winding; a third diode circuit rectifies the output of the disconnected secondary winding; and a fourth diode circuit rectifies the output of the disconnected tertiary winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gate command's on and off commands. The width of the off command is the same as the duration of one positive pulse of the second modulation signal, and the width of the off command is the same as the duration of one negative pulse of the second modulation signal. Whenever the off command is received, the positive pulse and the negative pulse of the second modulation signal are output alternately.

[0012] Additionally, as an embodiment, the modulation circuit is characterized by comprising: a rising edge detection circuit for detecting the rising edge of the gating instruction; a latching circuit for latching the gating instruction at a timing when the rising edge of the gating instruction is detected, and releasing the latch at the timing when the rising edge of the gating instruction is detected again while in the latched state; a first AND circuit for outputting a logical AND of the gating instruction and the output of the latching circuit; a NOT circuit for inverting the output of the latching circuit; a second AND circuit for outputting a logical AND of the gating instruction and the output of the NOT circuit; a driver IC for controlling the DC / AC modulation circuit based on the output of the first AND circuit and the output of the second AND circuit; and the DC / AC modulation circuit for outputting the first modulation signal based on the control of the driver IC.

[0013] Additionally, another approach is a gate driving circuit, characterized in that the gate driving circuit comprises: a modulation circuit that outputs a first modulation signal and a second modulation signal based on a gate control instruction for turning on and off; a turn-on rectifier circuit comprising: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, and a turn-on secondary winding and a turn-on tertiary winding for transforming and outputting the voltage applied to the turn-on primary winding; a first diode circuit for rectifying the output of the turn-on secondary winding; and a second diode circuit for rectifying the output of the turn-on tertiary winding; and a turn-off rectifier circuit comprising: a second pulse transformer having a turn-off primary winding to which the second modulation signal is applied, and a turn-off primary winding for transforming and outputting the voltage applied to the turn-off primary winding. The circuit includes a secondary winding on the open side and a tertiary winding on the closed side; a third diode circuit that rectifies the output of the secondary winding on the closed side; and a fourth diode circuit that rectifies the output of the tertiary winding on the closed side. The gate drive circuit controls the semiconductor element being driven according to the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gate command's on and off instructions. During the on instruction period of the gate command, the first modulation signal outputs a positive or negative pulse. The polarity of the first modulation signal is reversed at the beginning of each cycle of the gate command. The polarity of the first modulation signal is reversed when the output period of the first modulation signal has elapsed for a predetermined time.

[0014] Additionally, another approach is a gate driving circuit, characterized in that the gate driving circuit comprises: a modulation circuit that outputs a first modulation signal and a second modulation signal based on a gate control instruction for turning on and off; a turn-on rectifier circuit comprising: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, and a turn-on secondary winding and a turn-on tertiary winding for transforming and outputting the voltage applied to the turn-on primary winding; a first diode circuit for rectifying the output of the turn-on secondary winding; and a second diode circuit for rectifying the output of the turn-on tertiary winding; and a turn-off rectifier circuit comprising: a second pulse transformer having a turn-off primary winding to which the second modulation signal is applied, and a turn-off primary winding for transforming and outputting the voltage applied to the turn-off primary winding. The circuit includes a secondary winding on the open side and a tertiary winding on the closed side; a third diode circuit that rectifies the output of the secondary winding on the closed side; and a fourth diode circuit that rectifies the output of the tertiary winding on the closed side. The gate drive circuit controls the semiconductor element being driven according to the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gate command's on and off instructions. During the off instruction period of the gate command, the second modulation signal outputs a positive or negative pulse. The polarity of the second modulation signal is reversed at the beginning of each cycle of the gate command. The polarity of the second modulation signal is reversed when the output period of the second modulation signal has elapsed for a predetermined time.

[0015] Additionally, as an embodiment, it is characterized by comprising: an inversion permission signal generation unit that generates an inversion permission signal that switches between "1" and "0" on the falling edge of the gating command; a gating signal generation unit that generates gating signals GATE1 and GATE2, wherein gating signal GATE1 outputs "1" when the gating command is enabled and from the time the gating command is enabled until a predetermined time has elapsed, and is "0" otherwise; gating signal GATE2 outputs "1" after a predetermined time has elapsed from the time the gating command is enabled and is "0" otherwise; and a polarity selector unit that, when the inversion permission signal is "0", sets the positive output gating signal GATE_P to "1" when gating signal GATE1 is "1", and sets the positive output gating signal GATE_P to "1" when gating signal GATE2 is "1". The negative output gate signal GATE_N is set to "1" when the negative output gate signal GATE_P is set to "1", and the positive output gate signal GATE_P and the negative output gate signal GATE_N are set to "0" when the inversion permission signal is "1". When the gate signal GATE1 is "1", the negative output gate signal GATE_N is set to "1" when the gate signal GATE2 is "1", and the positive output gate signal GATE_P is set to "1" when the gate signal GATE2 is "1". Otherwise, the positive output gate signal GATE_P and the negative output gate signal GATE_N are set to "0". The driver IC controls the DC / AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N. The DC / AC modulation circuit outputs the first modulation signal based on the control of the driver IC.

[0016] Additionally, as an embodiment, the DC / AC modulation circuit is characterized as a modulation signal generation circuit, comprising: a synchronization circuit for synchronizing the gate command with a clock signal; a rising edge detection unit for detecting the rising edge of the output of the synchronization circuit; a falling edge detection unit for detecting the falling edge of the output of the synchronization circuit; a disconnect pulse width measurement unit that starts counting when the falling edge of the output of the synchronization circuit is detected and stops counting when the rising edge of the output of the synchronization circuit is detected, and adds the count value whenever the clock signal is input; and a disconnect-side 1-bit shift circuit for synchronizing the output of the disconnect pulse width measurement unit. The output is 1 / 2; the disconnect-side latch circuit latches the output of the disconnect-side 1-bit shift circuit at the rising edge of the output of the synchronization circuit; a first decrement counter is input to the output of the disconnect-side latch circuit and the clock signal, and the count value is subtracted whenever the clock signal is input; a second decrement counter is input to the output of the disconnect-side latch circuit, the output of the first decrement counter and the clock signal, and the count value is subtracted whenever the clock signal is input, wherein the modulation signal generation circuit outputs the second modulation signal until the counters of the first decrement counter and the second decrement counter become zero.

[0017] Additionally, as an embodiment, the DC / AC modulation circuit comprises: a capacitor; a full-bridge circuit for generating a turn-on signal, having a first and a second semiconductor element on the turn-on side connected in series between the two ends of the capacitor, and a third and a fourth semiconductor element on the turn-on side connected in series between the two ends of the capacitor; and a full-bridge circuit for generating a turn-off signal, having a first and a second semiconductor element on the turn-off side connected in series between the two ends of the capacitor, and a third and a fourth semiconductor element on the turn-off side connected in series between the two ends of the capacitor, wherein the primary winding of the turn-on side of the first pulse transformer is connected between the connection point of the first and second semiconductor elements on the turn-on side and the connection point of the third and fourth semiconductor elements on the turn-on side, and the primary winding of the turn-off side of the second pulse transformer is connected between the connection point of the first and second semiconductor elements on the turn-off side and the connection point of the third and fourth semiconductor elements on the turn-off side.

[0018] Additionally, as an embodiment, the modulation circuit is characterized by comprising: a synchronization circuit for synchronizing the gating command with a clock signal; a rising edge detection unit for detecting the rising edge of the output of the synchronization circuit; a falling edge detection unit for detecting the falling edge of the output of the synchronization circuit; a disconnect pulse width measuring unit that starts counting when a falling edge of the output of the synchronization circuit is detected and stops counting when a rising edge of the output of the synchronization circuit is detected, and adds the count value whenever the clock signal is input; a disconnect-side 1-bit shift circuit that halves the output of the disconnect pulse width measuring unit; and a disconnect-side latch circuit that, in the synchronization... The rising edge of the circuit output latches the output of the disconnected 1-bit shift circuit; a first decrement counter, input to the output of the disconnected latch circuit and the clock signal, subtracts the count value each time the clock signal is input, and outputs the gating instructions of the first and fourth semiconductor elements on the disconnected side until the count value becomes 0; a second decrement counter, input to the output of the disconnected latch circuit, the output of the first decrement counter and the clock signal, subtracts the count value each time the clock signal is input, and outputs the gating instructions of the second and third semiconductor elements on the disconnected side until the count value becomes 0.

[0019] Additionally, as an embodiment, the disconnect pulse width measuring unit is characterized by having an n (n: an integer greater than or equal to 1) level structure. In the first level, it includes: a first-on-side D flip-flop circuit that inputs the clock signal to the D-FF terminal and inputs the output of the / Q terminal of the first-on-side D flip-flop circuit to the D terminal, wherein the output of the Q terminal is a 1-bit signal. In the second level, it includes: a second-on-side XOR circuit that inputs the output of the Q terminal of the first-on-side D flip-flop circuit and the output of the Q terminal of the second-on-side D flip-flop circuit; and the second-on-side D flip-flop circuit that inputs the clock signal to the D-FF terminal and inputs the output of the second-on-side XOR circuit to the D terminal, wherein the output of the Q terminal is a 2-bit signal. In the third level, it includes: a third-on-side AND circuit that inputs the output of the Q terminal of the first-on-side D flip-flop circuit and the output of the second-on-side D flip-flop circuit. The output of the Q terminal of the D flip-flop circuit on the third turn-on side; the XOR circuit on the third turn-on side inputs the output of the AND circuit on the third turn-on side and the output of the Q terminal of the D flip-flop circuit on the third turn-on side; and the D flip-flop circuit on the third turn-on side inputs the clock signal to the D-FF terminal, inputs the output of the XOR circuit on the third turn-on side to the D terminal, and the output of the Q terminal is a 3-bit signal. In the 4th to nth stages, it has: the AND circuit on the k-th turn-on side inputs a k (k: an integer from 4 to n)-1 bit signal and a (k-2) bit·(k-3) bit·……2 bit·1 bit signal; the XOR circuit on the k-th turn-on side inputs the output of the AND circuit on the k-th turn-on side and the output of the Q terminal of the D flip-flop circuit on the k-th turn-on side; and the D flip-flop circuit on the k-th turn-on side inputs the clock signal to the D-FF terminal, inputs the output of the XOR circuit on the k-th turn-on side to the D terminal, and the output of the Q terminal is a k-bit signal.

[0020] Additionally, as an embodiment, the first and second decrementing counters are characterized by an n-stage (n: an integer greater than or equal to 1) structure. In the first stage, the circuit includes: a first disconnect-side D flip-flop circuit that inputs the clock signal to the D-FF terminal and inputs the output of the / Q terminal of the first disconnect-side D flip-flop circuit to the D terminal, with the output of the Q terminal being a 1-bit signal; in the second stage, the circuit includes: a second disconnect-side XOR circuit that inputs the output of the / Q terminal of the first disconnect-side D flip-flop circuit and the output of the / Q terminal of the second disconnect-side D flip-flop circuit; and the second disconnect-side D flip-flop circuit that inputs the clock signal to the D-FF terminal and inputs the output of the second disconnect-side XOR circuit to the D terminal, with the output of the Q terminal being a 2-bit signal; and in the third stage, the circuit includes: a third disconnect-side AND circuit that inputs the output of the / Q terminal of the first disconnect-side D flip-flop circuit and the output of the second disconnect-side D flip-flop circuit. The output of the / Q terminal of the trigger circuit; the third disconnect-side XOR circuit, input to the output of the third disconnect-side AND circuit and the output of the / Q terminal of the third disconnect-side D trigger circuit; and the third disconnect-side D trigger circuit, inputting the clock signal to the D-FF terminal, inputting the output of the third disconnect-side XOR circuit to the D terminal, and the output of the Q terminal is a 3-bit signal, in the 4th to nth stages, having: the k-th disconnect-side AND circuit, inputting / k (k: an integer from 4 to n) - 1 bit signal and / (k-2) bit · / (k-3) bit ... / 2 bit · / 1 bit signal; the k-th disconnect-side XOR circuit, inputting the output of the k-th disconnect-side AND circuit and the output of the / Q terminal of the k-th disconnect-side D trigger circuit; and the k-th disconnect-side D trigger circuit, inputting the clock signal to the D-FF terminal, inputting the output of the k-th disconnect-side XOR circuit to the D terminal, and the output of the Q terminal is a k-bit signal.

[0021] According to the present invention, a gate drive circuit is provided that suppresses bias magnetization and relaxes the minimum turn-on pulse width limitation when the pulse transformer is driven by a DC / AC modulation circuit. Attached Figure Description

[0022] Figure 1 The circuit structure diagrams of the gate drive circuits in embodiments 1 and 2 are shown.

[0023] Figure 2 A timing diagram showing the waveforms of the gate drive circuit.

[0024] Figure 3 A block diagram is shown for the modulation circuit 3 of embodiments 1 and 2.

[0025] Figure 4 Timing diagrams are shown for each waveform of the modulation circuit 3 in embodiments 1 and 2.

[0026] Figure 5A diagram showing the disconnected pulse width measurement unit (n-stage incrementing counter).

[0027] Figure 6 A diagram illustrating an n-stage decrementing counter.

[0028] Figure 7 The diagram illustrates another example of modulation circuits 2 and 3 in embodiments 1 and 2.

[0029] Figure 8 A block diagram showing the control section of the modulation circuit 3 in embodiments 1 and 2.

[0030] Figure 9 Timing diagrams showing the waveforms of the control section of the modulation circuit 3 in embodiments 1 and 2 are provided.

[0031] Figure 10 A diagram illustrating the existing modulation signal and the modulation signal of Embodiment 1.

[0032] Figure 11 A block diagram showing the control section of the modulation circuit 2 in Embodiment 1.

[0033] Figure 12 A timing diagram showing the waveforms of the control section of the modulation circuit 2 in Embodiment 1 is provided.

[0034] Figure 13 To show Figure 2 , Figure 12 The output waveform and characteristics of the modulation circuit are shown in the figure.

[0035] Figure 14 A block diagram showing the control section of the modulation circuit 2 in Embodiment 2.

[0036] Figure 15 A timing diagram showing the waveforms of the modulation circuit 2 in Embodiment 2 is provided.

[0037] Figure 16 A timing diagram showing another example of the waveforms of the modulation circuit 2 in Embodiment 2.

[0038] Figure 17 To illustrate the timing diagram of the existing gating commands and modulation signals. Detailed Implementation

[0039] The following is based on Figures 1-16 Detailed description of embodiments 1 and 2 of the gate drive circuit of the present invention.

[0040] [Implementation Method 1]

[0041] In this embodiment 1, by measuring the gating command and changing the driving frequency of the pulse transformer according to its pulse width, the time resolution of the output pulse (the pulse width of the gating command) of the device is improved without increasing the switching loss of the modulation circuit.

[0042] Figure 1 This diagram shows the gate drive circuit of Embodiment 1. Figure 2 The timing diagrams shown represent the waveforms of the gate drive circuit. Figure 3 A block diagram of the modulation circuit is shown. Figure 4 The timing diagrams of the waveforms of the modulation circuit are shown.

[0043] First of all, Figure 1 The gate drive circuit will be explained. For example... Figure 1 As shown, the gate drive circuit of this embodiment 1 includes modulation circuits 2 and 3, a turn-on rectifier circuit 4, a turn-off rectifier circuit 5, a demodulation circuit 6, and a gate circuit 7. The gate drive circuit controls the semiconductor element 8, which is the object to be driven.

[0044] The gating command to turn on is output to modulation circuit 2. Conversely, the gating command to turn off is output to modulation circuit 3. Figure 1 The diagram shows a modulation circuit 2 that receives an on command and a modulation circuit 3 that receives an off command, but it can also be a structure where the on and off commands are input to a single modulation circuit.

[0045] The primary winding of the first pulse transformer Tr1 in the rectifier circuit 4 is connected to the modulation circuit 2. The first pulse transformer Tr1 has a primary winding on the turn-on side, a secondary winding on the turn-on side that transforms and outputs the voltage applied to the primary winding on the turn-on side, and a tertiary winding on the turn-on side. The first diode circuit db1 is connected to the secondary winding on the turn-on side of the first pulse transformer Tr1, and the second diode circuit db2 is connected to the tertiary winding on the turn-on side of the first pulse transformer Tr1.

[0046] The primary winding of the second pulse transformer Tr2 in the disconnected-side rectifier circuit 5 is connected to the modulation circuit 3. The second pulse transformer Tr2 has a primary winding on the disconnected side, a secondary winding on the disconnected side that transforms and outputs the voltage applied to the primary winding, and a tertiary winding on the disconnected side. A third diode circuit db3 is connected to the secondary winding on the disconnected side of the second pulse transformer Tr2, and a fourth diode circuit db4 is connected to the tertiary winding on the disconnected side of the second pulse transformer Tr2. The first to fourth diode circuits db1 to db4 are, for example, a full-bridge circuit.

[0047] Next, the demodulation circuit 6 will be described. The anode of the first diode D1 is connected to one terminal of the first diode circuit db1. The anode of the second diode D2 is connected to one terminal of the second diode circuit db2. The anode of the third diode D3 is connected to one terminal of the third diode circuit db3. The anode of the fourth diode D4 is connected to one terminal of the fourth diode circuit db4.

[0048] Capacitors C1 and C2 are connected in series between the cathodes of diodes D1 and D3 and the other terminals of diodes db2 and db4. The other terminals of diodes db1 and db3 are connected to the junction of capacitors C1 and C2. Additionally, the cathodes of diodes D2 and D4 are connected to the junction of capacitors C1 and C2.

[0049] One end of the first resistor R1 is connected to the anode of the first diode D1. The other end of the first resistor R1 is connected to the second terminal (drain terminal) of the second semiconductor element Q2, the first terminal (gate terminal) of the third semiconductor element Q3, and the first terminal (gate terminal) of the fourth semiconductor element Q4.

[0050] One end of the fourth resistor R4 and the first terminal (gate terminal) of the first semiconductor element Q1 are connected to the anode of the second diode D2. The other end of the fourth resistor R4 is connected to the other terminals of the second and fourth diode circuits db2 and db4.

[0051] One end of the second resistor R2 is connected to the anode of the fourth diode D4. The other end of the second resistor R2 is connected to the second terminal (drain terminal) of the first semiconductor element Q1 and one end of the third resistor R3. The third terminal (source terminal) of the first semiconductor element Q1 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0052] One end of the third resistor R3 is connected to one end of the fifth resistor R5 and the first terminal (gate terminal) of the second semiconductor element Q2. The other end of the fifth resistor R5 is connected to the other terminal of the second and fourth diode circuits db2 and db4. The third terminal (source terminal) of the second semiconductor element Q2 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0053] Next, the gate circuit 7 will be described. The first terminal (gate terminal) of the third semiconductor element Q3 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the third semiconductor element Q3 is connected to the cathode of the first diode D1. The third terminal (source terminal) of the third semiconductor element Q3 is connected to one end of the on-side resistor Ron.

[0054] The first terminal (gate terminal) of the fourth semiconductor element Q4 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the fourth semiconductor element Q4 is connected to one end of the disconnect-side resistor Roff. The third terminal (source terminal) of the fourth semiconductor element Q4 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0055] The other ends of the on-side resistor Ron and the off-side resistor Roff are connected to the first terminal (gate terminal) of the semiconductor element 8, which is the object being driven. The third terminal (source terminal) of the semiconductor element 8, which is the object being driven, is connected to the cathodes of the second and fourth diodes D2 and D4.

[0056] Here, the first modulation signal (voltage) applied to the primary winding on the turn-on side of the first pulse transformer Tr1 is set as vTr1, and the second modulation signal (voltage) applied to the primary winding on the turn-off side of the second pulse transformer Tr2 is set as vTr2. Furthermore, the voltage of the first capacitor C1 is set as Vg+, and the voltage of the second capacitor C2 is set as Vg-. Moreover, the gate voltage (voltage between the gate and source) of the semiconductor element 8, which is the target of the drive, is set as Vgs.

[0057] Similar to Patent Document 1, Figure 1 The circuit drives the first and second pulse transformers Tr1 and Tr2 by modulating the turn-on and turn-off signals at the frequency driving the first and second pulse transformers Tr1 and Tr2. While transmitting power, it also transmits on / off commands to the gate circuit 7 by inputting a signal to the demodulation circuit 6. At this time, a counter measures the pulse width input as the gate command, and the second pulse transformer Tr2 is driven at a frequency of one cycle of that width, while the first pulse transformer Tr1 is driven at a frequency of half a cycle of that width. This allows the first and second pulse transformers Tr1 and Tr2 to be modulated at a frequency suitable for the pulse width of the gate command, thus achieving high resolution.

[0058] Figure 1 The circuit is characterized by having a first pulse transformer Tr1 for generating a gating turn-on command and a second pulse transformer Tr2 for generating a gating turn-off command. A voltage is applied to the first pulse transformer Tr1 to send an turn-on command, and a voltage is applied to the second pulse transformer Tr2 to send a turn-off command.

[0059] By configuring the first and second pulse transformers Tr1 and Tr2 with three-stage windings, a negative bias voltage can be applied to the gate voltage Vgs. Vg+ is the voltage after rectification of the secondary winding voltage, and Vg- is the voltage after rectification of the tertiary winding voltage. The magnitudes of voltages Vg+ and Vg- can be adjusted by the turns ratio of the first and second pulse transformers Tr1 and Tr2 and the voltages applied to the first and second pulse transformers Tr1 and Tr2 (the first and second modulation signals) vTr1 and vTr2.

[0060] Assuming that the outputs of the third and fourth semiconductor elements Q3 and Q4 constituting the push-pull circuit have their gate resistance values ​​separated on the on and off sides, forming a structure where the circuit is connected via a resistor, thus omitting the diode. The output of the push-pull circuit can also be connected without a resistor.

[0061] First, an overview of the process when the connection is established. Figure 2 The timing diagram is shown. Figure 2 In the timing diagram, for simplicity, it is assumed that the gate voltage thresholds of semiconductor elements Q1, Q2, Q3, and Q4 (numbers 1 to 4) are ignored. Figure 2 As shown, when the gate command is high, the voltage of the first modulation signal vTr1 is applied to the first pulse transformer Tr1, and the first and second capacitors C1 and C2 are charged through the first and second diode circuits db1 and db2.

[0062] At this time, a voltage is applied between the gate and source of the first semiconductor element Q1, turning it on and turning off the second semiconductor element Q2. Because the second semiconductor element Q2 is off, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 are charged through the first resistor R1. Therefore, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the first capacitor C1, turning on the third semiconductor element Q3, and its gate voltage Vgs rises until it reaches the charging voltage vg+ of the first capacitor C1.

[0063] The following outlines what happens when the connection is broken. For example... Figure 2 As shown, when the gate command is low, the voltage of the second modulation signal vTr2 is applied to the second pulse transformer Tr2, and the first and second capacitors C1 and C2 are charged through the third and fourth diode circuits db3 and db4.

[0064] At this time, the gate-source of the second semiconductor element Q2 is charged through the second resistor R2, thus turning on the second semiconductor element Q2. Consequently, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the second capacitor C2, thus turning on the fourth semiconductor element Q4, and the gate voltage Vgs decreases until it reaches the charging voltage of the second capacitor C2, -vg-. By setting the above operation to one cycle, the on / off operation of the semiconductor element 8, which is the driven element, can be controlled.

[0065] Next, the method for generating the second modulation signal vTr2 in Embodiment 1 will be described. The second modulation signal vTr2 can be generated by... Figure 3 The modulation circuit 3 shown is implemented in the example structure. Additionally, Figure 4 The timing diagrams of the waveforms of modulation circuit 3 are shown.

[0066] In synchronization circuit 9, a gating command (transmitter output) and a clock signal are input to synchronize the gating command (oscillator output) with the clock signal. Rising edge detection unit 10 detects the rising edge of synchronization circuit 9. Falling edge detection unit 11 detects the falling edge of synchronization circuit 9.

[0067] When a falling edge of the synchronization circuit 9 is detected, the pulse width measurement unit (incrementing counter) 12 is disconnected to start counting. When a rising edge is detected, counting stops. The count value is incremented every time a clock signal is input.

[0068] At this point, it is assumed that the rising and falling edges are synchronized with the clock signal through the operation of the synchronization circuit 9. Based on this, the pulse width of the disconnection can be determined.

[0069] By using the disconnected side 1-bit shift circuit 13, the output (count value) of the disconnected pulse width measuring unit 12 is reduced to 1 / 2.

[0070] The disconnect-side latch circuit 14 latches the output of the disconnect-side 1-bit shift circuit 13 at the timing of detecting the rising edge.

[0071] In the modulation signal generation counter (first decrement counter) 15, the output of the disconnect-side latch circuit 14 and the clock signal are input, and the count value is subtracted each time the clock signal is input. In the modulation signal generation counter (second decrement counter) 16, the output of the disconnect-side latch circuit 14, the output of the first decrement counter 15 and the clock signal are input, and the count value is subtracted each time the clock signal is input.

[0072] In the modulation signal generation circuit 17, the circuit (AC / DC conversion circuit) is configured such that the outputs of the first and second decrementing counters 15 and 16 are input and the modulation signal is output until the count value becomes 0, thereby generating a second modulation signal vTr2 with a duty cycle of 50% and a pulse width of 1 cycle as an instruction.

[0073] Therefore, the frequency of the second modulation signal vTr2 can be suppressed to twice the switching frequency of the semiconductor element 8 that is being driven, and the time resolution of the pulse width of the gate command can be improved without increasing the driving frequency of the second pulse transformer Tr2.

[0074] Next, the disconnected pulse width measuring unit 12 (incrementing counter) will be explained. As an example, Figure 5 Show an incrementing counter with n levels (n: an integer greater than 1).

[0075] In stage 1, the clock signal CLK is input to the D-FF terminal of the first-on-side D flip-flop circuit 18a. The output of the / Q terminal of the first-on-side D flip-flop circuit 18a is input to the D terminal. The output of the Q terminal of the first-on-side D flip-flop circuit 18a is output as a 1-bit signal.

[0076] In the second stage, the output of the Q terminal of the D flip-flop circuit 18a on the first turn-on side and the output of the Q terminal of the D flip-flop circuit 18b on the second turn-on side are input to the XOR circuit 19b on the second turn-on side.

[0077] A clock signal CLK is input to the D-FF terminal of the second-on-side D flip-flop circuit 18b, and the output of the second-on-side XOR circuit 19b is input to the D terminal. The output of the Q terminal of the second-on-side D flip-flop circuit 18b is output as a 2-bit signal.

[0078] In level 3, on the third turn-on side and circuit 20c, input 1-bit signal and 2-bit signal.

[0079] In the XOR circuit 19c on the third turn-on side, the output of the AND circuit 20c on the third turn-on side and the output of the Q terminal of the D flip-flop circuit 18c on the third turn-on side are input.

[0080] In the third-on-side D flip-flop circuit 18c, the clock signal CLK is input to the D-FF terminal, and the output of the third-on-side XOR circuit 19c is input to the D terminal. The output of the Q terminal of the third-on-side D flip-flop circuit 18c is output as a 3-bit signal.

[0081] In this way, the incrementing counter consists of n stages. In the k-th stage (k: an integer from 4 to n), the k-th stage and the circuit 20k are input with k-1 bits of signal and (k-2) bits, (k-3) bits, ..., 2 bits and 1 bit of signal.

[0082] In the k-th XOR circuit 19k, the output signal of the k-th AND circuit 20k and the output of the Q terminal of the k-th D flip-flop circuit 18k are input.

[0083] In the k-th D flip-flop circuit 18k, the clock signal CLK is input to the D-FF terminal, and the output signal of the k-th XOR circuit 19k is input to the D terminal. The output of the Q terminal of the k-th D flip-flop circuit 18k is a k-bit signal.

[0084] Next, the first and second decrementing counters 15 and 16 will be explained. Figure 6 This shows a decrementing counter with an n-stage structure.

[0085] In stage 1, in the first disconnected-side D flip-flop circuit 21a, the clock signal CLK is input to the D-FF terminal, and the output of the / Q terminal of the first disconnected-side D flip-flop circuit 21a is input to the D terminal. The output of the Q terminal of the first disconnected-side D flip-flop circuit 21a is output as a 1-bit signal.

[0086] In the second stage, the XOR circuit 22b on the second disconnect side receives the output of the / Q terminal of the D flip-flop circuit 21a on the first disconnect side and the output of the / Q terminal of the D flip-flop circuit 21b on the second disconnect side.

[0087] In the second disconnected-side D flip-flop circuit 21b, the clock signal CLK is input to the D-FF terminal, and the output of the second disconnected-side XOR circuit 22b is input to the D terminal. The output of the Q terminal of the second disconnected-side D flip-flop circuit 21b is output as a 2-bit signal.

[0088] In the third stage, on the third disconnect side and circuit 23c, the output of the / Q terminal of the D flip-flop circuit 21a on the first disconnect side and the output of the / Q terminal of the D flip-flop circuit 21b on the second disconnect side are input.

[0089] In the XOR circuit 22c on the third disconnect side, the output of the AND circuit 23c on the third disconnect side and the output of the / Q terminal of the D flip-flop circuit 21c on the third disconnect side are input.

[0090] In the third disconnected-side D flip-flop circuit 21c, the clock signal CLK is input to the D-FF terminal, and the output of the third disconnected-side XOR circuit 22c is input to the D terminal. The output of the Q terminal of the third disconnected-side D flip-flop circuit 21c is output as a 3-bit signal.

[0091] In this way, the decrementing counter has n stages. In the k-th stage (k: an integer from 4 to n), the k-th stage is input to the circuit 23k as a / k-1 bit signal and / (k-2) bit · / (k-3) bit ... / 2 bit · / 1 bit signal.

[0092] In the k-th XOR circuit 22k, the output signal of the k-th AND circuit 23k and the output of the / Q terminal of the k-th D flip-flop circuit 21k are input.

[0093] In the k-th D flip-flop circuit 21k, the clock signal CLK is input to the D-FF terminal, and the output signal of the k-th XOR circuit 22k is input to the D terminal. The output of the Q terminal of the k-th D flip-flop circuit 26k is a k-bit signal.

[0094] Figure 5 , Figure 6 Increment and decrement counters are structures whose count values ​​are changed when a clock signal is input. Figure 5 In this process, a bit is added each time a count is performed. Figure 6 In this process, the count value is subtracted each time a count is performed.

[0095] The pulse width can be determined by reading the output of the binary number (1 bit to n bits) and multiplying it by the clock cycle. The number of stages in the counter can be increased according to the desired pulse width.

[0096] By using the circuit structure and control method described above, gate voltage can be output at high resolution with respect to gating commands.

[0097] Next, regarding the application Figure 7 The structure will be described as a modulation circuit in Embodiment 1. It is characterized by comprising: a full-bridge circuit 24 for generating an on signal, driving a first pulse transformer Tr1 that transmits the on signal; and a full-bridge circuit 25 for generating an off signal, driving a second pulse transformer Tr2 that transmits the off signal.

[0098] A full-bridge circuit 24 for generating an on signal and a full-bridge circuit 25 for generating an off signal are connected in parallel to capacitor C. The first and second semiconductor elements S1on and S2on on the on side are connected in series across capacitor C. Additionally, the third and fourth semiconductor elements S3on and S4on on the on side are connected in series across capacitor C. The first to fourth semiconductor elements S1on to S4on on the on side constitute the full-bridge circuit 24 for generating the on signal.

[0099] The primary windings of capacitor Ch1 and the first pulse transformer Tr1 on the turn-on side are connected between the connection points of the first and second semiconductor elements S1on and S2on on the turn-on side and the connection points of the third and fourth semiconductor elements S3on and S4on on the turn-on side.

[0100] On the disconnect side, semiconductor elements S1off and S2off are connected in series across capacitor C. Additionally, semiconductor elements S3off and S4off on the disconnect side are connected in series across capacitor C. Semiconductor elements S1off to S4off on the disconnect side constitute a full-bridge circuit 25 for generating a disconnect signal.

[0101] The primary windings of capacitor Ch2 and the second pulse transformer Tr2 on the disconnected side are connected between the connection points of the first and second semiconductor elements S1off and S2off on the disconnected side and the connection points of the third and fourth semiconductor elements S3off and S4off on the disconnected side.

[0102] Capacitors Ch1 and Ch2 cut off the DC component. They are connected to prevent the magnetic saturation of the first and second pulse transformers Tr1 and Tr2, but they can be omitted.

[0103] The generation of the second modulation signal vTr2 can be achieved by using... Figure 8 The control unit shown uses a full-bridge circuit 25 to generate the disconnect signal. Figure 9 The sequence diagram is shown. Basic operations and... Figure 3 , Figure 4 It's the same.

[0104] When the falling edge of synchronization circuit 9 is detected, Figure 8 The disconnected pulse width measuring unit (incrementing counter) 12 shown starts counting and stops counting when a rising edge is detected. The count value is incremented every time a clock signal is input. At this time, it is assumed that the rising edge and falling edge are synchronized with the clock through the operation of the synchronization circuit 9.

[0105] This allows the determination of the disconnect pulse width. Then, using the disconnect side 1-bit shift circuit 13, the count value is reduced to 1 / 2.

[0106] The disconnect-side latch circuit 14 latches the output of the disconnect-side 1-bit shift circuit 13 at the timing of detecting the rising edge.

[0107] The circuit is configured such that the output of the disconnected latch circuit 14 is input to the gate generation counters (first and second decrement counters) 15 and 16 in the subsequent stage and the gate command is output until the count value becomes 0, thereby generating a modulated signal with a duty cycle of 50% and a pulse width of 1 cycle as the command.

[0108] As a specific action, when a disconnect signal is generated, during the period when the first decrementing counter 15 is counting (until the count value becomes 0), the gating instructions of the first and fourth semiconductor elements S1off and S4off on the disconnect side are set high, and the gating instructions of the second and third semiconductor elements S2off and S3off on the disconnect side are set low.

[0109] During the counting period of the second decrement counter 16 (until the count value becomes 0), the gating instructions of the second and third semiconductor elements S2off and S3off on the disconnect side are set high, and the gating instructions of the first and fourth semiconductor elements S1off and S4off on the disconnect side are set low.

[0110] Accordingly, the frequency of the second modulation signal vTr2 can be suppressed to twice the switching frequency of the driven object, and the time resolution of the gate command pulse width can be improved without increasing the driving frequency of the second pulse transformer Tr2. Therefore, the loss of the full-bridge circuit can be reduced and the resolution improved.

[0111] Next, the method for generating the first modulation signal vTr1 will be explained. Figure 10 The operating waveforms of the DC / AC modulation circuit in Embodiment 1 are shown. Figure 2 In the previous embodiment, for a single cycle of turn-on command, one positive pulse and one negative pulse of the first modulation signal vTr1 were output. However, in this embodiment 1, the output of one positive pulse and one negative pulse of the first modulation signal vTr1 is divided into two turn-on commands. That is, the width of the turn-on command is the same as the duration of one positive pulse of the first modulation signal vTr1, and the width of the turn-on command is the same as the duration of one negative pulse of the first modulation signal vTr1. Positive and negative pulses are output alternately each time a turn-on command is received. Accordingly, the limitation of the first modulation signal vTr1, which is subject to the minimum turn-on pulse width limitation, can be minimized.

[0112] Figure 11 An example of gating instruction generation for the DC / AC modulation circuit of Embodiment 1 is shown. Figure 12 for Figure 11 The signals of each part. For gating instructions, a latch circuit is used to generate an enable signal, and a logical AND operation is performed on the original instruction to generate a signal for the driver IC.

[0113] exist Figure 11 In the middle, the rising edge detection circuit 26 detects the rising edge of the gating command. The latch circuit 27 latches the command at the time when the rising edge is detected, and releases the latch at the time when a new rising edge is detected while the command is already latched.

[0114] The AND circuit 28 outputs a gate control instruction and the output of the latch circuit 27. The NOT circuit 29 inverts the output of the latch circuit 27. The AND circuit 30 outputs a gate control instruction and the output of the NOT circuit 29.

[0115] The driver IC 31 outputs the gate control command of the DC / AC modulation circuit based on the outputs of circuits 28 and 30.

[0116] The DC / AC modulation circuit is Figure 3 Modulation signal generation circuit 17 or Figure 7 The modulation circuit (full-bridge circuit 24 for generating turn-on signal) outputs the first modulation signal vTr1 according to the gating command output from the driver IC.

[0117] In this embodiment 1, for example, when the minimum pulse width is set to 100ns, the modulation circuit can output pulses of 100ns or more. Therefore, the semiconductor element can perform switching operations that are closer to gating commands, thereby improving the output voltage accuracy of the inverter.

[0118] Furthermore, when the frequency and duty cycle of the gating command change in a ramp-like manner, the excitation current will deflect to one of the positive or negative directions. This can be countered by connecting capacitors ch1 and ch2 in series on the primary side of the first pulse transformer Tr1. However, capacitors ch1 and ch2 can cut off the DC component of the pulse transformer. On the other hand, when DC is applied for a long time, the charge will be deposited into the capacitors themselves, so this is effective only when the excitation component is only deflected for a short period of time.

[0119] As shown above, according to Embodiment 1, the frequencies of the first and second modulation signals vTr1 and vTr2 can be varied according to the gating signal. Accordingly, magnetic saturation of the first and second pulse transformers Tr1 and Tr2 can be suppressed, and the switching losses of the modulation signal generation circuit (DC / AC conversion circuit) driving the first and second pulse transformers Tr1 and Tr2 can be minimized. Furthermore, since the time resolution of the gating command pulse width is not reduced, the command pulse can be reproduced and output with higher precision.

[0120] In addition, it can minimize the limitation of the first modulation signal vTr1, which is subject to the minimum turn-on pulse width limitation.

[0121] [Implementation Method 2]

[0122] exist Figure 2 In order to counteract magnetization, the first modulation signal vTr1 is output as one positive pulse and one negative pulse in the pulse width (on command) of the X-gating instruction, so that the duration of the positive and negative pulses is the same within one cycle of the on command of the X-gating instruction. Thus, magnetization can be eliminated within one cycle of the on command of the X-gating instruction, but since one positive and one negative pulse are output, a shorter gating pulse width cannot be output.

[0123] On the other hand, Figure 12 In this method, the output of the first modulation signal vTr1, consisting of one positive pulse and one negative pulse, is divided into two pulse widths of the X-gated command (on command). This is advantageous when the pulse width of the X-gated command is short, but when the pulse width of the X-gated command becomes longer, the application time of the primary voltage of the transformer also becomes longer, which can easily lead to damage due to magnetic saturation.

[0124] Figure 13 The summary Figure 2 , Figure 12The output waveform and characteristics of the modulation circuit. In addition to these characteristics, the output time period Ton of the first modulation signal Vtr1 (refer to...) will also be generated. Figure 2 When the pulse length increases, there is a problem that the accuracy of the gate voltage Vgs pulse width decreases due to the application of an undesirable voltage to the secondary side by the back electromotive force of the first pulse transformer Tr1, or the problem that the pulse transformer is enlarged in order to increase the saturation magnetic flux density or to deal with heat generation.

[0125] To address these two issues, it is necessary to limit the length of the output period Ton of the first modulation signal Vtr1. For example, when using a DC / AC modulation circuit as modulation circuit 2, the following control is required: to prevent magnetic saturation of the pulse transformer caused by bias magnetization (a certain or more of the time integral of the voltage towards unipolarity) without being affected by the length of the pulse width of the X-gated command, and to ensure operation during the shorter output period Ton of the first modulation signal Vtr1.

[0126] In this second embodiment, in order to solve the above-mentioned problems, a method that takes into account... Figure 2 , Figure 12 The superiority of this method.

[0127] In this second embodiment, in order to take into account Figure 2 , Figure 12 The superiority of this technology allows the polarity of the first modulation signal vTr1 to be reversed according to the pulse width of the X-gated command. By reversing the output polarity of the DC / AC modulation circuit under the following two conditions, it is possible to prevent the pulse transformer from becoming biased without limiting the pulse width setting of the X-gated command.

[0128] (1) Each cycle of the gating instruction ( Figure 2 The X-gated instruction is used every 1 cycle.

[0129] (2) When the output time period Ton has elapsed for a predetermined time.

[0130] That is, in the modulation circuit 2 of this embodiment 2, during the period of the X-gating instruction's turn-on instruction, a positive pulse or a negative pulse is output as the first modulation signal vTr1. Every one cycle of the X-gating instruction, the polarity of the first modulation signal vTr1 at the beginning of its output is reversed. When the output period Ton of the first modulation signal vTr1 has elapsed for a predetermined time, the polarity of the first modulation signal vTr1 is reversed.

[0131] Figure 14 The control block diagram of Embodiment 2 is shown. Figure 14 The block diagram includes: a reversal permission signal generation unit 32, which generates a reversal permission signal that operates under the above conditions (1) and (2); a gate signal generation unit 33, which writes an X gate instruction according to the provided periodic instruction; and a polarity selector unit 34.

[0132] X-gating commands and Figure 2 The same information is the command signal for modulation circuit 2. The period command Tinv is a constant predetermined by the designer. The output period Ton of modulation circuit 2 (the first modulation signal vTr1) is Tinv / 2. The period command Tinv is set to a length that will not cause magnetic saturation of the pulse transformer even if DC is applied.

[0133] like Figure 14 As shown, the inversion permission signal generation unit 32 uses the cycle counter 35 to count the cycle instruction Tinv while the X-gated instruction is "1", and clears it when the X-gated instruction is "0". The negative edge detection unit 36 ​​detects the falling edge of the cycle counter 35. The negative edge detection unit 37 detects the falling edge of the X-gated instruction.

[0134] The output of the negative edge detection unit 36 ​​is input to terminal C of the multiplexer 38. Buffer 39 outputs the value of the output of the multiplexer 38 one operation time ago. The NOT circuit 40 inverts the output of buffer 39. The output of buffer 39 is input to terminal 0 of the multiplexer 38, and the output of the NOT circuit 40 is input to terminal 1 of the multiplexer 38.

[0135] The output of the negative edge detection unit 37 is input to the C terminal of the multiplexer 41. The buffer 42 outputs the value of the output of the multiplexer 41 one operation time prior. The output of the buffer 42 is input to the 0 terminal of the multiplexer 41, and the output of the multiplexer 38 is input to the 1 terminal of the multiplexer 41. The output of the multiplexer 41 is the inversion enable signal EN_POL. That is, the inversion enable signal generation unit 32 generates the inversion enable signal EN_POL, which switches between "1" and "0" on the falling edge of the X-gating instruction.

[0136] The gate signal generation unit 33 uses divider 43 to halve the cycle instruction Tinv. Comparator 44 compares the output of divider 43 with the output of cycle counter 35; if the output of divider 43 is larger, it outputs "1"; otherwise, it outputs "0". Comparator 45 compares the output of cycle counter 35 with the output of divider 43; if the output of cycle counter 35 is larger, it outputs "1"; otherwise, it outputs "0".

[0137] In circuit 46, the output of comparator 44 and the X gate instruction are input. When both are "1", the output is "1"; otherwise, the output is "0" as the gate signal GATE1. In circuit 47, the output of comparator 45 and the X gate instruction are input. When both are "1", the output is "1"; otherwise, the output is "0" as the gate signal GATE2.

[0138] That is, the gate signal generation unit 33 generates gate signal GATE1 and gate signal GATE2. The gate signal GATE1 is "1" when the X gate command is turned on and from the time the X gate command is turned on until a predetermined time (1 / 2 of the cycle command Tinv) has elapsed since the X gate command was turned on, and is "0" otherwise. The gate signal GATE2 is "1" when the X gate command is turned on and after a predetermined time (1 / 2 of the cycle command Tinv) has elapsed since the X gate command is turned on, and is "0" otherwise.

[0139] The polarity selector section 34 includes multiplexers 48 and 49. An inversion enable signal EN_POL is input to terminal C of multiplexer 48, a gate signal GATE1 is input to terminal 0 of multiplexer 48, and a gate signal GATE2 is input to terminal 1 of multiplexer 48. Similarly, an inversion enable signal EN_POL is input to terminal C of multiplexer 49, a gate signal GATE2 is input to terminal 0 of multiplexer 49, and a gate signal GATE1 is input to terminal 1 of multiplexer 49. The output of multiplexer 48 is a positive output gate signal GATE_P, and the output of multiplexer 49 is a negative output gate signal GATE_N.

[0140] That is, when the inversion enable signal is "0", the polarity selector unit 34 sets the positive output gate signal GATE_P to "1" when the gate signal GATE1 is "1", sets the negative output gate signal GATE_N to "1" when the gate signal GATE2 is "1", and sets both the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0" otherwise. When the inversion enable signal is "1", the negative output gate signal GATE_N is set to "1" when the gate signal GATE1 is "1", sets the positive output gate signal GATE_P to "1" when the gate signal GATE2 is "1", and sets both the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0" otherwise.

[0141] The driver IC 50 outputs gate commands for the DC / AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N.

[0142] Here, multiplexers 38, 41, 48, and 49 are configured as follows: NOT circuit 51 inverts the signal input to terminal C. AND circuit 52 takes the output signal of NOT circuit 51 and the signal input to terminal 0 as inputs, outputting "1" when both are "1", and outputting "0" otherwise. AND circuit 53 takes the signal input to terminal C and the signal input to terminal 1 as inputs, outputting "1" when both are "1", and outputting "0" otherwise. OR circuit 54 takes the output signal of AND circuit 52 and the output signal of AND circuit 53 as inputs, outputting "1" when at least one is "1", and outputting "0" when both are "0". The output of OR circuit 54 is the output signal of the multiplexer.

[0143] Figure 15 The signals of each part of the control circuit in this embodiment 2 are shown. The inversion permission signal generation unit 32 and the polarity selector unit 34 are control blocks used to satisfy the polarity inversion condition (1).

[0144] When the cycle counter 35 is cleared (on a falling edge), the inversion enable signal EN_POL is switched, and the inversion enable signal EN_POL is only allowed to be updated on the falling edge of the gating instruction. This inversion enable signal EN_POL is used to invert the positive and negative outputs in the polarity selector section 34.

[0145] On the other hand, the gate signal generation unit 33 is a control block used to make the polarity reversal condition (2) true. By comparing half of the period instruction Tinv with the output of the period counter 35, a signal corresponding to the output period Ton is generated, and the gate signals GATE1 and GATE2 are generated by performing an AND operation with the X gate instruction.

[0146] The polarity selector section 34 determines the positive output gate signal GATE_P and the negative output gate signal GATE_N of the DC / AC modulation circuit based on the gate signals GATE1, GATE2 and the inversion permission signal EN_POL.

[0147] When the pulse width of the gating command is relatively long, such as Figure 2 As shown, the positive and negative pulses of the first modulation signal vTr1 are alternately output within the pulse width of the X-gated command. When the pulse width of the X-gated command is short, it can achieve the following: Figure 12 The diagram shows how to achieve positive control of the first modulation signal using two cycles. The result is that it balances... Figure 2 , Figure 12 Its advantages enable the expansion of the pulse width setting range and the miniaturization of the pulse transformer without relying on the pulse width length of the gating command.

[0148] As shown in equation (1) below, the bias is the case where the voltage deflects over time. The amount of bias equivalent to that generated by a single periodic command Tinv is within the allowable range, but the problem is that it is generated because it is accumulated. In this embodiment 2, when the pulse width of the X-gated command is an even number of Tinv / 4, if an odd number of Tinv / 4 repeats an even number of periods within its period, then within this range, even if an odd number of Tinv / 4 reaches an odd number of periods, it can be handled when it reaches an odd number of times again.

[0149] [Mathematical Expression 1]

[0150] ...(1)

[0151] Figure 16 The example below illustrates the activation pulse widths of the X-gating command with 3, 3, and 4 scales. Here, we assume 1 scale = Tinv / 4.

[0152] When the initial X-gated instruction is turned on, the output of the cycle counter 35 is less than half of the cycle instruction Tinv before the second scale, so the first modulation signal vTr1 outputs a positive pulse. After the second scale, the output of the cycle counter 35 becomes greater than half of the cycle instruction Tinv, so the first modulation signal vTr1 will reverse its polarity and output a negative pulse.

[0153] When the second X-gated instruction is enabled, before the second scale, the output of cycle counter 35 is less than half of the cycle instruction Tinv. Here, in each cycle of the X-gated instruction, the polarity of the output changes at the beginning, therefore the first modulation signal vTr1 outputs a negative pulse. After the second scale, the output of cycle counter 35 becomes greater than half of the cycle instruction Tinv, therefore the first modulation signal vTr1 will reverse its polarity and output a positive pulse. When the third X-gated instruction is enabled, ... Figure 15 same.

[0154] In this way, even if the pulse width of the X-gated instruction is not 1 / 4 of the even-numbered cycle instruction Tinv, flux bias can be eliminated in two cycles. Furthermore, even if it is an odd-numbered cycle, flux bias can be eliminated when it becomes an odd-numbered cycle again. Even if there are no more odd-numbered cycles, there is no problem as long as flux bias does not accumulate.

[0155] The reason for preventing biased magnetization is the damage caused by heat or magnetic saturation. Therefore, there is no problem as long as the average value of the excitation current is 0 over a long period of time (more than one cycle) (or, there is no problem as long as the current does not increase too much periodically).

[0156] As shown above, according to this embodiment 2, in a high-voltage high-frequency pulse power supply having a driver that drives the pulse transformer by a DC / AC modulation circuit, a high-precision gated pulse width can be achieved while preventing the pulse transformer from becoming biased.

[0157] The above description only details specific examples. However, it will be obvious to those skilled in the art that various modifications and variations can be made within the scope of the technical concept of the present invention, and such modifications and variations naturally fall within the scope of the claims.

[0158] For example, the semiconductor element 8, which is the driving object in embodiments 1 and 2, is used in power conversion devices (converters or inverters, etc.).

[0159] Furthermore, the control methods for the first modulation signal vTr1 in Embodiments 1 and 2 can also be applied to the second modulation signal vTr2. They can be applied to either Embodiment 1 or Embodiment 2, or both.

[0160] When the control method of Embodiment 1 is applied to the second modulation signal vTr2, the width of the disconnect command is made the same as the time period of one positive pulse of the second modulation signal vTr2, and the width of the disconnect command is made the same as the time period of one negative pulse of the second modulation signal vTr2. Whenever the disconnect command is issued, the positive pulse and the negative pulse of the second modulation signal vTr2 are output alternately.

[0161] When the control method of Embodiment 2 is applied to the second modulation signal vTr2, during the period of the gate disconnection command, a positive pulse or a negative pulse is output as the second modulation signal. In each cycle of the gate command, the polarity of the output of the second modulation signal vTr2 is reversed at the beginning. When the output period of the second modulation signal vTr2 has elapsed for a predetermined time, the polarity of the second modulation signal vTr2 is reversed.

Claims

1. A gate driving circuit, characterized in that, have: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. The width of the gating instruction is the same as the time period of one positive pulse of the first modulation signal, and the width of the gating instruction is the same as the time period of one negative pulse of the first modulation signal. Whenever the gating instruction is received, the positive pulse and the negative pulse of the first modulation signal are output alternately.

2. The gate driving circuit according to claim 1, characterized in that, The modulation circuit includes: Rising edge detection circuit to detect the rising edge of the gate command; The latching circuit latches the gate command at a time when the rising edge of the gate command is detected, and releases the latch at the time when the rising edge of the gate command is detected again while the gate command is latched. The first AND circuit outputs the logical AND of the gate control command and the output of the latch circuit; The non-circuit causes the output of the latch circuit to be reversed; The second AND circuit outputs the logical AND of the gate control command and the output of the non-circuit; The driver IC controls the DC / AC modulation circuit based on the outputs of the first AND circuit and the second AND circuit. as well as The DC / AC modulation circuit outputs the first modulation signal based on the control of the driver IC.

3. A gate driving circuit, characterized in that, have: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. During the gating instruction period, the first modulation signal outputs a positive pulse or a negative pulse. The polarity of the first modulation signal is reversed at the beginning of each cycle of the gating instruction. The polarity of the first modulation signal is reversed when the output period of the first modulation signal has elapsed for a predetermined time.

4. The gate driving circuit according to claim 3, characterized in that, have: The inversion permission signal generation unit generates an inversion permission signal that switches between "1" and "0" on the falling edge of the gate control command; The gate signal generation unit generates gate signal GATE1 and gate signal GATE2. The gate signal GATE1 outputs "1" when the gate command is turned on and from the time the gate command is turned on until a predetermined time has elapsed, and outputs "0" otherwise. The gate signal GATE2 outputs "1" after a predetermined time has elapsed from the time the gate command is turned on and outputs "0" otherwise. The polarity selector section, when the inversion permission signal is "0", sets the positive output gate signal GATE_P to "1" when the gate signal GATE1 is "1", and sets the negative output gate signal GATE_N to "1" when the gate signal GATE2 is "1", and otherwise sets both the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0". When the inversion permission signal is "1", the section sets the negative output gate signal GATE_N to "1" when the gate signal GATE1 is "1", and sets the positive output gate signal GATE_P to "1" when the gate signal GATE2 is "1", and otherwise sets both the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0". The driver IC controls the DC / AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N. as well as The DC / AC modulation circuit outputs the first modulation signal based on the control of the driver IC.

5. The gate driving circuit according to claim 2 or 4, characterized in that, The DC / AC modulation circuit is a modulation signal generation circuit. The modulation circuit includes: A synchronization circuit is used to synchronize the gate control command with the clock signal; The rising edge detection unit detects the rising edge of the output of the synchronization circuit; The falling edge detection unit detects the falling edge of the output of the synchronization circuit; Disconnect the pulse width measuring unit, start counting when the falling edge of the output of the synchronization circuit is detected, stop counting when the rising edge of the output of the synchronization circuit is detected, and add the count value every time the clock signal is input; Disconnect the 1-bit shift circuit on the disconnect side, so that the output of the disconnect pulse width measuring unit becomes 1 / 2; The disconnect-side latch circuit latches the output of the disconnect-side 1-bit shift circuit at the rising edge of the output of the synchronization circuit. The first decrementing counter receives the output of the disconnected side latch circuit and the clock signal, and subtracts the count value whenever the clock signal is input. as well as The second decrementing counter receives the output of the disconnected-side latch circuit, the output of the first decrementing counter, and the clock signal. It subtracts from the count value each time the clock signal is input. The modulation signal generation circuit outputs the second modulation signal until the counters of the first and second decrement counters become zero.

6. The gate driving circuit according to claim 2 or 4, characterized in that, The DC / AC modulation circuit includes: Capacitor; A full-bridge circuit for generating a turn-on signal has a first and a second semiconductor element on the turn-on side connected in series between the two ends of the capacitor, and a third and a fourth semiconductor element on the turn-on side connected in series between the two ends of the capacitor. as well as A full-bridge circuit for generating a disconnect signal has a first and a second semiconductor element connected in series between the two ends of the capacitor, and a third and a fourth semiconductor element connected in series between the two ends of the capacitor. The primary winding of the first pulse transformer is connected between the connection points of the first and second semiconductor elements on the turn-on side and the connection points of the third and fourth semiconductor elements on the turn-on side, and the primary winding of the second pulse transformer is connected between the connection points of the first and second semiconductor elements on the turn-off side and the connection points of the third and fourth semiconductor elements on the turn-off side.

7. The gate driving circuit according to claim 6, characterized in that, The modulation circuit includes: A synchronization circuit is used to synchronize the gate control command with the clock signal; The rising edge detection unit detects the rising edge of the output of the synchronization circuit; The falling edge detection unit detects the falling edge of the output of the synchronization circuit; Disconnect the pulse width measuring unit, start counting when the falling edge of the output of the synchronization circuit is detected, stop counting when the rising edge of the output of the synchronization circuit is detected, and add the count value every time the clock signal is input; Disconnect the 1-bit shift circuit on the disconnect side, so that the output of the disconnect pulse width measuring unit becomes 1 / 2; The disconnect-side latch circuit latches the output of the disconnect-side 1-bit shift circuit at the rising edge of the output of the synchronization circuit. The first decrementing counter receives the output of the disconnected side latch circuit and the clock signal. Whenever the clock signal is input, the count value is subtracted, and the gating instructions of the first and fourth semiconductor elements on the disconnected side are output until the count value becomes 0. as well as The second decrementing counter receives the output of the disconnected-side latch circuit, the output of the first decrementing counter, and the clock signal. Whenever the clock signal is input, the count value is subtracted, and the gating instructions of the second and third semiconductor elements on the disconnected side are output until the count value becomes 0.

8. The gate driving circuit according to claim 5, characterized in that, The disconnected pulse width measuring unit has an n-level structure, where n is an integer greater than or equal to 1. At level 1, it has: The first-on-side D flip-flop circuit receives the clock signal at the D-FF terminal and receives the output of the / Q terminal of the first-on-side D flip-flop circuit at the D terminal. The output of the Q terminal is a 1-bit signal. At level 2, it has: The second turn-on side XOR circuit receives the output of the Q terminal of the first turn-on side D flip-flop circuit and the output of the Q terminal of the second turn-on side D flip-flop circuit. as well as The second-on-side D flip-flop circuit receives the clock signal at the D-FF terminal, receives the output of the second-on-side XOR circuit at the D terminal, and outputs a 2-bit signal at the Q terminal. At level 3, it has: The third turn-on side AND circuit receives the output of the Q terminal of the first turn-on side D flip-flop circuit and the output of the Q terminal of the second turn-on side D flip-flop circuit. The third-side XOR circuit is input to the output of the third-side AND circuit and the output of the Q terminal of the third-side D flip-flop circuit; as well as The third-side-on D flip-flop circuit receives the clock signal at the D-FF terminal, receives the output of the third-side-on XOR circuit at the D terminal, and outputs a 3-bit signal at the Q terminal. In levels 4 through n, it has: The input circuit on the k-th turn-on side is the output of the Q terminal of the (k-1)-th turn-on side D flip-flop circuit and the output of the (k-1)-th turn-on side AND circuit, where k is an integer from 4 to n; The XOR circuit on the k-th turn-on side is input to the output of the AND circuit on the k-th turn-on side and the output of the Q terminal of the D flip-flop circuit on the k-th turn-on side. as well as The D flip-flop circuit on the k-th turn-on side inputs the clock signal to the D-FF terminal, inputs the output of the XOR circuit on the k-th turn-on side to the D terminal, and outputs a k-bit signal to the Q terminal.

9. The gate driving circuit according to claim 5, characterized in that, The first and second decrementing counters are of an n-stage structure, where n is an integer greater than or equal to 1. At level 1, it has: The first disconnect-side D flip-flop circuit receives the clock signal as input to the D-FF terminal and receives the output of the / Q terminal of the first disconnect-side D flip-flop circuit as input to the D terminal. The output of the Q terminal is a 1-bit signal. At level 2, it has: The second disconnection-side XOR circuit receives the output of the / Q terminal of the first disconnection-side D flip-flop circuit and the output of the / Q terminal of the second disconnection-side D flip-flop circuit. as well as The second disconnect-side D flip-flop circuit receives the clock signal at the D-FF terminal, receives the output of the second disconnect-side XOR circuit at the D terminal, and outputs a 2-bit signal at the Q terminal. At level 3, it has: The third disconnect side is connected to the circuit, which inputs the output of the / Q terminal of the first disconnect side D flip-flop circuit and the output of the / Q terminal of the second disconnect side D flip-flop circuit; The third disconnection-side XOR circuit is input to the output of the third disconnection-side AND circuit and the output of the / Q terminal of the third disconnection-side D flip-flop circuit; as well as The third disconnect-side D flip-flop circuit receives the clock signal at the D-FF terminal, receives the output of the third disconnect-side XOR circuit at the D terminal, and outputs a 3-bit signal at the Q terminal. In levels 4 through n, it has: The circuit on the k-th disconnect side is connected to the output of the / Q terminal of the (k-1)-th disconnect side D flip-flop circuit and the output of the (k-1)-th disconnect side AND circuit, where k is an integer from 4 to n; The XOR circuit on the k-th disconnected side is input to the output of the AND circuit on the k-th disconnected side and the output of the / Q terminal of the D flip-flop circuit on the k-th disconnected side. as well as The D flip-flop circuit on the k-th disconnect side inputs the clock signal to the D-FF terminal, inputs the output of the XOR circuit on the k-th disconnect side to the D terminal, and outputs a k-bit signal to the Q terminal.

10. A gate driving circuit, characterized in that, have: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. The width of the gating instruction is the same as the duration of one positive pulse of the second modulation signal, and the width of the gating instruction is the same as the duration of one negative pulse of the second modulation signal. Whenever the gating instruction is received, the positive pulse and the negative pulse of the second modulation signal are output alternately.

11. A gate driving circuit, characterized in that, have: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. During the period of the gating instruction's disconnection instruction, the second modulation signal outputs a positive pulse or a negative pulse. The polarity of the second modulation signal is reversed at the beginning of each cycle of the gating instruction. The polarity of the second modulation signal is reversed when the output period of the second modulation signal has elapsed for a predetermined time.

12. A power conversion device, characterized in that, The device comprises a gate driving circuit according to any one of claims 1, 3, 10 to 11, and a semiconductor element connected to the gate driving circuit as the driving target.

13. A control method for a gate driving circuit, characterized in that, The gate driving circuit includes: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. The width of the gating instruction is the same as the time period of one positive pulse of the first modulation signal, and the width of the gating instruction is the same as the time period of one negative pulse of the first modulation signal. Whenever the gating instruction is received, the positive pulse and the negative pulse of the first modulation signal are output alternately.

14. A control method for a gate driving circuit, characterized in that, The gate driving circuit includes: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The on-side rectifier circuit includes: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, an on-side secondary winding for transforming and outputting the voltage applied to the on-side primary winding, and an on-side tertiary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the on-side tertiary winding. The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction, so that the width of the gating instruction is the same as the duration of one positive pulse of the second modulation signal, and the width of the gating instruction is the same as the duration of one negative pulse of the second modulation signal. Whenever the gating instruction is received, the positive pulse and the negative pulse of the second modulation signal are output alternately.

15. A control method for a gate driving circuit, characterized in that, The gate driving circuit includes: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. During the gating instruction period, the first modulation signal outputs a positive pulse or a negative pulse. The polarity of the first modulation signal is reversed at the beginning of each cycle of the gating instruction. The polarity of the first modulation signal is reversed when the output period of the first modulation signal has elapsed for a predetermined time.

16. A control method for a gate driving circuit, characterized in that, The gate driving circuit includes: The modulation circuit outputs the first modulation signal and the second modulation signal based on the gating instruction's on and off instructions; The turn-on rectifier circuit includes: a first pulse transformer having a turn-on primary winding to which the first modulation signal is applied, a turn-on secondary winding for transforming and outputting the voltage applied to the turn-on primary winding, and a turn-on tertiary winding; and a first diode circuit for rectifying the output of the turn-on secondary winding. And the second diode circuit, which rectifies the output of the three-stage winding on the connected side; as well as The disconnect-side rectifier circuit comprises: a second pulse transformer having a disconnect-side primary winding to which the second modulation signal is applied, a disconnect-side secondary winding for transforming and outputting the voltage applied to the disconnect-side primary winding, and a disconnect-side tertiary winding; and a third diode circuit for rectifying the output of the disconnect-side secondary winding. And the fourth diode circuit, which rectifies the output of the disconnected three-stage winding. The gate drive circuit controls the semiconductor element being driven based on the outputs of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the width of the gating instruction and the width of the gating instruction. During the period of the gating instruction's disconnection instruction, the second modulation signal outputs a positive pulse or a negative pulse. The polarity of the second modulation signal is reversed at the beginning of each cycle of the gating instruction. The polarity of the second modulation signal is reversed when the output period of the second modulation signal has elapsed for a predetermined time.

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