Decoding device, control circuit, storage medium, and check matrix generation method

Abstract

A decoding device (320) is provided with: a storage unit (331) that stores a first check matrix which can be divided into small matrix blocks of P * P and has a maximum coding rate assumed as a check matrix of a low-density parity check code used in communication, where P is a positive integer; and a generation unit (332) that uses rows included in the first check matrix and including units of small matrices in the column direction to generate a first row in which some of the blocks are replaced by a 0 matrix, and further generates one or more second rows in which a predetermined block is replaced by a 0 matrix and the position of 1 included in the small matrices of the other blocks is shifted by a predetermined fixed value. A second check matrix having a lower encoding rate than the first check matrix is generated.

Description

Technical Field

[0001] The present disclosure relates to a decoding device, a control circuit, a storage medium, and a check matrix generation method used in a communication device. Background Art

[0002] In the past, in communication devices, multiple low-density parity check codes (hereinafter referred to as LDPC (Low Density Parity Check) codes) with equal code lengths and different coding rates were switched to perform encoding and decoding. For example, Patent Document 1 discloses the following technology: a part or all of the rows of the parity check matrix constituting the LDPC code are divided into two or more rows, and for the positions with "1" in the rows of the original parity check matrix, "1" is assigned to any of the two or more rows after the division, with the row vectors of the parity check matrix after the row division as the linear independence condition, thereby generating a new parity check matrix to realize LDPC codes based on multiple rates.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-109228 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, according to the above-mentioned conventional techniques, the newly generated parity check matrix has a row weight that is reduced relative to the original parity check matrix due to the increase in the number of rows. Regarding the column weight, when the number of columns of the parity check matrix is ​​increased to reduce the coding rate, a limit is imposed on the maximum value of the column weight, so there is a problem that the performance is sometimes not good enough. In addition, the newly generated check matrix has the following problems: the error floor is mostly generated at a high bit error rate.

[0008] The present disclosure has been made in view of the above-mentioned situation, and an object of the present disclosure is to obtain a decoding device capable of suppressing the degradation of code performance when the number of rows of a check matrix is ​​increased.

[0009] Means for solving problems

[0010] In order to solve the above-mentioned problems and achieve the purpose, the decoding device disclosed in the present invention is characterized in that, assuming P to be a positive integer, the decoding device comprises: a storage unit, which stores a first check matrix of a maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity-check code used in communication; and a generation unit, which uses rows contained in the first check matrix and containing units of small matrices in the column direction to generate a first row in which a part of the blocks are replaced by a 0 matrix, and further generates a second row in which a specified block is replaced by a 0 matrix and the positions of 1 contained in the small matrices of other blocks are shifted by one or more specified fixed values, thereby generating a second check matrix with a coding rate lower than that of the first check matrix.

[0011] Effects of the Invention

[0012] The decoding device of the present disclosure has an effect of being able to suppress the degradation of code performance when the number of rows of the check matrix is ​​increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a diagram showing a configuration example of a communication system including a communication device according to Embodiment 1.

[0014] Figure 2 This is a diagram showing an example of a method for adding rows of a parity check matrix by the check matrix generation apparatus according to Embodiment 1.

[0015] Figure 3 This is a flowchart showing the operation of the check matrix generation device according to Embodiment 1.

[0016] Figure 4 This is a diagram showing a configuration example of a processing circuit in which the processing circuit for implementing the communication device according to Embodiment 1 is constituted by a processor and a memory.

[0017] Figure 5 This is a diagram showing an example of a processing circuit in the case where the processing circuit of the communication device according to Embodiment 1 is configured by dedicated hardware.

[0018] Figure 6 This is a diagram showing a configuration example of a communication system having a communication device according to embodiment 2.

[0019] Figure 7 This is a diagram showing a configuration example of a row operation unit included in a decoding unit according to the second embodiment.

[0020] Figure 8 This is a flowchart showing the row operation operation performed by the row operation unit of the decoding unit according to the second embodiment.

[0021] Fig. 9 This is a diagram showing a configuration example of a column operation unit included in a decoding unit according to the third embodiment.

[0022] Fig.10 This is a flowchart showing the column calculation operation performed by the column calculation unit of the decoding unit according to the third embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, a decoding device, a control circuit, a storage medium, and a check matrix generation method according to an embodiment of the present disclosure will be described in detail based on the drawings.

[0024] Implementation Method 1

[0025] Figure 1 1 is a diagram showing a configuration example of a communication system 400 having communication devices 100 and 300 according to Embodiment 1. The communication system 400 is a system in which the communication device 100 transmits a signal that has been coded using an LDPC code to the communication device 300 via a communication path 200, and the communication device 300 performs a decoding process on the received signal. The communication device 100 includes a coding device 110 and a transmitting unit 140. The coding device 110 includes a check matrix generating device 120 and a coding unit 130. The check matrix generating device 120 includes a storage unit 121 and a generating unit 122. In addition, the communication device 300 includes a receiving unit 310 and a decoding device 320. The decoding device 320 includes a check matrix generating device 330 and a decoding unit 340. The check matrix generating device 330 includes a storage unit 331 and a generating unit 332.

[0026] In the communication device 100, the coding device 110 performs coding processing on the communication bits obtained from the upper device (not shown) and the like. In the coding device 110, the check matrix generation device 120 generates a parity check matrix used in the coding processing for the communication bits. The coding unit 130 obtains the parity check matrix from the check matrix generation device 120 and performs coding processing on the communication bits. The transmission unit 140 performs modulation processing on the communication bits coded by the coding unit 130 of the coding device 110, and transmits the modulated signal to the communication device 300 via the communication path 200. In the following description, the parity check matrix is ​​sometimes referred to as a check matrix.

[0027] In the communication device 300, the receiving unit 310 performs a demodulation process on the received signal received from the communication device 100 via the communication path 200. The decoding device 320 performs a decoding process on the demodulated signal to generate a decoding result, and outputs it to a higher-level device, etc., which is not shown in the figure. In the decoding device 320, the check matrix generation device 330 generates a parity check matrix used in the decoding process for the demodulated signal. The decoding unit 340 obtains the parity check matrix from the check matrix generation device 330 and performs a decoding process on the demodulated signal.

[0028] In Embodiment 1, the following method is described: the parity check matrix generation device 120 of the communication device 100 and the parity check matrix generation device 330 of the communication device 300 add rows to the original parity check matrix to generate a parity check matrix having a coding rate different from that of the original parity check matrix. In addition, the parity check matrix generation device 120 and the parity check matrix generation device 330 have the same structure. In addition, the storage unit 121 and the generation unit 122 of the parity check matrix generation device 120 have the same structure as the storage unit 331 and the generation unit 332 of the parity check matrix generation device 330. Since the parity check matrix generation device 120 and the parity check matrix generation device 330 perform the same operation, the parity check matrix generation device 330 is used as an example for description below.

[0029] Here, in Embodiment 1, it is assumed that the LDPC code to be processed is an organization code. When the parity check matrix is ​​assumed to be an m×n matrix, it is assumed that the m columns starting from the rightmost column of the parity check matrix correspond to the parity check bits. In addition, it is assumed that m and n are positive integers. However, with respect to the corresponding positions of the parity check bits, the corresponding positions of the columns may be appropriately replaced. In addition, in Embodiment 1, the decoding device 320 having the check matrix generation device 330 uses the coding matrix that lower-triangularizes the parity check matrix, i.e., the coding check matrix, to perform decoding processing of the LDPC code. The check matrix generation device 330 can make the coding rate of the LDPC code variable by adding the number of rows of the parity check matrix to the parity check matrix of the original LDPC code with the highest coding rate.

[0030] Figure 2 1 is a diagram showing an example of a method for adding rows of a parity check matrix by the check matrix generation device 330 of Embodiment 1. Figure 2 In the example, the parity check matrix of the upper coding rate 4 / 5 is pre-stored in the storage unit 331 and is the parity check matrix of the original LDPC code with the highest coding rate. The parity check matrix of the middle coding rate 3 / 5 is formed by adding 2 rows to the parity check matrix of the coding rate 4 / 5 by the generation unit 332. The parity check matrix of the lower coding rate 1 / 2 is formed by adding 3 rows to the parity check matrix of the coding rate 4 / 5 by the generation unit 332.

[0031] In the parity check matrix generation device 330, the generation unit 332 performs processing to add rows of the parity check matrix. Figure 1 The parity check matrix of the highest coding rate assumed in the communication system 400 shown, which is the coding rate 4 / 5 in the first embodiment, is pre-stored in the storage unit 331. When the common divisor of the number of rows m and the number of columns n of the parity check matrix is ​​set to P, the high parity check matrix with the highest coding rate is composed of small matrices of P×P matrices. In addition, P is also a positive integer. For example, Figure 1The parity check matrix of the coding rate 4 / 5 shown is composed of small matrices of P×P matrices of 2 blocks as row components, and is composed of small matrices of P×P matrices of 10 blocks as column components. In the following description, the high parity check matrix with the highest coding rate stored in the storage unit 331 is sometimes referred to as the first check matrix. That is, the storage unit 331 stores the first check matrix of the maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity check code used in communication.

[0032] In addition, the parity check matrix with the number of rows added generated by the generating unit 332 is sometimes referred to as a second check matrix.

[0033] The small matrix composed of P×P matrices is set to be a zero matrix with all component values ​​0, or a unit matrix, or a cyclic permutation matrix obtained by cyclically shifting the position of 1 in the unit matrix to the right by i positions. In addition, it is assumed that 0≤i≤P-1. Figure 2 In the parity check matrix shown in the middle and lower sections, the part represented by 0 is a 0 matrix, and the part represented by S(A1), S(B2), T(A1), etc. is a circulant permutation matrix.

[0034] First, the generation unit 332 generates Figure 2 As a process of adding rows of the parity check matrix, the generator 332 sets part of the row components of the first block of the parity check matrix of the code with the coding rate of 4 / 5 stored in the storage unit 331 to 0 matrix, and keeps the other parts of the parity check matrix of the coding rate of 4 / 5, thereby generating the rows of the first block of the parity check matrix.

[0035] Next, the generator 332 sets a portion of the row components of the first block of the parity check matrix of the code of the coding rate 4 / 5 to a zero matrix for the rows of the second block. At this time, the generator 332 makes the portion set to a zero matrix in the first block not a zero matrix. In addition, the generator 332 generates a position obtained by performing a fixed value cyclic shift on the position with "1" of the parity check matrix of the coding rate 4 / 5 for the portion not set to a zero matrix, and generates the rows of the second block of the parity check matrix.

[0036] In addition, the generating unit 332 sets part of the row components of the second block of the parity check matrix of the code with the coding rate 4 / 5 to a 0 matrix, and keeps the other parts as the parity check matrix of the coding rate 4 / 5, thereby generating the rows of the third block of the parity check matrix.

[0037] Next, the generator 332 sets a portion of the row components of the second block of the parity check matrix of the code of the coding rate 4 / 5 to a zero matrix for the rows of the fourth block. At this time, the generator 332 makes the portion set to a zero matrix in the third block not a zero matrix. In addition, the generator 332 generates a position in which a fixed value cyclic shift is performed on the position with "1" of the parity check matrix of the coding rate 4 / 5 for the portion not set to a zero matrix, and generates the rows of the fourth block of the parity check matrix.

[0038] The generator 332 can expand the rows as described above and generate a parity check matrix with a coding rate of 3 / 5, wherein the row components are composed of small P×P matrices of 4 blocks and the column components are composed of small P×P matrices of 10 blocks.

[0039] Similarly, the description generating unit 332 generates Figure 2 As a process of adding rows of the parity check matrix, the generator 332 sets a portion of the row components of the first block of the parity check matrix of the code with the coding rate of 4 / 5 stored in the storage unit 331 to 0 matrix, and keeps the other portion of the parity check matrix of the coding rate of 4 / 5, thereby generating the rows of the first block of the parity check matrix.

[0040] Next, the generator 332 sets a portion of the row components of the first block of the parity check matrix of the code of the coding rate 4 / 5 to a 0 matrix for the rows of the second block. In addition, the generator 332 generates a position obtained by performing a fixed value cyclic shift on the position of "1" of the parity check matrix of the coding rate 4 / 5 for the portion not set to a 0 matrix, and generates the rows of the second block of the parity check matrix.

[0041] Next, the generator 332 sets a portion of the row components of the first block of the parity check matrix of the code of the coding rate 4 / 5 to a zero matrix for the rows of the third block. At this time, the generator 332 makes the portion set to a zero matrix in the second block not a zero matrix. In addition, the generator 332 generates a position in which the position with "1" of the parity check matrix of the coding rate 4 / 5 is cyclically shifted by a fixed value different from that when the second block is generated, and generates the rows of the third block of the parity check matrix.

[0042] In addition, the generating unit 332 sets part of the row components of the second block of the parity check matrix of the code with the coding rate 4 / 5 to a 0 matrix, and keeps the other parts of the parity check matrix with the coding rate 4 / 5, thereby generating the rows of the fourth block of the parity check matrix.

[0043] Next, the generator 332 sets a portion of the row components of the 2nd block of the parity check matrix of the code of the coding rate 4 / 5 to a zero matrix for the rows of the 5th block. At this time, the generator 332 makes the portion set to a zero matrix in the 4th block not a zero matrix. In addition, the generator 332 generates a position in which a fixed value cyclic shift is performed on the position with "1" of the parity check matrix of the coding rate 4 / 5 for the portion not set to a zero matrix, and generates the row of the 5th block of the parity check matrix.

[0044] The generator 332 can expand the rows as described above and generate a parity check matrix with a coding rate of 1 / 2, wherein the row components are composed of small P×P matrices of 5 blocks and the column components are composed of small P×P matrices of 10 blocks.

[0045] The generator 332 can also generate parity check matrices of codes of other coding rates by the same method. The generator 332 can make the code length fixed and the coding rate variable for the parity check matrix used in the decoder 340 by the method described above. In addition, in the above example, the generator 332 generates the parity check matrix by performing a fixed value cyclic shift based on a fixed value for each row, but the shift amount can also be changed for each column component.

[0046] In addition, the generator 332 may also set a portion of the row blocks of the original parity check matrix to a 0 matrix and expand the blocks after shifting other blocks by a certain amount to multiple rows, thereby reducing the coding rate. Thus, the generator 332 sometimes also makes the row weight and column weight not smaller than the row weight and column weight of the original LDPC code, thereby suppressing degradation in code performance.

[0047] In addition, the generating unit 332 may also store the generated parity check matrix of the coding rate 3 / 5, the parity check matrix of the coding rate 1 / 2, etc. in the storage unit 331. Thus, even when the communication device 100 changes the coding rate of the coding process according to the situation of the communication path 200, the generating unit 332 can reduce the operation processing by storing the parity check matrix generated in the past, compared with the case where the parity check matrix is ​​generated every time the coding rate is changed.

[0048] Here, in the communication system 400, when the communication device 300 decodes the signal sent from the communication device 100, if it is known what coding rate the communication device 100 used to encode the parity check matrix, the decoding process can be performed efficiently. In the communication system 400, it is assumed that the communication device 100 and the communication device 300 operate according to a common rule, for example, the method of adding two rows of the parity check matrix is ​​as follows. Figure 2 As shown in the middle section of the method, the method of adding 3 rows of parity check matrix rows is as follows Figure 2In this case, in the communication system 400, the communication device 100 may notify the communication device 300 of the information of the coding rate of the parity check matrix to be used, or an upper device (not shown) may notify the communication device 100 and the communication device 300 of the coding rate of the parity check matrix to be used.

[0049] Figure 3 Flowchart showing the operation of the check matrix generation device 330 of the first embodiment. In the check matrix generation device 330, the generation unit 332 reads out from the storage unit 331 a parity check matrix that can be divided into blocks of P×P small matrices and has the highest coding rate assumed in the communication system 400 (step S101). The generation unit 332 selects a row from the read parity check matrix (step S102). The generation unit 332 uses the selected row to generate the first row in which a part of the blocks of the row components are set to a 0 matrix and the other part of the blocks are set to the original row components (step S103). The first row is equivalent to Figure 2 The first and third rows of the parity check matrix with a coding rate of 3 / 5 shown in the middle section, Figure 2 The first and fourth rows of the parity check matrix with coding rate 1 / 2 shown in the lower section, etc.

[0050] When the generator 332 generates a second row using the selected row (step S104: Yes), it generates a second row by setting blocks at positions different from the blocks set to 0 matrices in the first row as part of the row components and circularly shifting positions with "1" in other blocks by a predetermined fixed value (step S105). The second row generated in step S105 is equivalent to Figure 2 The 2nd and 4th rows of the parity check matrix with a coding rate of 3 / 5 shown in the middle section, Figure 2 The 5th row of the parity check matrix with coding rate 1 / 2 shown in the lower section, etc.

[0051] Alternatively, when the generator 332 generates two or more second rows using the selected row (step S104: No), it generates two or more second rows by setting the positions of blocks that are part of the row components and are different in the second row to 0 matrices and cyclically shifting the positions of "1" in other blocks by different fixed values ​​specified for each second row (step S106). The second row generated in step S106 is equivalent to Figure 2 The 2nd and 3rd rows of the parity check matrix with coding rate 1 / 2 shown in the lower section, etc.

[0052] If the number of rows of the parity check matrix to be generated does not reach the expected number of rows (step S107: No), the generator 332 returns to step S102 and selects an unselected row from the read parity check matrix. If the number of rows of the parity check matrix to be generated reaches the expected number of rows (step S107: Yes), the generator 332 ends the operation.

[0053] In this way, the generator 332 generates the first row in which a part of the blocks are replaced by the 0 matrix, using the rows of the units including the small matrix in the column direction included in the first check matrix, and further generates one or more second rows in which the specified blocks are replaced by the 0 matrix and the positions of the 1s included in the small matrix of other blocks are shifted by a specified fixed value, thereby generating a second check matrix having a lower coding rate than the first check matrix. When the generator 332 generates one second row, the blocks that are not replaced by the 0 matrix in the first row are replaced by the 0 matrix as the specified blocks. Alternatively, when the generator 332 generates two or more second rows, different blocks are replaced by the 0 matrix according to two or more second rows as the specified blocks, and the fixed value is set to different values ​​according to two or more second rows. The generator 332 generates the first row and one or more second rows for each row using a plurality of rows including the units including the small matrix in the column direction included in the first check matrix.

[0054] Next, the hardware structure of the communication device 300 is described. In the communication device 300, the receiving unit 310 is a communicator. The decoding device 320 is implemented by a processing circuit. The processing circuit can be a processor and a memory that executes a program stored in a memory, or it can be dedicated hardware. The processing circuit is also called a control circuit.

[0055] Figure 4 This diagram shows a configuration example of a processing circuit 90 in which a processing circuit for realizing the communication device 300 according to the first embodiment is constituted by a processor 91 and a memory 92 . Figure 4 The processing circuit 90 shown is a control circuit, and has a processor 91 and a memory 92. When the processing circuit 90 is composed of the processor 91 and the memory 92, each function of the processing circuit 90 is implemented by software, firmware, or a combination of software and firmware. The software or firmware is described as a program and stored in the memory 92. In the processing circuit 90, the processor 91 reads out and executes the program stored in the memory 92, thereby realizing each function. That is, the processing circuit 90 has a memory 92 for storing a program whose result is to execute the processing of the communication device 300. The program can also be said to be a program for causing the communication device 300 to execute each function implemented by the processing circuit 90. The program can be provided by a storage medium storing the program, or can be provided by other means such as a communication medium.

[0056] The above-mentioned program can also be said to be the following program: when the decoding device 320 has a storage unit 331 that stores blocks that can be divided into P×P small matrices and is assumed to be the first check matrix of the maximum coding rate as the check matrix of the low-density parity-check code used in communication, the program causes the communication device 300 to execute: a first step, the generation unit 332 uses the rows of small matrix units included in the first check matrix in the column direction to generate a first row in which a part of the blocks are replaced by a 0 matrix; and a second step, the generation unit 332 uses the rows of small matrix units included in the first check matrix in the column direction to further generate a second row in which a specified block is replaced by a 0 matrix and the positions of 1 contained in the small matrices of other blocks are shifted by one or more specified fixed values, thereby generating a second check matrix with a coding rate lower than that of the first check matrix.

[0057] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor), etc. In addition, the memory 92 is, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable ROM), an EEPROM (registered trademark) (Electrically EPROM), or other nonvolatile or volatile semiconductor memory, a magnetic disk, a floppy disk, an optical disk, a compact disk, a mini disk, or a DVD (Digital Versatile Disc), etc.

[0058] Figure 5 This is a diagram showing an example of a processing circuit 93 in the case where the processing circuit of the communication device 300 according to the first embodiment is implemented by dedicated hardware. Figure 5 The processing circuit 93 shown is, for example, equivalent to a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a circuit formed by combining them. The processing circuit may be partially implemented by dedicated hardware and partially implemented by software or firmware. In this way, the processing circuit can implement the above-mentioned functions by dedicated hardware, software, firmware, or a combination thereof.

[0059] The hardware structure of the communication device 300 has been described, and the hardware structure of the communication device 100 is the same. In the communication device 100, the transmission unit 140 is a communicator. The encoding device 110 is implemented by a processing circuit. The processing circuit can be a processor and a memory that executes a program stored in a memory, or it can be dedicated hardware.

[0060] As described above, according to the present embodiment, the generator 122 of the check matrix generator 120 and the generator 332 of the check matrix generator 330 generate the first row in which a part of the blocks are replaced by the 0 matrix, using the rows including the small matrix units in the column direction included in the first check matrix of the maximum coding rate assumed as the check matrix of the LDPC code used in communication and which can be divided into blocks of P×P small matrices. The generator 122 of the check matrix generator 120 and the generator 332 of the check matrix generator 330 use the rows including the small matrix units in the column direction included in the first check matrix to further generate the second row in which the predetermined block is replaced by the 0 matrix and the positions of 1 included in the small matrices of other blocks are shifted by one or more predetermined fixed values, thereby generating the second check matrix having a lower coding rate than the first check matrix. Therefore, the encoding device 110 having the check matrix generator 120 and the decoding device 320 having the check matrix generator 330 can suppress the degradation of the code performance when the number of rows of the check matrix is ​​increased.

[0061] Implementation Method 2

[0062] exist Figure 1 In the communication system 400 shown, the communication device 300 performs encoding processing in the communication device 100, and the decoding device 320 performs decoding processing on the signal received from the communication device 100 via the communication path 200. In the decoding device 320, the decoding unit 340 obtains the parity check matrix from the check matrix generation device 330, and generates a decoding result by repeatedly performing row operation processing and column operation processing. In the second embodiment, the row operation processing performed by the decoding unit 340 of the decoding device 320 is described.

[0063] Figure 6 This is a diagram showing a configuration example of a communication system 400 including communication devices 100 and 300 according to the second embodiment. Figure 6 The communication system 400 of the second embodiment shown in FIG. Figure 1 The communication system 400 of the first embodiment shown in FIG. 1 describes in detail the structure of the decoding unit 340 of the communication device 300. The decoding unit 340 uses the first check matrix or the second check matrix to perform a decoding process by repeatedly performing a row operation process and a column operation process. Figure 6 As shown, the decoding unit 340 includes a row operation unit 341 , a column operation unit 342 , and a storage unit 343 .

[0064] The row operation unit 341 performs row operation processing repeatedly performed by the decoding unit 340. The detailed structure and operation of the row operation unit 341 will be described later. The column operation unit 342 performs column operation processing repeatedly performed by the decoding unit 340. The detailed structure and operation of the column operation unit 342 will be described in Embodiment 3. The storage unit 343 stores the intermediate operation results of the row operation processing repeatedly performed by the row operation unit 341 and the column operation processing repeatedly performed by the column operation unit 342. In addition, in the decoding device 320, the storage unit 343 stores the row operation processing repeatedly performed by the row operation unit 341 and the column operation processing repeatedly performed by the column operation unit 342. Figure 6 In the example of , the storage unit 343 is composed of one storage unit, but may be composed of a plurality of storage units. The storage unit 343 may be composed of one storage unit together with the storage unit 331 included in the check matrix generation device 330.

[0065] The detailed structure and operation of the row operation unit 341 will be described. Figure 7 1 is a diagram showing a configuration example of a row operation unit 341 included in a decoding unit 340 according to Embodiment 2. The row operation unit 341 includes a mask unit 2 including mask units 2-1 to 2-K, a shift unit 3 including shift units 3-1 to 3-K, a row operation processing unit 4 including row operation processing units 4-1 to 4-P, a shift unit 5 including shift units 5-1 to 5-K, a memory switching unit 6, and a row block number counter 8. In addition, Figure 7 FIG. 2 shows a part of a storage unit 343 included in the decoding unit 340. The storage unit 343 includes a row operation input memory 1 composed of row operation input memories 1-1 to 1-K and a column operation input memory 7 composed of column operation input memories 7-1 to 7-L. Figure 7 In the equation, K is the number of P×P small matrices contained in one row block of the parity check matrix. When the code length is N, K=N / P is used to represent it. In addition, K, N and P are positive integers.

[0066] Next, the operation of the row operation unit 341 is described. First, in the communication device 300, the receiving unit 310 performs demodulation processing on the signal received from the communication device 100 via the communication path 200, and outputs the received soft decision data to the decoding device 320. In the storage unit 343, K parallel row operation input memories 1-1 to 1-K store the received soft decision data as initial values. Specifically, the received soft decision data is separated into P words, and P words of received soft decision data are written at one address in the row operation input memories 1-1 to 1-K.

[0067] In the row operation unit 341, the masking units 2-1 to 2-K simultaneously read the data written in the row operation input memory 1-1 to 1-K in units of blocks. That is, the masking unit 2 simultaneously reads K data written in the row operation input memory 1. The masking unit 2 performs mask processing on the blocks corresponding to the 0 matrix in the parity check matrix. The masking unit 2 outputs the blocks corresponding to the matrix after the unit matrix is ​​shifted in the parity check matrix without performing any special processing, rather than the blocks corresponding to the 0 matrix.

[0068] The shift unit 3 performs shift processing on the blocks of the parity check matrix that are equivalent to the unit matrix after the unit matrix is ​​shifted, rather than the blocks that are equivalent to the 0 matrix, that is, the blocks that have not been processed by the mask unit 2, so that they return to the amount equivalent to the shift amount after the unit matrix is ​​shifted. In this way, the received soft decision data written to the row operation input memories 1-1 to 1-K are subjected to mask processing based on the mask unit 2 or shift processing based on the shift unit 3 and input to the row operation processing unit 4.

[0069] In addition, regarding the operation of the mask unit 2 and the shift unit 3, the row block number counter 8 controls the operation based on the row block number being processed. The row block number counter 8 counts the row block number being processed. The row block number counter 8 controls the operation of the mask unit 2, the shift unit 3, the shift unit 5, and the memory switching unit 6 based on the counted value, that is, the row block number. It is assumed that the row block number counter 8 obtains information on the coding rate of the parity check matrix used in the communication device 100 and the communication device 300 by the method described in the first embodiment.

[0070] The row operation processing unit 4 divides the data output from the shift unit 3 and not masked by the mask unit 2 into P data. The data divided into P data are input to any one of the corresponding row operation processing units 4-1 to 4-P. The row operation processing units 4-1 to 4-P perform row operation processing on the S data inputted except the data masked by the mask unit 2 among the K data outputted from the shift unit 3, generate S data and output them. In addition, S is a positive integer less than K. For example, when the row operation processing is performed by the Min-sum algorithm, the row operation processing units 4-1 to 4-P of the row operation processing unit 4 generate and output the value obtained by the product of the minimum value of the absolute value of S combinations and the positive and negative signs for (S-1) data after removing one data respectively. The row operation processing unit 4 combines the S data from the row operation processing units 4-1 to 4-P operating in parallel in units of blocks, i.e., data stored in the row operation input memories 1-1 to 1-K, and outputs the K data after the row operation processing.

[0071] The shift unit 5 performs an inverse shift process in the opposite direction to the shift process in the shift unit 3 on the data output from the row operation processing unit 4. The shift unit 5 does not perform an inverse shift process on the portion that has not been shifted by the shift unit 3.

[0072] The memory switching unit 6 stores the data that has been subjected to the inverse shift process or the data that has not been subjected to the inverse shift process by the shift unit 5 in the corresponding address of the column operation input memory 7 .

[0073] The row block number counter 8 also controls the operations of the shift unit 5 and the memory switching unit 6 based on the row block number being processed. The row block number counter 8 specifies the memory number and address of the L parallel column operation input memories 7-1 to 7-L into which data is to be written to the memory switching unit 6.

[0074] Data that is subjected to row operation processing by the row operation unit 341 and is used in column operation by the column operation unit 342 described later is written to the column operation input memories 7 - 1 to 7 -L.

[0075] Figure 8 1 is a flowchart showing the row operation operation performed by the row operation unit 341 of the decoding unit 340 according to the second embodiment. In the row operation unit 341, the mask unit 2 reads data from the row operation input memory 1 of the storage unit 343 (step S201), and when it is a block corresponding to the zero matrix (step S202: Yes), the mask unit 2 performs mask processing (step S203) and outputs it to the shift unit 3. In addition, when the mask unit 2 is not a block corresponding to the zero matrix (step S202: No), the mask unit 2 outputs it to the shift unit 3 without performing mask processing. When the data obtained from the mask unit 2 is a block after the unit matrix is ​​shifted (step S204: Yes), the shift unit 3 performs shift processing to shift the data back by an amount corresponding to the shift amount (step S205), and outputs it to the row operation processing unit 4. In addition, when the data is not a block after the unit matrix is ​​shifted (step S204: No), the shift unit 3 outputs it to the row operation processing unit 4 without performing shift processing.

[0076] The row operation processing unit 4 performs row operation processing using the data obtained from the shift unit 3 (step S206), and outputs the result of the row operation processing to the shift unit 5. When the data obtained from the row operation processing unit 4 is equivalent to the data after the shift processing by the shift unit 3 (step S207: Yes), the shift unit 5 performs inverse shift processing in the opposite direction to the shift unit 3 (step S208) and outputs it to the memory switching unit 6. In addition, when the data is not equivalent to the data after the shift processing by the shift unit 3 (step S207: No), the shift unit 5 does not perform inverse shift processing and outputs it to the memory switching unit 6. Based on the instruction of the row block number counter 8, the memory switching unit 6 causes the column operation input memory 7 to store the data obtained from the shift unit 5 (step S209).

[0077] As described above, according to the present embodiment, in the decoding unit 340 of the decoding device 320, the row operation unit 341 performs masking and shifting according to the position in the parity check matrix in which the 0 matrix is ​​configured in the row operation repeatedly performed, thereby making it possible to easily perform row operations for LDPC codes of multiple coding rates whose coding rates are extended by the method described in Embodiment 1. As row operation processing, the row operation unit 341 performs masking processing on blocks of small matrices replaced with 0 matrices, and performs shift processing on blocks of small matrices shifted by a fixed value to return the shift amount, thereby making it possible to perform the same operation processing as the row operation processing for the first parity check matrix even when using a parity check matrix of a different coding rate.

[0078] Implementation 3

[0079] exist Figure 1 In the communication system 400 shown, the communication device 300 performs a decoding process on a signal that is encoded by the communication device 100 and received from the communication device 100 via the communication path 200 in the decoding device 320. In the decoding device 320, the decoding unit 340 obtains the parity check matrix from the check matrix generation device 330, and generates a decoding result by repeatedly performing row operation processing and column operation processing. In the third embodiment, the column operation processing performed by the decoding unit 340 of the decoding device 320 is described.

[0080] In the third embodiment, the structure of the communication system 400 including the communication devices 100 and 300 is the same as that of the Figure 6 The communication system 400 including the communication devices 100 and 300 of the second embodiment shown has the same structure.

[0081] The detailed structure and operation of the column calculation unit 342 will be described. Fig. 9 1 is a diagram showing a configuration example of a column operation unit 342 included in a decoding unit 340 according to Embodiment 3. The column operation unit 342 includes a mask unit 10 including mask units 10-1 to 10-L, a column operation processing unit 11 including column operation processing units 11-1 to 11-P, a memory switching unit 12, and a column block number counter 13. Fig. 9 FIG. 2 shows a part of a storage unit 343 included in the decoding unit 340. The storage unit 343 includes a row operation input memory 1 composed of row operation input memories 1-1 to 1-K, a column operation input memory 7 composed of column operation input memories 7-1 to 7-L, and an input memory 9. Fig. 9 In the equation, L is the number of P×P small matrices contained in one column block in the parity check matrix. When the code length is N and the information bit length is J, it is represented by L=(NJ) / P. In addition, J, L, N and P are positive integers.

[0082] Next, the operation of the column operation unit 342 is described. First, in the communication device 300, the receiving unit 310 performs demodulation processing on the signal received from the communication device 100 via the communication path 200, and outputs the received soft decision data to the decoding device 320. In the storage unit 343, the input memory 9 stores the received soft decision data. Specifically, the received soft decision data of P words is written to one address of the input memory 9. In addition, in the L parallel column operation input memories 7-1 to 7-L, no value is input when the received soft decision data is input to the input memory 9, but the result of the row operation processing is written by the row operation unit 341 described in the second embodiment.

[0083] The column operation unit 342 simultaneously reads the data written to the input memory 9 and the L parallel column operation input memories 7-1 to 7-L. In the column operation unit 342, the masking units 10-1 to 10-L simultaneously read the data written to the column operation input memories 7-1 to 7-L in units of blocks. That is, the masking unit 10 simultaneously reads the L data written to the column operation input memory 7. The masking unit 10 performs mask processing on the blocks corresponding to the 0 matrix in the parity check matrix. The masking unit 10 outputs the blocks corresponding to the matrix after the unit matrix is ​​shifted in the parity check matrix without performing any special processing, rather than the blocks corresponding to the 0 matrix.

[0084] In addition, regarding the operation of the mask unit 10, the column block number counter 13 controls based on the column block number being processed. The column block number counter 13 counts the column block number being processed. The column block number counter 13 controls the operation of the mask unit 10 and the memory switching unit 12 based on the counted value, that is, the column block number. It is assumed that the column block number counter 13 obtains information on the coding rate of the parity check matrix used in the communication device 100 and the communication device 300 by the method described in the first embodiment.

[0085] The column operation processing unit 11 divides the received soft decision data read from the input memory 9 and the data not masked in the mask unit 10 into P data respectively. The data divided into P data are input to any one of the corresponding column operation processing units 11-1 to 11-P. The column operation processing units 11-1 to 11-P perform column operation processing on the T data input except the data masked by the mask unit 10 among the L data output from the mask unit 10, generate T data and output them. In addition, T is a positive integer less than L. As a column operation processing operation, the column operation processing unit 11 generates T data obtained by adding (T-1) data after removing 1 data from the T data input and the value of the received soft decision data from the input memory 9, and outputs them.

[0086] Here, the column operation processing unit 11, after performing a predetermined number of repetitive column operation operations, uses the sign bit of the value obtained by adding the T data input from the mask unit 10 and the value of the received soft decision data as a decoding result, combines it with the P data from the column operation processing units 11-1 to 11-P that are operating in parallel, and outputs the P-bit data as a decoding result.

[0087] When the column operation operation is not repeated a predetermined number of times, the column operation processing unit 11 combines T data from the column operation processing units 11-1 to 11-P that are operating in parallel with each other in units of blocks, i.e., data stored in the column operation input memories 7-1 to 7-L, and outputs K data after the column operation processing.

[0088] The memory switching unit 12 stores the data output from the column operation processing unit 11 at the corresponding address of the row operation input memory 1 .

[0089] The operation of the memory switching unit 12 is also controlled by the column block number counter 13 based on the column block number being processed. The column block number counter 13 specifies the memory switching unit 12 the memory numbers and addresses of the K parallel row operation input memories 1-1 to 1-K into which data is to be written.

[0090] Data that has been subjected to column operation processing by the column operation unit 342 and used in the row operation of the row operation unit 341 is written into the row operation input memories 1 - 1 to 1 -K.

[0091] Fig.10 1 is a flowchart showing the column operation operation performed by the column operation unit 342 of the decoding unit 340 according to the third embodiment. In the column operation unit 342, the mask unit 10 reads data from the column operation input memory 7 of the storage unit 343 (step S301). When the data is a block corresponding to the zero matrix (step S302: yes), the mask unit 10 performs mask processing (step S303) and outputs the data to the column operation processing unit 11. The column operation processing unit 11 performs column operation processing using the data obtained from the input memory 9 and the mask unit 10 (step S304). When the column operation processing is not performed for a predetermined number of times (step S305: no), the result of the column operation processing is output to the memory switching unit 12. Based on the instruction of the column block number counter 13, the memory switching unit 12 causes the row operation input memory 1 to store the data obtained from the column operation processing unit 11 (step S306). When the column operation processing unit 11 has performed the column operation processing for a predetermined number of iterations (step S305 : Yes), it outputs the result of the column operation processing as a decoding result (step S307 ).

[0092] As described above, according to the present embodiment, in the decoding unit 340 of the decoding device 320, the column operation unit 342 performs masking according to the position in the parity check matrix in which the 0 matrix is ​​arranged in the column operation repeatedly performed, thereby making it possible to easily perform column operations for LDPC codes of multiple coding rates whose coding rates are extended by the method described in Embodiment 1. As the column operation, the column operation unit 342 performs masking on blocks of small matrices replaced with 0 matrices, thereby making it possible to perform the same operation as the column operation for the second parity check matrix with the lowest coding rate even when using a parity check matrix of a different coding rate.

[0093] The configuration described in the above embodiment is merely an example, and can be combined with other known technologies, the embodiments can be combined with each other, and part of the configuration can be omitted or modified within a scope not departing from the gist.

[0094] Description of symbols

[0095] 1. 1-1 to 1-K: row operation input memory; 2. 2-1 to 2-K, 10. 10-1 to 10-L: mask unit; 3. 3-1 to 3-K, 5. 5-1 to 5-K: shift unit; 4. 4-1 to 4-P: row operation processing unit; 6. 12: memory switching unit; 7. 7-1 to 7-L: column operation input memory; 8: row block number counter; 9: input memory; 11. 11-1 to 11-P: column operation processing unit ; 13: column block number counter; 100, 300: communication device; 110: encoding device; 120, 330: check matrix generating device; 121, 331, 343: storage unit; 122, 332: generating unit; 130: encoding unit; 140: sending unit; 200: communication path; 310: receiving unit; 320: decoding device; 340: decoding unit; 341: row operation unit; 342: column operation unit; 400: communication system.

Claims

1. A decoding device, characterized in that: Let P be a positive integer, The decoding device has: A storage unit that stores a first check matrix of a maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity-check code used in communication; as well as A generating unit, which uses the rows of the units of the small matrix in the column direction included in the first check matrix to generate a first row in which a part of the blocks are replaced by a 0 matrix, and further generates one or more second rows in which the positions of 1s included in the small matrices of other blocks are replaced by a 0 matrix and shifted by a specified fixed value, thereby generating a second check matrix with a lower coding rate than the first check matrix.

2. The decoding device according to claim 1, characterized in that When generating one of the second rows, the generating unit replaces blocks that have not been replaced with a zero matrix in the first row with a zero matrix as the predetermined blocks.

3. The decoding device according to claim 1, characterized in that When generating two or more of the second rows, the generating unit replaces different blocks with a 0 matrix as the predetermined blocks according to the two or more second rows, and sets the fixed value to a different value according to the two or more second rows.

4. The decoding device according to any one of claims 1 to 3, characterized in that: The generating unit generates the first row and one or more second rows for each row, using a plurality of rows that are included in the first check matrix and include the unit of the small matrix in the column direction.

5. The decoding device according to any one of claims 1 to 4, characterized in that: The decoding device includes a decoding unit that uses the first check matrix or the second check matrix to perform a decoding process that repeatedly performs a row operation process and a column operation process.

6. The decoding device according to claim 5, characterized in that The decoding unit includes a row operation unit, which performs mask processing on blocks of the small matrix replaced by the 0 matrix as the row operation processing, and performs shift processing on blocks of the small matrix after shifting by the fixed value to return the shift amount, thereby, even if a check matrix with a different coding rate is used, the same operation processing as the row operation processing for the first check matrix is ​​performed.

7. The decoding device according to claim 5 or 6, characterized in that: The decoding unit includes a column operation unit, which performs masking processing on blocks of small matrices replaced with the 0 matrix as the column operation processing, thereby performing the same operation processing as the column operation processing for the second check matrix with the smallest coding rate even when using a check matrix with a different coding rate.

8. A control circuit for controlling a decoding device, characterized in that: Let P be a positive integer, The decoding device includes a storage unit that stores a first check matrix of a maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity check code used in communication, The control circuit enables the decoding device to implement: Using the rows of the small matrix units in the column direction included in the first check matrix, a first row of a matrix in which a part of blocks is replaced with 0 is generated, Using the rows of the units of the small matrix in the column direction contained in the first check matrix, a second check matrix having a lower coding rate than the first check matrix is ​​generated by replacing a specified block with a 0 matrix and shifting the positions of 1s contained in the small matrices of other blocks by a specified fixed value.

9. A storage medium storing a program for controlling a decoding device, characterized in that: Let P be a positive integer, The decoding device includes a storage unit that stores a first check matrix of a maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity check code used in communication, The program causes the decoding device to implement: Using the rows of the small matrix units in the column direction included in the first check matrix, a first row of a matrix in which a part of blocks is replaced with 0 is generated, Using the rows of the units of the small matrix in the column direction contained in the first check matrix, a second check matrix having a lower coding rate than the first check matrix is ​​generated by replacing a specified block with a 0 matrix and shifting the positions of 1s contained in the small matrices of other blocks by a specified fixed value.

10. A method for generating a check matrix of a decoding device, characterized in that: Let P be a positive integer, The decoding device includes a storage unit that stores a first check matrix of a maximum coding rate that can be divided into blocks of P×P small matrices and is assumed as a check matrix of a low-density parity check code used in communication, The check matrix generation method comprises: In the first step, a generator generates a first row in which a part of blocks is replaced with a 0 matrix, using a row in the first check matrix that includes the unit of the small matrix in the column direction; and In the second step, the generating unit uses the rows of the units of the small matrix in the column direction contained in the first check matrix, and further generates one or more second rows after replacing the specified blocks with 0 matrices and shifting the positions of 1s contained in the small matrices of other blocks by a specified fixed value, thereby generating a second check matrix with a lower coding rate than the first check matrix.

11. The method for generating a check matrix according to claim 10, characterized in that: In the second step, when the generating unit generates one of the second rows, the generating unit replaces the blocks that have not been replaced with the zero matrix in the first row with the zero matrix as the predetermined blocks.

12. The method for generating a check matrix according to claim 10, characterized in that: In the second step, when the generating unit generates more than two second rows, the generating unit replaces different blocks with 0 matrices as the specified blocks according to more than two second rows, and sets the fixed value to different values ​​according to more than two second rows.

13. The method for generating a check matrix according to any one of claims 10 to 12, characterized in that: In the first step, the generating unit generates the first row for each row using a plurality of rows that are included in the first check matrix and that include the unit of the small matrix in the column direction. In the second step, the generating unit generates one or more second rows for each row, using a plurality of rows that are included in the first check matrix and that include the unit of the small matrix in the column direction.

14. The method for generating a check matrix according to any one of claims 10 to 13, characterized in that: The parity check matrix generation method further includes a third step in which a decoding unit uses the first parity check matrix or the second parity check matrix to perform a decoding process of repeatedly performing a row operation process and a column operation process.

15. The method for generating a check matrix according to claim 14, characterized in that: In the third step, as the row operation processing, the decoding unit performs mask processing on the blocks of the small matrix replaced by the 0 matrix, and performs shift processing on the blocks of the small matrix after shifting by the fixed value to return the shift amount, thereby, even if a check matrix with a different coding rate is used, the same operation processing as the row operation processing for the first check matrix is ​​performed.

16. The method for generating a check matrix according to claim 14 or 15, characterized in that: In the third step, as the column operation processing, the decoding unit performs mask processing on the blocks of the small matrix replaced by the 0 matrix, thereby performing the same operation processing as the column operation processing for the second check matrix with the smallest coding rate even when using a check matrix with a different coding rate.

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