Data writing method, device, equipment and medium

Abstract

The embodiment of the present application provides a data writing method, a data writing device, a computer device and a computer-readable storage medium, which relates to the field of computer technology. The data writing method includes: based on a target cache line miss request, directly allocating an entry for the target cache line miss request in a first cache line buffer, merging the target to-be-written data corresponding to the target cache line miss request into the entry, and when it is detected that all the data in the entry is written, writing the merged entry into the memory. Compared with the related art, there is no need to read the cache line from the memory first, and the entry can be directly allocated and the target to-be-written data can be merged into the entry, thereby saving memory access time and thus improving data writing efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular, to a data writing method, a data writing device, a computer equipment and a computer-readable storage medium. Background Art

[0002] The central processing unit (CPU) is the core hardware component of a computer, responsible for executing instructions and controlling various operations of the computer. Memory is a component in a computer system used to store data and instructions, which can provide data access for the CPU to support the CPU's calculation and processing tasks. Data cache (dcache) can provide faster data access for the CPU, but due to the storage technology it uses, its storage capacity is smaller than that of memory. Therefore, data cache usually stores a small amount of data to support the CPU's needs to read and write data.

[0003] When the data that the CPU needs to write is not in the data cache, a cache miss occurs. In this case, it is usually necessary to read the cache line corresponding to the data to be written from the memory to the buffer (lbuf), and merge the cache line and the data to be written in the buffer (line buffer, lbuf). After the data merge is completed, the new cache line is written back to the memory.

[0004] However, the above method consumes a lot of memory access time, which leads to the problem of low data writing efficiency. Summary of the invention

[0005] The embodiments of the present application provide a data writing method, a data writing device, a computer device and a computer-readable storage medium, which can overcome the problem of low data writing efficiency caused by long memory access time.

[0006] A first aspect of an embodiment of the present application provides a data writing method, comprising:

[0007] In response to the target cache line miss request, allocating an entry in the first cache line buffer for the target cache line miss request;

[0008] Merge the target to-be-written data corresponding to the target cache line miss request into the entry;

[0009] When it is detected that all the data in the entry has been written, the merged entry is written into the memory.

[0010] In an optional embodiment of the present application, the above method further includes:

[0011] When it is detected that not all data in the entry has been written, reading an existing cache line corresponding to the target cache line miss request from the memory into a second cache line buffer;

[0012] In the second cache line buffer, merging the target data to be written into the existing cache line;

[0013] Write the merged existing cache lines into memory.

[0014] In an optional embodiment of the present application, the above method further includes:

[0015] When a write instruction is received, the storage address corresponding to the write instruction is searched in the cache;

[0016] When the storage address exists in the cache, the target data to be written is written into the cache;

[0017] When a store address does not exist in the cache, a target cache line miss request is generated.

[0018] In an optional embodiment of the present application, in response to a target cache line miss request, allocating an entry for the target cache line miss request in a first cache line buffer includes:

[0019] In response to the specified cache line miss request, reading the specified cache line corresponding to the specified cache line miss request from the memory into the second cache line buffer;

[0020] Merge the to-be-written data in the specified cache line miss request into the specified cache line;

[0021] If it is detected that all data in the specified cache line is written, the merged specified cache line is written into the memory and the counter is updated;

[0022] When the value of the counter meets a preset condition, in response to the target cache line miss request, an entry is allocated in the first cache line buffer for the target cache line miss request.

[0023] In an optional embodiment of the present application, the above method further includes:

[0024] When the value of the counter is greater than or equal to the preset value, it is determined that the value of the counter meets the preset condition.

[0025] In an optional embodiment of the present application, the above method further includes:

[0026] When it is detected that not all data in the entry has been written, the value of the counter is cleared.

[0027] In an optional embodiment of the present application, the above method further includes:

[0028] When it is detected that the valid bit and dirty bit corresponding to each data block in the entry are both 1 and the write status is true, it is determined that all data in the entry is written.

[0029] A second aspect of an embodiment of the present application provides a data writing device, including:

[0030] a cache line allocation unit, configured to allocate an entry in a first cache line buffer in response to a target cache line miss request for the target cache line miss request;

[0031] A data merging unit, configured to merge the target to-be-written data corresponding to the target cache line miss request into the entry;

[0032] The data writing unit is used to write the merged entry into the memory when it is detected that all the data in the entry has been written.

[0033] In an optional embodiment of the present application, the above device further includes:

[0034] A cache line reading unit, configured to read an existing cache line corresponding to a target cache line miss request from a memory into a second cache line buffer when it is detected that not all data in the entry has been written;

[0035] The data merging unit is further used to merge the target to-be-written data into the existing cache line in the second cache line buffer;

[0036] The data writing unit is also used to write the merged existing cache lines into the memory.

[0037] In an optional embodiment of the present application, the above device further includes:

[0038] A query unit, configured to query a storage address corresponding to the write instruction in the cache after receiving the write instruction;

[0039] A response unit, used for writing the target data to be written into the cache when the storage address exists in the cache;

[0040] The request generation unit is used to generate a target cache line miss request when the storage address does not exist in the cache.

[0041] In an optional embodiment of the present application, the cache line allocation unit allocates an entry for the target cache line miss request in the first cache line buffer in response to the target cache line miss request, including:

[0042] In response to the specified cache line miss request, reading the specified cache line corresponding to the specified cache line miss request from the memory into the second cache line buffer;

[0043] Merge the to-be-written data in the specified cache line miss request into the specified cache line;

[0044] If it is detected that all data in the specified cache line is written, the merged specified cache line is written into the memory and the counter is updated;

[0045] When the value of the counter meets a preset condition, in response to the target cache line miss request, an entry is allocated in the first cache line buffer for the target cache line miss request.

[0046] In an optional embodiment of the present application, the above device further includes:

[0047] The condition determination unit is used to determine whether the value of the counter satisfies a preset condition when the value of the counter is greater than or equal to a preset value.

[0048] In an optional embodiment of the present application, the above device further includes:

[0049] The counter control unit is used to clear the value of the counter when it is detected that not all data in the entry has been written.

[0050] In an optional embodiment of the present application, the above device further includes:

[0051] The detection unit is used to determine that all data in the entry are written when it is detected that the valid bit and the dirty bit corresponding to each data block in the entry are both 1 and the write status is true.

[0052] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0053] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0054] The embodiment of the present application can directly allocate entries for the target cache line miss request in the first cache line buffer based on the target cache line miss request, merge the target to-be-written data corresponding to the target cache line miss request into the entry, and write the merged entry into the memory when it is detected that all the data in the entry has been written. On the one hand, compared with the related art, there is no need to read the cache line from the memory first, and the entry can be directly allocated and the target to-be-written data can be merged into the entry, thereby saving memory access time and improving data writing efficiency. On the other hand, since the present application writes the merged entry into the memory only when it is detected that all the data in the entry has been written, this can avoid writing the erroneous entry that has not been fully written back to the memory, thereby avoiding the problem of erroneous write back. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0056] Figure 1 A schematic diagram of the computer device structure provided for one embodiment of the present application;

[0057] Figure 2 A flowchart of a data writing method provided by one embodiment of the present application;

[0058] Figure 3 A schematic diagram of a storage structure including a first cache line buffer and a second cache line buffer provided for one embodiment of the present application;

[0059] Figure 4 A flowchart of a data writing method provided by another embodiment of the present application;

[0060] Figure 5 A schematic diagram of the structure of a data writing device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0061] In the process of implementing the present application, the inventor discovered that the current automated way of implementing division operations consumes a lot of equipment resources.

[0062] In response to the above problems, a data writing method is provided in an embodiment of the present application to save memory access time and thereby improve data writing efficiency.

[0063] The solutions in the embodiments of the present application can be implemented in various languages, for example, Verilog, SystemVerilog, SystemC, and Chisel.

[0064] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0065] The following is a brief description of the application environment of the data writing method provided in the embodiment of the present application:

[0066] For example, Figure 1 The following is a schematic diagram of a computer device provided in an embodiment of the present application. The computer device may be a terminal. Figure 1As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program, etc. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data writing method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0067] See also Figure 2 The following embodiments take the above-mentioned computer device as the execution subject, and apply the data writing method provided in the embodiment of the present application to the above-mentioned computer device as an example for specific description. The data writing method provided in the embodiment of the present application includes the following steps 201 to 203:

[0068] Step 201 : In response to a target cache line miss request, allocate an entry for the target cache line miss request in a first cache line buffer.

[0069] Specifically, since the related technology needs to first read from the memory into lbuf, then merge the data in lbuf, and then write it back to the memory, this process has the problem of low data writing efficiency and requires more memory access time.

[0070] Therefore, the present application configures a first cache line buffer, in which direct data merging can be achieved. That is, after receiving a target cache line miss request, there is no need to read the corresponding cache line from the memory. An entry can be directly allocated to the target cache line miss request in the first cache line buffer, and data merging can be achieved in the entry, and then written back to the memory. This can save memory access time and improve data writing efficiency.

[0071] The first cache line buffer is implemented in the form of a register array, etc., and the specific form of the first cache line buffer is not limited here. In this application, the functions that can be implemented by the first cache line buffer include but are not limited to data merging, data caching, and stream data processing functions, which are not limited in the embodiments of this application.

[0072] Exemplarily, the first cache line buffer may be represented as ws_lbuf. It is understandable that in actual application, the first cache line buffer may also be named in other ways that suit the needs, and the present application does not limit this.

[0073] When a target cache line miss request is received, an entry can be allocated for the target cache line miss request in the first cache line buffer; wherein the entry can be used to store data blocks and metadata related to the data blocks, and after the entry is allocated, the target to-be-written data corresponding to the target cache line miss request can be merged into the entry. An entry is the same size as a cache line (cacheLine) in memory (e.g., 64 bytes), and a cache line is the smallest unit in cache storage. The first cache line buffer may include one or more entries, which is not limited in the embodiments of the present application.

[0074] Step 202: Merge the target to-be-written data corresponding to the target cache line miss request into an entry.

[0075] Specifically, the target data to be written can be merged with the entry. If the target data to be written is used to merge all the data in the entry, the entry can be replaced with the target data to be written. If the target data to be written is used to merge part of the data in the entry, the data to be replaced in the entry can be replaced with the target data to be written.

[0076] Step 203: When it is detected that all the data in the entry has been written, the merged entry is written into the memory.

[0077] Among them, when all the data in the entry is written, it means that the write mode is streaming_mode_write. Streaming_mode_write refers to a mode of continuous data writing, which is suitable for sequential write operations of large amounts of data. In streaming_mode_write mode, data is written in a stream manner, and there is no need to wait for confirmation of each write operation. In one example, when the compiler compiles a memcpy function for copying a block of memory data from a source memory address to a target memory address or a memset function for setting a block of memory to a specific value, when these functions are called in the source code, the compiler analyzes the parameters of the function (such as the source address, the target address, and the number of bytes). In order to improve performance, the compiler usually generates a set of compact storage instructions (store instructions) instead of processing byte by byte, which can utilize the processor's memory writing capability and reduce the number of instructions and execution time. These instructions write data blocks to memory in a continuous manner. This write mode is the mode of continuous data writing.

[0078] Based on this, accurate entries that have not been written by mistake can be obtained, and then the entries can be written into the memory. The specific way of writing into the memory is to replace the data of the cache line in the memory corresponding to the target cache line miss request with the data in the entry. Furthermore, after completing the memory write, the request response result can be returned to the upstream module (such as the load store unit (LSU), address generation unit (AGU), etc.).

[0079] In an optional embodiment of the present application, the above method further includes:

[0080] When it is detected that not all data in the entry has been written, reading an existing cache line corresponding to the target cache line miss request from the memory into a second cache line buffer;

[0081] In the second cache line buffer, merging the target data to be written into the existing cache line;

[0082] Write the merged existing cache lines into memory.

[0083] Specifically, if not all data in the entry is written, it means that the write mode is non-streaming mode write, which is a non-continuous write mode, usually involving the write operation of a single data item or a small block of data. In this mode, each write operation needs to wait for confirmation to ensure that the data has been successfully written.

[0084] Based on this, it can be considered that not all data in the entry has been written, that is, the data that has not been written in the entry may be different from that stored in the memory. If the entry overwrites the corresponding cache line in the memory, this will cause a wrong write problem.

[0085] Therefore, the existing cache line corresponding to the target cache line miss request can be read from the memory to the second cache line buffer; wherein, the existing cache line refers to the cache line corresponding to the target cache line miss request in the memory, and the existing cache line records the existing data. After reading the existing cache line into the entry of the second cache line buffer, the target data to be written can be written to the corresponding position in the existing cache line to achieve replacement of part of the data in the existing cache line, and then, the merged new cache line is used to write back to the memory so that the data stored at the address in the memory remains up to date; wherein, the second cache line buffer can usually contain multiple entries for data merging with the read cache line.

[0086] For a schematic diagram of the structure of the first cache line buffer and the second cache line buffer, please refer to Figure 3 .

[0087] exist Figure 3 In the embodiment, the first cache line buffer (lbuf) and the second cache line buffer (ws_lbuf) can both receive requests sent from the cache (decache) and can both write entries back to the memory (memory). The first cache line buffer can include an entry assigned to the target cache line miss request, so that the target to-be-written data corresponding to the target cache line miss request can be directly merged into the entry to save memory access time.

[0088] The second cache line buffer may include multiple entries (e.g., entry0, entry1, entry2, ..., entryn, where n is a positive integer), which are used to merge data with corresponding cache lines read from the memory based on different requests, and perform a write-back operation after the data merge is completed. Writing data through the first cache line buffer and the second cache line buffer in parallel can save the memory access time of streaming writing and meet the non-streaming writing requirements.

[0089] It can be seen that by implementing this optional embodiment, when not all data in the entry is written, the write operation can be processed by the second cache line buffer to ensure that the cache line in the memory is correctly written.

[0090] In an optional embodiment of the present application, the above method further includes:

[0091] When a write instruction is received, the storage address corresponding to the write instruction is searched in the cache;

[0092] When the storage address exists in the cache, the target data to be written is written into the cache;

[0093] When a store address does not exist in the cache, a target cache line miss request is generated.

[0094] Specifically, after receiving a write instruction (store instruction) sent by the CPU, the storage address corresponding to the write instruction can be queried in the cache. If the storage address does not exist in the cache, it means that there is no cache line in the cache that can support writing, and the data required to be written by the write instruction cannot be replaced in the cache line. In this case, a target cache line miss request needs to be generated to trigger a direct write operation in the first cache line buffer or a read-first-then-write operation in the second cache line buffer. In addition, if the storage address exists in the cache, it means that the cache line where the data required to be written by the write instruction is located can be queried, and then the target data to be written can be written into the cache, that is, the data write operation is performed.

[0095] It can be seen that by implementing this optional embodiment, a target cache line miss request for triggering a subsequent write process can be generated in a timely manner when a cache line is missed.

[0096] In an optional embodiment of the present application, in response to a target cache line miss request, allocating an entry for the target cache line miss request in a first cache line buffer includes:

[0097] In response to the specified cache line miss request, reading the specified cache line corresponding to the specified cache line miss request from the memory into the second cache line buffer;

[0098] Merge the to-be-written data in the specified cache line miss request into the specified cache line;

[0099] If it is detected that all data in the specified cache line is written, the merged specified cache line is written into the memory and the counter is updated;

[0100] When the value of the counter meets a preset condition, in response to the target cache line miss request, an entry is allocated in the first cache line buffer for the target cache line miss request.

[0101] Specifically, when a specified cache line miss request is received, a read-before-write process can be performed for the specified cache line miss request, that is, the specified cache line corresponding to the specified cache line miss request is read from the memory to the second cache line buffer, and the data is merged in the second cache line buffer and then written back to the memory and the counter is updated. If a target cache line miss request is detected again, whether the counter meets the preset conditions is detected. If it is satisfied, it means that multiple streaming writes have been performed. For the next request, the operation of directly merging data in the first cache line buffer can be performed; wherein, the target cache line miss request has the same structure as the specified cache line miss request, except that the corresponding sending time is different and the corresponding data to be written is different. In addition, the preset condition defines the condition for enabling the first cache line buffer. In addition, the method for updating the counter can be adding 1, or any method for updating the counter, which is not limited here.

[0102] It can be seen that by implementing this optional embodiment, when the value of the counter meets the preset condition, a direct data merge operation can be implemented based on the first cache line buffer, which can reduce the probability of using the first cache line buffer but failing to write all entries to a certain extent.

[0103] In an optional embodiment of the present application, the above method further includes:

[0104] When the value of the counter is greater than or equal to the preset value, it is determined that the value of the counter meets the preset condition.

[0105] Specifically, the preset value can be expressed as a positive integer or other forms, and the preset value can be configured through a register, which is not limited in the embodiments of the present application. The preset value can be a personalized value or a value corresponding to the data type / data source of the target data to be written. In addition, optionally, when the value of the counter satisfies a preset expression, it is determined that the value of the counter meets the preset condition; wherein the variables included in the preset expression may include but are not limited to the write time, the operator that triggers the write instruction, the data type, and the data source, which are not limited in the embodiments of the present application.

[0106] It can be seen that by implementing this optional embodiment, when the value of the counter is greater than or equal to the preset value, the first cache line buffer can be used in time to implement a direct data merging operation to save memory access time.

[0107] In an optional embodiment of the present application, the above method further includes:

[0108] When it is detected that not all data in the entry has been written, the value of the counter is cleared.

[0109] Specifically, when it is detected that not all data in the entry is written, not only the target data to be written needs to be read first and then written through the second cache line buffer, but also the value of the counter needs to be cleared. The condition for enabling the first cache line buffer next time is that the counter counts again and accumulates to a preset value.

[0110] It can be seen that by implementing this optional embodiment, when not all data in the entry is written, it can be determined that the next write mode is likely to still be non-streaming write, and the value of the counter can be cleared in time.

[0111] In an optional embodiment of the present application, the above method further includes:

[0112] When it is detected that the valid bit and dirty bit corresponding to each data block in the entry are both 1 and the write status is true, it is determined that all data in the entry is written.

[0113] Specifically, each data block corresponds to a valid bit, a dirty bit, and a write status. The valid bit is used to indicate whether the data in the entry is valid. If the valid bit is 1, it means that the data in the entry is valid; if the valid bit is 0, it means that the data is invalid. The dirty bit is used to indicate whether the data in the entry has been modified. If the dirty bit is 1, it means that the data in the entry has been modified but has not been written back to the main memory; if it is 0, it means that the data has not been modified or has been successfully written back. The write status indicates the current data write status. If the write status is true, it means that the write operation of the data in the entry is in progress or has been completed. When it is detected that the valid bit and dirty bit corresponding to each data block in the entry are 1 and the write status is true, it can be confirmed that the data has been successfully written and is in a valid state.

[0114] It can be seen that by implementing this optional embodiment, it is possible to accurately determine whether all data writing is completed.

[0115] It can be seen that the implementation Figure 2 The method shown can directly allocate entries for the target cache line miss request in the first cache line buffer based on the target cache line miss request, merge the target to-be-written data corresponding to the target cache line miss request into the entry, and write the merged entry into the memory when it is detected that all the data in the entry has been written. On the one hand, compared to the related art, there is no need to read the cache line from the memory first, and the entry can be directly allocated and the target to-be-written data can be merged into the entry, thereby saving memory access time and improving data writing efficiency. On the other hand, since the present application writes the merged entry into the memory only when it is detected that all the data in the entry has been written, this can avoid writing the erroneous entry that has not been fully written back to the memory, thereby avoiding the problem of erroneous write back.

[0116] See also Figure 4 , Figure 4 This is a flow chart of a data writing method provided by another embodiment of the present application. Figure 4 As shown, another embodiment provides a data writing method including: Step 401-Step 412:

[0117] Step 401: after receiving a write instruction, query the cache for the storage address corresponding to the write instruction. If the storage address exists in the cache, execute step 402; if the storage address does not exist in the cache, execute step 403.

[0118] Step 402: Write the target data to be written into the cache.

[0119] Step 403: Generate a target cache line miss request.

[0120] Step 404: In response to the designated cache line miss request, read the designated cache line corresponding to the designated cache line miss request from the memory into the second cache line buffer.

[0121] Step 405: merge the data to be written in the designated cache line miss request into the designated cache line. If it is detected that all the data in the designated cache line is written, execute step 407; if it is detected that not all the data in the designated cache line is written, execute step 406.

[0122] Step 406: Clear the value of the counter.

[0123] Step 407: Write the merged designated cache line into the memory and update the counter.

[0124] Step 408: When receiving a target cache line miss request, determine whether the value of the counter is greater than or equal to a preset value. If yes, execute step 409; if not, respond to the target cache line miss request based on the method defined in steps 404 to 405.

[0125] Step 409: In response to the target cache line miss request, allocate an entry for the target cache line miss request in the first cache line buffer.

[0126] Step 410: merge the target to-be-written data corresponding to the target cache line miss request into the entry. When it is detected that all the data in the entry is written, execute step 411; when it is detected that not all the data in the entry is written, execute step 412.

[0127] Step 411: Write the merged entries into the memory and update the counter.

[0128] Step 412: read the existing cache line corresponding to the target cache line miss request from the memory to the second cache line buffer, merge the target data to be written into the existing cache line in the second cache line buffer, and then write the merged existing cache line into the memory and clear the value of the counter.

[0129] It should be noted that steps 401 to 412 are Figure 1 The steps and their embodiments shown correspond to each other. For the specific implementation of steps 401 to 412, please refer to Figure 1 In the steps and their embodiments shown, steps 401 to 412 are used to define an optional execution order between the steps, and the specific implementation methods of steps 401 to 412 are not described in detail here.

[0130] It can be seen that the implementation Figure 4The method shown can directly allocate entries for the target cache line miss request in the first cache line buffer based on the target cache line miss request, merge the target to-be-written data corresponding to the target cache line miss request into the entry, and write the merged entry into the memory when it is detected that all the data in the entry has been written. On the one hand, compared to the related art, there is no need to read the cache line from the memory first, and the entry can be directly allocated and the target to-be-written data can be merged into the entry, thereby saving memory access time and improving data writing efficiency. On the other hand, since the present application writes the merged entry into the memory only when it is detected that all the data in the entry has been written, this can avoid writing the erroneous entry that has not been fully written back to the memory, thereby avoiding the problem of erroneous write back.

[0131] See also Figure 5 An embodiment of the present application provides a data writing device 500, comprising: a cache line allocation unit 510, a data merging unit 520, and a data writing unit 530, wherein:

[0132] A cache line allocation unit 510, configured to allocate an entry for a target cache line miss request in a first cache line buffer in response to the target cache line miss request;

[0133] A data merging unit 520, configured to merge the target to-be-written data corresponding to the target cache line miss request into the entry;

[0134] The data writing unit 530 is configured to write the merged entry into the memory when it is detected that all the data in the entry has been written.

[0135] It can be seen that the implementation Figure 5 The device shown can directly allocate entries for the target cache line miss request in the first cache line buffer based on the target cache line miss request, merge the target to-be-written data corresponding to the target cache line miss request into the entry, and write the merged entry into the memory when it is detected that all the data in the entry has been written. On the one hand, compared to the related art, there is no need to read the cache line from the memory first, and the entry can be directly allocated and the target to-be-written data can be merged into the entry, thereby saving memory access time and improving data writing efficiency. On the other hand, since the present application writes the merged entry into the memory only when it is detected that all the data in the entry has been written, this can avoid writing the erroneous entry that has not been fully written back to the memory, thereby avoiding the problem of erroneous write back.

[0136] In an optional embodiment of the present application, the above device further includes:

[0137] A cache line reading unit, configured to read an existing cache line corresponding to a target cache line miss request from a memory into a second cache line buffer when it is detected that not all data in the entry has been written;

[0138] The data merging unit is further used to merge the target to-be-written data into the existing cache line in the second cache line buffer;

[0139] The data writing unit is also used to write the merged existing cache lines into the memory.

[0140] It can be seen that by implementing this optional embodiment, when not all data in the entry is written, the write operation can be processed by the second cache line buffer to ensure that the cache line in the memory is correctly written.

[0141] In an optional embodiment of the present application, the above device further includes:

[0142] A query unit, configured to query a storage address corresponding to the write instruction in the cache after receiving the write instruction;

[0143] A response unit, used for writing the target data to be written into the cache when the storage address exists in the cache;

[0144] The request generation unit is used to generate a target cache line miss request when the storage address does not exist in the cache.

[0145] It can be seen that by implementing this optional embodiment, a target cache line miss request for triggering a subsequent write process can be generated in a timely manner when a cache line is missed.

[0146] In an optional embodiment of the present application, the cache line allocation unit allocates an entry for the target cache line miss request in the first cache line buffer in response to the target cache line miss request, including:

[0147] In response to the specified cache line miss request, reading the specified cache line corresponding to the specified cache line miss request from the memory into the second cache line buffer;

[0148] Merge the to-be-written data in the specified cache line miss request into the specified cache line;

[0149] If it is detected that all data in the specified cache line is written, the merged specified cache line is written into the memory and the counter is updated;

[0150] When the value of the counter meets a preset condition, in response to the target cache line miss request, an entry is allocated in the first cache line buffer for the target cache line miss request.

[0151] It can be seen that by implementing this optional embodiment, when the value of the counter meets the preset condition, a direct data merge operation can be implemented based on the first cache line buffer, which can reduce the probability of using the first cache line buffer but failing to write all entries to a certain extent.

[0152] In an optional embodiment of the present application, the above device further includes:

[0153] The condition determination unit is used to determine whether the value of the counter satisfies a preset condition when the value of the counter is greater than or equal to a preset value.

[0154] It can be seen that by implementing this optional embodiment, when the value of the counter is greater than or equal to the preset value, the first cache line buffer can be used in time to implement a direct data merging operation to save memory access time.

[0155] In an optional embodiment of the present application, the above device further includes:

[0156] The counter control unit is used to clear the value of the counter when it is detected that not all data in the entry has been written.

[0157] It can be seen that by implementing this optional embodiment, when not all data in the entry is written, it can be determined that the next write mode is likely to still be non-streaming write, and the value of the counter can be cleared in time.

[0158] In an optional embodiment of the present application, the above device further includes:

[0159] The detection unit is used to determine that all data in the entry are written when it is detected that the valid bit and the dirty bit corresponding to each data block in the entry are both 1 and the write status is true.

[0160] It can be seen that by implementing this optional embodiment, it is possible to accurately determine whether all data writing is completed.

[0161] For the specific limitations of the above-mentioned devices, please refer to the limitations of the data writing method above, which will not be repeated here. Each module in the above-mentioned devices can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0162] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 1As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a data writing method as described above is implemented, including: including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the data writing method as described above is implemented.

[0163] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above data writing method can be implemented.

[0164] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0165] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0166] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1A function specified in one or more boxes.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0168] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0169] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data writing method, characterized in that: The method comprises: In response to a target cache line miss request, allocating an entry for the target cache line miss request in a first cache line buffer; comprising: In response to a designated cache line miss request, reading a designated cache line corresponding to the designated cache line miss request from a memory into a second cache line buffer; Merging the to-be-written data in the designated cache line miss request into the designated cache line; If it is detected that all data in the designated cache line is written, writing the merged designated cache line into the memory and updating the counter; When the value of the counter meets a preset condition, in response to the target cache line miss request, allocating an entry for the target cache line miss request in the first cache line buffer; Merging the target to-be-written data corresponding to the target cache line miss request into the entry; When it is detected that all the data in the entry is written, the merged entry is written into the memory.

2. The data writing method according to claim 1, characterized in that: The method further comprises: When it is detected that not all data in the entry has been written, reading the existing cache line corresponding to the target cache line miss request from the memory into the second cache line buffer; In the second cache line buffer, merging the target data to be written into the existing cache line; The merged existing cache lines are written into the memory.

3. The data writing method according to claim 1, characterized in that: The method further comprises: After receiving the write instruction, query the cache for the storage address corresponding to the write instruction; When the storage address exists in the cache, writing the target data to be written into the cache; When the storage address does not exist in the cache, the target cache line miss request is generated.

4. The data writing method according to claim 1, characterized in that: The method further comprises: When the value of the counter is greater than or equal to a preset value, it is determined that the value of the counter meets the preset condition.

5. The data writing method according to claim 1, characterized in that: The method further comprises: When it is detected that not all data in the entry has been written, the value of the counter is cleared.

6. The data writing method according to claim 5, characterized in that: The method further comprises: When it is detected that the valid bit and the dirty bit corresponding to each data block in the entry are both 1 and the write status is true, it is determined that all the data in the entry are written.

7. A data writing device, characterized in that: The device comprises: A cache line allocation unit, configured to allocate an entry for a target cache line miss request in a first cache line buffer in response to the target cache line miss request; comprising: In response to a designated cache line miss request, reading a designated cache line corresponding to the designated cache line miss request from a memory into a second cache line buffer; Merging the to-be-written data in the designated cache line miss request into the designated cache line; If it is detected that all data in the designated cache line is written, writing the merged designated cache line into the memory and updating the counter; When the value of the counter meets a preset condition, in response to the target cache line miss request, allocating an entry for the target cache line miss request in the first cache line buffer; A data merging unit, configured to merge the target to-be-written data corresponding to the target cache line miss request into the entry; The data writing unit is used to write the merged entry into the memory when it is detected that all the data in the entry has been written.

8. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

Images