Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, relating to the field of display technology. A pixel driving circuit includes a driving transistor, a first reset module, and a data writing module. The gate of the driving transistor is connected to a first node, the first electrode is connected to a second node, and the second electrode is connected to a third node. Two ends of the first reset module are respectively connected to a first reset signal line and a first node, and a control end is connected to a first scan line. Two ends of the data writing module are respectively connected to a data signal line and a second node, and a control end is connected to a second scan line. The display area includes a first display area and a second display area arranged along a first direction, and the first display area is located between the second display area and a binding area. In each pixel driving circuit, a first capacitor is formed between the first node and the second scan line. The capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area, so as to improve display uniformity.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] At present, how to improve the uniformity of display brightness of display products to enhance display effects has become one of the technical problems that need to be solved urgently. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area and a binding area located on one side of the display area along a first direction, wherein the display area comprises a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements;

[0006] The pixel driving circuit includes a driving transistor, a first reset module, and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light-emitting element;

[0007] The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in each of the pixel driving circuits, a first capacitor is formed between the first node and the second scanning line; the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area.

[0008] In a second aspect, the present disclosure provides another display panel, comprising a display area and a binding area located on one side of the display area along a first direction, the display area comprising a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; the pixel driving circuit comprising a driving transistor, a first reset module, and a data writing module, wherein a gate of the driving transistor is connected to a first node, a first electrode is connected to a second node, and a second electrode is connected to a third node; two ends of the first reset module are respectively connected to a first reset signal line and the first node, and a control end is connected to a first scan line; two ends of the data writing module are respectively connected to a data signal line and the second node, and a control end is connected to a second scan line; the third node is used to be electrically connected to the light-emitting element;

[0009] The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in the pixel driving circuit of the first display area, a shielding portion is provided on the side of the first node toward the second scanning line along a direction parallel to the light emitting surface of the display panel, and the shielding portion receives a fixed potential signal.

[0010] In a third aspect, the present disclosure provides a display device comprising the display panel described in any one of the first and second aspects of the present disclosure.

[0011] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0012] In the display panel and display device provided by the present disclosure, in each pixel driving circuit, a first capacitor is formed between the first node and the second scan line. Since the first node and the second scan line are adjacent, the first capacitor can be regarded as a coupling capacitor between the two. The first capacitors in the first display area and the second display area are designed differently, so that the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area. In this way, the coupling capacitance between the second scan line and the first node in the first display area is reduced, so that the coupling effect of the signal jump on the second scan line in the first display area on the first node is reduced, the dim brightness of the first display area is improved, and the potential of the first node in the first display area after being affected by the coupling capacitor is consistent or nearly consistent, thereby reducing the problem of large difference in display brightness between the first display area and the second display area due to inconsistent potential of the first node, thereby improving the overall display brightness uniformity of the display panel and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0014] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 FIG2 is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0016] Figure 2 Shown is a connection diagram of a pixel driving circuit and a light-emitting element in a display panel;

[0017] Figure 3 Shown with Figure 2 A driving timing diagram corresponding to the pixel driving circuit in FIG.

[0018] Figure 4 FIG. 1 is a schematic diagram showing a connection between a scan line and a gate drive circuit;

[0019] Figure 5 A schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure is shown;

[0020] Figure 6 The figure shows a film layer structure diagram of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 7 FIG2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0022] Figure 8 FIG2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0023] Figure 9 FIG2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0024] Figure 10 FIG2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0025] Figure 11 FIG2 is another schematic diagram of a layout of a pixel driving circuit provided in an embodiment of the present disclosure;

[0026] Figure 12 Shown is another connection diagram of the pixel driving circuit and the light-emitting element in the display panel;

[0027] Figure 13 Shown is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] Figure 1 FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram showing a connection between a pixel driving circuit 10 and a light emitting element 30 in a display panel. Figure 3 Shown with Figure 2 A driving timing diagram corresponding to the pixel driving circuit 10, Figure 4 FIG2 is a schematic diagram showing a connection between a scan line and a gate drive circuit. It should be noted that the embodiments of the present disclosure are merely illustrative of an example in which all transistors in the pixel drive circuit 10 are P-type transistors. The effective level signal for turning on the P-row transistors is a low-level signal, and the cutoff signal is a high-level signal. However, the present disclosure is not limited to this. In other embodiments of the present disclosure, the transistors in the pixel drive circuit 10 may all be N-type transistors, or a combination of P-type and N-type transistors. The present disclosure does not specifically limit this. The effective level signal for turning on the N-type transistors is a high-level signal, and the cutoff signal is a low-level signal.

[0031] Please refer to Figures 1 to 4The present disclosure provides a display panel including a display area A1 and a binding area A2 located on one side of the display area along a first direction D1. The display area A1 includes a plurality of light-emitting elements 30 and a pixel driving circuit 10 connected to the light-emitting elements 30. The pixel driving circuit 10 includes a driving transistor DT, a first reset module 71 (using transistor T1 as an example for illustration), and a data writing module 72 (using transistor T5 as an example for illustration). The driving transistor DT has a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first reset module 71 has two terminals connected to a first reset signal line Vref1 and the first node N1, respectively, and a control terminal connected to a first scan line S1. The data writing module 72 has two terminals connected to a data signal line DL and a second node N2, respectively, and a control terminal connected to a second scan line S2. The third node N3 is electrically connected to the light-emitting elements 30. The display area A1 of the display panel includes a first display area A11 and a second display area A12 arranged along the first direction D1, with the first display area A11 located between the second display area A12 and the binding area A2.

[0032] Optionally, the pixel driving circuit 10 further includes a first light-emitting control module 73 (using a transistor T3 as an example for illustration) and a second light-emitting control module 74 (using a transistor T4 as an example for illustration). The first light-emitting control module 73 is connected between the first power signal terminal PVDD and the second node N2, and the second light-emitting control module 74 is connected between the third node N3 and the light-emitting element 30. The control terminals of the first light-emitting control module 73 and the second light-emitting control module 74 are connected to the light-emitting control signal line EM. Optionally, the pixel driving circuit 10 further includes a threshold compensation module 75 (using a transistor T6 as an example for illustration). The threshold compensation module 75 is connected between the first node N1 and the third node N3, and the control terminal of the threshold compensation module 75 is connected to the second scan line S2.

[0033] The working process of the pixel driving circuit 10 includes:

[0034] First reset stage: the first scan line S1 provides an effective level signal to the first reset module 71, the first reset module 71 is turned on, and the reset signal on the first reset signal line Vref1 is transmitted to the first node N1 to reset the first node N1.

[0035] Data writing and threshold compensation stage: the second scan line S2 provides a valid level signal to the data writing module 72 and the threshold compensation module 75, the data writing module 72 and the threshold compensation module 75 are turned on, the data signal on the data signal line DL is transmitted to the second node N2, and the gate of the driving transistor DT is threshold compensated through the threshold compensation module 75.

[0036] Light-emitting stage: the light-emitting control signal line EM sends an effective level signal to the first light-emitting control module 73 and the second light-emitting control module 74 to control the first light-emitting control module 73 and the second light-emitting control module 74 to be turned on, and the signal of the first power signal terminal PVDD is transmitted to the driving transistor DT to form a current that drives the light-emitting element 30 to emit light.

[0037] In the above pixel driving circuit 10, the stability of the potential of the gate of the driving transistor DT (corresponding to the first node N1 in the figure) directly affects the magnitude of the driving current formed in the light emitting stage. Figure 3 In the driving sequence shown, after data writing is completed, the potential on the second scan line S2 jumps from a low level to a high level. If the second scan line S2 is close to the first node N1, the change in the signal on the second scan line S2 will be coupled to the first node N1, causing the potential of the first node N1 to change, affecting the magnitude of the driving current. If the number of pixel driving circuits 10 connected to each second scan line S2 in the display panel is the same, the load of the second scan line S2 is the same or nearly the same, and the coupling effect of the second scan line S2 on the first node N1 will also be the same. In this case, the overall display brightness of the display panel will also be consistent.

[0038] However, for Figure 4 In the structure shown, the load of the second scan line S2 is not uniform. Figure 4 In an optional embodiment of the present disclosure, the display panel includes M pixel driving circuit rows H; the display panel includes N cascaded gate driving circuits (respectively Scan1 to Scan(n)), N=M+s; the first scan line S1 corresponding to the pixel driving circuit 10 located in the mth row is electrically connected to the gate driving circuit of the mth level, and the second scan line S2 corresponding to the pixel driving circuit 10 located in the mth row is electrically connected to the gate driving circuit of the m+sth level; wherein, 1≤m≤M, s≥2, this embodiment is described with s=7 as an example, but is not limited thereto. The row of pixel driving circuits 10 connected to the gate driving circuits of the M+1th to M+sth levels (corresponding to Scan(n-13) to Scan(n-7) in the figure) is located in the first display area A11. Figure 4Taking the illustrated architecture as an example, the first scan line S1 corresponding to the first row of pixel driving circuits 10 is connected to the first-level gate driving circuit Scan1, and the second scan line S2 corresponding to the first row of pixel driving circuits 10 is connected to the eighth-level gate driving circuit Scan8. That is, after resetting the first node N1 of the first row of pixel driving circuits 10, data is written after an interval of eight scan lines (8H). This helps increase the time required to reset the first node N1, restoring the potential of the first node N1 to its initial state. For the second row of pixel driving circuits 10, the first scan line S1 is connected to the second-level gate driving circuit Scan2, the second scan line S2 is connected to the ninth-level gate driving circuit Scan9, and so on. In this way, when there are M rows of pixel driving circuits 10 in the display panel, it will be necessary to design M+7 levels of gate driving circuits in the display panel. The first M levels of gate driving circuits (Scan1 to Scan(n-12)) will be connected to two rows of pixel driving circuits 10, and for the last 7 levels of gate driving circuits (Scan(n-13) to Scan(n-7)), each gate driving circuit will only be connected to 1 row of pixel driving circuits, and provide a control signal to the second scan line S2 corresponding to 1 row of pixel driving circuits. The 7 rows of pixel driving circuits connected to the last 7 levels of gate driving circuits are located in the first display area A11. As a result, the second scan lines S2 in the first display area A11 are electrically connected to only one row of pixel driving circuits 10, while the second scan lines S2 in the second display area A12 are electrically connected to two rows of pixel driving circuits 10. That is, the loads of the second scan lines S2 in the first display area A11 and the second display area A12 are different. When data writing is completed and the signal on the second scan line S2 jumps to a high level, the load on the second scan line S2 in the first display area A11 is smaller due to the different loads. The signal transition of the second scan line S2 in the first display area A11 and the second display area A12 will have different coupling effects on the first node N1. After being coupled by the signal on the second scan line S2, the first node N1 in the first display area A11 will be pulled up by a larger amplitude. As a result, the potentials of the first node N1 in the first display area A11 and the second display area A12 after coupling are different, resulting in different display brightness in the first display area A11 and the second display area A12. The brightness of the first display area A11 may be darker than that of the second display area A12.

[0039] To solve the above technical problems, the present disclosure provides two improved solutions:

[0040] The first improved solution is: In each pixel driving circuit 10, a first capacitor is formed between the first node N1 and the second scan line S2. Since the first node N1 and the second scan line S2 are adjacent, the first capacitor can be regarded as a coupling capacitor between them. The first improved solution provided by this embodiment essentially differentiates the first capacitors of the first display area A11 and the second display area A12, so that the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the first display area A11 is smaller than the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the second display area A12. In this way, the coupling capacitance between the second scan line S2 and the first node N1 in the first display area A11 is reduced, so that the coupling effect of the signal jump on the second scan line S2 in the first display area A11 on the first node N1 is reduced, and the dark brightness of the first display area A11 is improved, so that the potential of the first node N1 in the first display area A11 after being affected by the coupling capacitance is consistent or nearly consistent, thereby reducing the problem of large difference in display brightness between the first display area A11 and the second display area A12 due to inconsistent potential of the first node N1, so it is beneficial to improve the overall display brightness uniformity of the display panel and improve the display effect.

[0041] On the basis of the first solution, in order to realize the differentiated design of the first capacitor corresponding to the first display area A11 and the second display area A12, please refer to Figure 5 , Figure 5 FIG. 1 is a schematic diagram showing a layout of a pixel driving circuit 10 provided in an embodiment of the present disclosure. Figure 6 FIG. 1 shows a film layer structure diagram of a display panel provided by an embodiment of the present disclosure. Optionally, in the pixel driving circuit 10 of the first display area A11, a shielding portion 90 is provided on the side of the first node N1 toward the second scan line S2, parallel to the light-emitting surface of the display panel. The shielding portion 90 receives a fixed potential signal. In this embodiment, the shielding portion 90, which receives a fixed potential signal, is introduced in the region between the first node N1 and the second scan line S2. When the signal on the second scan line S2 transitions, the shielding portion 90 reduces the effect of the transition on the first node N1, thereby reducing the coupling capacitance between the second scan line S2 and the first node N1 in the first display area A11. This ensures that the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the first display area A11 is smaller than the capacitance of the first capacitor in the pixel driving circuit 10 corresponding to the second display area A12, thereby reducing the difference in display brightness between the first display area A11 and the second display area A12.

[0042] The second solution is: in the pixel driving circuit 10 of the first display area A11, a shielding portion 90 is provided on the side of the first node N1 toward the second scan line S2 in a direction parallel to the light emitting surface of the display panel, and the shielding portion 90 receives a fixed potential signal. Figure 5 and Figure 6 , and combined with Figures 1 to 4 In this embodiment, a shielding portion 90 for receiving a fixed potential signal is introduced in the region between the first node N1 and the second scan line S2. When the signal on the second scan line S2 jumps, the shielding portion 90 can reduce the influence of the jumping signal on the first node N1 in the first display area A11, thereby reducing the coupling capacitance between the second scan line S2 in the first display area A11 and the first node N1. This is beneficial to improving the problem that the second scan line S2 in the first display area A11 has a smaller load after data writing is completed. , the coupling influence on the first node N1 when the signal jumps, which is beneficial to balancing the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, and is beneficial to balancing the potential of the first node N1 after the signal of the second scan line S2 affects the first node N1 after the data writing is completed. When the potential of the first node N1 is close in the light-emitting stage, the driving current provided to the light-emitting element 30 will also be close, so it is beneficial to improve the display brightness uniformity of the first display area A11 and the second display area A12, and is beneficial to improving the overall display effect of the display panel.

[0043] The first and second solutions mentioned above will be further explained below. It should be noted that the following embodiments are applicable to both the first and second solutions mentioned above, and can be regarded as further expansions of the first solution mentioned above, or as further expansions of the second solution mentioned above. The similarities will not be expressed separately.

[0044] Please refer to Figure 6 , Figure 6The film structure of the display panel is schematically illustrated. Optionally, the display panel provided in the embodiment of the present disclosure includes a substrate 00, a driving layer 40, and a display layer 10, wherein the display layer 10 includes a pixel definition layer 19, which defines a plurality of pixel openings; a light-emitting material layer 302 is located at least in the pixel openings, and along a direction perpendicular to the substrate 00, an anode 301 and a cathode 303 are located on either side of the light-emitting material layer 302, with the anode 301 located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is further provided on the side of the cathode 303 away from the anode 301. Optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second organic layer 53 arranged in a stacked manner. The pixel driving circuit mentioned in the above embodiment is located in the driving layer 40, and the pixel driving circuit includes a plurality of transistors T. Optionally, in the driving layer 40, the gate of the transistor is provided on the first metal layer M1, and the source and drain of the transistor are provided on the second metal layer M2. The array substrate 10 also includes a semiconductor layer poly arranged on the side of the first metal layer M1 facing the substrate 00 and an auxiliary metal layer M0 arranged on the side of the semiconductor layer poly facing the substrate 00. It should be noted that the display panel may include a transistor with a dual-gate structure. In this case, one of the gates of the transistor may be located in the first metal layer M1, and the other gate may be located in the auxiliary metal layer M0. In the direction perpendicular to the plane where the substrate 00 is located, the first metal layer M1 and the auxiliary metal layer M0 both overlap with the semiconductor layer poly. The auxiliary metal layer M0 also has a light-shielding function to prevent light from affecting the semiconductor layer poly. Optionally, a capacitor metal layer Mc is further included between the first metal layer M1 and the second metal layer M2. The capacitor metal layer Mc can form a capacitor structure with the second metal layer M2. Optionally, a third metal layer M3 is also included on the side of the second metal layer M2 facing away from the substrate 00. Another metal layer can be provided on the side of the third metal layer m3 facing away from the substrate according to actual needs. This disclosure does not specifically limit this. Each metal layer can be used for the layout of signal lines. Optionally, please combine Figure 5 The first scan line S1 and the second scan line S2 are located in the first metal layer M1, the first reset signal line Vref1 and the second reset signal line Vref2 are located in the capacitor metal layer Mc, and the data signal line DL and the first power signal line PVDD are located in the second metal layer M2, but the embodiment of the present disclosure is not limited to this.

[0045] Please continue to refer to Figure 5 and Figure 6In an optional embodiment of the present disclosure, the gate of the driving transistor DT is electrically connected to the first node N1 via a first connecting portion L1. The first connecting portion L1 and the second scan line S2 are arranged in different layers. This embodiment is described by taking the first connecting portion L1 located in the third metal layer M3 and the second scan line S2 located in the first metal layer M1 as an example, but is not limited to this. Along the second direction D2, the first connecting portion L1 and the second scan line S2 overlap to form a first overlapping area. The second direction D2 is perpendicular to the plane where the light emitting surface of the display panel is located. In the first display area A11, the shielding portion 90 includes a first shielding portion 91. Along the second direction D2, the first shielding portion 91 overlaps with the first overlapping area, and at least a portion of the first shielding portion 91 is located between the first connecting portion L1 and the second scan line S2. Optionally, the first shielding portion 91 is located in the capacitor metal layer Mc.

[0046] Because the first connection portion L1 is used to connect the gate of the driving transistor and the first node N1, the potential of the gate of the driving transistor DT, the potential of the first connection portion L1, and the potential of the first node N1 are equal. When the first connection portion L1 and the second scan line S2 are located in different film layers and overlap to form a first overlapping region, due to the presence of coupling capacitance in the first overlapping region, when a signal transition occurs on the second scan line S2, the transition will be coupled to the first connection portion L1, affecting the potential of the first connection portion L1, and further affecting the potential of the first node N1. Therefore, when the first shielding portion 91 is introduced into the first display area A11 of the display panel and the first shielding portion 91 overlaps with the first overlapping area, the first shielding portion 91 can at least partially shield the jump signal of the second scan line S2, thereby avoiding or reducing the influence of the jump signal on the potential on the first connection portion L1, and further avoiding or reducing the influence of the jump signal on the potential on the first node N1, that is, reducing the influence of the second scan line S2 in the first display area A11 on the potential of the first node N1, and reducing the difference in influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12. Therefore, the potential difference between the first node N1 in the first display area A11 and the second display area A12 during the light-emitting stage can be reduced, which is beneficial to reducing the display brightness difference between the first display area A11 and the second display area A12, and therefore is beneficial to improving the display brightness uniformity of the first display area A11 and the second display area A12.

[0047] Figure 7 FIG. 1 is another schematic diagram of a layout of the pixel driving circuit 10 provided in an embodiment of the present disclosure. Figure 7In an optional embodiment of the present disclosure, the second scan line S2 includes a main body portion 81, which extends along a third direction D3, and the main body portion 81 and the first node N1 are arranged along the first direction D1, and the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; in the first display area A11, the shielding portion 90 includes a second shielding portion 92, and along the first direction D1, the second shielding portion 92 is located between the first node N1 and the main body portion 81 of the second scan line S2.

[0048] This embodiment shows another arrangement of the shielding portion 90 in the first display area A11. When the main portion 81 of the second scan line S2 and the first node N1 are arranged along the first direction D1, it is equivalent to the first node N1 being located on one side of the main portion 81 of the second scan line S2 along the first direction D1. At this time, a lateral coupling capacitor will exist between the main portion 81 of the second scan line S2 and the first node N1. When the signal on the second scan line S2 jumps after the data writing stage, the potential of the first node N1 will change accordingly due to the influence of the lateral coupling capacitor. When the embodiment of the present disclosure introduces the second shielding portion 92 on the side of the main portion 81 of the second scan line S2 toward the first node N1 along the first direction D1, the second shielding portion 92 is located between the first node N1 and the main portion 81. In this way, the second shielding portion 92 can be used to isolate the jump signal on the main portion 81 to a certain extent, thereby reducing the influence of the jump signal of the main portion 81 of the second scan line S2 in the first display area A11 on the potential of the first node N1. This is also conducive to reducing the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, and is also conducive to improving the display brightness uniformity of the first display area A11 and the second display area A12.

[0049] Figure 8 FIG. 1 is another schematic diagram of a layout of a pixel driving circuit 10 provided in an embodiment of the present disclosure. In this embodiment, the shielding portion 90 in the first display area A11 includes a first shielding portion 91 and a second shielding portion 92. Figure 8 In an optional embodiment of the present disclosure, when the shielding portion 90 includes a first shielding portion 91 and a second shielding portion 92 , the first shielding portion 91 and the second shielding portion 92 are electrically connected and located on the same layer.

[0050] Specifically, in this embodiment, when the first shielding portion 91 and the second shielding portion 92 are disposed on the same layer and electrically connected, the first shielding portion 91 and the second shielding portion 92 can be manufactured in the same manufacturing process, eliminating the need for separate manufacturing processes for the first shielding portion 91 and the second shielding portion 92. This simplifies the manufacturing process of the shielding portion 90, and thus the overall manufacturing process of the display panel, thereby improving production efficiency. Furthermore, when the first shielding portion 91 and the second shielding portion 92 are electrically connected in the same film layer, the shielding area of ​​the shielding portion 90 is increased, improving the shielding effectiveness of the shielding portion 90 and reducing the impact of the second scan line S2 on the potential of the first node N1 in the first display area A11.

[0051] The above embodiment shows a scheme of introducing the shielding portion 90 between the first node N1 and the main portion 81 of the second scan line S2. In some other embodiments of the present disclosure, the shielding portion 90 may be introduced between the first node N1 and the extension portion 82 of the second scan line S2. For example, please refer to Figure 9 and Figure 10 , Figure 9 and Figure 10 Shown are another layout diagram of the pixel driving circuit 10 provided in the embodiment of the present disclosure. This embodiment describes the scheme of introducing the third shielding portion 93 in the first display area A11. In an optional embodiment of the present disclosure, the second scan line S2 includes a main body portion 81 and an extension portion 82 connected to the main body portion 81, the main body portion 81 extends along a third direction D3, the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion 82 extends along the first direction D1 and is located on the side of the main body portion 81 facing the first node N1; the main body portion 81 and the first node N1 are arranged along the first direction D1, and the extension portion 82 and the first node N1 are arranged along the third direction D3. The shielding portion 90 includes a third shielding portion 93, please refer to Figure 9 Along the third direction D3, the third shielding portion 93 is located between the first node N1 and the extension portion 82. In this case, the third shielding portion 93 can be embodied as a long strip structure arranged between the extension portion 82 and the first node N1 arranged along the third direction D3. By introducing this type of third shielding portion 93, it is possible to shield at least part of the influence of the jumping signal on the extension portion 82 on the first node N1, thereby also helping to reduce the difference in the influence of the second scan line S2 on the potential of the first node N1 between the first display area A11 and the second display area A12, and helping to improve the display brightness uniformity of the first display area A11 and the second display area A12.

[0052] Please refer to Figure 10The third shielding portion 93 includes a first sub-portion 931 and a second sub-portion 932 that are electrically connected. Along the third direction D3, the first sub-portion 931 is located between the first node N1 and the extension portion 82. Along the first direction D1, the second sub-portion 932 is located between the first node N1 and the main body portion 81. This embodiment describes another feasible structure of the third shielding portion 93. In this embodiment, the extension portion 82 and the main portion 81 form a vertical corner structure, and the first node N1 is located on one side of the opening of the corner structure. The third shielding portion 93 can be regarded as an L-shaped structure arranged between the corner structure and the first node N1 along the shape of the corner structure, wherein the first sub-portion 931 can shield the influence of the extension portion 82 on the first node N1, and the second sub-portion 932 can shield the influence of the main portion 81 on the first node N1. The combined structure of the first sub-portion 931 and the second sub-portion 932 increases the shielding range of the shielding portion 90, thereby being more conducive to reducing the influence of the second scan line S2 in the first display area A11 on the potential of the first node N1, and thus being more conducive to improving the display brightness difference between the first display area A11 and the second display area A12. It should be noted that Figure 10 The embodiment shows a solution of setting the first sub-section 931 and the second sub-section 932 in the auxiliary metal layer M0 of the display panel, but is not limited to this. In some other embodiments of the present disclosure, the first sub-section 931 and the second sub-section 932 can also be located in other metal layers.

[0053] It should be noted that the several embodiments of the first shielding portion 91, the second shielding portion 92 and the third shielding portion 93 mentioned in the aforementioned embodiments can be arbitrarily combined. For example, the first shielding portion 91 in the first display area A11 can be combined with the second shielding portion 92, or with the third shielding portion 93, or a combination of the three, or the three can exist separately in an area corresponding to a pixel in the first display area A11. This disclosure does not specifically limit this.

[0054] Figure 11 The figure shows another layout schematic diagram of the pixel driving circuit 10 provided in an embodiment of the present disclosure. In an optional embodiment of the present disclosure, the second scan line S2 includes a main body 81 and an extension portion 82 connected to the main body 81, the main body 81 extends along a third direction D3, the third direction D3 intersects with the first direction D1 and is parallel to the plane where the light emitting surface of the display panel is located; the extension portion 82 extends along the first direction D1 and is located on the side of the main body 81 facing the first node N1; the main body 81 and the first node N1 are arranged along the first direction D1, and the extension portion 82 and the first node N1 are arranged along the third direction D3; the shielding portion 90 includes a fourth shielding portion 94, and the fourth shielding portion 94 overlaps with the extension portion 82 along the second direction, and the second direction is perpendicular to the plane where the light emitting surface of the display panel is located.

[0055] This embodiment describes another feasible structure of the shielding portion 90. Specifically, a fourth shielding portion 94 is introduced into the film layer above or below the extension portion 82 in the second scan line S2, so that the fourth shielding portion 94 overlaps with the extension portion 82 of the second scan line S2. Since the fourth shielding portion 94 receives a fixed potential signal, when the fourth shielding portion 94 overlaps with the extension portion 82, it is also beneficial to reduce the signal influence of the second scan line S2 on the first node N1, thereby reducing the difference in the influence of the second scan line S2 on the first node N1 in the first display area A11 and the second display area A12, thereby also facilitating improved display brightness uniformity in the first display area A11 and the second display area A12.

[0056] It should be noted that the first shielding portion 91, the second shielding portion 92, the third shielding portion 93 and the fourth shielding portion 94 in the above embodiment can exist separately in the pixel driving circuit 10 of the first display area A11, or can be combined in any two, or in any three, or all four can exist simultaneously in the same pixel driving circuit 10 of the first display area A11. They can be set according to actual needs, and this disclosure does not specifically limit this.

[0057] Please continue to refer to Figure 2 In an optional embodiment of the present disclosure, the pixel driving circuit 10 includes a second reset module 76 (taking the transistor T2 as an example for explanation), the two ends of the second reset module 76 are respectively connected to the second reset signal line Vref2 and the fourth node N4, and the fourth node N4 is connected to the anode of the light emitting element 30; please combine Figure 11 The second reset signal line Vref2 includes a main line 70 extending along the third direction D3 and a connecting line 71 extending along the first direction D1. The main line 70 and the connecting line 71 are electrically connected. The third direction D3 intersects the first direction D1. The display panel includes a plurality of pixel driving circuits 10 arranged along the first direction D1. In the second reset signal lines Vref2 corresponding to two adjacent pixel driving circuits 10 along the first direction D1, the two main lines 70 are electrically connected through the connecting line 71. The fourth shielding portion 94 is electrically connected to the connecting line 71.

[0058] This embodiment illustrates a scheme for reusing the film layer of the connecting line 71 in the second reset signal line Vref2 as the fourth shielding portion 94. Specifically, the second reset signal line Vref2 is a signal line that provides a reset signal to the second reset module 76 in the pixel driving circuit 10. When the second reset module 76 is turned on, the reset signal is transmitted to the anode of the light-emitting element 30, thereby resetting the anode of the light-emitting element 30. Because the reset signal on the second reset signal line Vref2 is a global signal, that is, the signal for resetting the light-emitting elements 30 in different regions is the same, in the disclosed embodiment, the second reset signal line Vref2 includes a main line 71 and a connecting line 71 extending in different directions and electrically connected. This is equivalent to configuring the second reset signal line Vref2 into a mesh structure. This helps reduce the overall impedance of the second reset signal line Vref2, reduces the voltage drop of the reset signal in different regions, and improves the uniformity of resetting the light-emitting elements 30 in different regions. When the fourth shielding portion 94 is introduced into the first display area A11, the embodiment of the present disclosure connects the fourth shielding portion 94 to the connecting line 71 in the second reset signal line Vref2, which is equivalent to extending from the connecting line 71 along the third direction D3. At this time, the fourth shielding portion 94 can be manufactured in the same manufacturing process as the connecting line 71. There is no need to introduce another manufacturing process separately for the fourth shielding portion 94. The reset signal on the connecting line 71 can be reused, which is conducive to simplifying the manufacturing process of the display panel and improving production efficiency.

[0059] Please refer to Figure 2 、 Figures 5 to 11 In an optional embodiment of the present disclosure, the display panel includes a fixed potential signal line (a feasible fixed potential signal line will be described in subsequent embodiments), and the shielding portion 90 is electrically connected to the fixed potential signal line. When the shielding portion 90 is connected to the fixed potential signal line already in the display panel, there is no need to introduce a new signal line to provide a fixed potential signal to the shielding portion 90. Utilizing the existing fixed potential signal line to provide a fixed potential to the shielding portion 90 facilitates simplifying the overall design of the display panel when the shielding portion 90 is introduced into the display panel, thereby improving the production efficiency of the display panel.

[0060] The scheme of using the fixed potential signal in the display panel to provide the fixed potential signal to the shielding portion 90 will be described in detail below.

[0061] Figure 12 FIG. 1 is another connection diagram of the pixel driving circuit 10 and the light emitting element 30 in the display panel, which is similar to FIG. Figure 2 The difference is that a bias module is introduced into the pixel driving circuit 10, please refer to Figure 2 and Figure 12In an optional embodiment of the present disclosure, the pixel driving circuit 10 includes a second reset module 76 and a bias module 77. The two ends of the second reset module 76 are respectively connected to the second reset signal line Vref2 and the fourth node N4, and the fourth node N4 is connected to the anode of the light-emitting element 30. The two ends of the bias module 77 are respectively connected to the bias signal line DVH and the second node N2, or the two ends of the bias module 77 are respectively connected to the bias signal line DVH and the third node N3. The figure uses the bias module 77 connected to the third node N3 as an example for description, and this disclosure does not specifically limit this. The display panel also includes a power signal line. The fixed potential signal line includes one of the power signal line, the first reset signal line Vref1, the second reset signal line Vref2, and the bias signal line DVH. The shielding portion 90 is provided on the same layer as the fixed potential signal line electrically connected thereto.

[0062] For the pixel driving circuit 10, the signal lines connected thereto and capable of transmitting fixed-potential signals include a first reset signal line Vref1 that transmits a reset signal to the first reset module 71, a second reset signal line Vref2 that transmits a reset signal to the second reset module 76, power signal lines PVDD and PVEE required for light emission, and a bias signal line DVH that provides a bias potential signal to the bias module 77. The power signal lines further include a positive power signal line PVDD and a negative power signal line PVEE. When a shielding portion 90 is introduced into the first display area A11, the shielding portion 90 can be electrically connected to any of the above-mentioned fixed-potential signal lines, with the corresponding fixed-potential signal being provided as the shielding signal to the shielding portion 90. Figure 10 and Figure 11 The embodiment shown shows a scheme of electrically connecting the shielding portion 90 to the second reset signal line Vref2. Figure 7 and Figure 8 The illustrated embodiment shows a scheme for electrically connecting the shielding portion 90 to the power signal line PVDD. In some other embodiments of the present disclosure, the shielding portion 90 may also be electrically connected to the bias signal line DVH. During actual connection, the shielding portion 90 and the corresponding fixed potential signal line may be arranged on the same layer, which is equivalent to forming a portion of the extension portion 82 as the shielding portion 90 on the basis of the original fixed potential signal line. The shielding portion 90 and the fixed potential signal line do not need to be connected through a via, and can be manufactured and formed in the same process as the corresponding fixed potential signal line, thereby helping to simplify the overall manufacturing process of the display panel.

[0063] Please refer to Figure 1In an optional embodiment of the present disclosure, the first display area A11 includes a first sub-area A01 and a second sub-area A02 arranged along a first direction D1, the first sub-area A01 is located between the second sub-area A02 and the binding area A2, and the projection area of ​​the shielding portion 90 corresponding to the pixel driving circuit 10 in the first sub-area A01 on the plane where the light emitting surface of the display panel is located is larger than the projection area of ​​the shielding portion 90 corresponding to the pixel driving circuit 10 in the second sub-area A02 on the plane where the light emitting surface of the display panel is located. The first sub-area A01 in the first display area A11 can be regarded as an area closer to the binding area A2, and the second sub-area A02 is farther away from the binding area A2 than the first sub-area A01. Therefore, the voltage drop on the second scan line S2 in the first sub-area A01 is smaller than the voltage drop on the second scan line S2 in the second sub-area A02. When a signal jump occurs, the signal influence of the second scan line S2 in the first sub-area A01 on the first node N1 will be greater than the signal influence of the second scan line S2 in the second sub-area A02 on the first node N1. Therefore, in the embodiment of the present disclosure, the first sub-area A01 and the second sub-area A02 are connected to each other. The area of ​​the shielding portion 90 introduced in the second sub-area A02 is designed differently, so that the area of ​​the shielding portion 90 in the first sub-area A01 is larger than the area of ​​the shielding portion 90 in the second sub-area A02, thereby reducing the influence of the second scan line S2 in the first sub-area A01 on the first node N1 and balancing the difference in the influence of the second scan line S2 on the potential of the first node N1 in the first sub-area A01 and the second sub-area A02, thereby facilitating the improvement of the display brightness uniformity of the first sub-area A01 and the second sub-area A02, and further facilitating the improvement of the overall display brightness uniformity of the display panel. When the shielding portion 90 in the second sub-area A02 and the first sub-area A01 are designed differently, the shielding portion 90 in the first sub-area A01 can be, for example, Figure 8 The structure shown in FIG. 1 (the area of ​​the shielding portion 90 is larger), the shielding portion 90 in the second sub-area A02 can be formed as follows: Figure 7 It should be noted that the first sub-area A01 and the second sub-area A02 in the figure are only for illustration and do not limit the number of pixel circuit rows actually included in the first sub-area A01 and the second sub-area A02.

[0064] Based on the same inventive concept, the present disclosure further provides a display device 200, Figure 13 FIG2 is a schematic diagram of a structure of a display device 200 provided in an embodiment of the present disclosure. Figure 13The display device 200 includes the display panel 100 of any of the above-mentioned embodiments. The display device 200 provided in the embodiments of the present disclosure can be any electronic device with a display function, such as a tablet computer with touch and display functions, a display product in a display cabinet, a television, or an in-vehicle display device. The display device 200 provided in the embodiments of the present disclosure has the beneficial effects of the display panel 100 provided in the embodiments of the present disclosure. For details, please refer to the detailed description of the display panel 100 in the above-mentioned embodiments, and will not be repeated in this embodiment.

[0065] It is understandable that Figure 13 The display device is illustrated only in a rectangular structure. In some other embodiments of the present disclosure, the display device 200 may also be embodied as a circle, a rounded rectangle, an ellipse, or any other feasible shape, which is not specifically limited in the present disclosure.

[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0067] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a display area and a binding area located on one side of the display area along a first direction, wherein the display area includes a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; The pixel driving circuit includes a driving transistor, a first reset module, and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light-emitting element; The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in each of the pixel driving circuits, a first capacitor is formed between the first node and the second scanning line; the capacitance of the first capacitor in the pixel driving circuit corresponding to the first display area is smaller than the capacitance of the first capacitor in the pixel driving circuit corresponding to the second display area.

2. The display panel according to claim 1, wherein: In the pixel driving circuit of the first display area, a shielding portion is provided on a side of the first node facing the second scan line in a direction parallel to the light emitting surface of the display panel, and the shielding portion receives a fixed potential signal.

3. The display panel according to claim 2, wherein: The gate of the driving transistor is electrically connected to the first node via a first connecting portion, the first connecting portion and the second scanning line are provided in a different layer, and along a second direction, the first connecting portion and the second scanning line overlap to form a first overlapping region, and the second direction is perpendicular to a plane where a light emitting surface of the display panel is located; The shielding portion includes a first shielding portion. Along the second direction, the first shielding portion overlaps with the first overlapping region, and at least a portion of the first shielding portion is located between the first connecting portion and the second scanning line.

4. The display panel according to claim 2 or 3, wherein: The second scanning line includes a main body portion, the main body portion extends along a third direction, and the main body portion and the first node are arranged along the first direction, and the third direction intersects the first direction and is parallel to a plane where a light emitting surface of the display panel is located; The shielding portion includes a second shielding portion located between the first node and the main portion of the second scan line along the first direction.

5. The display panel according to claim 4, wherein: When the shielding portion includes a first shielding portion and a second shielding portion, the first shielding portion and the second shielding portion are electrically connected and located on the same layer.

6. The display panel according to claim 2, wherein: The second scanning line includes a main portion and an extension portion connected to the main portion, the main portion extending along a third direction, the third direction intersecting the first direction and being parallel to a plane where a light emitting surface of the display panel is located; the extension portion extending along the first direction and located on a side of the main portion facing the first node; the main portion and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a third shielding portion, which is located between the first node and the extension portion along the third direction; or the third shielding portion includes a first sub-portion and a second sub-portion that are electrically connected, and the first sub-portion is located between the first node and the extension portion along the third direction, and the second sub-portion is located between the first node and the main portion along the first direction.

7. The display panel according to claim 2, wherein: The second scanning line includes a main portion and an extension portion connected to the main portion, the main portion extending along a third direction, the third direction intersecting the first direction and being parallel to a plane where a light emitting surface of the display panel is located; the extension portion extending along the first direction and located on a side of the main portion facing the first node; the main portion and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a fourth shielding portion. Along a second direction, the fourth shielding portion overlaps with the extending portion. The second direction is perpendicular to a plane where the light emitting surface of the display panel is located.

8. The display panel according to claim 7, wherein: The pixel driving circuit includes a second reset module, wherein two ends of the second reset module are respectively connected to a second reset signal line and a fourth node, and the fourth node is connected to the anode of the light-emitting element; the second reset signal line includes a main line extending along a third direction and a connecting line extending along the first direction, the main line and the connecting line are electrically connected, and the third direction intersects the first direction; The display panel includes a plurality of pixel driving circuits arranged along a first direction, wherein two main lines of the second reset signal lines corresponding to two adjacent pixel driving circuits along the first direction are electrically connected via the connecting line; The fourth shielding portion is electrically connected to the connecting line.

9. The display panel according to claim 2, wherein: The display panel includes a fixed potential signal line, and the shielding portion is electrically connected to the fixed potential signal line.

10. The display panel according to claim 9, wherein: The pixel driving circuit includes a second reset module and a bias module, wherein two ends of the second reset module are respectively connected to the second reset signal line and the fourth node, and the fourth node is connected to the anode of the light-emitting element; two ends of the bias module are respectively connected to the bias signal line and the second node, or two ends of the bias module are respectively connected to the bias signal line and the third node; The display panel also includes a power signal line, the fixed potential signal line includes the power signal line, the first reset signal line, the second reset signal line and one of the bias signal lines, and the shielding portion and the fixed potential signal line electrically connected thereto are arranged on the same layer.

11. The display panel according to claim 2, wherein: The first display area includes a first sub-area and a second sub-area arranged along the first direction, the first sub-area is located between the second sub-area and the binding area, and the projection area of ​​the shielding part corresponding to the pixel driving circuit in the first sub-area on the plane where the light-emitting surface of the display panel is located is larger than the projection area of ​​the shielding part corresponding to the pixel driving circuit in the second sub-area on the plane where the light-emitting surface of the display panel is located.

12. The display panel according to claim 1, wherein The display panel includes M pixel driving circuit rows; the display panel includes N cascaded gate driving circuits, where N=M+s; The first scan line corresponding to the pixel driving circuit located in the mth row is electrically connected to the gate driving circuit of the mth level, and the second scan line corresponding to the pixel driving circuit located in the mth row is electrically connected to the gate driving circuit of the m+sth level; wherein 1≤m≤M, s≥2; The pixel driving circuit rows connected to the gate driving circuits of the M+1th to M+sth stages are located in the first display area.

13. A display panel, characterized in that: It includes a display area and a binding area located on one side of the display area along a first direction, wherein the display area includes a plurality of light-emitting elements and a pixel driving circuit connected to the light-emitting elements; The pixel driving circuit includes a driving transistor, a first reset module, and a data writing module, wherein the gate of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the two ends of the first reset module are respectively connected to the first reset signal line and the first node, and the control end is connected to the first scan line; the two ends of the data writing module are respectively connected to the data signal line and the second node, and the control end is connected to the second scan line; the third node is used to be electrically connected to the light-emitting element; The display area includes a first display area and a second display area arranged along the first direction, and the first display area is located between the second display area and the binding area; in the pixel driving circuit of the first display area, a shielding portion is provided on the side of the first node toward the second scanning line along a direction parallel to the light emitting surface of the display panel, and the shielding portion receives a fixed potential signal.

14. The display panel according to claim 13, wherein: The gate of the driving transistor is electrically connected to the first node via a first connecting portion, the first connecting portion and the second scanning line are provided in a different layer, and along a second direction, the first connecting portion and the second scanning line overlap to form a first overlapping region, and the second direction is perpendicular to a plane where a light emitting surface of the display panel is located; The shielding portion includes a first shielding portion. Along the second direction, the first shielding portion overlaps with the first overlapping region, and at least a portion of the first shielding portion is located between the first connecting portion and the second scanning line.

15. The display panel according to claim 13 or 14, characterized in that: The second scanning line includes a main body portion, the main body portion extends along a third direction, and the main body portion and the first node are arranged along the first direction, and the third direction intersects the first direction and is parallel to a plane where a light emitting surface of the display panel is located; The shielding portion includes a second shielding portion. Along the first direction, the second shielding portion is located between the first node and the second scan line.

16. The display panel according to claim 15, wherein: When the shielding portion includes a first shielding portion and a second shielding portion, the first shielding portion and the second shielding portion are electrically connected and located on the same layer.

17. The display panel according to claim 16, wherein: The second scanning line includes a main portion and an extension portion connected to the main portion, the main portion extending along a third direction, the third direction intersecting the first direction and being parallel to a plane where a light emitting surface of the display panel is located; the extension portion extending along the first direction and located on a side of the main portion facing the first node; the main portion and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a third shielding portion, which is located between the first node and the extension portion along the third direction; or the third shielding portion includes a first sub-portion and a second sub-portion that are electrically connected, and the first sub-portion is located between the first node and the extension portion along the third direction, and the second sub-portion is located between the first node and the main portion along the first direction.

18. The display panel according to claim 13, wherein: The second scanning line includes a main portion and an extension portion connected to the main portion, the main portion extending along a third direction, the third direction intersecting the first direction and being parallel to a plane where a light emitting surface of the display panel is located; the extension portion extending along the first direction and located on a side of the main portion facing the first node; the main portion and the first node are arranged along the first direction, and the extension portion and the first node are arranged along the third direction; The shielding portion includes a fourth shielding portion. Along a second direction, the fourth shielding portion overlaps with the extending portion. The second direction is perpendicular to a plane where the light emitting surface of the display panel is located.

19. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 18.

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