Low-noise image reading circuit and device applied to X-ray detector

Abstract

The invention provides a low-noise image reading circuit and device applied to an X-ray detector. A working process of a module M3 comprises the following steps of: 1, resetting a previous result before each work; secondly, voltage is grabbed for a capacitor C1, and at the moment, a module M2 is in a reset state; thirdly, voltage is grabbed for a capacitor C2, and at the moment, a module M2 is set to be in a normal state; and step 4, the module M3 stores the preceding-stage voltage on the C1 and the C2, and then the module M3 and the module M4 form a switched capacitor amplifier circuit, so that the signal is output to the interior of an ADC (Analog-to-Digital Converter). On the basis of an image reading circuit of a classical X-ray detector, RC noise enhancement and correlated double sampling processing are added, so that imbalance and noise of a front-stage integrator end circuit are greatly suppressed, and higher image output quality is obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low-noise image reading circuit and device applied to an X-ray detector. Background Art

[0002] X-ray detectors are widely used in industry, security and medical fields, especially in the medical field, including DR, DRF (dynamic DR), C-type outer arm, etc. Amorphous silicon has gradually become the mainstream detector in the market due to mature technology, good adaptability and low cost. Its principle is to convert X-rays into visible light, which is collected by PD sensor devices and converted into electrical signals. After passing through the internal reading circuit of the chip, it is output as a digital signal that can be processed by a computer. Thus, by sensing the intensity of X-rays passing through the object, it is processed by the computer into different gray levels, so that people can observe the image.

[0003] Figure 1 Image readout circuit for a classic X-ray detector. Figure 1 In module 1, the PD device, Ca capacitor, and TFT switch part constitute the X-ray sensor module, and Cp is the parasitic capacitance and wiring capacitance of the TFT switch; in module 2, the AMP1 operational amplifier and the Ci capacitor form an integrator circuit to process the sensor input charge, in which the switch S0 is used for reset operation; in module 3, the AMP2 operational amplifier forms a unit gain amplifier, which is used to drive the post-stage ADC module. The output signal of the integrator circuit enters the ADC module and is converted into a digital code stream output.

[0004] Figure 1 The image reading circuit of the classic X-ray detector shown has the following limitations:

[0005] a) After the electrical signal is output by the previous integrator circuit, it is directly sent to the next-stage unity gain amplifier circuit. The offset and noise brought by the integrator end are not processed, which will greatly affect the quality of the output signal;

[0006] b) For applications with low noise requirements, additional high-frequency filtering cannot be provided, and lower noise cannot be achieved overall.

[0007] Terminology explanation:

[0008] (1) DR: Digital Radiography: Digital X-ray imaging system

[0009] (2) PD: Photodiode

[0010] (3) TFT: Thin-Film-Transistor: Thin-Film Transistor

[0011] (4)AMP: Operational-Amplifier: Operational amplifier

[0012] (5) CMOS: Complementary-Metal-Oxide-Semiconductor

[0013] (6) ADC: Analog-to-Digital-Converter Summary of the invention

[0014] In view of the defects in the prior art, an object of the present invention is to provide a low-noise image reading circuit and device for an X-ray detector.

[0015] A low-noise image reading circuit for an X-ray detector provided by the present invention comprises:

[0016] Module M1, including a PD device, a Ca capacitor and a TFT switch; the PD device and the Ca capacitor are connected to one end of the TFT switch, and the Cp capacitor is connected to the other end of the TFT switch;

[0017] Module M2, including AMP1 operational amplifier, switch S0 and Ci capacitor; switch S0 is used for reset operation, capacitor Ci and switch S0 are connected to the negative input terminal and output terminal of AMP1 operational amplifier, the negative input terminal of AMP1 operational amplifier is connected to the TFT switch, and the positive input terminal of AMP1 operational amplifier is connected to the ground level;

[0018] Module M3, including capacitors C1 and C2, switches S1 to S10, and reference voltages Vref1, Vref2, and Vcmn; capacitor C1 is connected to the lower ends of switches S2 and S3, and the upper ends of switches S2 and S3 are connected to Vref1 and Vref2 respectively; capacitor C2 is connected to the upper ends of switches S6 and S7, and the lower ends of switches S6 and S7 are connected to Vref1 and Vref2 respectively; the upper end of switch S9 is connected to the right end of switch S1 and the left end of capacitor C1, and the lower end of switch S9 is connected to the right end of switch S5 and the left end of capacitor C2; the left end of switch S1 and the left end of switch S5 are connected to the output end of operational amplifier AMP1, the left end of switch S4 is connected to capacitor C1, the left end of switch S8 is connected to capacitor C2, the middle level of two sets of switches S10 is connected to Vcmn, and the two ends are used as outputs of module M3 respectively;

[0019] Module M4 includes an operational amplifier AMP2, a capacitor Cf, switches S11 to S14, and reference voltages Vcmn and Vcmp; two groups of upper and lower Cf capacitors, switches S11 to S14, and reference voltages Vcmn and Vcmp are the same, which are respectively connected to the positive and negative input terminals of the operational amplifier AMP2, and the positive phase VOUTP and negative phase VOUTN of the output terminals; the capacitor Cf is connected between switches S12 and S13, and the other ends of switches S12 and S13 are connected to Vcmn and Vcmp, the right end of switch S11 is connected to the left end of capacitor Cf, and the left end of switch S11 serves as the input terminal of module M4, the left end of switch S14 is connected to the right end of capacitor Cf, and the right end of switch S14 serves as the output terminal of module M4.

[0020] Preferably, the working process of the module M3 includes:

[0021] The first step is to reset the previous result before each work;

[0022] The second step is to capture the voltage of capacitor C1, at which time module M2 is in reset state;

[0023] The third step is to capture the voltage of capacitor C2, and at this time, module M2 is set to normal state;

[0024] In the fourth step, module M3 stores the previous stage voltage on C1 and C2, and then forms a switched capacitor amplifier circuit with module M4, thereby outputting the signal to the inside of the ADC.

[0025] Preferably, in the first step of the operation of module M3: module M2 is in a reset state, switch S0 is closed, switches S2, S3, S6, S7, and S10 of module M3 are in a closed state, and other switches are in an open state; switches S12 and S13 of module M4 are in a closed state, and other switches are in an open state.

[0026] Preferably, in the second step of the operation of the module M3: the module M2 continues to be in the reset state, the switches S2 and S3 in the module M3 are disconnected, and the switch S1 is closed, and the voltage is stored at both ends of the capacitor C1.

[0027] Preferably, in the third step of the operation of the module M3: the module M2 is in a normal state, and the switch S0 is disconnected; the switches S1, S6, and S7 in the module M3 are disconnected, and the switch S5 is closed, and the voltage is stored at both ends of the capacitor C2.

[0028] Preferably, in the fourth step of the operation of the module M3: switches S5 and S10 of the module M3 are disconnected, and switches S4, S8, and S9 are closed, and the output of two sets of voltages is realized at this time; switches S12 and S13 of the module M4 are disconnected, and switches S11 and S14 are closed, and the voltage of the previous module M3 is captured at this time, and VOUTP and VOUTN are output to the inside of the ADC.

[0029] Preferably, a first-stage RC filter circuit is inserted between the module M2 and the module M4;

[0030] The primary RC filter circuit includes two groups of adjustable resistors R, capacitors C, and switches S1 and S6; the upper group of switches S1, resistors R, and capacitors C form one filter path, the resistor R is connected between the right end of the switch S1 and the capacitor C, and the left end of the switch S1 is connected to the output end of the module M2; the lower group of switches S6, resistors R, and capacitors C form another filter path, the resistor R is connected between the right end of the switch S6 and the capacitor C, and the left end of the switch S6 is connected to the output end of the module M2;

[0031] The upper ends of the upper and lower capacitors in module M3 are connected to the input of the next-level module M3 as the output of the first-level RC filter circuit; when a certain filter path is selected, the resistor R and the capacitor C provide a low-pass filter circuit with a pole of 1 / RC to filter out high-frequency noise. At the same time, the resistor R is adjustable, and different pole solutions can be selected according to system requirements.

[0032] The low-noise image reading device applied to an X-ray detector provided by the present invention comprises the low-noise image reading circuit applied to the X-ray detector.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The present invention adopts RC noise enhancement and correlated double sampling processing to greatly suppress offset and noise. At the same time, for the capacitive correlated double sampling circuit, an adaptive switched capacitor type driving circuit is proposed. The driving circuit can capture the output of the correlated double sampling circuit and can also drive the subsequent ADC.

[0035] (2) Based on the image reading circuit of the classical X-ray detector, the present invention adds RC noise enhancement and correlated double sampling processing, so that the offset and noise of the front-end integrator circuit are greatly suppressed, thereby obtaining a higher image output quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 Image reading circuit for a classic X-ray detector;

[0038] Figure 2 An image reading circuit with added correlated double sampling processing;

[0039] Figure 3 The invention relates to an image reading circuit of noise enhancement type and correlated double sampling processing. DETAILED DESCRIPTION

[0040] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0041] Example

[0042] The present invention provides a low-noise image reading circuit for use in an X-ray detector, such as Figure 2, wherein the PD device, Ca capacitor, and TFT switch in module 1 constitute an X-ray sensor module, Cp is the parasitic capacitance and wiring capacitance of the TFT switch, the PD device and Ca capacitor are connected to the left end of the TFT switch, and the CP capacitor is connected to the right end of the TFT switch; the AMP1 operational amplifier and Ci capacitor in module 2 constitute an integrator circuit to process the sensor input charge, wherein the switch S0 is used for reset operation, the capacitor Ci and the switch S0 are connected to the negative input and output ends of the AMP1 operational amplifier, and the AMP1 operational amplifier of module 2 The negative input terminal of the device is connected to the right end of the TFT switch of module 1, and the positive input terminal of the AMP1 operational amplifier of module 2 is connected to the ground level; in module 3, capacitors C1 and C2, switches S1 to S10, reference voltages Vref1, Vref2, and Vcmn form a correlated double sampling module, in which C1 is connected to the lower ends of switches S2 and S3, the upper ends of S2 and S3 are connected to Vref1 and Vref2 respectively, C2 is connected to the upper ends of switches S6 and S7, the lower ends of S6 and S7 are connected to Vref1 and Vref2 respectively, and the upper end of switch S9 is connected to switch The right end of S1 and the left end of C1 are connected together, the lower end of switch S9 is connected to the right end of switch S5 and the left end of C2; the left end of switch S1 and the left end of S5 are connected to the output end of AMP1 operational amplifier in module 2, the left end of switch S4 is connected to capacitor C1, the left end of switch S8 is connected to capacitor C2, the middle level of the two groups of S10 is connected to Vcmn, and the two ends are used as the output of module 3 respectively; AMP2 operational amplifier, capacitor Cf, switches S11~S14, reference voltage Vcmn, Vcmp in module 4 , wherein the upper and lower groups of Cf capacitors, switches S11 to S14, and reference voltages Vcmn and Vcmp are the same, respectively connected to the positive and negative input terminals of the operational amplifier AMP2, and the output terminals of VOUTP and VOUTN, the capacitor Cf is connected between switches S12 and S13, and the other terminals of S12 and S13 are connected to Vcmn and Vcmp, the right end of switch S11 is connected to the left end of capacitor Cf, the left end of switch S11 is used as the input terminal of module 4, the left end of switch S14 is connected to the right end of capacitor Cf, and the right end of switch S14 is used as the output terminal of module 4. In particular, module 4 and capacitors C1 and C2 in the previous module 3 together form an integral amplifier module, which can realize the pickup of the previous stage signal, and the output signal is also used to drive the subsequent ADC module, and the output signal of the integrator circuit enters the ADC module and is converted into a digital code stream output.

[0043] Figure 2The working principle of module 3: The working process can be divided into 4 groups of steps. The first step is the reset state of the entire module. The previous result needs to be reset before each work. The second step is the capacitor C1 grabbing the voltage. At this time, the front-stage integrator module 2 is still in the reset state. The third step is the capacitor C2 grabbing the voltage. At this time, the front-stage integrator module 2 is set to the normal state. The fourth step is the operation state of the two groups of voltages at the front stage. At this time, the result is output to the next-stage module 4. The working process of module 4 is to store the front-stage voltage on C1 and C2 in module 3, and then form a switched capacitor amplifier circuit with module 4, so as to realize the output signal to the inside of the ADC.

[0044] Figure 2 The specific workflow of the first step: Integrator module 2 is in the reset state, the S0 switch is closed, S2, S3, S6, S7, and S10 of module 3 are in the closed state, and the others are in the open state. S12 and S13 of module 4 are in the closed state, and the others are in the open state. Figure 2 The specific working process of the second step is as follows: the integrator module 2 continues to be in the reset state, S2 and S3 in the module 3 are disconnected, and S1 is closed, and the voltage is stored at both ends of the capacitor C1. Figure 2 The specific working process of the third step is as follows: Integrator module 2 is in normal state, S0 is disconnected. In module 3, S1, S6, and S7 are disconnected, and S5 is closed, and the voltage is stored at both ends of capacitor C2. Figure 2 The specific workflow of the fourth step is: S5 and S10 of module 3 are disconnected, S4, S8, and S9 are closed, and two sets of voltage outputs are realized. S12 and S13 of module 4 are disconnected, and S11 and S14 are closed. At this time, the voltage of the previous module 3 can be captured and VOUTP and VOUTN can be output to the ADC.

[0045] Figure 3 For Figure 2 An image reading circuit of an X-ray detector with adjustable noise level is proposed based on the invention, wherein a first-stage RC filter circuit is inserted between the integrator module 2 and the correlated double sampling circuit module 4. In module 3, two groups of adjustable resistors R, capacitors C, switches S1 and S6 form a first-stage filter circuit, wherein the upper group of switches S1, resistors R, and capacitors C form a filter path, the resistor R is connected between the right end of switch S1 and capacitor C, and the left end of S1 is connected to the output end of module 2; the lower group of switches S6, resistors R, and capacitors C form another filter path, the resistor R is connected between the right end of switch S6 and capacitor C, and the left end of S6 is connected to the output end of module 2, and the upper ends of the upper and lower capacitors in module 3 are connected to the input of the next-stage correlated double sampling circuit as the output of the first-stage RC filter circuit; when a certain filter path is selected, the resistor R and capacitor C can provide a low-pass filter circuit with a pole of 1 / RC to achieve the effect of filtering out high-frequency noise, and at the same time, the resistor R is adjustable, and different pole schemes can be selected according to system requirements; this scheme is Figure 2 On this basis, noise filtering can be further achieved, and different gears can be provided to correspond to different applications.

[0046] In the description of the present application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0047] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0048] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A low-noise image reading circuit for an X-ray detector, characterized in that: include: Module M1, including PD device, Ca capacitor and TFT switch; The PD device and the Ca capacitor are connected to one end of the TFT switch, and the Cp capacitor is connected to the other end of the TFT switch; Module M2, including AMP1 operational amplifier, switch S0 and Ci capacitor; switch S0 is used for reset operation, capacitor Ci and switch S0 are connected to the negative input terminal and output terminal of AMP1 operational amplifier, the negative input terminal of AMP1 operational amplifier is connected to the TFT switch, and the positive input terminal of AMP1 operational amplifier is connected to the ground level; Module M3, including capacitors C1 and C2, switches S1 to S10, and reference voltages Vref1, Vref2, and Vcmn; capacitor C1 is connected to the lower ends of switches S2 and S3, and the upper ends of switches S2 and S3 are connected to Vref1 and Vref2 respectively; capacitor C2 is connected to the upper ends of switches S6 and S7, and the lower ends of switches S6 and S7 are connected to Vref1 and Vref2 respectively; the upper end of switch S9 is connected to the right end of switch S1 and the left end of capacitor C1, and the lower end of switch S9 is connected to the right end of switch S5 and the left end of capacitor C2; the left end of switch S1 and the left end of switch S5 are connected to the output end of operational amplifier AMP1, the left end of switch S4 is connected to capacitor C1, the left end of switch S8 is connected to capacitor C2, the middle level of two sets of switches S10 is connected to Vcmn, and the two ends are used as outputs of module M3 respectively; Module M4 includes an operational amplifier AMP2, a capacitor Cf, switches S11 to S14, and reference voltages Vcmn and Vcmp; two groups of upper and lower Cf capacitors, switches S11 to S14, and reference voltages Vcmn and Vcmp are the same, which are respectively connected to the positive and negative input terminals of the operational amplifier AMP2, and the positive phase VOUTP and negative phase VOUTN of the output terminals; the capacitor Cf is connected between switches S12 and S13, and the other ends of switches S12 and S13 are connected to Vcmn and Vcmp, the right end of switch S11 is connected to the left end of capacitor Cf, and the left end of switch S11 serves as the input terminal of module M4, the left end of switch S14 is connected to the right end of capacitor Cf, and the right end of switch S14 serves as the output terminal of module M4.

2. The low-noise image reading circuit for X-ray detector according to claim 1, characterized in that: The working process of the module M3 includes: The first step is to reset the previous result before each work; The second step is to capture the voltage of capacitor C1, at which time module M2 is in reset state; The third step is to capture the voltage of capacitor C2, and at this time, module M2 is set to normal state; In the fourth step, module M3 stores the previous stage voltage on C1 and C2, and then forms a switched capacitor amplifier circuit with module M4, thereby outputting the signal to the inside of the ADC.

3. The low-noise image reading circuit for an X-ray detector according to claim 2, characterized in that: In the first step of the operation of module M3: module M2 is in a reset state, switch S0 is closed, switches S2, S3, S6, S7, and S10 of module M3 are in a closed state, and other switches are in an open state; switches S12 and S13 of module M4 are in a closed state, and other switches are in an open state.

4. The low-noise image reading circuit for X-ray detector according to claim 3, characterized in that: In the second step of the operation of the module M3: the module M2 continues to be in the reset state, the switches S2 and S3 in the module M3 are disconnected, and the switch S1 is closed, and the voltage is stored at both ends of the capacitor C1.

5. The low-noise image reading circuit for X-ray detector according to claim 4, characterized in that: In the third step of the operation of module M3: module M2 is in a normal state, and switch S0 is disconnected; switches S1, S6, and S7 in module M3 are disconnected, and switch S5 is closed, and voltage is stored at both ends of capacitor C2.

6. The low-noise image reading circuit for X-ray detector according to claim 5, characterized in that: In the fourth step of the operation of module M3: switches S5 and S10 of module M3 are disconnected, and switches S4, S8, and S9 are closed, and two sets of voltages are output; switches S12 and S13 of module M4 are disconnected, and switches S11 and S14 are closed, and the voltage of the previous module M3 is captured, and VOUTP and VOUTN are output to the inside of the ADC.

7. The low-noise image reading circuit for an X-ray detector according to claim 1, characterized in that: Insert a first-stage RC filter circuit between module M2 and module M4; The primary RC filter circuit includes two groups of adjustable resistors R, capacitors C, and switches S1 and S6; the upper group of switches S1, resistors R, and capacitors C form one filter path, the resistor R is connected between the right end of the switch S1 and the capacitor C, and the left end of the switch S1 is connected to the output end of the module M2; the lower group of switches S6, resistors R, and capacitors C form another filter path, the resistor R is connected between the right end of the switch S6 and the capacitor C, and the left end of the switch S6 is connected to the output end of the module M2; The upper ends of the upper and lower capacitors in module M3 are connected to the input of the next-level module M3 as the output of the first-level RC filter circuit; when a certain filter path is selected, the resistor R and the capacitor C provide a low-pass filter circuit with a pole of 1 / RC to filter out high-frequency noise. At the same time, the resistor R is adjustable, and different pole solutions can be selected according to system requirements.

8. A low-noise image reading device for an X-ray detector, characterized in that: A low-noise image reading circuit applied to an X-ray detector comprising any one of claims 1 to 7.

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