Sensor pixel unit, signal processing circuit and electronic equipment

Abstract

The embodiment of the invention discloses a sensor pixel unit, a signal processing circuit and electronic equipment, and the sensor pixel unit comprises an analog voltage domain module, a voltage domain conversion module, and a digital voltage domain module. The analog voltage domain module is used for receiving an optical signal in an exposure duration to generate a voltage signal, and sending a first analog signal to the voltage domain conversion module through a first output end in response to the fact that the voltage signal reaches a preset threshold value; when the exposure period is reached, a second analog signal is output through a second output end; the voltage domain conversion module is used for converting the first analog signal into a first digital signal and inputting the first digital signal into the digital voltage domain module; and the digital voltage domain module is used for sending out a reading request signal and outputting the first digital signal according to the received permission signal.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor technology, and in particular to a sensor pixel unit, a signal processing circuit and an electronic device. Background Art

[0002] Pulse sequence image sensors reflect light intensity by detecting the time required for photogenerated charge to accumulate to a certain threshold. The stronger the light, the shorter the time required for photogenerated charge to accumulate to the threshold. In actual imaging, the light intensity received by each pixel unit in the pixel array is different, and the time it takes for its photogenerated charge to reach the threshold is also different. For signal reading, if the pixel array signal is read synchronously at a fixed frame rate, there will inevitably be pixel units that have reached the threshold early, but have to wait for all other pixel units to reach the threshold before they can be output together. Obviously, this reading method has low time efficiency and cannot reflect the light intensity corresponding to each pixel unit. Summary of the invention

[0003] Embodiments of the present disclosure provide a sensor pixel unit, a signal processing circuit, and an electronic device.

[0004] In one aspect of an embodiment of the present disclosure, a sensor pixel unit is provided, comprising: an analog voltage domain module, a voltage domain conversion module, and a digital voltage domain module;

[0005] The analog voltage domain module is used to receive the light signal within the exposure time to generate a voltage signal, and in response to the voltage signal reaching a preset threshold, send the first analog signal to the voltage domain conversion module through the first output terminal; and output the second analog signal through the second output terminal when the exposure period is reached;

[0006] The voltage domain conversion module is used to convert the first analog signal into a first digital signal, and input the first digital signal into the digital voltage domain module;

[0007] The digital voltage domain module is used to send a read request signal and output the first digital signal according to the received permission signal.

[0008] Optionally, the analog voltage domain module includes: a photodiode, a first reset transistor, an auxiliary circuit and a positive feedback unit;

[0009] The photodiode is used to receive the light signal within the exposure time to generate the voltage signal, and in response to the voltage signal reaching a preset threshold value during the exposure period, output the voltage signal to the positive feedback unit, and in response to reaching the exposure period, output the voltage signal to the auxiliary circuit;

[0010] The first reset transistor is used to control the photodiode to perform reset according to the analog reset signal;

[0011] The auxiliary circuit is used for controlling the second output terminal to output the second analog signal according to the received voltage signal when the exposure period is reached;

[0012] The positive feedback unit is used to convert the voltage signal into the first analog signal, and output the first analog signal to the voltage domain conversion module.

[0013] Optionally, the positive feedback unit includes a first inverter and a pull-down transistor;

[0014] The pull-down transistor is connected in parallel with the input terminal and the output terminal of the first inverter via the drain terminal and the gate terminal, and the source terminal of the pull-down transistor is grounded;

[0015] The first inverter arranges the input voltage signal into an analog power signal, and inputs the analog power signal into the voltage domain conversion module based on the output end of the first inverter as the first output end.

[0016] Optionally, the auxiliary circuit includes a source follower transistor and a readout transistor;

[0017] One end of the photodiode is grounded, and the other end is connected to the drain end of the reset transistor, the gate end of the source follower transistor and the positive feedback unit;

[0018] The source terminal of the reset transistor is connected to the analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives the analog reset signal;

[0019] The source terminal of the source follower transistor is connected to the analog power supply signal, the gate terminal is connected to the other end of the photodiode, the drain terminal of the reset transistor and the positive feedback unit, and the drain terminal is connected to the drain terminal of the readout transistor;

[0020] The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives a readout signal, and the source terminal serves as a second output terminal.

[0021] Optionally, the first reset transistor, the pull-down transistor, the source follower transistor, the readout transistor, and two transistors included in the first inverter are high-voltage transistors.

[0022] Optionally, the voltage domain conversion module includes: a second inverter composed of a first conversion transistor and a second conversion transistor;

[0023] The gate terminal of the first conversion transistor is connected to the gate terminal of the second conversion transistor as the input terminal of the second inverter, and the drain terminal of the first conversion transistor is connected to the source terminal of the second conversion transistor as the output terminal of the second inverter; the source terminal of the first conversion transistor is connected to a digital power supply signal, and the drain terminal of the second conversion transistor is grounded.

[0024] Optionally, the first conversion transistor and the second conversion transistor are high voltage transistors.

[0025] Optionally, the digital voltage domain module includes: a pulse output transistor, an enable transistor, a request transistor and a pulse latch unit;

[0026] The drain terminal of the pulse output transistor is connected to the voltage domain conversion module, the gate terminal of the request transistor and the pulse latch unit, the gate terminal is connected to the enable signal, and the source terminal serves as a third output terminal, and outputs the first digital signal according to the control of the enable signal;

[0027] The drain terminal of the enabling transistor is connected to the digital power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit. In response to the second digital signal latched by the pulse latch unit being at a high level, the enabling transistor is turned on;

[0028] The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the voltage domain conversion module, and the drain terminal serves as a fourth output terminal; in response to the first digital signal being at a low level and the enable transistor being turned on, a read request signal is output through the fourth output terminal;

[0029] The pulse latch unit is used to latch the second digital signal according to the control of the digital reset signal, and turn on the enable transistor in response to the second digital signal being at a high level; and turn off the enable transistor in response to receiving the enable signal within an exposure cycle.

[0030] Optionally, the pulse latch unit includes: a second reset transistor, a third inverter, a trigger termination transistor and a request enabling transistor;

[0031] The source terminal of the second reset transistor is connected to the digital power supply signal, the drain terminal is connected to the source terminal of the trigger termination transistor and the source terminal of the request permission transistor as a latch point, and the gate terminal receives the digital reset signal;

[0032] The source terminal of the request permission transistor is connected to the latch point, the drain terminal is connected to the voltage domain conversion module, and the gate terminal receives the permission signal; the first digital signal is written into the latch point according to the control of the permission signal;

[0033] The input end of the third inverter is connected to the latch point, and the output end is connected to the gate end of the enable transistor, and is used to inversely process the second digital signal latched by the latch point and input it into the gate end of the enable transistor to control whether the enable transistor is turned on;

[0034] The trigger termination transistor is connected in parallel with the third inverter via a source terminal and a gate terminal, and a drain terminal is grounded, and is used to ground the latch point when the output of the third inverter is at a high level.

[0035] Optionally, the pulse output transistor, the enable transistor, the request transistor, the second reset transistor, the trigger termination transistor, the request enabling transistor, and the transistors included in the third inverter in the digital voltage domain module are all low voltage transistors.

[0036] Another aspect of the embodiments of the present disclosure provides a signal processing circuit, comprising: a pixel array consisting of n rows and m columns of sensor pixel units as described in any one of the above embodiments, a row drive control module, a row arbitration module and a column readout module; n and m are integers greater than or equal to 1 respectively;

[0037] The row drive control module is used to provide analog reset signals, digital reset signals and readout signals to the sensor pixel units in the pixel array row by row;

[0038] The pixel array is used to perform a reset according to the analog reset signal and the digital reset signal, send a read request signal to the row arbitration module in response to the first analog signal reaching a preset threshold value during an exposure period, and send a first digital signal to the column readout module under the control of the enable signal fed back by the row arbitration module; when the exposure period is reached, send a second analog signal to the column readout module under the control of the readout signal; the first digital signal is determined based on the first analog signal;

[0039] The row arbitration module is used to receive the read request signal sent by at least one row of the sensor pixel units in the pixel array, and feed back the permission signal to at least one row of the sensor pixel units according to the time sequence of receiving the read request signal;

[0040] The column readout module is used to receive the first digital signal and the second analog signal sent by at least one column of the sensor pixel units.

[0041] Optionally, it also includes: a row address encoder and a clock module;

[0042] When the row arbitration module feeds back an enabling signal to a row of the sensor pixel units, the row address encoder encodes row information of the sensor pixel units receiving the enabling signal into a row address;

[0043] The clock module is used to record the time information when the row address encoder generates the row address, and associate the time information with the row address.

[0044] Optionally, the column readout module comprises: m analog-to-digital converters, m column buffers and a column address encoder; each of the analog-to-digital converters corresponds to a column of the sensor pixel units, each of the column buffers corresponds to a column of the sensor pixel units; each of the analog-to-digital converters corresponds to one of the column buffers;

[0045] The column buffer is used to store the first digital signal output by the sensor pixel unit of the corresponding column and transmit the first digital signal to the column address encoder;

[0046] The column address encoder is used to receive the first digital signal output by the column buffer, encode the column information corresponding to the first digital signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the first digital signal;

[0047] The analog-to-digital converter is used to receive the second analog signal output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second analog signals, and perform analog-to-digital conversion on the differential operation result to obtain a third digital signal.

[0048] Optionally, it also includes: a conversion interface circuit;

[0049] The conversion interface circuit is used to receive the signal output by the column readout module.

[0050] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the sensor pixel unit described in any of the above embodiments or the signal processing circuit described in any of the above embodiments;

[0051] The memory stores computer-executable instructions;

[0052] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

[0053] Optionally, the electronic device is included in any one of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment.

[0054] The sensor pixel unit, signal processing circuit and electronic device provided based on the above embodiments of the present disclosure include: an analog voltage domain module, a voltage domain conversion module and a digital voltage domain module; the analog voltage domain module is used to receive a light signal within an exposure time to generate a voltage signal, and in response to the voltage signal reaching a preset threshold, send a first analog signal to the voltage domain conversion module through a first output terminal; and when the exposure period is reached, output a second analog signal through a second output terminal; the voltage domain conversion module is used to convert the first analog signal into a first digital signal, and input the first digital signal into the digital voltage domain module; the digital voltage domain module is used to send a read request signal, and output the first digital signal according to the received permission signal. In the disclosed embodiment, when the first analog signal reaches a preset threshold value during the exposure period, a first digital signal is requested to be issued to realize asynchronous reading of the pixel unit; and when the exposure period is reached, a second analog signal is output to realize synchronous reading of the pixel unit; a working mode combining synchronous reading and asynchronous reading of the pixel unit is realized, and while a light signal with a stronger light intensity is expressed by the asynchronously read signal, synchronous reading ensures that a light signal with a weaker light intensity is output during the exposure period, thereby having the beneficial effects of both synchronous reading and asynchronous reading.

[0055] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0057] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0058] Figure 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0059] Figure 2 is a schematic diagram of the circuit structure of an analog voltage domain module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0060] Figure 3 is a schematic diagram of the circuit structure of an analog voltage domain module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0061] Figure 4 is a schematic diagram of a circuit structure of a voltage domain conversion module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0062] Figure 5 is a circuit structure diagram of a digital voltage domain module in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0063] Figure 6 is a circuit structure diagram of a digital voltage domain module in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0064] Figure 7 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an optional exemplary embodiment of the present disclosure;

[0065] Figure 8 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0066] Fig. 9 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0067] Fig.10 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0068] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0069] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0070] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0071] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0072] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0073] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0074] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0075] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0076] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0077] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0078] The embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0079] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0080] In the process of implementing the present disclosure, the inventors found that the synchronous reading of pixel units has the disadvantages of low time efficiency and inability to reflect the light intensity corresponding to each pixel unit; while the asynchronous reading of pixel units can make the pixel output a signal when it reaches the threshold, and reset after the output, and directly enter the next exposure. The asynchronous reading method avoids the situation where the pixel is still waiting after reaching the threshold, but for weaker light intensities, the triggering output time is longer. In a pixel array, the pixel unit that receives strong light has output signals many times, while the pixel unit that receives weak light may not have output once. This makes the information of the strong light part of the image signal very rich or even too redundant, while the information of the weak light part may be missing. Therefore, the reading method of simple synchronous output or asynchronous output is not perfect.

[0081] In view of the technical problems existing in the existing synchronous readout and asynchronous readout, the present disclosure proposes the following sensor pixel unit.

[0082] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the sensor pixel unit (hereinafter referred to as pixel unit) provided in this embodiment includes: an analog voltage domain module 11, a voltage domain conversion module 12 and a digital voltage domain module 13.

[0083] The analog voltage domain module 11 is used to receive the light signal within the exposure time to generate a voltage signal Vpd. In response to the voltage signal Vpd reaching a preset threshold, the first analog signal Vpd is sent to the voltage domain conversion module 12 through the first output terminal; and when the exposure cycle is reached, the second analog signal Vout is output through the second output terminal.

[0084] Optionally, the voltage signal Vpd may be an analog voltage signal.

[0085] In some optional embodiments, since the analog power supply voltage is usually much higher than the digital power supply voltage, in order to ensure the normal operation of components in the analog voltage domain, optionally, the transistors included in the analog voltage domain module and the voltage domain conversion module are high-voltage transistors; and the transistors in the digital voltage domain are low-voltage transistors. The area of ​​low-voltage transistors is smaller. By adopting low-voltage transistors, the area and power consumption of the pixel unit can be greatly reduced.

[0086] The main structure of the voltage domain conversion module 11 in this embodiment may include a photosensitive unit of a 3T structure (including 3 transistors) and a positive feedback unit, through which the photosensitive unit outputs a first analog signal when the voltage signal Vpd generated based on the light signal reaches a preset threshold, to achieve asynchronous reading of the pixel unit, and to achieve that the light intensity of the pixel unit can be reflected by the duration of the accumulation of photogenerated charges when the light intensity is strong, thereby avoiding the situation where the pixel unit is still waiting after reaching the preset threshold. At the same time, for the case of weak light intensity, the photosensitive unit provided in this embodiment outputs a second analog signal Vout when the exposure cycle is reached, to achieve synchronous reading of the pixel unit, thereby ensuring that the signal with weak light intensity is output within one exposure cycle.

[0087] The voltage domain conversion module 12 is used to convert the first analog signal into a first digital signal, and input the first digital signal into the digital voltage domain module 13 .

[0088] In this embodiment, since there is a large difference between the voltage value of the analog voltage domain and the voltage value of the digital voltage domain, if the first analog signal is input into the digital voltage domain module 13, it may not be output normally. Therefore, this embodiment converts the first analog signal into a first digital signal through the voltage domain conversion module 12, so that all signals processed in the digital voltage domain module 13 are digital signals.

[0089] The digital voltage domain module 13 is used to send a read request signal and output a first digital signal according to the received permission signal.

[0090] In this embodiment, the output of the first digital signal is controlled based on the enable signal through the digital voltage domain module, thereby avoiding the problem of output error caused by simultaneous asynchronous output of multiple rows of pixel units in the pixel array of the sensor.

[0091] The sensor pixel unit, signal processing circuit and electronic device provided by the above-mentioned embodiments of the present disclosure include: an analog voltage domain module, a voltage domain conversion module and a digital voltage domain module; the analog voltage domain module is used to receive a light signal within an exposure time to generate a first analog signal, and in response to the first analog signal reaching a preset threshold, the first analog signal is sent to the voltage domain conversion module through a first output terminal; and when the exposure period is reached, a second analog signal is output through a second output terminal; the voltage domain conversion module is used to convert the first analog signal into a first digital signal, and input the first digital signal into the digital voltage domain module; the digital voltage domain module is used to issue a read request signal, and output the first digital signal according to the received permission signal. In the disclosed embodiment, when the first analog signal reaches a preset threshold value during the exposure period, a first digital signal is requested to be issued to realize asynchronous reading of the pixel unit; and when the exposure period is reached, a second analog signal is output to realize synchronous reading of the pixel unit; a working mode combining synchronous reading and asynchronous reading of the pixel unit is realized, and while a light signal with a stronger light intensity is expressed by the asynchronously read signal, synchronous reading ensures that a light signal with a weaker light intensity is output during the exposure period, thereby having the beneficial effects of both synchronous reading and asynchronous reading.

[0092] The pulse sequence image sensor reflects the intensity of the illumination signal (light intensity) by detecting the time required for the photogenerated charge to accumulate to a certain threshold. The stronger the illumination signal, the shorter the time required for the photogenerated charge to accumulate to the threshold. In a certain frame period (exposure period), the pixel unit that reaches the threshold in advance triggers asynchronous reading, and the pixel unit that has not reached the threshold after the exposure is completed is synchronously read, which can take into account the photosensitivity and data transmission efficiency of strong light and weak light. For asynchronous reading, the pixel unit only needs to output a 1-bit pulse signal representing the threshold (corresponding to the first digital signal in this embodiment), while for synchronous reading, the pixel unit needs to output the analog signal converted from all the photogenerated charges accumulated in the exposure period (corresponding to the second analog signal in this embodiment). Generally speaking, from the perspective of simple design, all signals in the pixel period, including the output pulse signal and analog signal, work in the analog voltage domain, and then a voltage domain conversion module is set around the pixel array to convert the analog voltage into a digital voltage. Moreover, the power supply voltage of the analog voltage domain is usually much higher than that of the digital voltage domain. For a 1-bit pulse signal, the low-voltage digital voltage domain can fully express the information. Using analog voltage to express and transmit will increase the area and power consumption and decrease the speed. Therefore, in the embodiment of the present disclosure, a voltage domain conversion module is added inside the pixel unit to convert the first analog signal asynchronously output by the analog voltage domain module into a first digital signal. Converting the pulse signal to the digital voltage domain in advance in the pixel unit can reduce the area and power consumption of the pixel unit and improve the transmission efficiency of the pulse signal.

[0093] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of an analog voltage domain module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 2 As shown, the analog voltage domain module 11 in the sensor pixel unit provided in this embodiment includes a photodiode 111, a first reset transistor 112, an auxiliary circuit 113 and a positive feedback unit 114;

[0094] The photodiode 111 is used to receive a light signal during the exposure time to generate a voltage signal Vpd. During the exposure period, in response to the voltage signal Vpd reaching a preset threshold, the voltage signal Vpd is output to the positive feedback unit 114. In response to reaching the exposure period, the voltage signal is output to the auxiliary circuit 113.

[0095] A photodiode is a photodetector that can convert light into current or voltage signals depending on how it is used. The die often uses a PN junction with photosensitive characteristics, which is very sensitive to changes in light, has unidirectional conductivity, and changes electrical properties when the light intensity is different. Therefore, the light intensity can be used to change the voltage or current in the circuit.

[0096] The first reset transistor 112 is used to control the photodiode 111 to perform a reset according to an analog reset signal.

[0097] In this embodiment, whether the photodiode 111 is reset is controlled by turning on or off the first reset transistor. Optionally, the source terminal of the first reset transistor 112 is connected to the analog power supply signal AVDD, and the drain terminal is connected to the other end of the photodiode 112. The first reset transistor 112 is turned on or off according to the reset signal received at the gate terminal. When the first reset transistor 112 is turned on, the photodiode 111 is connected to the analog power supply signal AVDD, thereby resetting the photodiode 111.

[0098] Optionally, the first reset transistor is an N-type transistor, and the reset transistor is turned on in response to the reset signal being at a high level; optionally, the first reset transistor is a P-type transistor, and the reset transistor is turned on in response to the reset signal being at a low level.

[0099] The auxiliary circuit 113 is used to control the second output terminal to output the second analog signal Vout according to the received voltage signal when the exposure period is reached.

[0100] The positive feedback unit 114 is used to convert the voltage signal into a first analog signal, and output the first analog signal to the voltage domain conversion module 12 .

[0101] In this embodiment, in response to the voltage signal Vpd reaching a preset threshold, the voltage signal is input into the positive feedback unit 114, and the voltage signal is converted into a first analog signal that is the same as the analog power supply signal through the positive feedback unit 114. In addition, through the positive feedback provided by the positive feedback unit, the voltage signal input to the positive feedback unit can be quickly reduced to a 0 level, so that the time when the voltage signal reaches the preset threshold can be more accurately located, thereby improving the accuracy of asynchronous reading.

[0102] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of an analog voltage domain module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 3 As shown, the positive feedback unit 114 includes a first inverter 1141 and a pull-down transistor 1142.

[0103] The pull-down transistor 1142 is connected in parallel to the input terminal and the output terminal of the first inverter 1141 through the drain terminal and the gate terminal, and the source terminal of the pull-down transistor 1142 is grounded GND.

[0104] In this embodiment, the drain terminal of the pull-down transistor 1142 receives a voltage signal. In response to the voltage signal reaching a preset threshold, the voltage signal can be considered to be at a low level. The low-level signal is converted into a first analog signal of a high level after being processed by the first inverter 1141. Since the first analog signal is connected to the gate terminal of the pull-down transistor 1142, the pull-down transistor 1142 is turned on, that is, the voltage signal is grounded, so that the voltage signal quickly drops to 0 level, thereby achieving a more accurate positioning of the time when the voltage signal drops to the preset threshold, thereby improving the sensitivity of the sensor using the pixel unit to strong light collection.

[0105] The first inverter 1141 converts the input voltage signal into an analog power signal, and inputs the analog power signal into the voltage domain conversion module 12 based on the output terminal of the first inverter as the first output terminal.

[0106] Optionally, the first inverter 1141 includes two transistors, for example, a first positive feedback transistor and a second positive feedback transistor, wherein the first positive feedback transistor is a P-type transistor, the gate terminal of the first positive feedback transistor and the gate terminal of the second positive feedback transistor are connected as the input terminal of the first inverter, the drain terminal of the first positive feedback transistor and the source terminal of the second positive feedback transistor are connected as the output terminal of the first inverter, and the source terminal of the first positive feedback transistor is connected to the analog voltage signal; the second positive feedback transistor is an N-type transistor, and the drain of the second positive feedback transistor is grounded; therefore, when the voltage signal is reduced to a low level, the first positive feedback transistor is turned on, and at this time, the analog voltage signal is output to the voltage domain conversion module as the first analog signal.

[0107] like Figure 3As shown, the auxiliary circuit 113 includes a source follower transistor 1131 and a readout transistor 1132 , wherein one end of the photodiode 111 is grounded GND, and the other end is connected to the drain end of the first reset transistor 112 , the gate end of the source follower transistor 1131 and the positive feedback unit 114 .

[0108] The first reset transistor 112 has a source terminal connected to the analog power signal AVDD, a drain terminal connected to the other end of the photodiode 111 , and a gate terminal receiving the analog reset signal ARST.

[0109] The source follower transistor 1131 has a source terminal connected to the analog power signal AVDD, a gate terminal connected to the other end of the photodiode 111 , a drain terminal of the first reset transistor 112 and the positive feedback unit 114 , and a drain terminal connected to the drain terminal of the readout transistor 1132 .

[0110] In response to the voltage signal output by the photodiode being at a high level, the source follower transistor 1131 is turned on, and generates a corresponding analog voltage signal following the change of the voltage signal. When the readout transistor is turned on, the analog voltage signal is output as the second analog signal Vout.

[0111] The drain terminal of the readout transistor 1132 is connected to the drain terminal of the source follower transistor 1131, the gate terminal receives the readout signal Read (outputs the second analog signal when the exposure period is reached through the timing control of the readout signal), and the source terminal serves as the second output terminal.

[0112] Optionally, the source follower transistor 1131 and the readout transistor 1132 are generally N-type transistors, and are in a turned-on state according to receiving a high level at the gate.

[0113] In the embodiments provided in the present disclosure, since the voltage value in the analog voltage domain is usually significantly higher than the voltage value in the digital voltage domain, the low-voltage transistor cannot withstand the voltage in the analog voltage domain, while the gate oxide layer of the high-voltage transistor is thicker and can withstand the higher analog domain voltage. Therefore, optionally, the first reset transistor, the pull-down transistor, the source follower transistor, the readout transistor included in the analog voltage domain, and the two transistors included in the first inverter (for example, the first positive feedback transistor and the second positive feedback transistor) are high-voltage transistors. In addition, since the gate oxide layer of the high-voltage transistor is thicker, the area of ​​the high-voltage transistor is larger, and the current and power consumption are also larger. Therefore, a low-voltage transistor is used in the digital voltage domain module to reduce the overall area occupied by the pixel unit.

[0114] Figure 4 FIG. 1 is a schematic diagram of a circuit structure of a voltage domain conversion module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 4As shown, the voltage domain conversion module 12 provided in this embodiment includes: a second inverter composed of a first conversion transistor 121 and a second conversion transistor 122 .

[0115] The gate terminal of the first conversion transistor 121 is connected to the gate terminal of the second conversion transistor 122 as the input terminal of the second inverter, and the drain terminal of the first conversion transistor 121 is connected to the source terminal of the second conversion transistor 122 as the output terminal of the second inverter; the source terminal of the first conversion transistor 121 is connected to the digital power signal DVDD, and the drain terminal of the second conversion transistor 122 is grounded.

[0116] Optionally, the first conversion transistor is a P-type transistor, and the source terminal of the first conversion transistor is connected to the digital voltage signal DVDD; the second conversion transistor is an N-type transistor, and the drain of the second conversion transistor is grounded; therefore, when the voltage signal generated by the photodiode is reduced to a low level, the analog voltage domain module outputs a first analog signal of a high level through the first output terminal, at which time the second conversion transistor is turned on, and the converted first digital signal is a digital signal of a low level. When the voltage signal generated by the photodiode is a high level (for example, an analog reset signal), the first analog signal is a low level, and at this time the first conversion transistor is turned on, and the digital voltage signal DVDD (high level) is output to the digital voltage domain module. Therefore, the signals input to the digital voltage domain module are all digital signals, realizing the conversion of analog signals to digital signals.

[0117] Optionally, since the signal input into the voltage domain conversion module is an analog signal, if a low-voltage transistor is used in the voltage domain conversion module, the voltage domain conversion module will not be able to operate normally. Therefore, the first conversion transistor and the second conversion transistor in this embodiment are high-voltage transistors.

[0118] In some optional embodiments, within an exposure cycle, the voltage signal output by the photodiode starts to decrease from the reset signal. When it decreases to a preset threshold, the voltage signal is sorted and converted from analog to digital through a first inverter and a second inverter connected in series to obtain a low-voltage first digital signal. The level of the first digital signal is consistent with the voltage signal. When the voltage signal is a high-level analog signal, the first digital signal is a high-level digital signal; when the voltage signal is a low-level analog signal, the first digital signal is a low-level digital signal.

[0119] Figure 5 FIG. 1 is a circuit structure diagram of a digital voltage domain module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 5 As shown, the digital voltage domain module 13 includes: a pulse output transistor 131 , an enable transistor 132 , a request transistor 133 and a pulse latch unit 134 .

[0120] The drain terminal of the pulse output transistor 131 is connected to the voltage domain conversion module 12, the gate terminal of the request transistor 133 and the pulse latch unit 134, the gate terminal is connected to the enable signal Ack, and the source terminal serves as the third output terminal, outputting the first digital signal Vspi according to the control of the enable signal Ack.

[0121] Optionally, this embodiment determines whether to output the first digital signal Vspi by the conduction condition of the pulse output transistor 131. Only when the high-level enable signal Ack is received, the pulse output transistor 131 is controlled to be turned on, so that the third output terminal is connected to the output terminal of the second inverter, so as to output the first digital signal through the third output terminal. Before receiving the enable signal Ack, the pulse output transistor 131 is in a normally off state and cannot output the first digital signal.

[0122] The drain terminal of the enable transistor 132 is connected to the digital power signal DVDD, the source terminal is connected to the source terminal of the request transistor 133, and the gate terminal is connected to the pulse latch unit 134. In response to the second digital signal latched by the pulse latch unit 134 being at a high level, the enable transistor 132 is turned on.

[0123] The source terminal of the request transistor 133 is connected to the source terminal of the enable transistor 132, the gate terminal is connected to the voltage domain conversion module 12, and the drain terminal serves as the fourth output terminal; in response to the first digital signal being at a low level and the enable transistor 132 being turned on, the read request signal Req is output through the fourth output terminal.

[0124] In this embodiment, the connection path from the digital power supply signal DVDD to the fourth output terminal is formed by the enable transistor 132 and the request transistor 133. Only when the enable transistor 132 and the request transistor 133 are turned on at the same time, the high-level read request signal Req is output from the fourth output terminal; wherein, whether the enable transistor 132 is turned on is determined by the second digital signal latched by the pulse latch unit 134, and whether the request transistor 133 is turned on is determined by the first digital signal obtained by processing the voltage signal. Optionally, both the enable transistor 132 and the request transistor 133 are P-type transistors, that is, they are turned on when the signal input to the gate terminal is at a low level. The external circuit feeds back a high-level enable signal Ack according to the high-level read request signal Req, and the pulse output transistor 131 is turned on by the enable signal Ack. At this time, the first digital signal Vspi is output through the third output terminal.

[0125] The pulse latch unit 134 is used to latch the second digital signal according to the control of the digital reset signal, and turn on the enable transistor 132 in response to the second digital signal being at a high level; and turn off the enable transistor 132 in response to receiving an over-enabling signal within an exposure cycle.

[0126] The present embodiment controls the pulse latch unit to output only one first digital signal asynchronously in one exposure cycle. Once the permission signal is received in one exposure cycle, the enable transistor 132 is disconnected by controlling the pulse latch unit 134, that is, the read request signal cannot be issued. The embodiment provided by the present embodiment controls the pulse latch unit to make the pixel unit output only one first digital signal asynchronously in one exposure cycle, thereby reducing the frequency difference between the synchronous output and the asynchronous output in the pixel unit, and avoiding the problem of redundant information in the strong light part due to excessive number of asynchronous reading output signals in the case of strong light intensity.

[0127] Figure 6 FIG. 1 is a circuit structure diagram of a digital voltage domain module in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure. Figure 6 As shown, the pulse latch unit 134 includes: a second reset transistor 1341, a third inverter 1342, a trigger termination transistor 1343 and a request enabling transistor 1344;

[0128] The source terminal of the second reset transistor 1341 is connected to the digital power signal DVDD, the drain terminal is connected to the source terminal of the trigger termination transistor 1343 and the source terminal of the request enable transistor 1344 as a latch point, and the gate terminal receives the digital reset signal DRST.

[0129] The source terminal of the request enabling transistor 1344 is connected to the latch point, the drain terminal is connected to the voltage domain conversion module 12, and the gate terminal receives the enabling signal Ack; the first digital signal is written into the latch point according to the control of the enabling signal.

[0130] In response to the enable signal received from the external circuit being at a high level, the request enable transistor 1344 is turned on. At this time, the first digital signal is written to the latch point. When the first digital signal is at a low level, the second digital signal latched by the latch point is changed to a low voltage. After being processed by the third inverter, the enable transistor 132 is disconnected, that is, a read request signal cannot be issued, thereby achieving the technical effect that asynchronous reading can no longer be performed after receiving the enable signal.

[0131] The input end of the third inverter 1342 is connected to the latch point, and the output end is connected to the gate end of the enable transistor 132, which is used to reversely process the second digital signal latched by the latch point and input it into the gate end of the enable transistor 132 to control whether the enable transistor 132 is turned on.

[0132] The trigger termination transistor 1343 is connected in parallel with the third inverter 1342 via a source terminal and a gate terminal, and a drain terminal is grounded, so as to ground the latch point when the output of the third inverter 1342 is at a high level.

[0133] The trigger termination transistor 1343 provided in this embodiment, when turned on, grounds the latch point, so that the signal at the latch point always remains in a low voltage state. The low level of the latch point is processed by the third inverter to be a high level. The high level signal input triggers the gate end of the termination transistor 1343, so that the trigger termination transistor 1343 remains turned on, forming a cycle in which the second digital signal of the latch point remains at a low level. Correspondingly, the enabling transistor remains in a disconnected state. Before the second reset transistor 1341 (next exposure cycle) receives the next digital reset signal, the digital voltage domain module can no longer issue a read request signal, that is, only one first data signal can be issued within one exposure cycle.

[0134] Optionally, the third inverter 1342 may include: a first latch transistor and a second latch transistor;

[0135] The gate terminal of the first latch transistor is connected to the gate terminal of the second latch transistor as the input terminal of the third inverter, the source terminal of the first latch transistor is connected to the drain terminal of the second latch transistor as the output terminal of the third inverter, the drain terminal of the first latch transistor is connected to the digital power signal DVDD, and the source terminal of the second latch transistor is grounded.

[0136] Optionally, the first latch transistor is a P-type transistor, and the drain terminal of the first latch transistor is connected to the digital power signal DVDD; the second latch transistor is an N-type transistor, and the source terminal of the second latch transistor is grounded; therefore, when the second digital signal output at the latch point is low level, the first latch transistor is turned on, and the third inverter outputs a high level digital power signal, and the enable transistor is an N-type transistor, and when the gate terminal of the enable transistor receives a high level signal, the enable transistor is turned off; and when the second digital signal output at the latch point is high level, the second latch transistor is turned on, and the third inverter outputs a low level signal, even if the gate terminal of the enable transistor is grounded, at this time, the enable transistor is turned on.

[0137] In the embodiment provided by the present disclosure, the high-voltage transistor has a thick gate oxide layer and can withstand a higher analog domain voltage. However, due to the thick gate oxide layer, the high-voltage transistor has a larger area, and the current and power consumption are also larger. Therefore, in order to reduce the area and power consumption of the pixel unit, the pulse output transistor, the enable transistor, the request transistor, the second reset transistor, the trigger termination transistor, the request permission transistor, and the two transistors (the first latch transistor and the second latch transistor) included in the digital voltage domain module in this embodiment are all low-voltage transistors; the gate oxide layer of the low-voltage transistor is thinner and can only withstand a lower digital domain voltage, and its area, current and power consumption are smaller, and the voltage flip speed is faster. By using low-voltage transistors in the digital voltage domain module, the area and power consumption of the pixel unit are effectively reduced.

[0138] Figure 7 1 is a schematic diagram of a circuit structure of a sensor pixel unit provided by an optional exemplary embodiment of the present disclosure, and shows a specific structure of an analog voltage domain module 11, a voltage domain conversion module 12 and a digital voltage domain module 13 in the pixel unit.

[0139] The analog voltage domain module 11 includes: a photodiode 111 , a first reset transistor 112 , a source follower transistor 1131 and a readout transistor 1132 , as well as a first inverter 1141 (including a first positive feedback transistor and a second positive feedback transistor) and a pull-down transistor 1142 .

[0140] The voltage domain conversion module 12 includes: a second inverter composed of a first conversion transistor 121 and a second conversion transistor 122 .

[0141] The digital voltage domain module 13 includes: a pulse output transistor 131, an enable transistor 132, a request transistor 133 and a pulse latch unit 134. The pulse latch unit 134 includes: a second reset transistor 1341, a third inverter 1342 (a first latch transistor and a second latch transistor), a trigger termination transistor 1343 and a request enable transistor 1344.

[0142] The connection relationship of the various components in this embodiment can refer to the description and drawings of the above embodiments.

[0143] Optionally, in an exposure cycle of the pixel unit: first enter the reset phase, in which a low-level analog reset signal ARST and a digital reset signal DRST are provided to the pixel unit through an external circuit, so that the first reset transistor and the second reset transistor are turned on, the voltage signal Vpd corresponding to the photodiode is reset to the analog power signal AVDD, and the second digital signal Req_EN corresponding to the latch point is reset to the digital power signal DVDD. After the reset is completed, the timing of the analog reset signal ARST and the digital reset signal DRST are pulled to a high level (for example, AVDD and DVDD), the first reset transistor and the second reset transistor are turned off, and the exposure phase is entered.

[0144] In the exposure phase, the photodiode converts the light signal into photogenerated charge, and the voltage signal Vpd decreases as the photogenerated charge accumulates. The stronger the light signal received by the pixel unit, the faster the rate of accumulation of the photogenerated charge. When the light intensity exceeds a certain range, Vpd will drop to a specific threshold (preset threshold) before the end of exposure. When this specific threshold is reached, the first positive feedback transistor is turned on, so that the voltage output by the first inverter gradually rises, and then the pull-down transistor is turned on. After the pull-down transistor is turned on, the voltage signal is accelerated to drop, which in turn promotes the conduction of the first positive feedback transistor, thereby forming positive feedback, accelerating the voltage signal Vpd to 0 level, and the first analog signal output by the first inverter is pulled to AVDD. The high-level first analog signal is input to the voltage domain conversion module, turning on the second conversion transistor 122, so that the first digital signal output by the second inverter is low level, and the low-level first digital signal is input to the request transistor to turn on the request transistor. Since the previous reset process has reset the second digital signal Req_EN to a high level, the enabling transistor is always in the on state. Therefore, when Vpd drops to the preset threshold, the pixel unit will pull the read request signal Req to DVDD and send the high-level read request signal Req to the external circuit. Since the actual read time of each pixel unit in the asynchronous read process is uncertain, and there are multiple pixel units (a row of pixel units in the pixel array) sharing a signal output line, an external circuit is required to confirm the read request signal of the pixel unit, and the external circuit determines the priority of the current output, and confirms the output of the pixel unit corresponding to the read request signal with the highest priority. Therefore, after the pixel unit outputs the high-level Req signal, it is necessary to wait until the external circuit sends a high-level enable signal Ack to the pixel unit, and the pulse output transistor will be turned on, so that the first digital signal Req_N is output through the third output terminal. At the same time as the signal is output, the request permission transistor will also be turned on because the permission signal Ack rises to a high level; for the pixel unit that issues a request and receives a permission signal, after the request permission transistor is turned on, the second digital signal Req_EN will be pulled to a low level, thereby disconnecting the enable transistor, and because the second digital signal is at a low level, it will trigger the termination transistor to turn on, so that the second digital signal is always locked at a low level, and then the pixel unit cannot issue a request signal again until the reset phase of the next exposure cycle arrives. When the exposure time is over, the pixel unit performs a synchronous readout, at which time the external circuit provides the pixel unit with a high-level readout signal Read, turning on the readout transistor, and accumulating the voltage signal Vpd corresponding to the photogenerated charge of the complete exposure cycle. The signal is read out through the source follower transistor and the readout transistor, and the second analog signal Vout is output through the second output terminal. After the synchronous readout is completed, a complete exposure cycle is completed, and the next exposure cycle is cycled to continuously image.

[0145] Figure 8 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure. Figure 8 As shown, the signal processing circuit provided in this embodiment includes: a pixel array 81 composed of n rows and m columns of sensor pixel units 811 (hereinafter referred to as pixel units) provided in any one of the above embodiments, a row drive control module 82, a row arbitration module 83 and a column readout module 84; n and m are integers greater than or equal to 1 respectively.

[0146] The row drive control module 82 is used to provide analog reset signals, digital reset signals and readout signals to the sensor pixel units 811 in the pixel array 81 row by row.

[0147] In this embodiment, the row drive control module 82 provides the analog reset signal ARST, the digital reset signal DRST and the readout signal Read of the corresponding period for each row of sensor pixel units 811 in the pixel array row by row according to the exposure period. Usually, the analog reset signal ARST and the digital reset signal DRST are given a low level at the beginning of the exposure period (high level at other times), and the readout signal Read is given a high level at the end of the exposure period (low level at other times).

[0148] The pixel array 81 is used to perform reset according to the analog reset signal and the digital reset signal. During the exposure period, in response to the first analog signal reaching a preset threshold, a read request signal is sent to the row arbitration module 83, and a first digital signal is sent to the column readout module 84 under the control of the enable signal fed back by the row arbitration module 83; when the exposure period is reached, a second analog signal is sent to the column readout module through the control of the transfer signal and the readout signal.

[0149] The first digital signal is determined based on the first analog signal. Optionally, the first analog signal voltage domain conversion module processes the first analog signal to obtain a sorted first digital signal.

[0150] Optionally, the sensor pixel units 811 in the pixel array output the first digital signal and the second analog signal row by row according to the control of the row drive control module 82 .

[0151] The row arbitration module 83 is used to receive a read request signal Req sent by at least one row of sensor pixel units 811 in the pixel array 81, and feed back an enable signal Ack to at least one row of sensor pixel units according to the time sequence of receiving the read request signal.

[0152] In this embodiment, the row arbitration module 83 receives a read request signal issued by a row of sensor pixel units 811 each time. When the number of read request signals received exceeds one, the multiple read request signals Req can be sorted according to the receiving time, and the multiple read request signals can be processed in sequence, with the read request signal received first being processed first.

[0153] The column readout module 84 is used to receive the first digital signal and the second analog signal sent by at least one column of sensor pixel units 811 .

[0154] Optionally, the column readout module receives, by column, the first digital signal and the second analog signal sent by the sensor pixel unit 811. The column readout module in this embodiment implements synchronous reading and asynchronous reading of the sensor pixel unit, and achieves the beneficial effects of synchronous reading and asynchronous reading.

[0155] The circuit structures of the row drive control module 82, the row arbitration module 83 and the column readout module 84 involved in this embodiment can all adopt the commonly used circuit structures in the prior art. The present disclosure does not limit the specific circuit structures of the row drive control module 82, the row arbitration module 83 and the column readout module 84.

[0156] Fig. 9 FIG. 1 is a circuit structure diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure. Fig. 9 As shown, the signal processing circuit provided in this embodiment further includes: a row address encoder 85 and a clock module 86;

[0157] When the row arbitration module 83 feeds back an enabling signal to a row of sensor pixel units 811 , the row address encoder 85 encodes the row information of the sensor pixel units 811 receiving the enabling signal into a row address Row addr.

[0158] In this embodiment, the circuit structure of the row address encoder can be any circuit structure that can implement address encoding in the prior art, and the encoding method can be any encoding method in the prior art. The encoded row address indicates the row where the pixel unit outputting the first digital signal is located.

[0159] The clock module 86 is used to record the time information Timestamp when the row address encoder 85 generates the row address, and associate the time information with the row address.

[0160] In this embodiment, the clock module may be any module in the prior art that can provide time information, and the time information is associated with the row address, that is, each row address corresponds to unique time information, so as to distinguish different row addresses.

[0161] like Fig. 9As shown, the column readout module 84 includes: m analog-to-digital converters 841 , m column buffers 842 and a column address encoder 843 .

[0162] Each analog-to-digital converter 841 corresponds to a column of sensor pixel units 811 , each column buffer 842 corresponds to a column of sensor pixel units 811 ; and each analog-to-digital converter 841 corresponds to a column buffer 842 .

[0163] The column buffer 842 is used to store the first digital signal Vspi output by the sensor pixel unit 811 of the corresponding column, and transmit the first digital signal to the column address encoder 843 .

[0164] Since the first digital signal output by the sensor pixel unit 811 in this embodiment is read asynchronously, the output time is not when the exposure period is reached, and different sensor pixel units output the first digital signal at different times. Therefore, after receiving the first digital signal, the first digital signal is stored by the column buffer 842.

[0165] The column address encoder 843 is used to receive the first digital signal output by the column buffer 842, encode the column information corresponding to the first digital signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the first digital signal.

[0166] After receiving and storing the first digital signal, since the column readout module reads out a corresponding column of pixel units each time, when the first digital signal is obtained, only the column address corresponding to the first digital signal can be determined. At this time, in order to determine the specific position of the pixel unit corresponding to the first digital signal, and then determine the light intensity of the pixel unit at the specific position, this embodiment associates the time information of the first digital signal with the row address and its corresponding time information based on time, and associates the row address and column address of the same time information (moment) to obtain the specific position of the pixel unit corresponding to the first digital signal corresponding to the time information (the row address and the column address determine the unique position). Based on the position and time corresponding to the first digital signal, the light intensity corresponding to each pixel unit in the pixel array can be determined. Optionally, the shorter the time information of the output first digital signal is relative to the reset time interval, the greater the light intensity corresponding to the position.

[0167] The analog-to-digital converter 841 is used to receive the second analog signal Vout output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second analog signals Vout, and perform analog-to-digital conversion on the differential operation result to obtain a third digital signal.

[0168] The second analog signal in this embodiment is a signal associated with the voltage signal output by the photodiode, and is correlated with the voltage signal reflecting the amount of photogenerated charge accumulated by the photodiode. It can be understood that the second analog signal is equal to the voltage signal, which can determine the voltage difference between the photodiode before and after the photodiode receives light to generate photogenerated charge during the exposure period, that is, determine the amount of photogenerated charge generated by the photodiode according to the received light. Therefore, this embodiment performs differential operations and analog-to-digital conversion on the two second analog signals in the analog-to-digital converter to determine the third digital signal that is output synchronously.

[0169] like Fig. 9 As shown, the signal processing circuit provided in this embodiment further includes: a conversion interface circuit 87.

[0170] The conversion interface circuit 87 is used to receive the signal output by the column readout module 84 .

[0171] In this embodiment, after the signal processing circuit obtains the first digital signal and the third digital signal, in order to facilitate other devices or circuits to process and / or use the first digital signal and the third digital signal, this embodiment receives the signal output by the column readout module through a conversion interface circuit and provides an interface to connect with an external circuit or device.

[0172] The signal processing circuit provided by the embodiment of the present disclosure first enters the reset stage during operation, and a low-level analog reset signal ARST and a digital reset signal DRST are given through the row drive control module. The photogenerated charge on the photodiode in the pixel unit is cleared through ARST control, and the second digital signal Req_EN in the pulse latch unit in the pixel unit is reset to a high level through DRST. After the reset is completed, the exposure stage is entered, and the photodiode begins to be exposed and accumulates photogenerated charge. During the exposure period, the light intensity received by different pixel units is different. The pixel unit that receives stronger light reaches the preset threshold during the exposure period. The voltage signal generated by the photodiode is low, which triggers the asynchronous output. The pixel unit that triggers the asynchronous output first enters the trigger request stage, and the first analog signal is input to the voltage domain conversion module to obtain the processed first digital signal to turn on the request transistor. At this time, since the second digital signal is high, the enable transistor is also turned on. Therefore, at this time, the drain end of the request transistor pulls the read request signal Req of the row to a high level, and sends a read request signal Req to the row arbitration circuit. The row arbitration module determines the priority of the row where the pixel unit currently sending the request is located, and sends an enable signal Ack to the row pixel unit with the highest priority. The priority is determined by the arrival time of the read request signal Req, and the signal that arrives first is fed back as the enable signal first. The first digital signal Vspi of a row of pixel units that are allowed to output is input to the column buffer. The row address encoder, column address encoder and clock module record and read out the current time, the currently allowed row address, and the column address of all pixel units in the row that reach the preset threshold, and determine the specific address of the asynchronously read pixel unit. After the exposure time (exposure cycle) ends, the pixel unit enters the synchronous readout stage. First, the second photodiode is reset, and the second analog signal Vout at this time is read out to the analog-to-digital converter. After all signals are read out, a frame cycle is completed. In this way, continuous imaging can be achieved.

[0173] The signal processing circuit provided in the embodiment of the present disclosure can be integrated in one or more chips. In an optional example, the signal processing circuit is integrated in one chip. The chip mainly includes a pixel array 81, a row drive control module 82, a row arbitration module 83, a row address encoder 85, a column readout module 84, a clock module 86 and a conversion interface circuit 87. The row drive control module 82, the row arbitration module 83, the row address encoder 85, the column readout module 84, the clock module 86 and the conversion interface circuit 87 are all prior art, so the detailed implementation method thereof is not described in detail in this embodiment, and only the logical functions undertaken by the same in the present disclosure are described. Among them, the pixel array is composed of the pixel units provided in the above embodiment of n rows and m columns. The row drive control module is used to output the analog reset signal ARST, the digital reset signal DRST and the signal timing of the readout signal Read of all row pixel units. The row arbitration module is used to receive the read request signal Req output by all row pixel units, and output the enable signal Ack to the row pixel unit with the highest current output priority. All row enable signals Ack are simultaneously output to the row address encoder, which encodes the specific position of the currently enabled row pixel unit into a row address (Row addr) and outputs it, and at the same time controls the clock module to output the current time (Timestamp). The column readout module mainly includes m column-level analog-to-digital converters (ADCs), mbit column buffers, and column address encoders. When the Read signal of a row of pixel units is high (outputting the second analog signal), the row of pixel units outputs the second analog signal Vout to the analog-to-digital converter of the corresponding column for analog-to-digital conversion. When a row of pixel units receives an enable signal (high level), the first digital signal Vspi (pulse signal) of the row of pixel units will be input to the corresponding column buffer. The column address encoder performs address encoding on the position of the first digital signal in the column buffer and outputs it to the conversion interface circuit. The analog-to-digital converter outputs the result to the conversion interface circuit after completing the analog-to-digital conversion each time. For weak light signals, the digital signal converted from the accumulated photogenerated charge signal within an exposure cycle can reflect the specific light intensity; for strong light signals, the moment when the photogenerated charge signal accumulates to the threshold can reflect the specific light intensity.

[0174] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0175] Memory for storing computer programs;

[0176] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the sensor pixel unit or the signal processing circuit described in any of the above embodiments of the present disclosure is implemented.

[0177] The electronic device provided by the present disclosure can be included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0178] The electronic device provided by the present disclosure can be applied to any of the following: image data acquisition equipment, audio / video players, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0179] Fig.10 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Fig.10 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0180] like Fig.10 As shown, the electronic device includes one or more processors and memory.

[0181] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0182] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the sensor pixel unit or signal processing circuit of each embodiment of the present disclosure described above and / or other desired functions.

[0183] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0184] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0185] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0186] Of course, to simplify, Fig.10 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0187] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the sensor pixel unit or signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0188] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0189] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the sensor pixel unit or signal processing circuit according to various embodiments of the present disclosure described in the above part of this specification.

[0190] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0191] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0192] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0193] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0194] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0195] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0196] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0197] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A sensor pixel unit, characterized in that: include: Analog voltage domain module, voltage domain conversion module, digital voltage domain module; The analog voltage domain module is used to receive the light signal within the exposure time to generate a voltage signal, and in response to the voltage signal reaching a preset threshold, send the first analog signal to the voltage domain conversion module through the first output terminal; and output the second analog signal through the second output terminal when the exposure period is reached; The voltage domain conversion module is used to convert the first analog signal into a first digital signal, and input the first digital signal into the digital voltage domain module; The digital voltage domain module is used to send a read request signal and output the first digital signal according to the received permission signal.

2. The pixel unit according to claim 1, characterized in that: The analog voltage domain module includes: a photodiode, a first reset transistor, an auxiliary circuit and a positive feedback unit; The photodiode is used to receive the light signal within the exposure time to generate the voltage signal, and in response to the voltage signal reaching a preset threshold value during the exposure period, output the voltage signal to the positive feedback unit, and in response to reaching the exposure period, output the voltage signal to the auxiliary circuit; The first reset transistor is used to control the photodiode to perform reset according to the analog reset signal; The auxiliary circuit is used for controlling the second output terminal to output the second analog signal according to the received voltage signal when the exposure period is reached; The positive feedback unit is used to convert the voltage signal into the first analog signal, and output the first analog signal to the voltage domain conversion module.

3. The pixel unit according to claim 2, characterized in that: The positive feedback unit includes a first inverter and a pull-down transistor; The pull-down transistor is connected in parallel with the input terminal and the output terminal of the first inverter via the drain terminal and the gate terminal, and the source terminal of the pull-down transistor is grounded; The first inverter arranges the input voltage signal into an analog power signal, and inputs the analog power signal into the voltage domain conversion module based on the output terminal of the first inverter as the first output terminal.

4. The pixel unit according to claim 3, characterized in that: The auxiliary circuit includes a source follower transistor and a readout transistor; One end of the photodiode is grounded, and the other end is connected to the drain end of the reset transistor, the gate end of the source follower transistor and the positive feedback unit; The source terminal of the reset transistor is connected to the analog power supply signal, the drain terminal is connected to the other end of the photodiode, and the gate terminal receives the analog reset signal; The source terminal of the source follower transistor is connected to the analog power supply signal, the gate terminal is connected to the other end of the photodiode, the drain terminal of the reset transistor and the positive feedback unit, and the drain terminal is connected to the drain terminal of the readout transistor; The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the gate terminal receives a readout signal, and the source terminal serves as a second output terminal.

5. The pixel unit according to claim 4, characterized in that: The first reset transistor, the pull-down transistor, the source follower transistor, the readout transistor, and two transistors included in the first inverter are high-voltage transistors.

6. The pixel unit according to any one of claims 1 to 5, characterized in that: The voltage domain conversion module includes: a second inverter composed of a first conversion transistor and a second conversion transistor; The gate terminal of the first conversion transistor is connected to the gate terminal of the second conversion transistor as the input terminal of the second inverter, and the drain terminal of the first conversion transistor is connected to the source terminal of the second conversion transistor as the output terminal of the second inverter; the source terminal of the first conversion transistor is connected to a digital power supply signal, and the drain terminal of the second conversion transistor is grounded.

7. The pixel unit according to claim 6, characterized in that: The first switching transistor and the second switching transistor are high voltage transistors.

8. The pixel unit according to any one of claims 1 to 7, characterized in that: The digital voltage domain module includes: a pulse output transistor, an enable transistor, a request transistor and a pulse latch unit; The drain terminal of the pulse output transistor is connected to the voltage domain conversion module, the gate terminal of the request transistor and the pulse latch unit, the gate terminal is connected to the enable signal, and the source terminal serves as a third output terminal, and outputs the first digital signal according to the control of the enable signal; The drain terminal of the enabling transistor is connected to the digital power signal, the source terminal is connected to the source terminal of the request transistor, and the gate terminal is connected to the pulse latch unit. In response to the second digital signal latched by the pulse latch unit being at a high level, the enabling transistor is turned on; The source terminal of the request transistor is connected to the source terminal of the enable transistor, the gate terminal is connected to the voltage domain conversion module, and the drain terminal serves as a fourth output terminal; in response to the first digital signal being at a low level and the enable transistor being turned on, a read request signal is output through the fourth output terminal; The pulse latch unit is used to latch the second digital signal according to the control of the digital reset signal, and turn on the enable transistor in response to the second digital signal being at a high level; and turn off the enable transistor in response to receiving the enable signal within an exposure cycle.

9. The pixel unit according to claim 8, characterized in that: The pulse latch unit comprises: a second reset transistor, a third inverter, a trigger termination transistor and a request enabling transistor; The source terminal of the second reset transistor is connected to the digital power supply signal, the drain terminal is connected to the source terminal of the trigger termination transistor and the source terminal of the request permission transistor as a latch point, and the gate terminal receives the digital reset signal; The source terminal of the request permission transistor is connected to the latch point, the drain terminal is connected to the voltage domain conversion module, and the gate terminal receives the permission signal; the first digital signal is written into the latch point according to the control of the permission signal; The input end of the third inverter is connected to the latch point, and the output end is connected to the gate end of the enable transistor, and is used to inversely process the second digital signal latched by the latch point and input it into the gate end of the enable transistor to control whether the enable transistor is turned on; The trigger termination transistor is connected in parallel with the third inverter via a source terminal and a gate terminal, and a drain terminal is grounded, and is used to ground the latch point when the output of the third inverter is at a high level.

10. A signal processing circuit, characterized in that: include: A pixel array consisting of n rows and m columns of sensor pixel units according to any one of claims 1 to 9, a row drive control module, a row arbitration module and a column readout module; n and m are integers greater than or equal to 1 respectively; The row drive control module is used to provide analog reset signals, digital reset signals and readout signals to the sensor pixel units in the pixel array row by row; The pixel array is used to perform a reset according to the analog reset signal and the digital reset signal, send a read request signal to the row arbitration module in response to the first analog signal reaching a preset threshold value during an exposure period, and send a first digital signal to the column readout module under the control of the enable signal fed back by the row arbitration module; when the exposure period is reached, send a second analog signal to the column readout module under the control of the readout signal; the first digital signal is determined based on the first analog signal; The row arbitration module is used to receive the read request signal sent by at least one row of the sensor pixel units in the pixel array, and feed back the permission signal to at least one row of the sensor pixel units according to the time sequence of receiving the read request signal; The column readout module is used to receive the first digital signal and the second analog signal sent by at least one column of the sensor pixel units.

11. The signal processing circuit according to claim 10, characterized in that: Also includes: Row address encoder and clock module; When the row arbitration module feeds back an enabling signal to a row of the sensor pixel units, the row address encoder encodes row information of the sensor pixel units receiving the enabling signal into a row address; The clock module is used to record the time information when the row address encoder generates the row address, and associate the time information with the row address.

12. The signal processing circuit according to claim 11, characterized in that: The column readout module comprises: m analog-to-digital converters, m column buffers and a column address encoder; each of the analog-to-digital converters corresponds to a column of the sensor pixel units, each of the column buffers corresponds to a column of the sensor pixel units; each of the analog-to-digital converters corresponds to one of the column buffers; The column buffer is used to store the first digital signal output by the sensor pixel unit of the corresponding column and transmit the first digital signal to the column address encoder; The column address encoder is used to receive the first digital signal output by the column buffer, encode the column information corresponding to the first digital signal into a column address, and associate the column address with the row address based on the time information to determine the sensor pixel unit corresponding to the first digital signal; The analog-to-digital converter is used to receive the second analog signal output by the sensor pixel unit of the corresponding column, perform a differential operation on two consecutively received second analog signals, and perform analog-to-digital conversion on the differential operation result to obtain a third digital signal.

13. The signal processing circuit according to any one of claims 10 to 12, characterized in that: Also includes: Conversion interface circuit; The conversion interface circuit is used to receive the signal output by the column readout module.

14. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor, further comprising the sensor pixel unit of claims 1-9 or the signal processing circuit of any one of claims 10-13; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

15. The device according to claim 14, characterized in that The electronic device is included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, and security equipment.

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