A system internal timing system based on FPGA and its working method

Abstract

The present disclosure provides a system internal time synchronization system based on FPGA, including host computer software and FPGA unit, the FPGA unit includes an external B code receiving module and a register, a time value extraction module, an internal B code generation module, an internal and external B code switching module, a time information generation module, and a system time synchronization module which are sequentially connected head to tail; the output end of the host computer software is connected to the input end of the register; the output end of the register is respectively connected to the input end of the time value extraction module, the input end of the internal B code generation module, and the input end of the internal and external B code switching module, and the output end of the system time synchronization module is connected to the input end of the host computer software; the output end of the external B code receiving module is connected to the input end of the internal and external B code switching module. The present disclosure can solve the technical problem that the actual test value has a large gap with the theoretical value due to the introduction of measurement errors in the absence of network timing and external unified B code.

Description

Technical Field

[0001] The present disclosure relates to the fields of satellite measurement and control, ground testing, laboratory testing, automatic index testing, and more particularly to an FPGA-based system internal timing system and a working method thereof. Background Art

[0002] Nowadays, satellite testing is based on establishing a satellite-to-ground communication channel between the ground test system and the satellite, and completing various satellite test items through information exchange between the satellite and the ground through the satellite-to-ground communication channel. On the one hand, the ground test system sends ground remote control commands to the satellite through the satellite-to-ground communication channel to set and control the status of the satellite; on the other hand, the ground test system receives telemetry data transmitted from the satellite through the satellite-to-ground communication channel to obtain the current health status of the satellite, receive digital data transmitted from the satellite, and analyze the operating status and results of the satellite payload. In the process of satellite ground testing, it is extremely important to meet the requirements of indicators such as the time of data injection accuracy, the command delay of the remote control command, and the command time accuracy.

[0003] Host computer systems are widely used in satellite measurement and control, ground testing, laboratory testing, automatic index testing and other fields. Usually, the host computer system consists of two major parts: host computer software and hardware, mainly including: (A) Host computer software: The host computer software is the core part of the host computer system, responsible for processing, monitoring and controlling the collected raw data. Common host computer software includes Visual Studio, LabView, etc.; (B) Host computer hardware: The host computer hardware usually uses embedded PCs, industrial computers and other devices as the control center of the host computer system; (C) Lower computer equipment: Lower computer equipment refers to the equipment controlled and monitored by the host computer, including PLC, sensors, etc.; (D) Communication interface: Serial ports, Ethernet interfaces, etc. are usually used for data transmission between the host computer and the lower computer equipment.

[0004] The existing methods for unifying local time information in ground test software mostly use a combination of external B code and network timing. However, in laboratory environments or field test environments, network timing and timing equipment that provide external B code cannot be used normally due to the influence of site and external factors, which brings inconvenience to the test process.

[0005] Therefore, it is desired to have a technical solution to overcome or at least alleviate at least one of the above-mentioned defects of the prior art.

[0006] In this regard, there is currently no technical solution on the market to solve the above technical problems. Summary of the invention

[0007] In response to the above technical problems in the related art, the present disclosure proposes an FPGA-based system internal timing system that can screen out products within the required power range and capable of constant power control before installation, which can overcome the above shortcomings of the prior art.

[0008] To achieve the above technical objectives, the technical solution of the present disclosure is implemented as follows:

[0009] The first object of the present disclosure is to provide an internal time calibration system based on FPGA, including a host computer software and an FPGA unit that cooperate with each other, the FPGA unit including an external B code receiving module and a register connected in series, a time value extraction module, an internal B code generating module, an internal and external B code switching module, a time information generating module, and a system time calibration module;

[0010] Among them, the output end of the upper computer software is connected to the input end of the register; the output end of the register is respectively connected to the input end of the time value extraction module, the input end of the internal B code generation module, and the input end of the internal and external B code switching module; the output end of the time value extraction module is connected to the input end of the internal B code generation module, the output end of the internal B code generation module is connected to the input end of the internal and external B code switching module, the output end of the internal and external B code switching module is connected to the input end of the time information generation module, the output end of the time information generation module is connected to the input end of the system timing module, and the output end of the system timing module is connected to the input end of the upper computer software; the output end of the external B code receiving module is connected to the input end of the internal and external B code switching module;

[0011] Host computer software: Initialize the host computer, set system parameters, and transfer system parameters to registers; transfer time calibration signals, B code selection signals, and software local time information to registers; receive and analyze the output time of the system time calibration module, and finally calibrate the local time of the host computer system based on the analysis results;

[0012] Register: Receive and temporarily store system parameters, time calibration signals, software local time information, and B code selection signals transmitted by the host computer software, transmit system parameters, time calibration signals, and software local time information to the time value extraction module, pass system parameters to the internal B code generation module, and transmit B code selection signals to the internal and external B code switching module;

[0013] Time value extraction module: firstly, it receives system parameters, time calibration signal and software local time information from registers, then calibrates itself through time calibration signal, converts software local time information into 32-bit time code information according to system parameters, and then transmits time code information and time calibration signal to internal B code generation module, thus ensuring the synchronization of time code information and time calibration signal; among them, time code information includes day, hour, minute and second information, day occupies 10 bits, hour occupies 6 bits, minute occupies 7 bits, second occupies 6 bits, and the remaining bits are set to 0, such as Figure 2 As shown;

[0014] Internal B code generation module: firstly, it receives the synchronized time coding information and time calibration signal from the time value extraction module, then performs time calibration on itself through the time calibration signal, converts the time coding information into internal B code in the form of serial code elements, and transmits it to the internal and external B code switching module, thereby ensuring the synchronization of the internal B code with the local time information of the software;

[0015] External B code receiving module: receives external B code and transmits it to the internal and external B code switching module. The external B code is also in the form of serial code elements.

[0016] Internal and external B code switching module: receives internal B code and external B code from internal B code generation module and external B code receiving module respectively, reads B code selection signal from register, selects internal B code and external B code according to B code selection signal, and transmits the selection result as result B code to time information generation module;

[0017] Time information generation module: The result B code received from the internal and external B code switching module is processed into 48-bit time information and transmitted to the system time calibration module; in the 48-bit time information, the upper 32 bits store the accumulated millisecond information converted from the hour, minute, second, and millisecond of the day, and the lower 16 bits store the microsecond information of the day, such as Figure 3 As shown;

[0018] System timing module: The 48-bit time information received from the time information generation module is forwarded to the host computer software as its output time. The host computer software then receives and parses it, and uses the parsed result to calibrate the local time of the host computer system. The 48-bit time information is the same as the output time, thereby ensuring that the entire host computer system and FPGA unit share the same result B code.

[0019] This disclosure mainly solves the time calibration work of the host computer system. When implemented, the time coding information can refer to Figure 2 , 48-bit time information can be found at Figure 3 .like Figure 2As shown, the hours, minutes, and seconds in the time coding information are set in pairs, and the remaining bits set to 0 can play an interval role, which is more convenient for reading, processing, parsing, etc. As for system parameters, time calibration signals, B code selection signals, and software local time information, they can all be implemented with reference to the existing technology. How the time value extraction module and the internal B code generation module perform self-time calibration through the time calibration signal belongs to the existing technology. The host computer software, registers, time value extraction module, internal B code generation module, internal and external B code switching module, time information generation module, and system time calibration module constitute a connection circle for time calibration operations.

[0020] Preferably, both the internal B code and the external B code are in IRIG-B code format. The IRIG-B format is an internationally used B code format, which is the IRIG-B time synchronization code standard defined by the InterRange Instrumentation Group (IRIG) of the United States, and is common knowledge. The serial code element form of the internal B code and the external B code is common knowledge or prior art in the art.

[0021] Preferably, the upper computer software sets the system parameters according to the parameters of the designated user, and the parameters of the designated user include frame length, frame format, data rate, etc. The system parameters are prior art.

[0022] Preferably, the host computer software transfers data to the register via DMA (Direct Memory Access).

[0023] Preferably, during the analysis of the output time or 48-bit time information by the host computer software, the accumulated millisecond information stored in the output time or 48-bit time information is used to calculate the hour, minute, second and millisecond corresponding to the day, such as Figure 4 As shown; the host computer software also parses the microseconds corresponding to the day by outputting the time or the microsecond information stored in the 48-bit time information.

[0024] Preferably, the specific process of the external B code receiving module receiving the external B code can be as follows: the external B code is input from the channel board port SMA of the host computer system through TTL, and is converted into a 1.8V single-ended signal by the driver of the host computer system, and then transmitted to the external B code receiving module. TTL, channel board, port SMA, 1.8V signal, and single-ended input signal can all be realized through existing technologies.

[0025] Preferably, the internal and external B code switching module reads the B code selection signal from the register, receives the internal B code from the internal B code generation module, receives the external B code from the external B code receiving module, selects one of the internal B code and the external B code according to the time calibration signal, and transmits the selection result as the result B code to the time information generation module. Subsequently, the time information generation module processes the received result B code into 48-bit time information, and then transmits it to the system time calibration module; the system time calibration module receives the 48-bit time information and transmits it to the host computer software as the output time, and the host computer software receives and analyzes the output time of the system time calibration module, and finally calibrates the local time of the host computer system according to the analysis result, thereby ensuring that the host computer system and the FPGA unit share the same result B code. Among them, the transmission method can be: the result B code is sent to the device backplane of the host computer through the inter-board interconnection line of the host computer, so that all boards and FPGA units in the host computer share the same B code, and then transmitted to the time information generation module.

[0026] The second object of the present disclosure is to provide a working method of an internal timing system of a system based on FPGA, comprising the following steps:

[0027] S1 initialization: The host computer software initializes the host computer, sets system parameters, transfers system parameters to registers, and defines the final calibration time FCT used for time calibration;

[0028] S2 sends signals in a loop: the host computer software continuously sends a dynamically changing time calibration signal, software local time information, and B code selection signal to the register every cycle period T; the software local time information is the local time of the host computer software itself; the time calibration signal is a high-low pulse signal, which is valid when high, and the high level lasts for M;

[0029] S3: Is time calibration allowed? If the time calibration signal is high, the time calibration operation is allowed and S4 is continued. Otherwise, the time calibration operation is not allowed and the waiting time should be continued, so S2 is returned.

[0030] S4: Is there network timing? If the host computer software is using network timing, it means that the network timing method should be used, that is, the current network time is assigned to the final calibration time FCT, and the process directly jumps to S12; otherwise, it means that the system timing method should be used, and the process continues to S5.

[0031] S5 generates time code:

[0032] S5.1: First, the time value extraction module receives the software local time information, system parameters, and time calibration signals from the register;

[0033] S5.2: Then, the time value extraction module performs time calibration on itself through the time calibration signal, and converts the software local time information into time coding information according to the system parameters, thereby ensuring that the time coding information and the time calibration signal remain synchronized;

[0034] S5.3: Finally, the time value extraction module transmits the synchronized time coding information and the time calibration signal to the internal B code generation module;

[0035] S6 generates internal B code:

[0036] S6.1: First, the internal B code generation module receives the time coding information and the time calibration signal transmitted by the time value extraction module;

[0037] S6.2: Then, the internal B code generation module performs time calibration on itself through the time calibration signal;

[0038] S6.3: Finally, the internal B code generation module converts the time code information into an internal B code in the form of a serial code element, and transmits the internal B code to the internal and external B code switching module, so that the internal B code and the software local time information are also synchronized;

[0039] S7 receives external B code: the external B code receiving module receives the external B code and transmits it to the internal and external B code switching module;

[0040] S8 Selected B Code:

[0041] S8.1: First, the internal and external B code switching module receives the internal B code and the external B code from the internal B code generating module and the external B code receiving module respectively;

[0042] S8.2: Then, the internal and external B code switching module reads the B code selection signal from the register;

[0043] S8.3: Finally, the internal and external B code switching module selects one of the internal B code and the external B code according to the B code selection signal, and transmits the selection result as the result B code to the time information generation module;

[0044] S9 analysis result B code: time information generation module, parses and processes the received result B code into 48-bit time information, and then transmits the 48-bit time information to the system time calibration module;

[0045] S10 Time calibration module preparation: The system time calibration module transmits the 48-bit time information received from the time information generation module as its output time to the host computer software;

[0046] S11 parses the output time: the host computer software parses the output time received from the system time calibration module and assigns the parsing result to the final calibration time FCT;

[0047] S12 performs time calibration: the host computer software uses the final calibration time FCT to calibrate the local time of the host computer system, and then returns to S2.

[0048] Preferably, S4 specifically includes the following steps:

[0049] S4.1: Check whether the host computer software is using network timing;

[0050] S4.2: If yes, the network time calibration method should be adopted, that is, the current network time is assigned to the final calibration time, and the process directly jumps to S11; otherwise, it means that the current network time calibration cannot be realized, so the system time calibration method should be adopted, and the process continues to S2.3;

[0051] S4.3: First, the host computer software generates its software local time information;

[0052] S4.4: Then, the host computer software transmits the software local time information to the time value extraction module;

[0053] S4.5: Finally, continue with S5.

[0054] Preferably, the accuracy of the final calibration time FCT is accurate to 1 μs.

[0055] Preferably, the cycle period T depends on actual needs, and is preferably >= 5S.

[0056] Preferably, the high level duration M is shorter than the cycle period T. <T。

[0057] Preferably, M can be determined according to actual needs, and the high level duration M is preferably = 2S.

[0058] Preferably, the host computer software determines which time code should be used according to the on-site test status, thereby generating a B code selection signal.

[0059] Beneficial effects of the present disclosure: The FPGA-based system internal timing system and its working method provided by the present disclosure can ensure the uniformity of the time information of the equipment in the laboratory test and satellite ground simulation test of the measurement and control baseband; in the absence of network timing, it can also ensure the uniformity of the time between the various subsystems of the equipment, ensuring that the test results are accurate and high in precision. The present disclosure can solve the technical problem that the actual test value and the theoretical value are greatly different due to the introduction of measurement errors in the absence of network timing and external unified B code.

[0060] The present disclosure can solve the technical problem in the prior art that the actual test value is far from the theoretical value due to the introduction of measurement errors in the absence of network timing and external unified B code. The present disclosure can ensure the time uniformity between the various subsystems of the equipment, ensure the accuracy of the test results, and have the following advantages:

[0061] (A) Using an FPGA-based method to implement the system internal time calibration method.

[0062] (B). Through the internal and external B code selection module, all boards and FPGAs in the system can share the same B code in a simple and fast manner. This method is simple and easy to operate, and does not require the use of external equipment for time unification, ensuring the accuracy and high precision of the test results.

[0063] (C) It can flexibly adapt to various satellite ground testing requirements for different experiments, tests, joint tests and other application scenarios.

[0064] (D). By adopting modular design, the number of devices in the system can be easily increased when needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0066] Figure 1 The structure block diagram of the internal timing system based on FPGA described in the embodiment of the present invention.

[0067] Figure 2 This is a logical diagram of the composition of the time coding information described in an embodiment of the present invention.

[0068] Figure 3 This is a logical diagram of the composition of the 48-bit time information described in an embodiment of the present invention.

[0069] Figure 4 This is how the host computer software described in the embodiment of the present invention calculates the hour, minute, second, millisecond and other information of the day by accumulating millisecond information.

[0070] Figure 5 FIG. 1 is a schematic diagram of basic code elements of B code in the prior art.

[0071] Figure 6 FIG. 1 is a schematic diagram of a B-code pulse sequence structure of one frame per second in the prior art.

[0072] Figure 7 The present invention is a logical flow chart of the working method of the FPGA-based system internal timing system according to the embodiment of the present invention. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0074] like Figure 1-7 As shown, in order to facilitate the understanding of the above technical solutions of the present disclosure, the above technical solutions of the present disclosure are described in detail below through specific usage methods.

[0075] The first object of the present disclosure is to provide an internal time calibration system based on FPGA, comprising a host computer software 201 and an FPGA unit that cooperate with each other, wherein the FPGA unit comprises an external B code receiving module 205 and a register 202 connected in series, a time value extraction module 203, an internal B code generating module 204, an internal and external B code switching module 206, a time information generating module 207, and a system time calibration module 208;

[0076] Among them, the output end of the host computer software 201 is connected to the input end of the register 202; the output end of the register 202 is respectively connected to the input end of the time value extraction module 203, the input end of the internal B code generation module 204, and the input end of the internal and external B code switching module 206; the output end of the time value extraction module 203 is connected to the input end of the internal B code generation module 204, the output end of the internal B code generation module 204 is connected to the input end of the internal and external B code switching module 206, the output end of the internal and external B code switching module 206 is connected to the input end of the time information generation module 207, the output end of the time information generation module 207 is connected to the input end of the system time calibration module 208, and the output end of the system time calibration module 208 is connected to the input end of the host computer software 201; the output end of the external B code receiving module 205 is connected to the input end of the internal and external B code switching module 206;

[0077] Host computer software 201: Initialize the host computer, set system parameters, and pass system parameters to register 202; pass time calibration signal, B code selection signal and software local time information to register 202; receive and analyze the output time of system time calibration module 208, and finally calibrate the local time of the host computer system according to the analysis result;

[0078] Register 202: receives and temporarily stores system parameters, time calibration signals, software local time information, and B code selection signals transmitted by the host computer software 201, transmits system parameters, time calibration signals, and software local time information to the time value extraction module 203, transmits system parameters to the internal B code generation module 204, and transmits the B code selection signal to the internal and external B code switching module 206;

[0079] The time value extraction module 203 first receives the system parameters, the time calibration signal, and the software local time information from the register 202, then performs time calibration on itself through the time calibration signal, converts the software local time information into a total of 32 bits of time code information according to the system parameters, and then transmits the time code information and the time calibration signal to the internal B code generation module 204, thereby ensuring the synchronization of the time code information and the time calibration signal; wherein the time code information includes day, hour, minute, and second information, where the day occupies 10 bits, the hour occupies 6 bits, the minute occupies 7 bits, and the second occupies 6 bits, and the remaining bits of data are set to 0, such as Figure 2 As shown;

[0080] Internal B code generation module 204: firstly receives the synchronized time code information and time calibration signal from the time value extraction module 203, then performs time calibration on itself through the time calibration signal, converts the time code information into an internal B code in the form of serial code elements, and transmits it to the internal and external B code switching module 206, thereby ensuring the synchronization of the internal B code with the local time information of the software;

[0081] External B code receiving module 205: receives external B code and transmits it to internal / external B code switching module 206. The external B code is also in the form of serial code element.

[0082] Internal and external B code switching module 206: receives internal B code and external B code from internal B code generating module 204 and external B code receiving module 205 respectively, reads B code selection signal from register 202, selects internal B code and external B code according to B code selection signal, and transmits the selection result as result B code to time information generating module 207;

[0083] The time information generation module 207 processes the 48-bit time information received from the time information generation module 206 into 48-bit time information and transmits it to the system time adjustment module 208; in the 48-bit time information, the upper 32 bits store the accumulated millisecond information converted from the hour, minute, second, and millisecond of the day, and the lower 16 bits store the microsecond information of the day, such as Figure 3 As shown;

[0084] System time calibration module 208: forwards the 48-bit time information transmitted by the time information generation module 207 to the host computer software 201 as its output time. The host computer software 201 then receives and parses it, and uses the parsed result to calibrate the local time of the host computer system. The 48-bit time information is the same as the output time, thereby ensuring that the entire host computer system and FPGA unit share the same result B code.

[0085] This disclosure mainly solves the time calibration work of the host computer system. When implemented, the time coding information can refer to Figure 2 , 48-bit time information can be found at Figure 3 .like Figure 2 As shown, the hours, minutes, and seconds in the time coding information are set in pairs, and the remaining bits set to 0 can play an interval role, so that it is easier to read, process, analyze, etc. As for the system parameters, time calibration signal, B code selection signal, and software local time information, they can all be implemented with reference to the existing technology. How the time value extraction module 203 and the internal B code generation module 204 perform self-time calibration through the time calibration signal belongs to the existing technology. The host computer software 201, register 202, time value extraction module 203, internal B code generation module 204, internal and external B code switching module 206, time information generation module 207, and system time calibration module 208 constitute a connection circle for time calibration operations.

[0086] In one embodiment, both the internal B code and the external B code are in IRIG-B code format. The IRIG-B format is an internationally used B code format, which is the IRIG-B time synchronization code standard defined by the InterRange Instrumentation Group (IRIG) of the United States, and is common knowledge. The serial code element form of the internal B code and the external B code is common knowledge or prior art in the art.

[0087] Supplementary introduction to the IRIG-B code format: In the prior art, the IRIG time coding sequence is divided into six coding formats, namely G, A, B, E, H, and D. The most widely used is the IRIG-B code format, referred to as B code. Its outstanding advantage is that the time synchronization signal and time code information such as seconds, minutes, hours, and days are loaded into a signal carrier with a frequency of 1kHz. The B code signal is a time string code with one frame per second. Its basic code elements are "0" code element, "1" code element, and "P" code element. Each code element occupies 10ms of time, and one frame of the string code contains 100 code elements. The pulse widths corresponding to code elements "0" and "1" are 2 ms and 5 ms, respectively. The "P" code element is a position code element with a corresponding pulse width of 8ms. The schematic diagram of the basic code elements of the B code information is shown as follows. Figure 5 shown.

[0088] The schematic diagram of the B-code pulse sequence structure with one frame per second is shown in Figure 6 . Two consecutive "P" code elements indicate the beginning of a whole second. The pulse leading edge of the second "P" code element is the "punctual" reference point, which is defined as "Pr". There is a position code element for every 10 code elements, and there are 10 in total, which are defined as P1, P2, ..., P9, P0. The time sequence of the B code time format is seconds-minutes-hours-days, and the information bits occupied are 7 bits for seconds, 7 bits for minutes, 6 bits for hours, and 10 bits for days, and its position is between P0 and P5. If the code elements are numbered starting from "Pr", and defined as code elements 0, 1, 2, ..., 99, respectively, the "second" information is located at code elements 1, 2, 3, 4, 6, 7, 8, the "minute" information is located at code elements 10, 11, 12, 13, 15, 16, 17, the "hour" information is located at code elements 20, 21, 22, 23, 25, 26, and the "day" information is located at code elements 30, 31, 32, 33, 35, 36, 37, 38, 40, 41. Days, hours, minutes, and seconds are represented by BCD codes, with the ones digit in front and the tens digit in the back. There is an index mark code element with a pulse width of 2ms between the ones and tens digits. For example Figure 6 The B code sequence shown is the time of 14 hours, 8 minutes and 32 seconds on the 191st day of the year. The control function code is between P5 and P8. The SBS time code starts from P8. The SBS time code is a time coding method that directly uses binary second signals to represent the time of a day. There are 17 binary signals in total, which are repeated every day.

[0089] In one embodiment, the host computer software 201 sets the system parameters according to the parameters of the designated user, and the parameters of the designated user include frame length, frame format, data rate, etc. The system parameters are prior art.

[0090] In one embodiment, the host computer software 201 transfers data to the register 202 via DMA (Direct Memory Access).

[0091] In one embodiment, during the analysis of the output time or 48-bit time information by the host computer software 201, the accumulated millisecond information stored in the output time or 48-bit time information is used to calculate the hour, minute, second, and millisecond corresponding to the day, such as Figure 4 As shown; the host computer software 201 also parses the microseconds corresponding to the day by outputting the microsecond information stored in the time or 48-bit time information. Figure 4The 86400000 is the total number of milliseconds in a day, 3600000 is the total number of milliseconds in an hour, 60000 is the total number of milliseconds in a minute, and 1000 is the total number of milliseconds in a second. The remainder is calculated to perform the analysis and settlement.

[0092] In one embodiment, the specific process of the external B code receiving module 205 receiving the external B code can be as follows: the external B code is input from the channel board port SMA of the host computer system through TTL, and is converted into a 1.8V single-ended signal by a driver of the host computer system, and then transmitted to the external B code receiving module 205. TTL, channel board, port SMA, 1.8V signal, and single-ended input signal can all be implemented through existing technologies.

[0093] In a certain embodiment, the internal and external B code switching module 206 reads the B code selection signal from the register 202, receives the internal B code from the internal B code generation module 204, receives the external B code from the external B code receiving module 205, selects one of the internal B code and the external B code according to the time calibration signal, and transmits the selection result as the result B code to the time information generation module 207. Subsequently, the time information generation module 207 processes the received result B code into 48-bit time information, and then transmits it to the system time calibration module 208; the system time calibration module 208 receives the received 48-bit time information and transmits it to the host computer software 201 as the output time. The host computer software 201 receives and analyzes the output time of the system time calibration module 208, and finally calibrates the local time of the host computer system according to the analysis result, thereby ensuring that the host computer system and the FPGA unit share the same result B code. The transmission method may be: the result B code is sent to the device backplane of the host computer through the board interconnection line of the host computer, so that all boards and FPGA units in the host computer share the same B code, and then transmitted to the time information generation module 207.

[0094] The second object of the present disclosure is to provide a working method of an internal timing system of a system based on FPGA, comprising the following steps:

[0095] S1 initialization: the host computer software 201 initializes the host computer, sets system parameters, transfers system parameters to the register 202, and defines the final calibration time FCT used for time calibration;

[0096] S2 cyclically sends signals: the host computer software 201 continuously cycles and sends a dynamically changing time calibration signal, software local time information, and B code selection signal to the register 202 every cycle period T; wherein the software local time information is the local time of the host computer software 201 itself; the time calibration signal is a high-low pulse signal, which is valid when at a high level, and the high level duration is M;

[0097] S3: Is time calibration allowed? If the time calibration signal is high, the time calibration operation is allowed and S4 is continued. Otherwise, the time calibration operation is not allowed and the waiting time should be continued, so S2 is returned.

[0098] S4: Is there network timing? If the host computer software 201 is using network timing, it means that the network timing method should be used, that is, the current network time is assigned to the final calibration time FCT, and the process directly jumps to S12; otherwise, it means that the system timing method should be used, and the process continues to S5;

[0099] S5 generates time code:

[0100] S5.1: First, the time value extraction module 203 receives the software local time information, system parameters, and time calibration signal from the register 202;

[0101] S5.2: Then, the time value extraction module 203 performs time calibration on itself through the time calibration signal, and converts the software local time information into time coding information according to the system parameters, thereby ensuring that the time coding information and the time calibration signal remain synchronized;

[0102] S5.3: Finally, the time value extraction module 203 transmits the time coding information and the time calibration signal for maintaining synchronization to the internal B code generation module 204;

[0103] S6 generates internal B code:

[0104] S6.1: First, the internal B code generation module 204 receives the time coding information and the time calibration signal transmitted by the time value extraction module 203;

[0105] S6.2: Then, the internal B code generation module 204 performs time calibration on itself through the time calibration signal;

[0106] S6.3: Finally, the internal B code generation module 204 converts the time code information into an internal B code in the form of serial code elements, and transmits the internal B code to the internal and external B code switching module 206, so that the internal B code and the software local time information are also synchronized;

[0107] S7: receiving external B code: the external B code receiving module 205 receives the external B code and transmits it to the internal and external B code switching module 206;

[0108] S8 Selected B Code:

[0109] S8.1: First, the internal and external B code switching module 206 receives the internal B code and the external B code from the internal B code generating module 204 and the external B code receiving module 205 respectively;

[0110] S8.2: Then, the internal and external B code switching module 206 reads the B code selection signal from the register 202;

[0111] S8.3: Finally, the internal and external B code switching module 206 selects one of the internal B code and the external B code according to the B code selection signal, and transmits the selection result as the result B code to the time information generation module 207;

[0112] S9: Analyze the result code B: The time information generating module 207 parses and processes the received result code B into 48-bit time information, and then transmits the 48-bit time information to the system time calibration module 208;

[0113] S10 Time calibration module preparation: The system time calibration module 208 transmits the 48-bit time information received from the time information generation module 207 as its output time to the host computer software 201;

[0114] S11 Analyze output time: The host computer software 201 analyzes the output time received from the system time calibration module 208 and assigns the analysis result to the final calibration time FCT;

[0115] S12 performs time calibration: the host computer software 201 uses the final calibration time FCT to calibrate the local time of the host computer system, and then returns to S2.

[0116] In one embodiment, S4 specifically includes the following steps:

[0117] S4.1: Check whether the host computer software 201 is using network timing;

[0118] S4.2: If yes, the network time calibration method should be adopted, that is, the current network time is assigned to the final calibration time, and the process directly jumps to S11; otherwise, it means that the current network time calibration cannot be realized, so the system time calibration method should be adopted, and the process continues to S2.3;

[0119] S4.3: First, the host computer software 201 generates its software local time information;

[0120] S4.4: Then, the host computer software 201 transmits the software local time information to the time value extraction module 203;

[0121] S4.5: Finally, continue with S5.

[0122] In one embodiment, the accuracy of the final calibration time FCT is accurate to 1 μs.

[0123] In one embodiment, the cycle period T depends on actual needs and is preferably >= 5S.

[0124] In one embodiment, the high level duration M is less than the cycle period T. That is, M <T。

[0125] In a certain embodiment, M may be determined according to actual needs, and the high level duration M is preferably = 2S.

[0126] In one embodiment, the host computer software 201 determines which time code should be used according to the field test status, thereby generating a B code selection signal.

[0127] In summary, through the unique design of the present invention, compared with the prior art, (i) the present invention provides an FPGA-based system internal timing system, which solves the problem in the prior art that the virtual channel frame counting is performed after the virtual channel identifier is extracted due to the use of FIFO cache data, thereby causing a huge waste of hardware FPGA resources and increasing the system processing delay; (ii) the present invention adopts a method based on a single-port RAM to realize the virtual channel frame counting under different virtual channel identifiers; (iii) the present invention uses a single-port RAM module to simply and quickly realize the virtual channel frame counting under different virtual channel identifiers. This method has an extremely low FPGA resource occupancy rate and reduces the system processing delay; (iv) the present invention can flexibly adapt to various satellite simulation test requirements for different modulation modes, frame lengths, frame formats and data rates; (v) the present invention adopts a modular design, which can easily increase the number of users when needed.

[0128] The above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An internal timing system based on FPGA, characterized in that: It comprises a host computer software (201) and an FPGA unit that cooperate with each other, wherein the FPGA unit comprises an external B code receiving module (205) and a register (202) connected in series, a time value extraction module (203), an internal B code generating module (204), an internal and external B code switching module (206), a time information generating module (207), and a system time calibration module (208); The output end of the host computer software (201) is connected to the input end of the register (202); the output end of the register (202) is respectively connected to the input end of the time value extraction module (203), the input end of the internal B code generation module (204), and the input end of the internal and external B code switching module (206); the output end of the time value extraction module (203) is connected to the input end of the internal B code generation module (204), the output end of the internal B code generation module (204) is connected to the input end of the internal and external B code switching module (206), the output end of the internal and external B code switching module (206) is connected to the input end of the time information generation module (207), the output end of the time information generation module (207) is connected to the input end of the system time calibration module (208), and the output end of the system time calibration module (208) is connected to the input end of the host computer software (201); the output end of the external B code receiving module (205) is connected to the input end of the internal and external B code switching module (206); The host computer software (201) is used to initialize the host computer, set system parameters, and transfer the system parameters to the register (202); transfer a time calibration signal, a B code selection signal, and software local time information to the register (202); receive and analyze the output time of the system time calibration module (208), and finally calibrate the local time of the host computer system according to the analysis result; Register (202): receiving and temporarily storing the system parameters, time calibration signal, software local time information, and B code selection signal transmitted by the host computer software (201), transmitting the system parameters, time calibration signal, and software local time information to the time value extraction module (203), passing the system parameters to the internal B code generation module (204), and transmitting the B code selection signal to the internal and external B code switching module (206); The time value extraction module (203) first receives the system parameters, the time calibration signal, and the software local time information from the register (202), then performs time calibration on itself through the time calibration signal, converts the software local time information into a total of 32 bits of time code information according to the system parameters, and then transmits the time code information and the time calibration signal to the internal B code generation module (204) to ensure the synchronization of the time code information and the time calibration signal; wherein the time code information includes day, hour, minute, and second information, where the day occupies 10 bits, the hour occupies 6 bits, the minute occupies 7 bits, the second occupies 6 bits, and the remaining bits of data are set to 0; The internal B code generation module (204) first receives the synchronized time code information and time calibration signal from the time value extraction module (203), then performs time calibration on itself through the time calibration signal, converts the time code information into an internal B code in the form of a serial code element, and transmits it to the internal and external B code switching module (206), thereby ensuring that the internal B code is synchronized with the local time information of the software; External B code receiving module (205): receiving external B code and transmitting it to internal and external B code switching module (206), wherein the external B code is also in the form of serial code element; An internal and external B code switching module (206) receives the internal B code and the external B code from the internal B code generating module (204) and the external B code receiving module (205) respectively, reads the B code selection signal from the register (202), selects one of the internal B code and the external B code according to the B code selection signal, and transmits the selection result as the result B code to the time information generating module (207); The time information generating module (207) processes the result B code received from the internal and external B code switching module (206) into 48-bit time information and transmits it to the system time calibration module (208); in the 48-bit time information, the upper 32 bits store the accumulated millisecond information converted from the hour, minute, second and millisecond of the day, and the lower 16 bits store the microsecond information of the day; System time calibration module (208): forwards the 48-bit time information received from the time information generation module (207) as the output time to the host computer software (201), and then the host computer software (201) receives and parses the information and uses the parsed result to calibrate the local time of the host computer system. The 48-bit time information is the same as the output time, thereby ensuring that the entire host computer system and FPGA unit share the same result B code.

2. The FPGA-based internal timing system according to claim 1, characterized in that: The internal B code and the external B code are both in IRIG-B code format.

3. The FPGA-based internal timing system according to claim 1, characterized in that: The upper computer software (201) sets the system parameters according to the parameters of the designated user, wherein the parameters of the designated user include frame length, frame format and data rate.

4. The FPGA-based internal timing system according to claim 1, characterized in that: The host computer software (201) transfers data to the register (202) via DMA.

5. The FPGA-based internal timing system according to claim 1, characterized in that: During the analysis of the output time or the 48-bit time information by the host computer software (201), the hour, minute, second and millisecond corresponding to the day are calculated through the accumulated millisecond information stored in the output time or the 48-bit time information; The host computer software (201) further parses the microseconds corresponding to the current day through the microsecond information stored in the output time or the 48-bit time information.

6. The FPGA-based internal timing system according to claim 1, characterized in that: The specific process of the external B code receiving module (205) receiving the external B code is as follows: the external B code is input from the channel board port SMA of the host computer system through TTL, and is converted into a 1.8V single-ended signal by a driver of the host computer system, and then transmitted to the external B code receiving module (205).

7. The working method of the internal timing system based on FPGA according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1 initialization: the host computer software (201) initializes the host computer, sets the system parameters, transfers the system parameters to the register (202), and defines the final calibration time FCT used for time calibration; S2 cyclically sends signals: the host computer software (201) continuously cycles and sends the dynamically changing time calibration signal, software local time information, and B code selection signal to the register (202) every cycle period T; wherein the software local time information is the local time of the host computer software (201) itself; the time calibration signal is a high-low pulse signal, which is effective when at a high level, and the high level duration is M; S3: Whether time calibration is allowed: If the time calibration signal is at a high level, the time calibration operation is allowed, and S4 is continued; otherwise, the time calibration operation is not allowed, and waiting should be continued, so the process returns to S2; S4: Whether there is network timing: If the host computer software (201) is using network timing, it means that the network timing method should be used, that is, the current network time is assigned to the final calibration time FCT, and the process directly jumps to S12; otherwise, it means that the system timing method should be used, and the process continues to S5; S5 generates time code: S5.1: First, the time value extraction module (203) receives the software local time information, system parameters, and time calibration signal from the register (202); S5.2: Then, the time value extraction module (203) performs time calibration on itself through the time calibration signal, and converts the software local time information into the time coding information according to the system parameters, thereby ensuring that the time coding information and the time calibration signal remain synchronized; S5.3: Finally, the time value extraction module (203) transmits the synchronized time coding information and time calibration signal to the internal B code generation module (204); S6 generates internal B code: S6.1: First, the internal B code generation module (204) receives the time coding information and the time calibration signal transmitted by the time value extraction module (203); S6.2: Then, the internal B code generation module (204) performs time calibration on itself through the time calibration signal; S6.3: Finally, the internal B code generation module (204) converts the time code information into an internal B code in the form of serial code elements, and transmits the internal B code to the internal and external B code switching module (206), so that the internal B code is also synchronized with the software local time information; S7: receiving the external B code: the external B code receiving module (205) receives the external B code and transmits it to the internal and external B code switching module (206); S8 Selected B Code: S8.1: First, the internal and external B code switching module (206) receives the internal B code and the external B code from the internal B code generating module (204) and the external B code receiving module (205) respectively; S8.2: Then, the internal and external B code switching module (206) reads the B code selection signal from the register (202); S8.3: Finally, the internal and external B code switching module (206) selects one of the internal B code and the external B code according to the B code selection signal, and transmits the selection result as the result B code to the time information generation module (207); S9: Parsing result code B: the time information generating module (207) parses and processes the received result code B into the 48-bit time information, and then transmits the 48-bit time information to the system time calibration module (208); S10: Time calibration module preparation: the system time calibration module (208) transmits the 48-bit time information received from the time information generation module (207) as its output time to the host computer software (201); S11: parsing the output time: the host computer software (201) parses the output time received from the system time calibration module (208), and assigns the parsing result to the final calibration time FCT; S12 performs time calibration: the host computer software (201) uses the final calibration time FCT to calibrate the local time of the host computer system, and then returns to S2.

8. The working method according to claim 7, characterized in that The S4 specifically comprises the following steps: S4.1: Check whether the host computer software (201) is using network timing; S4.2: If yes, the network time calibration method should be adopted, that is, the current network time is assigned to the final calibration time, and the process directly jumps to S11; otherwise, it means that the current network time calibration cannot be implemented, so the system time calibration method should be adopted, and the process continues to S2.3; S4.3: First, the host computer software (201) generates its software local time information; S4.4: Then, the host computer software (201) transmits the software local time information to the time value extraction module (203); S4.5: Finally, continue with S5.

9. The working method according to claim 7, characterized in that The accuracy of the final calibration time FCT is accurate to 1 μs; in S2, the cycle period T>=5S, and the high level duration M=2S.

10. The working method according to claim 7, characterized in that The host computer software (201) determines which time code should be used according to the on-site test status, thereby generating the B code selection signal.

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