Display Panel, Electronic Device, and Repair Method of Display Panel

Abstract

The present application discloses a display panel, an electronic device, and a repair method for the display panel. The display panel includes: a substrate; a first electrode group disposed in a first electrode region, including a first power electrode, a second power electrode, and a plurality of data signal electrodes; a bonding pin group is disposed in the bonding region, including a first bonding pin, a second bonding pin, and a plurality of third bonding pins. The first bonding pin is electrically connected to the first power electrode, the second bonding pin is electrically connected to the second power electrode, and the plurality of third bonding pins are electrically connected to the plurality of data signal electrodes one by one. The display panel of the present application can ensure the reliability of display.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel, an electronic device, and a repair method for the display panel. Background Art

[0002] With the continuous development of display technologies, the application scope of display panels has become increasingly wide, and people's requirements for display panels have also become higher and higher. For example, people increasingly focus on display image quality.

[0003] However, the inventors of the present application have found that the display reliability of current display panels needs to be improved, and the manufacturing difficulty needs to be further reduced. Summary of the Invention

[0004] The present application provides a display panel, an electronic device, and a repair method for the display panel, which can not only ensure the display reliability of the display panel, but also reduce the manufacturing difficulty.

[0005] In a first aspect of an embodiment of the present application, a display panel is provided. The display panel includes: a substrate having a first surface and a second surface opposite to each other. Among them, a first electrode region and a bonding region are provided on the second surface, and the first electrode region and the bonding region are spaced along a first direction; a first electrode group disposed in the first electrode region, the first electrode group includes a plurality of first electrodes spaced along a second direction, and the plurality of first electrodes include at least one first power electrode, at least one second power electrode, and a plurality of data signal electrodes. Among them, in the first electrode group, at least one of the first power electrodes is distributed between two of the data signal electrodes, and / or at least one of the second power electrodes is distributed between two of the data signal electrodes, and the second direction intersects the first direction; a bonding pin group, the bonding pin group is provided in the bonding region, the bonding pin group includes a plurality of bonding pins, the plurality of bonding pins include a first bonding pin, a second bonding pin, and a plurality of third bonding pins, the first bonding pin is electrically connected to the first power electrode, the second bonding pin is electrically connected to the second power electrode, and the plurality of third bonding pins are electrically connected to the plurality of data signal electrodes in one-to-one correspondence.

[0006] In a second aspect of an embodiment of the present application, an electronic device is provided, including the display panel in any one of the above, where the number of the display panels is multiple, and the multiple display panels are spliced together.

[0007] In a third aspect of the embodiments of the present application, a method for repairing a display panel is provided. The method is applied to the display panel in any of the above, and the repair method includes: when detecting a short circuit between a first target trace and a second target trace, determining a short circuit point between the first target trace and the second target trace; performing a cutting process on the first target trace on both sides of the short circuit point; wherein, the first target trace and the second target trace are formed on the second surface of the substrate, the number of the first target traces is multiple, and at least part of the first target traces are arranged on different layers from the second target trace and their orthographic projections on the substrate intersect, and the first target trace is electrically connected to the first power electrode and the first bonding pin, or the first target trace is electrically connected to the second power electrode and the second bonding pin.

[0008] The beneficial effect is that in the present application, at least one first power electrode is arranged between two data signal electrodes, and / or at least one second power electrode is arranged between two data signal electrodes, which can avoid the aggregation of the first power electrode, and / or avoid the aggregation of the second power electrode, thereby avoiding a large current density of the first power signal and / or the second power signal in the first electrode group, avoiding problems such as too high local temperature caused by a large local current density, avoiding abnormal display, and ensuring the reliability of the display. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, where:

[0010] Figure 1 is a schematic diagram of the arrangement structure of light-emitting elements on a display panel in the prior art;

[0011] Figure 2 is a schematic diagram of a partial circuit structure for driving light-emitting elements to emit light in the prior art;

[0012] Figure 3 is a schematic diagram of the front structure of an embodiment of the display panel of the present application;

[0013] Figure 4 is Figure 3 the schematic diagram of the back structure of the display panel in

[0014] Figure 5 is a schematic diagram of the back structure of a display panel in the prior art;

[0015] Figure 6Schematic diagram of the structure in the prior art where a light-emitting element is electrically connected to a second electrode group;

[0016] Figure 7 Schematic diagram of the structure in the prior art where display panels are spliced together;

[0017] Figure 8 Schematic diagram of the structure in the present application where a light-emitting element is electrically connected to a second electrode group;

[0018] Figure 9 Schematic diagram of the structure in the present application where display panels are spliced together;

[0019] Figure 10 Schematic diagram of the back surface of a display panel in another embodiment of the present application;

[0020] Figure 11 Schematic diagram of a first electrode group in one embodiment of the present application;

[0021] Figure 12 Schematic diagram of the structure of an electronic device in one embodiment of the present application;

[0022] Figure 13 Is Figure 12 Schematic cross-sectional structure diagram of the electronic device in an application scenario;

[0023] Figure 14 Is Figure 13 Top view structure diagram of the back surface of the electronic device;

[0024] Figure 15 Schematic diagram of the structure of a signal source in one embodiment of the present application;

[0025] Figure 16 Schematic diagram of the structure of a signal source in another embodiment of the present application;

[0026] Figure 17 Schematic flowchart of one embodiment of the method for repairing a display panel in the present application;

[0027] Figure 18 Schematic diagram of the back surface of a display panel in one embodiment of the present application;

[0028] Figure 19 Schematic diagram of cutting the first target trace. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0030] It should be noted that the terms "first" and "second" in the present application are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0031] Before introducing the solution of the present application, a brief introduction to the background of the present application will be given first:

[0032] Currently, in order to achieve large-size display, several display panels are spliced together. In order to achieve a borderless display panel and an extremely small splicing gap, currently, the signal source for driving the display panel to display is bonded on the non-display surface of the display panel. Currently, there are two mainstream methods. The first is to use a single substrate (such as glass), with the front side for display and the back side for bonding the signal source. The second is to stack two substrates, and one of the surfaces facing away from each other of the two substrates is used as the display surface, and the other is used as the bonding signal source.

[0033] At the same time, as Figure 1 shown, on the front side of the display panel, a plurality of light-emitting elements 11 (i.e., sub-pixels) form a plurality of display columns. The plurality of light-emitting elements 11 in the same display column are electrically connected to the same data line 12, and the light-emitting elements 11 in different display columns are electrically connected to different data lines 12. That is to say, the display columns correspond one-to-one with the data lines 12, and the data lines 12 are electrically connected to all the light-emitting elements 11 in the corresponding display columns. Among them, the data line 12 is used to transmit the data signal output by the signal source to the light-emitting elements 11 in the corresponding display column.

[0034] Among them, in addition to having a data signal, in order to make the light-emitting element 11 emit light normally, as Figure 2As shown, it is also necessary to apply an ELVSS signal and an ELVDD signal to both ends of the light-emitting element 11 respectively. It should be noted that there is also a certain circuit connected in series between the light-emitting element 11 and the ELVDD signal. This application will not introduce this circuit.

[0035] The following will Figures 3 to 19 , in combination with, introduce the solution of this application in detail. First of all, it should be noted that for the sake of clarity of the illustration, all electrodes and pins transmitting the first power signal are labeled 1 in the accompanying drawings, all electrodes and pins transmitting the second power signal are labeled 2, and all electrodes and pins transmitting data signals are labeled 3.

[0036] Refer to Figure 3 and Figure 4 , in an embodiment of this application, the display panel 10 includes a substrate 100, a first electrode group 200, a bonding pin group 300, and a second electrode group 400.

[0037] The substrate 100 can be a flexible substrate or a rigid substrate. Its material can be glass, polyimide, plastic, etc. The substrate 100 can be a single-layer structure or a stacked structure formed by laminating multiple sub-substrates, which is not limited here. The substrate 100 has a first surface 110 and a second surface 120 opposite to each other. The second surface 120 is used for bonding the signal source. The first surface 110 includes a display area 111 and a non-display area 112. Structures such as light-emitting elements and data lines are arranged in the display area 111. The structures such as light-emitting elements and data lines in the display area 111 are the same as those in the prior art. The second electrode group 400 is arranged in the non-display area 112. The second electrode group 400 is used to transmit the signal transmitted by the signal source bonded to the second surface 120 to the light-emitting element. For specific details, please refer to the following introduction.

[0038] The second surface 120 is provided with a first electrode area 101 and a bonding area 102. The first electrode area 101 and the bonding area 102 are arranged at intervals along the first direction Y. Among them, the number of bonding areas 102 can be one, two, three, or more, which is not limited here. In the accompanying drawings, the number of bonding areas 102 is shown as two for illustration. The bonding area 102 is used for bonding the signal source. It should be noted that when the number of bonding areas 102 is multiple, multiple bonding areas 102 can all be used for bonding the signal source, but as long as the signal source is bonded to at least one of the bonding areas 102, the display panel 10 can display normally. For specific details, please refer to the following introduction.

[0039] The first electrode group 200 is disposed in the first electrode region 101. The first electrode group 200 includes a plurality of first electrodes 210 arranged at intervals along the second direction X, which intersects with the first direction Y. The two may be perpendicular or not perpendicular, and the plurality of first electrodes 210 are insulated from each other. At the same time, the plurality of first electrodes 210 include at least one first power electrode 211, at least one second power electrode 212, and a plurality of data signal electrodes 213. The number of the first power electrodes 211 may be one or more, and the number of the second power electrodes 212 may be one or more. The first power electrode 211 is used to transmit a first power signal, and the second power electrode 212 is used to transmit a second power signal. In an application scenario, the first power signal is an ELVDD signal, and the second power signal is an ELVSS signal. In another application scenario, the first power signal is an ELVSS signal, and the second power signal is an ELVDD signal. For the convenience of description, hereinafter, it is described with the first power signal being an ELVDD signal and the second power signal being an ELVSS signal.

[0040] The data signal electrodes 213 are used to transmit data signals. Among them, the data signal electrodes 213 correspond one by one to a plurality of display columns on the first surface 110, and the data signal electrodes 213 are electrically connected to all the light-emitting elements 11 in the corresponding display columns at the same time.

[0041] Continue to refer to Figure 3 , the second electrode group 400 includes a plurality of second electrodes 410 arranged at intervals along the second direction X. The plurality of second electrodes 410 correspond one by one to the plurality of first electrodes 210 in the first electrode group 200, and the second electrode 410 is electrically connected to the corresponding first electrode 210. Among them, the second electrode 410 is electrically connected to the corresponding first electrode 210 through a side-walking line (not shown in the figure). It can be understood that the second electrode 410 electrically connected to the first power electrode 211 is used to transmit the first power signal, the second electrode 410 electrically connected to the second power electrode 212 is used to transmit the second power signal, and the second electrode 410 electrically connected to the data signal electrode 213 is used to transmit the data signal. Among them, for the convenience of description, the second electrode 410 electrically connected to the first power electrode 211 is defined as the second electrode 411, the second electrode 410 electrically connected to the second power electrode 212 is defined as the second electrode 412, and the second electrode 410 electrically connected to the data signal electrode 213 is defined as the second electrode 413.

[0042] Among them, the plurality of second electrodes 413 in the second electrode group 400 correspond one by one to the display columns. That is to say, the second electrode 413 is electrically connected to all the light-emitting elements 11 in the corresponding display columns at the same time to transmit data signals to the light-emitting elements 11 in the corresponding display columns respectively.

[0043] Continue to refer toFigure 3 and Figure 4 In this embodiment, along the second direction X, the arrangement position of the second electrode 410 in the second electrode group 400 is the same as the arrangement position of the first electrode 210 electrically connected thereto in the first electrode group 200.

[0044] Specifically, along the second direction X, if a certain second electrode 410 is the first electrode in the second electrode group 400, then along the second direction X, the first electrode 210 electrically connected to the second electrode 410 is also the first electrode in the first electrode group 200, and so on. Along the second direction X, if a certain second electrode 410 is the last electrode in the second electrode group 400, then along the second direction X, the first electrode 210 electrically connected to the second electrode 410 is also the last electrode in the first electrode group 200.

[0045] This setting can enable the side-walk routing connecting the first electrode group 200 and the second electrode group 400 to be arranged on the same layer, avoid short circuits caused by the intersection of side-walk routings, and also reduce the difficulty of the manufacturing process.

[0046] Continue to refer to Figure 4 , in the first electrode group 200, at least one first power electrode 211 is distributed between two data signal electrodes 213, and / or at least one second power electrode 212 is distributed between two data signal electrodes 213.

[0047] Specifically, only the first power electrode 211 can be distributed between two data signal electrodes 213, only the second power electrode 212 can be distributed between two data signal electrodes 213, or both the first power electrode 211 and the second power electrode 212 can be distributed between two data signal electrodes 213.

[0048] Continue to refer to Figure 4 , a bonding pin group 300 is provided in each bonding area 102 for bonding a signal source (not shown in the figure). The bonding pin group 300 includes a plurality of bonding pins 310. The plurality of bonding pins 310 include a first bonding pin 311, a second bonding pin 312, and a plurality of third bonding pins 313. The first bonding pin 311 is electrically connected to the first power electrode 211, the second bonding pin 312 is electrically connected to the second power electrode 212, the plurality of third bonding pins 313 correspond to the plurality of data signal electrodes 213 one by one, and the third bonding pin 313 is electrically connected to the corresponding data signal electrode 213.

[0049] Specifically, the number of the third bonding pins 313 included in the bonding pin group 300 is equal to the number of the data signal electrodes 213 included in the first electrode group 200, and the third bonding pins 313 included in the bonding pin group 300 and the data signal electrodes 213 included in the first electrode group 200 are in one-to-one correspondence, and the corresponding third bonding pins 313 and data signal electrodes 213 are electrically connected.

[0050] It can be understood that after the driving signal source is bonded on the bonding area 102, the first power signal output by the signal source is transmitted to the first power electrode 211 through the first bonding pin 311, the second power signal output by the signal source is transmitted to the second power electrode 212 through the second bonding pin 312, and the data signal output by the signal source is transmitted to the data signal electrode 213 through the third bonding pin 313.

[0051] Meanwhile, in this embodiment, when the number of the bonding areas 102 is multiple, the first bonding pins 311 in any two adjacent bonding areas 102 are electrically connected to each other, the second bonding pins 312 are electrically connected to each other, and the third bonding pins 313 electrically connected to the same data signal electrode 213 are electrically connected to each other.

[0052] Specifically, along the first direction Y, the first bonding pins 311 in two adjacent bonding areas 102 are in series, the second bonding pins 312 in two adjacent bonding areas 102 are in series, and the third bonding pins 313 electrically connected to the same data signal electrode 213 are in series. This setting can enable the signal output by the signal source to be transmitted to the first surface 110 of the substrate 100 when the signal source is bonded to any one of the bonding areas 102.

[0053] Refer to Figure 5 , in the related art, multiple data signal electrodes 213 are arranged continuously, and there will be no first power electrode 211 and second power electrode 212 between any two adjacent data signal electrodes 213. At this time, multiple second power electrodes 212 are distributed on both sides of multiple data signal electrodes 213, multiple first power electrodes 211 are distributed on both sides of multiple second power electrodes 212, and there is only one bonding area 102, which will cause the following problems:

[0054] First, multiple first power electrodes 211 and multiple second power electrodes 212 are gathered together, so that the current density in the area where multiple first power electrodes 211 and multiple second power electrodes 212 are gathered together (see the dashed box N in Figure 5 ) is large, which is likely to cause local overheating and thus cause display abnormality of the display panel 10.

[0055] Second, when the arrangement position of the second electrode 410 in the second electrode group 400 is the same as that of the electrically connected first electrode 210 in the first electrode group 200, as Figure 6 shown, at this time, multiple second electrodes 413 also gather together. Multiple second electrodes 412 are distributed on both sides of the multiple second electrodes 413, and multiple second electrodes 411 are distributed on both sides of the multiple second electrodes 412. At this time, along the second direction X, there is an IR drop problem, resulting in a change in the brightness of the light-emitting element 11 along the second direction X, resulting in uneven display.

[0056] Third, when the position of the second electrode 410 in the second electrode group 400 is the same as that of the electrically connected first electrode 210 in the first electrode group 200, as Figure 6 shown, multiple second electrodes 413 also gather together. Since each second electrode 413 needs to be electrically connected to the light-emitting elements in the corresponding display column through traces, this will cause the slope of some traces to become smaller. At this time, in order to increase the slope of the traces, only the distance between the light-emitting element 11 and the second electrode 413 can be increased, but this is not conducive to the development of the borderless display panel 10.

[0057] Fourth, referring to Figure 7 , when two display panels are spliced together to form a larger display panel, a support plate is needed to support each display panel at the same time. In order to bond the signal source, through slots need to be opened on the support plate to expose the bonding area 102 on the display panel. In order to avoid the influence of slotting on the strength of the support plate, first, the bonding area 102 is set on one side close to the edge of the substrate 100. Second, when splicing the display panels, usually the substrates 100 are spliced head-to-head or tail-to-tail, that is, one of the substrates 100 needs to be rotated 180 degrees around the center point (when splicing head-to-head or tail-to-tail, the through slots opened on the support plate can be spaced at a certain distance, thus ensuring the strength of the support plate). This brings a problem. When transferring the light-emitting elements 11 on the first surface 110 of the substrate 100, in order to meet the requirement that some substrates need to be rotated 180 degrees during splicing, two sets of transfer processes need to be adopted. For example, one set is arranged according to RGB, and the other set is arranged according to BGR. Otherwise, it will cause the overall red light-emitting elements 11 not to be on a straight line after splicing, and the overall blue light-emitting elements 11 not to be on a straight line, thus increasing the complexity of the process.

[0058] However, in the solution of the present application, at least one first power electrode 211 is arranged between two data signal electrodes 213, and / or at least one second power electrode 212 is arranged between two data signal electrodes 213, so as to avoid the aggregation of the first power electrode 211, and / or avoid the aggregation of the second power electrode 212. On the one hand, it can avoid the large current density of the first power signal and / or the second power signal in the first electrode group 200, ensure that problems such as too high local temperature caused by large local current density will not occur, and avoid abnormal display. On the other hand, when the arrangement position of the second electrode 410 in the second electrode group 400 is the same as the arrangement position of the electrically connected first electrode 210 in the first electrode group 200, at least one second electrode 411 and / or at least one second electrode 412 are also arranged between two second electrodes 413, so as to improve the uniformity of the first power signal and / or the second power signal in the second direction X, ensure the uniformity of the display brightness. In addition, as Figure 8 shown, when the arrangement position of the second electrode 410 in the second electrode group 400 is the same as the arrangement position of the electrically connected first electrode 210 in the first electrode group 200, since at least one second electrode 411 and / or at least one second electrode 412 are also arranged between two second electrodes 413, the slope of the trace connecting the light-emitting element 11 and the second electrode 413 and located at the edge will become larger, so as to reduce the wiring space, which is beneficial to the development of the borderless display panel 10.

[0059] Meanwhile, when multiple bonding areas 102 are provided, multiple bonding areas 102 can all be used to bond the signal source. Therefore, when splicing multiple display panels 10 together, it is not necessary to rotate the display panel 10 by 180 degrees, and only a suitable bonding area 102 needs to be selected, so that when transferring the light-emitting element 11, only one transfer process is required. For the sake of easy understanding, taking the Figure 9 structure as an example for illustration:

[0060] First, Figure 9 the two display panels 10 in are respectively defined as the first display panel 1 and the second display panel 2. When bonding the signal source, the bonding area 102 on the first display panel 1 that is farthest from the second display panel 2 can be used to bond the signal source, and the bonding area 102 on the second display panel 2 that is farthest from the first display panel 1 can be used to bond the signal source, so as to increase the distance between the through slots opened on the support plate, ensure the strength of the support plate, and there is no need to rotate the display panel 2 by 180 degrees.

[0061] It should be noted that although it is introduced above that when multiple bonding areas 102 are provided, the distance of the through slots formed in the support plate can be increased to ensure the strength of the support plate without rotating the display panel 2 by 180 degrees, this does not mean that the number of bonding areas 102 in the solution of the present application must be multiple. That is to say, in an embodiment of the present application, the number of bonding areas 102 can also be one. At this time, the setting of the first electrode group 200 can avoid the large current density of the first power signal and / or the second power signal in the first electrode group 200, ensure that problems such as too high local temperature caused by large local current density will not occur, and avoid abnormal display.

[0062] Referring to Figure 4 , in an embodiment, the number of bonding areas 102 is two. For the convenience of description, the two bonding areas 102 are defined as the first bonding area 1021 and the second bonding area 1022. Among them, the distance from the first bonding area 1021 to the first side 1011 of the substrate 100 is equal to the distance from the second bonding area 1022 to the second side 1012 of the substrate 100. This setting can ensure the uniformity of the distribution of the bonding areas 102.

[0063] Of course, in other embodiments, the distance from the first bonding area 1021 to the first side 1011 of the substrate 100 may not be equal to the distance from the second bonding area 1022 to the second side 1012 of the substrate 100.

[0064] At the same time, in other embodiments, when the number of bonding areas 102 is more than three, along the first direction Y, the multiple bonding areas 102 can be evenly distributed on the substrate 100, and at this time the distance between any two bonding areas 102 is equal.

[0065] Continuing to refer to Figure 4 , in an embodiment, along the second direction X, the arrangement position of the bonding pins 310 in the bonding pin group 300 is the same as the arrangement position of the first electrode 210 electrically connected thereto in the first electrode group 200. That is to say, along the second direction X, if the first electrode 210 is arranged in the first position in the first electrode group 200, then along the second direction X, the bonding pin 310 electrically connected to the first electrode 210 is also arranged in the first position in the bonding pin group 300, and so on. That is to say, at this time, the first electrode 210 in the first electrode group 200 is electrically connected to the bonding pin 310 in the bonding pin group 300 in one-to-one correspondence and has the same arrangement order. This setting can ensure that all the traces electrically connecting the first electrode group 200 and the bonding pin group 300 can be fabricated using the same layer of metal, thereby reducing the fabrication difficulty and cost. That is to say, at this time, the orthographic projections of all the traces electrically connecting the first electrode group 200 and the bonding pin group 300 on the substrate 100 do not cross.

[0066] Referring toFigure 10 , in another embodiment, the number of the first bonding pins 311 and the second bonding pins 312 is plural, and the plural second bonding pins 312 are distributed on both sides of the plural third bonding pins 313, and the plural first bonding pins 311 are distributed on both sides of the plural second bonding pins 312, different from Figure 4 the embodiment, at this time, among all the traces electrically connecting the first electrode group 200 and the bonding pin group 300, the orthographic projections of some traces on the substrate 100 intersect, and at least two layers of metal need to be used to prepare all the traces electrically connecting the first electrode group 200 and the bonding pin group 300.

[0067] All in all, the present application does not specifically limit the arrangement positions of the bonding pins 310 in the bonding pin group 300.

[0068] Referring to Figure 11 , when the number of the first power supply electrodes 211 and the second power supply electrodes 212 is plural, the plural data signal electrodes 213 are divided into plural data signal electrode groups Q, wherein, the second power supply electrodes 212 are distributed between some adjacent data signal electrode groups Q, and the first power supply electrodes 211 are distributed between some other adjacent data signal electrode groups Q.

[0069] Specifically, considering that the number of the data signal electrodes 213 is greater than the number of the first power supply electrodes 211 and the second power supply electrodes 212, therefore, grouping the plural data signal electrodes 213 can ensure the uniformity of the distribution of the first power supply electrodes 211 and the second power supply electrodes 212 among the plural data signal electrodes 213.

[0070] Continuing to refer to Figure 11 , along the second direction X, the first power supply electrodes 211 and the second power supply electrodes 212 are alternately arranged. Generally speaking, if only looking at the first power supply electrodes 211 and the second power supply electrodes 212, the first power supply electrodes 211 and the second power supply electrodes 212 are alternately arranged. This arrangement can ensure the display uniformity of the display panel 10 in the second direction X and avoid the IR drop problem in the second direction X.

[0071] Certainly, in other embodiments, along the second direction X, the first power supply electrodes 211 and the second power supply electrodes 212 may not be alternately arranged.

[0072] Continuing to refer to Figure 11 , in order to further ensure the uniformity of the distribution, the second power supply electrodes 212 and the first power supply electrodes 211 are respectively distributed on both sides of any data signal electrode group Q.

[0073] Among them, each data signal electrode group Q includes one or more data signal electrodes 213, and the number of data signal electrodes 213 included in each data signal electrode group Q can be different; for example, in Figure 11 the data signal electrode group Q includes two data signal electrodes 213, while in Figure 4 the data signal electrode group Q includes one data signal electrode 213; it is also possible that some data signal electrode groups Q include one data signal electrode 213, and some data signal electrode groups Q include two or more data signal electrodes 213.

[0074] Continuing to refer to Figure 10 when the numbers of the first power electrode 211 and the second power electrode 212 are both multiple, in the first electrode region 101, some of the second power electrodes 212 are distributed between the multiple data signal electrodes 213, and some of the second power electrodes 212 are distributed on both sides of the multiple data signal electrodes 213, while the multiple first power electrodes 211 are distributed on both sides of the multiple data signal electrodes 213 and the multiple second power electrodes 212.

[0075] Specifically, different from Figure 4 and Figure 11 at this time, in Figure 10 only some of the second power electrodes 212 are distributed between the multiple data signal electrodes 213, and some of the second power electrodes 212 are distributed on both sides of the multiple data signal electrodes 213, and at this time the multiple first power electrodes 211 are distributed on both sides of all the second power electrodes 212 and the data signal electrodes 213.

[0076] In other embodiments, it is also possible to only distribute some of the first power electrodes 211 between the multiple data signal electrodes 213. In short, the present application does not limit the specific arrangement manner of the first electrodes 210 in the first electrode group 200.

[0077] Continuing to refer to Figure 4 the second surface 120 is further provided with a second electrode region 103. The first electrode region 101, the bonding region 102, and the second electrode region 103 are sequentially arranged at intervals along the first direction Y. The second electrode region 103 is also provided with a first electrode group 200. The first power electrode 211 in the second electrode region 103 is electrically connected to the first bonding pin 311 in the adjacent bonding region 102. The second power electrode 212 in the second electrode region 103 is electrically connected to the second bonding pin 312 in the adjacent bonding region 102. The multiple data signal electrodes 213 in the second electrode region 103 are electrically connected to the multiple third bonding pins 313 in the adjacent bonding region 102 in one-to-one correspondence.

[0078] Specifically, the first electrode group 200 in the second electrode region 103 is distributed exactly the same as the first electrode group 200 in the first electrode region 101, and the electrical connection relationship between the first electrode group 200 in the second electrode region 103 and the bonding pin group 300 in the adjacent bonding region 102 is exactly the same as the electrical connection relationship between the first electrode group 200 in the first electrode region 101 and the bonding pin group 300 in the adjacent bonding region 102.

[0079] The setting of the second electrode region 103 can enable the signals transmitted by the signal source to be transmitted to the second surface 120 simultaneously from the first side 1011 and the second side 1012 of the substrate 100, ensuring the stability of transmission. It should be noted that in other embodiments, the second electrode region 103 may not be provided.

[0080] Continue to refer to Figure 4 and Figure 10 , the first bonding pins 311 in any two adjacent bonding regions 102 are electrically connected in one-to-one correspondence, and the second bonding pins 312 are electrically connected in one-to-one correspondence. This setting can ensure the transmission stability of the first power signal and the second power signal.

[0081] It should be noted that in other embodiments, the first bonding pins 311 in the bonding region 102 can be electrically connected to multiple first bonding pins 311 in the adjacent bonding region 102 at the same time, and / or the second bonding pins 312 in the bonding region 102 can be electrically connected to multiple second bonding pins 312 in the adjacent bonding region 102 at the same time.

[0082] Refer to Figure 12 , in an embodiment of the present application, the electronic device 20 includes the display panel 10 in any one of the above embodiments.

[0083] Among them, the electronic device 20 can be any type of device such as a mobile phone, a computer, or a calculator, and is not limited herein.

[0084] Among them, the number of display panels 10 included in the electronic device 20 is multiple, and the multiple display panels 10 are spliced together.

[0085] Refer to Figure 13 , at this time, the electronic device 20 further includes a support plate 30. The support plate 30 supports the multiple display panels 10, and the support plate 30 is located on the non-display surface side of the display panel 10, that is, the second surfaces 120 of the substrates 100 all face the support plate 30.

[0086] For the convenience of description, one of the multiple display panels 10 is defined as the first display panel 1, and the other display panel 10 is defined as the second display panel 2. The first display panel 1 and the second display panel 2 are spliced together.

[0087] Combined with Figure 13 and Figure 14 , the support plate 30 is provided with a first through groove 301 and a second through groove 302. The first through groove 301 exposes a bonding area 102 of the first display panel 1, and the second through groove 302 exposes a bonding area 102 of the second display panel 2.

[0088] Among them, a signal source (not shown in the figure) is bonded on the bonding area 102 exposed from the support plate 30. Specifically, a signal source is bonded on each display panel 10 to ensure the normal display of the display panel 10.

[0089] Among them, in order to ensure the support strength of the support plate 30, other bonding areas 102 are distributed between the bonding area 102 exposed through the first through groove 301 and the bonding area 102 exposed through the second through groove 302. Combined with Figure 9 , that is to say, when bonding the signal source, the bonding area 102 on the first display panel 1 that is farthest from the second display panel 2 is used to bond the signal source, and the bonding area 102 on the second display panel 2 that is farthest from the first display panel 1 is used to bond the signal source, so as to increase the distance between the first through groove 301 and the second through groove 302 and ensure the strength of the support plate 30.

[0090] It should be noted that in other embodiments, the support plate 30 may not be provided with the first through groove 301 and the second through groove 302. At this time, during assembly, the signal source can be bonded on the display panel 10 first, and then the display panel 10 can be placed on the support plate 30.

[0091] Refer to Figure 4 and Figure 15 , in an embodiment of the present application, the signal source 40 includes a substrate 41 and a driving chip 42 disposed on the substrate 41. At this time, a plurality of pins provided on the driving chip 42 are electrically connected to a plurality of bonding pins 310 in the bonding pin group 300 one by one. That is to say, at this time, the driving chip 42 outputs a first power signal, a second power signal, and a data signal at the same time. Among them, the material of the substrate 41 can be any material, and the present application does not make any restrictions.

[0092] Refer to Figure 4 and Figure 16 , in another embodiment of the present application, the signal source 50 includes a substrate 51 and a first chip 52 and a second chip 53 disposed on the substrate 51.

[0093] A plurality of pins provided on the first chip 52 are electrically connected to the first bonding pin 311 and the second bonding pin 312 in the bonding pin group 300 one by one, and a plurality of pins provided on the second chip 53 are electrically connected to a plurality of third bonding pins 313 in the bonding pin group 300 one by one.

[0094] Specifically, the first chip 52 is bonded to the display panel 10 through the first bonding pins 311 and the second bonding pins 312, and the second chip 53 is bonded to the display panel 10 through the third bonding pins 313. That is to say, the first chip 52 transmits the first power signal and the second power signal simultaneously, while the second chip 53 only transmits data signals.

[0095] In Figure 16 the embodiment, the signal source 50 further includes a first trace (not shown in the figure) and a second trace (not shown in the figure) disposed on the substrate 51. The first chip 52 is electrically connected to the first bonding pins 311 and the second bonding pins 312 through a plurality of first traces respectively, and the second chip 53 is electrically connected to the plurality of third bonding pins 313 through a plurality of second traces respectively. The plurality of first traces are disposed on the same layer, the plurality of second traces are disposed on the same layer, and the first trace and the second trace are not disposed on the same layer.

[0096] Specifically, the first trace realizes the electrical connection between the first chip 52 and the bonding pin group 300, and the second trace realizes the electrical connection between the second chip 53 and the bonding pin group 300.

[0097] In order to flexibly adapt to various arrangement manners of the bonding pins 310 in the bonding pin group 300, all the first traces electrically connected to the first chip 52 are disposed on the same layer, all the second traces electrically connected to the second chip 53 are disposed on the same layer, and the first trace and the second trace are not disposed on the same layer. That is to say, at least two layers of metal are required in the signal source 50 to form all the traces at this time.

[0098] The repair method of the display panel of the present application is introduced below:

[0099] Refer to Figure 17 and Figure 18 , when a plurality of second bonding pins 312 are distributed on both sides of a plurality of third bonding pins 313, and a plurality of first bonding pins 311 are distributed on both sides of the plurality of second bonding pins 312, the repair method of the display panel includes:

[0100] S110: When it is detected that the first target trace 601 is short-circuited with the second target trace 602, determine the short-circuit point O between the first target trace 601 and the second target trace 602.

[0101] S120: Cut the first target trace 601 on both sides of the short-circuit point O.

[0102] Specifically, both the first target trace 601 and the second target trace 602 are formed on the second surface 120 of the substrate 100. The number of the first target traces 601 is multiple, and at least some of the first target traces 601 are arranged in a different layer from the second target trace 602 and intersect in the orthographic projection on the substrate 100, that is, at least some of the first target traces 601 and the second target trace 602 are made of different-layer metals. Thus, during the manufacturing process, when environmental dust particles are likely to fall on the substrate 100, once an external pressure is applied to the particle, it will cause a short circuit between different-layer metals. That is to say, there is a risk of short circuit between the first target trace 601 and the second target trace 602.

[0103] Among them, the first target trace 601 is electrically connected to the first power electrode 211 and the first bonding pin 311, or the first target trace 601 is electrically connected to the second power electrode 212 and the second bonding pin 312, and the second target trace 602 can be any trace electrically connecting the first electrode group 200 and the bonding pin group 300.

[0104] Since the number of the first target traces 601 is multiple, removing one first target trace 601 will not affect the normal display of the display panel 10. Therefore, when it is detected that a short circuit occurs between the first target trace 601 and the second target trace 602, first, the short-circuit point O is searched. After the short-circuit point O is determined, as Figure 19 shown, the first target trace 601 is cut on both sides of the short-circuit point O, so that the first target trace 601 can neither transmit signals to the first electrode group 200 nor transmit signals to the bonding pin group 300, thus not affecting the normal transmission of the second target trace 602, and further enabling the normal display of the display panel 10.

[0105] The above description is only an embodiment of the present application, and thus does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate having a first surface and a second surface opposite to each other, wherein the second surface is provided with a first electrode region and a bonding region, and the first electrode region and the bonding region are spaced apart along a first direction; a first electrode group disposed in the first electrode region, the first electrode group including a plurality of first electrodes spaced apart along a second direction, the plurality of first electrodes including at least one first power electrode, at least one second power electrode, and a plurality of data signal electrodes, wherein in the first electrode group, at least one of the first power electrodes is distributed between two of the data signal electrodes, and / or at least one of the second power electrodes is distributed between two of the data signal electrodes, and the second direction intersects the first direction; a bonding pin group, the bonding pin group is disposed in the bonding region, the bonding pin group including a plurality of bonding pins, the plurality of bonding pins including a first bonding pin, a second bonding pin, and a plurality of third bonding pins, the first bonding pin is electrically connected to the first power electrode, the second bonding pin is electrically connected to the second power electrode, and the plurality of third bonding pins are electrically connected to the plurality of data signal electrodes one by one.

2. The display panel according to claim 1, wherein Along the second direction, the arrangement position of the bonding pin in the bonding pin group is the same as the arrangement position of the first electrode electrically connected thereto in the first electrode group; Alternatively, the number of the first bonding pins and the second bonding pins is plural, and the plurality of second bonding pins are distributed on both sides of the plurality of third bonding pins, and the plurality of first bonding pins are distributed on both sides of the plurality of second bonding pins.

3. The display panel according to claim 1, wherein The number of the first power electrode and the second power electrode in the first electrode group is plural; The plurality of data signal electrodes are divided into a plurality of data signal electrode groups, wherein the second power electrode is distributed between some adjacent data signal electrode groups, and the first power electrode is distributed between some other adjacent data signal electrode groups.

4. The display panel according to claim 3, wherein Along the second direction, the first power electrode and the second power electrode are alternately arranged.

5. The display panel according to claim 3, wherein The second power electrode and the first power electrode are respectively distributed on both sides of any data signal electrode group.

6. The display panel according to claim 3, wherein, The data signal electrode group includes one or more of the data signal electrodes.

7. The display panel according to claim 1, characterized in that, The number of the first power electrode and the second power electrode in the bonding pin group is plural; In the first electrode region, some of the second power electrodes are distributed between the plurality of data signal electrodes, some other of the second power electrodes are distributed on both sides of the plurality of data signal electrodes, and at the same time, the plurality of first power electrodes are distributed on both sides of the plurality of data signal electrodes and the plurality of second power electrodes.

8. The display panel according to claim 1, wherein The display panel further includes: The second electrode group is disposed on the first surface. The second electrode group includes a plurality of second electrodes spaced along the second direction, and the plurality of second electrodes are electrically connected to the plurality of first electrodes in the first electrode group one by one; Wherein, along the second direction, the arrangement position of the second electrode in the second electrode group is the same as the arrangement position of the first electrode electrically connected thereto in the first electrode group.

9. The display panel according to claim 1, characterized in that, The second surface is further provided with a second electrode region. The first electrode region, the bonding region, and the second electrode region are sequentially spaced along the first direction; The first electrode group is disposed in the second electrode region. The first power supply electrode in the second electrode region is electrically connected to the first bonding pin in the adjacent bonding region, the second power supply electrode in the second electrode region is electrically connected to the second bonding pin in the adjacent bonding region, and the plurality of data signal electrodes in the second electrode region are electrically connected to the plurality of third bonding pins in the adjacent bonding region one by one.

10. The display panel according to any one of claims 1 to 9, characterized in that, The number of the bonding regions is multiple. The first electrode region and the multiple bonding regions are sequentially spaced along the first direction; wherein, a bonding pin group is disposed in each bonding region, and the first bonding pins in any two adjacent bonding regions are electrically connected to each other, the second bonding pins are electrically connected to each other, and the third bonding pins electrically connected to the same data signal electrode are electrically connected to each other.

11. The display panel according to claim 10, wherein The first bonding pins in any two adjacent bonding regions are electrically connected to each other one by one, and the second bonding pins are electrically connected to each other one by one.

12. The display panel according to claim 10, wherein The number of the bonding regions is two. The two bonding regions include a first bonding region and a second bonding region. Along the first direction, the distance from the first bonding region to the first side of the substrate is equal to the distance from the second bonding region to the second side of the substrate.

13. The display panel according to claim 1, wherein The first power supply electrode is used to transmit the ELVDD signal, and the second power supply electrode is used to transmit the ELVSS signal.

14. An electronic device, characterized in that, Including the display panel according to any one of claims 1 to 13, wherein the number of the display panels is multiple, and the multiple display panels are spliced together.

15. The electronic device according to claim 14, wherein The electronic device further includes: A support plate for supporting the multiple display panels and the second surfaces of the multiple substrates all face the support plate; A signal source bonded to the bonding region.

16. The electronic device according to claim 15, wherein The signal source includes a substrate and a driving chip disposed on the substrate. A plurality of pins provided on the driving chip are electrically connected to the plurality of bonding pins in the bonding pin group one by one.

17. The electronic device according to claim 15, wherein The signal source includes a substrate, a first chip disposed on the substrate, and a second chip. A plurality of pins provided on the first chip are electrically connected to the first bonding pins and the second bonding pins in the bonding pin group in a one-to-one correspondence. A plurality of pins provided on the second chip are electrically connected to a plurality of the third bonding pins in the bonding pin group in a one-to-one correspondence; Wherein, the signal source further includes a first trace and a second trace disposed on the substrate. The first chip is electrically connected to the first bonding pin and the second bonding pin through a plurality of the first traces respectively. The second chip is electrically connected to a plurality of the third bonding pins through a plurality of the second traces respectively. The plurality of the first traces are disposed on the same layer, the plurality of the second traces are disposed on the same layer, and the first trace and the second trace are not disposed on the same layer.

18. A repair method for a display panel, characterized in that, The method is applied to the display panel according to any one of claims 1 to 13. The repair method includes: When it is detected that a first target trace is short-circuited with a second target trace, determining a short-circuit point between the first target trace and the second target trace; Performing a cutting process on the first target trace on both sides of the short-circuit point; Wherein, the first target trace and the second target trace are formed on the second surface of the substrate. The number of the first target traces is multiple, and at least part of the first target traces are disposed on different layers from the second target trace and intersect in the orthographic projection on the substrate. And the first target trace is electrically connected to the first power electrode and the first bonding pin, or the first target trace is electrically connected to the second power electrode and the second bonding pin.

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