Pixel driving circuit and display panel
By controlling multiple scan lines with a single pin, the problem of increased bezel width and layout difficulties caused by the increase in drive signal traces is solved, resulting in reduced costs, narrow bezel design, and improved work efficiency.
Patent Information
- Application Number
- CN202411827423.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2044-12-12
AI Technical Summary
The increased number of drive signal traces in existing display panels leads to increased bezel width and layout difficulties, and the increased demand for integrated circuits leads to higher costs.
The structure uses a single pin line to control multiple scan lines. Through the cooperation of eight transistors and four signal lines, it can achieve that at any given time, only one of the three scan lines is at a high level, while the remaining two are at a low level, thus reducing the use of pin lines and integrated circuits.
It effectively reduces the area occupied by non-display areas, lowers overall costs, promotes narrow bezel design, reduces wiring difficulty, and improves work efficiency.
Smart Images
Figure CN119446032B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of driving circuit, in particular to a pixel driving circuit and a display panel. BACKGROUND
[0002] The driving signal wire of the display panel is arranged in the non-display area of the display panel, which is also the position of the frame of the display panel. With the increase of the pixel units, the driving signal wire also increases, and the increase of the driving signal wire will lead to the increase of the area occupied by the non-display area, and further lead to the increase of the frame width of the display panel, which is not conducive to improving the screen ratio. In addition, the increase of the driving signal wire brings difficulties to the layout when the driving signal wire and the display driving chip are electrically connected.
[0003] The existing display screen has diversified development, and consumers have higher and higher requirements for narrow frame. Therefore, the number of ICs (integrated circuits) also increases, which leads to an increase in the overall cost.
[0004] Therefore, it is necessary to provide a pixel driving circuit and a display panel which can reduce the use of integrated circuits, reduce costs, and also meet the demand for narrow frame. SUMMARY
[0005] In order to overcome the shortcomings of the prior art, the present application provides a pixel driving circuit and a display panel.
[0006] The technical scheme of the present application is as follows:
[0007] A pixel driving circuit comprises:
[0008] A plurality of pixel units arranged in an array;
[0009] A plurality of scan lines extending in the row direction, the scan lines being interposed between two rows of pixel units;
[0010] At least one pin line, the pin line being electrically connected to the plurality of scan lines;
[0011] A plurality of signal lines extending in the column direction;
[0012] A plurality of transistors, the gate of each transistor being electrically connected to a signal line, the first end of each transistor being electrically connected to a scan line, and the second end of each transistor being electrically connected to a signal line or a pin line, the number of transistors connected to the pin line being equal to the number of scan lines.
[0013] As a further improvement of the application, one of the pin lines is electrically connected to three scan lines, and when one of the scan lines outputs a high level, the other two scan lines maintain a low level.
[0014] As a further improvement of the application, eight transistors are arranged between the three scan lines and the pin line, the three scan lines are respectively a first scan line, a second scan line and a third scan line, the eight transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the signal line has four signal lines, which are respectively a first signal line, a second signal line, a third signal line and a fourth signal line, the first end of the first transistor is electrically connected to the first scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the first signal line; the first end of the second transistor is electrically connected to the first scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the second signal line; the first end of the third transistor is electrically connected to the first scan line, the second end is electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the fourth transistor is electrically connected to the second scan line, the second end is electrically connected to the second signal line, and the gate is electrically connected to the first signal line; the first end of the fifth transistor is electrically connected to the second scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the second signal line; the first end of the sixth transistor is electrically connected to the second scan line, the second end is electrically connected to the first signal line, and the gate is electrically connected to the third signal line; the first end of the seventh transistor is electrically connected to the third scan line, the second end is electrically connected to the pin line, and the gate is electrically connected to the third signal line; and the first end of the eighth transistor is electrically connected to the third scan line, the second end is electrically connected to the third signal line, and the gate is electrically connected to the fourth signal line.
[0015] As a further improvement of the application, the cycle period of the output signals of the four signal lines is a first cycle period, the first cycle period is 3T, and the first cycle period is divided into three intervals, including a first interval, a second interval and a third interval.
[0016] As a further improvement of the application, in the first interval, the first signal line is at a high level, the second signal line is at a low level, the third signal line is at a low level, and the fourth signal line is at a high level; in the second interval, the first signal line is at a low level, the second signal line is at a high level, the third signal line is at a low level, and the fourth signal line is at a high level; and in the third interval, the first signal line is at a low level, the second signal line is at a low level, the third signal line is at a high level, and the fourth signal line is at a low level.
[0017] As a further improvement of the present application, the cycle period of the output signal of the pin line is a second cycle period, the second cycle period covers at least two first cycle periods, the second cycle period is n times of the first cycle period, n is an integer, and at least three continuous intervals output high level in the second cycle period.
[0018] As a further improvement of the present application, the number of the pin lines is m, and n≥m.
[0019] As a further improvement of the present application, the output signals of two adjacent pin lines are different by one first cycle period.
[0020] As a further improvement of the present application, the pin lines are two, the second cycle period is equal to two first cycle periods, the second cycle period is 6T and is divided into six intervals, three continuous intervals output the same level in the second cycle period, and the other three intervals output another level.
[0021] A display panel comprises a display driving chip and the pixel driving circuit.
[0022] According to the technical scheme of the present application, the present application has the following beneficial effects:
[0023] The present application provides a pixel driving circuit and a display panel, which adopts a structure of one pin line controlling three scanning lines, breaks the conventional design of one-to-one control of pin lines and scanning lines, can effectively reduce the number of pin lines, thereby reducing the use of integrated circuits, can reduce the overall manufacturing cost, can reduce the occupied area of the non-display area, promotes the narrow frame design, meets the demand of consumers for narrow frame, and reduces the wiring difficulty and improves the work efficiency. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 is a structural schematic diagram of the pixel driving circuit of the present application;
[0025] Figure 2 is a timing diagram of the pixel driving circuit of the present application. DETAILED DESCRIPTION
[0026] The technical scheme of the present application will be described in detail below with reference to the drawings, obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.
[0027] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0028] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0029] Referring to Figure 1 The present application provides a pixel driving circuit, comprising:
[0030] A plurality of pixel units, the plurality of pixel units are arranged in an array, and the AA region is a pixel module composed of the plurality of pixel units;
[0031] A plurality of scan lines, the plurality of scan lines extend along the row direction, all the scan lines pass through the pixel module, and the scan lines are interleaved between two rows of pixel units, each scan line is electrically connected to a row of pixel units, and similarly, the arrangement position of the scan lines can be adjusted appropriately according to specific use requirements, such as the scan lines are arranged alternately with the row of pixel units, that is, two scan lines, two rows of pixel units, two scan lines, two rows of pixel units are arranged in turn along the column direction, and the arrangement is continued in this way;
[0032] At least one pin line, one pin line is electrically connected to one pin of the integrated circuit, and the pin line is electrically connected to the plurality of scan lines;
[0033] A plurality of signal lines, the plurality of signal lines extend along the column direction;
[0034] A plurality of transistors, the gate of each transistor is electrically connected with a signal line, that is, the transistor is controlled by one of the signal lines, the first end of each transistor is electrically connected with a scan line, and the second end of each transistor is electrically connected with a signal line or a pin line, that is, when the transistor is turned on, the connection of one scan line and one signal line or one scan line and one pin line can be realized, so that the level on the signal line or the pin line is transmitted to the corresponding scan line, the number of transistors connected with the pin line is equal to the number of scan lines, so that one transistor is arranged between each scan line and the pin line to control the on-off between the two, and the normal work of the pixel driving circuit is ensured.
[0035] The structure of the application can control a plurality of scan lines by one pin line, break the conventional design of one-to-one control of the pin line and the scan line, effectively reduce the number of pin lines, reduce the use of integrated circuits, reduce the overall manufacturing cost, reduce the occupied area of the non-display area, promote the narrow frame design, meet the needs of consumers for narrow frame, and reduce the wiring difficulty and improve the work efficiency.
[0036] As an embodiment of the application, one pin line is electrically connected with three scan lines, for example, the pin line is pin1, and the three scan lines are first scan line G1, second scan line G2 and third scan line G3, wherein when one of the scan lines outputs a high level, the other two scan lines maintain a low level; when the first scan line G1 outputs a high level, the second scan line G2 and the third scan line G3 maintain a low level; when the second scan line G2 outputs a high level, the first scan line G1 and the third scan line G3 maintain a low level; and when the third scan line G3 outputs a high level, the first scan line G1 and the second scan line G2 maintain a low level. Compared with the conventional one-to-one control structure, the design of controlling three scan lines by one pin line can save 2 / 3 of the pin lines, and when the number of scan lines is large and a plurality of integrated circuits are needed, the application can save 2 / 3 of the number of integrated circuits, thereby effectively reducing the cost.
[0037] As an embodiment of the application, eight transistors are arranged between the three scan lines and the pin line, and the eight transistors are first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4, fifth transistor Q5, sixth transistor Q6, seventh transistor Q7 and eighth transistor Q8. There are four signal lines, and the four signal lines are first signal line V1, second signal line V2, third signal line V3 and fourth signal line V4. Through the cooperation between the eight transistors and the four signal lines, only one of the three scan lines can output a high level at the same time, and the other two scan lines can maintain a low level.
[0038] As an embodiment of the present application, the first end of the first transistor Q1 is electrically connected to the first scan line G1, the second end is electrically connected to the pin line, and the gate is electrically connected to the first signal line V1; the first end of the second transistor Q2 is electrically connected to the first scan line G1, the second end is electrically connected to the third signal line V3, and the gate is electrically connected to the second signal line V2; the first end of the third transistor Q3 is electrically connected to the first scan line G1, the second end is electrically connected to the first signal line V1, and the gate is electrically connected to the third signal line V3; the first end of the fourth transistor Q4 is electrically connected to the second scan line G2, the second end is electrically connected to the second signal line V2, and the gate is electrically connected to the first signal line V1; the first end of the fifth transistor Q5 is electrically connected to the second scan line G2, the second end is electrically connected to the pin line, and the gate is electrically connected to the second signal line V2; the first end of the sixth transistor Q6 is electrically connected to the second scan line G2, the second end is electrically connected to the first signal line V1, and the gate is electrically connected to the third signal line V3; the first end of the seventh transistor Q7 is electrically connected to the third scan line G3, the second end is electrically connected to the pin line, and the gate is electrically connected to the third signal line V3; the first end of the eighth transistor Q8 is electrically connected to the third scan line G3, the second end is electrically connected to the third signal line V3, and the gate is electrically connected to the fourth signal line V4, wherein the first transistor Q1 is controlled by the first signal line V1 to turn on and off to realize the turn-on and off between the first scan line G1 and the pin line pin1, the fifth transistor Q5 is controlled by the second signal line V2 to turn on and off to realize the turn-on and off between the second scan line G2 and the pin line pin1, and the seventh transistor Q7 is controlled by the third signal line V3 to turn on and off to realize the turn-on and off between the third scan line G3 and the pin line pin1, and the rest of the transistors and the fourth signal line V4 are used to maintain the low level of the first scan line G1 or the second scan line G2 or the third scan line G3 to ensure the working stability of the pixel driving circuit.
[0039] Referring to Figure 2 As an embodiment of the present application, the cycle period of the output signals of the four signal lines is a first cycle period, the first cycle period is 3T, and the first cycle period is divided into three intervals, including a first interval T1, a second interval T2, and a third interval T3; preferably, in the first interval T1, the first signal line V1 is at a high level, the second signal line V2 is at a low level, the third signal line V3 is at a low level, and the fourth signal line V4 is at a high level; in the second interval T2, the first signal line V1 is at a low level, the second signal line V2 is at a high level, the third signal line V3 is at a low level, and the fourth signal line V4 is at a high level; in the third interval T3, the first signal line V1 is at a low level, the second signal line V2 is at a low level, the third signal line V3 is at a high level, and the fourth signal line V4 is at a low level, and the pin line pin1 outputs the same level in one first cycle period.
[0040] When the pin line pin1 outputs a high level,
[0041] In the first interval T1, the first signal line V1 is high to turn on the first transistor Q1, realizing that the pin line pin1 is in communication with the first scan line G1, so the first scan line G1 inputs high level, and also turns on the fourth transistor Q4, realizing that the second scan line G2 is in communication with the second signal line V2, because the second signal line V2 is low, so the second scan line G2 inputs low level, the second signal line V2 cannot turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is high to turn on the eighth transistor Q8, realizing that the third scan line G3 is in communication with the third signal line V3, because the third signal line V3 is low, so the third scan line G3 inputs low level, that is, only the first scan line G1 inputs high level, and the second scan line G2 and the third scan line G3 maintain low level;
[0042] In the second interval T2, the first signal line V1 cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is high to turn on the second transistor Q2, realizing that the first scan line G1 is in communication with the third signal line V3, because the third signal line V3 is low, so the first scan line G1 inputs low level, and also turns on the fifth transistor Q5, realizing that the second scan line G2 is in communication with the pin line pin1, so the second scan line G2 inputs high level, the third signal line V3 cannot turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is high to turn on the eighth transistor Q8, realizing that the third scan line G3 is in communication with the third signal line V3, because the third signal line V3 is low, so the third scan line G3 inputs low level, that is, only the second scan line G2 inputs high level, and the first scan line G1 and the third scan line G3 maintain low level;
[0043] In the third interval T3, the first signal line V1 cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 cannot turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 is high to turn on the third transistor Q3, realizing that the first scan line G1 is in communication with the first signal line V1, because the first signal line V1 is low, so the first scan line G1 inputs low level, and also turns on the sixth transistor Q6, realizing that the second scan line G2 is in communication with the first signal line V1, because the first signal line V1 is low, so the second scan line G2 inputs low level, and also turns on the seventh transistor Q7, realizing that the third scan line G3 is in communication with the pin line pin1, so the third scan line G3 inputs high level, the fourth signal line V4 cannot turn on the eighth transistor Q8, that is, only the third scan line G3 inputs high level, and the first scan line G1 and the second scan line G2 maintain low level;
[0044] When the pin line pin1 outputs low level,
[0045] In the first interval T1, the first signal line V1 is high level to turn on the first transistor Q1, realizing the pin line pin1 and the first scan line G1 communication, because the pin line pin1 is low level, so the first scan line G1 input low level, also turn on the fourth transistor Q4, realizing the second scan line G2 and the second signal line V2 communication, because the second signal line V2 is low level, so the second scan line G2 input low level, the second signal line V2 is low level can not turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 is low level can not turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is high level to turn on the eighth transistor Q8, realizing the third scan line G3 and the third signal line V3 communication, because the third signal line V3 is low level, so the third scan line G3 input low level, that is, the first scan line G1, the second scan line G2, the third scan line G3 all maintain low level;
[0046] In the second interval T2, the first signal line V1 is low level can not turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is high level to turn on the second transistor Q2, realizing the first scan line G1 and the third signal line V3 communication, because the third signal line V3 is low level, so the first scan line G1 input low level, also turn on the fifth transistor Q5, realizing the second scan line G2 and the pin line pin1 communication, because the pin line pin1 is low level, so the second scan line G2 input low level, the third signal line V3 is low level can not turn on the third transistor Q3, the sixth transistor Q6 and the seventh transistor Q7, the fourth signal line V4 is high level to turn on the eighth transistor Q8, realizing the third scan line G3 and the third signal line V3 communication, because the third signal line V3 is low level, so the third scan line G3 input low level, that is, the first scan line G1, the second scan line G2, the third scan line G3 all maintain low level;
[0047] In the third interval T3, the first signal line V1 is low and cannot turn on the first transistor Q1 and the fourth transistor Q4, the second signal line V2 is low and cannot turn on the second transistor Q2 and the fifth transistor Q5, the third signal line V3 is high and turns on the third transistor Q3, realizing that the first scan line G1 is in communication with the first signal line V1, since the first signal line V1 is low, the first scan line G1 inputs low level, at the same time, the sixth transistor Q6 is turned on, realizing that the second scan line G2 is in communication with the first signal line V1, since the first signal line V1 is low, the second scan line G2 inputs low level, at the same time, the seventh transistor Q7 is turned on, realizing that the third scan line G3 is in communication with the pin line pin1, since the pin line pin1 is low, the third scan line G3 inputs low level, the fourth signal line V4 is low and cannot turn on the eighth transistor Q8, that is, the first scan line G1, the second scan line G2 and the third scan line G3 all maintain low level.
[0048] Therefore, in the first interval T1, the second interval T2 and the third interval T3, the first scan line G1, the second scan line G2 and the third scan line G3 all maintain low level.
[0049] As an embodiment of the present application, the cycle period of the output signal of the pin line is a second cycle period, the second cycle period covers at least two first cycle periods, and the length of the second cycle period is n times of the first cycle period, n is an integer, the number of pin lines is m, n≥m, and the output of the same level is output in the continuous three intervals in the second cycle period, the length of the second cycle period can be adjusted according to the specific use requirement, preferably, the second cycle period is equal to two first cycle periods, the second cycle period is 6T and is divided into six intervals, the output of the same level is output in the continuous three intervals in the second cycle period, and the output of another level is output in the other three intervals, that is, if the output of high level is output in the continuous three intervals, the output of low level is output in the other three intervals, and if the output of low level is output in the continuous three intervals, the output of high level is output in the other three intervals.
[0050] As an embodiment of the present application, the output signals of the adjacent two pin lines are different by one first cycle period, which can ensure that only one pin line is high and the remaining pin lines are low at the same time, that is, only one scan line outputs high level at the same time, and similarly, the difference of the output signals of the adjacent two pin lines can be adjusted according to the specific use requirement, but the difference of the two should not be less than the first cycle period.
[0051] Working principle: if the pin line has two, pin line pin1 and pin line pin2, the driving signal cycle of the pin line is 6T, pin line pin1 corresponds to the first scan line G1, the second scan line G2, the third scan line G3, pin line pin2 corresponds to the fourth scan line G4, the fifth scan line G5, the sixth scan line G6, in the period T1-T3, pin line pin1 outputs high level, pin line pin2 outputs low level, in the period T4-T6, pin line pin1 outputs low level, pin line pin2 outputs high level;
[0052] If the pin line has three, pin line pin1, pin line pin2 and pin line pin3, the driving signal cycle of the pin line is 9T, pin line pin1 corresponds to the first scan line G1, the second scan line G2, the third scan line G3, pin line pin2 corresponds to the fourth scan line G4, the fifth scan line G5, the sixth scan line G6, pin line pin3 corresponds to the seventh scan line G7, the eighth scan line G8, the ninth scan line G9, in the period T1-T3, pin line pin1 outputs high level, pin line pin2 outputs low level, pin line pin3 outputs low level, in the period T4-T6, pin line pin1 outputs low level, pin line pin2 outputs high level, pin line pin3 outputs low level, in the period T7-T9, pin line pin1 outputs low level, pin line pin2 outputs low level, pin line pin3 outputs high level;
[0053] If the number of pin lines continues to increase, according to the above logic, it can be concluded that if there are m pin lines, the three scan lines corresponding to pin(m) are G(3m-2), G(3m-1) and G(3m), that is, in the period T(3m-2)-T(3m), pin(m) outputs high level, and other pin lines output low level.
[0054] The application provides a display panel, which comprises a display driving chip and the pixel driving circuit, can reduce the use of integrated circuits, does not need to additionally increase a mask, can reduce the overall manufacturing cost, can reduce the occupied area of a non-display area, promotes narrow frame design, meets the demand of consumers for narrow frame, reduces wiring difficulty, and improves work efficiency.
[0055] In summary, the present application provides a pixel driving circuit and a display panel, which adopts a structure of controlling multiple scan lines by one pin line, breaks the conventional design of one-to-one control between the pin line and the scan line, can effectively reduce the number of pin lines, thereby reducing the use of integrated circuits, and does not need to additionally increase the mask, can reduce the overall manufacturing cost, can reduce the occupied area of the non-display area, promotes the narrow frame design, meets the demand of consumers for narrow frame, reduces the wiring difficulty, improves the work efficiency; through the mutual cooperation between the eight transistors and the four signal lines, only one of the three scan lines is high at the same time, and the other two scan lines are all low, which ensures the working stability of the pixel driving circuit; the length of the second cycle period is an integer multiple of the first cycle period, and the high level is output in the continuous three intervals in the second cycle period, which can adjust the length of the second cycle period according to the specific use demand, improve the overall application range, improve the overall reliability and compatibility.
[0056] It should be emphasized that: the above is only the preferred embodiment of the present application, not any form of limitation on the present application, any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application still belongs to the scope of the technical scheme of the present application.
Claims
1. A pixel driving circuit, characterized in that, include: Multiple pixel units, wherein the multiple pixel units are arranged in an array; Multiple scan lines extend along the row direction, and the scan lines are interspersed between two rows of pixel units; At least one pin line, said pin line being electrically connected to the plurality of said scan lines; Multiple signal lines, wherein the multiple signal lines extend along the column direction; A plurality of transistors, wherein the gate of each transistor is electrically connected to a signal line, the first end of each transistor is electrically connected to a scan line, and the second end of each transistor is electrically connected to a signal line or a pin line, wherein the number of transistors connected to the pin lines is equal to the number of scan lines; One of the pin lines is electrically connected to three of the scan lines; Eight transistors are disposed between the three scan lines and the pin lines. The three scan lines are designated as a first scan line, a second scan line, and a third scan line. The eight transistors are designated as a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. There are four signal lines, designated as a first signal line, a second signal line, a third signal line, and a fourth signal line. The first terminal of the first transistor is electrically connected to the first scan line, the second terminal is electrically connected to the pin line, and the gate is electrically connected to the first signal line. The first terminal of the second transistor is electrically connected to the first scan line, the second terminal is electrically connected to the third signal line, and the gate is electrically connected to the second signal line. The first terminal of the third transistor is electrically connected to the first scan line. The first transistor has one end electrically connected to the first signal line, and its gate is electrically connected to the third signal line; the second transistor has one end electrically connected to the second scan line, and its second end electrically connected to the second signal line, and its gate is electrically connected to the first signal line; the fifth transistor has one end electrically connected to the second scan line, and its second end electrically connected to the pin line, and its gate is electrically connected to the second signal line; the sixth transistor has one end electrically connected to the second scan line, and its second end electrically connected to the first signal line, and its gate is electrically connected to the third signal line; the seventh transistor has one end electrically connected to the third scan line, its second end electrically connected to the pin line, and its gate is electrically connected to the third signal line; the eighth transistor has one end electrically connected to the third scan line, its second end electrically connected to the third signal line, and its gate is electrically connected to the fourth signal line.
2. The pixel driving circuit according to claim 1, characterized in that, When one of the scan lines outputs a high level, the other two scan lines remain at a low level.
3. The pixel driving circuit according to claim 1, characterized in that, The cycle period of the output signal of the four signal lines is the first cycle period, which is 3T. The first cycle period is divided into three intervals, including the first interval, the second interval, and the third interval.
4. The pixel driving circuit according to claim 3, characterized in that, Within the first interval, the first signal line is at a high level, the second signal line is at a low level, the third signal line is at a low level, and the fourth signal line is at a high level; within the second interval, the first signal line is at a low level, the second signal line is at a high level, the third signal line is at a low level, and the fourth signal line is at a high level; within the third interval, the first signal line is at a low level, the second signal line is at a low level, the third signal line is at a high level, and the fourth signal line is at a low level.
5. The pixel driving circuit according to claim 4, characterized in that, The output signal of the pin line has a cycle period of a second cycle period, which covers at least two of the first cycle periods. The second cycle period is n times the first cycle period, where n is an integer. Within the second cycle period, three consecutive intervals are output with a high level.
6. The pixel driving circuit according to claim 5, characterized in that, The number of pins is m, where n ≥ m.
7. The pixel driving circuit according to claim 6, characterized in that, The output signals of two adjacent pin lines differ by one of the first cycle periods.
8. The pixel driving circuit according to claim 7, characterized in that, There are two pin lines. The second cycle is equal to two of the first cycle. The second cycle is 6T and is divided into six intervals. Within the second cycle, three consecutive intervals output the same level, and the other three intervals output a different level.
9. A display panel, characterized in that, It includes a display driver chip and a pixel driver circuit as described in any one of claims 1-8.
Citation Information
Patent Citations
Drive circuit and drive method of LCD device
CN101329484A
Scanning driving circuit and display panel
CN104217694A
Flat panel display device
KR1020120131463A
Flat panel display
US20090079669A1