Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. According to an embodiment of the present disclosure, a display device may include an active layer, a gate electrode disposed on the active layer, a first insulating layer disposed on the gate electrode, fully covering the gate electrode, and including a flat surface, and a second insulating layer disposed on the first insulating layer and including a flat surface, and the first insulating layer and the second insulating layer may include inorganic materials different from each other.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] The display device may include a pixel circuit layer including a pixel circuit. The pixel circuit may include a semiconductor layer and an electrode. The semiconductor layer and the electrode may be electrically connected to each other through a contact hole structure passing through an insulating layer included in the pixel circuit layer.

[0003] When the thickness of the pixel circuit layer increases, the etching depth for forming the contact hole structure may increase. In this case, it may be difficult to properly form the contact hole structure. For example, when the etching depth for forming the contact hole structure increases, it may be difficult to apply the etching process to the desired area.

[0004] Accordingly, research into reducing the etching depth for forming a contact hole structure is being conducted. Summary of the invention

[0005] A feature of the present disclosure is to provide a display device capable of reducing an etching depth for forming a contact hole structure and a method of manufacturing the display device.

[0006] According to an embodiment of the present disclosure, a display device may include an active layer, a gate electrode disposed on the active layer, a first insulating layer disposed on the gate electrode, completely covering the gate electrode and including a flat surface, and a second insulating layer disposed on the first insulating layer and including a flat surface. The first insulating layer and the second insulating layer may include inorganic materials different from each other.

[0007] According to an embodiment of the present disclosure, the active layer and the gate electrode may be spaced apart from each other. The display device may further include a first gate insulating layer and a second gate insulating layer disposed on the active layer. The gate electrode may include a first gate electrode disposed on the first gate insulating layer and a second gate electrode disposed on the second gate insulating layer.

[0008] According to an embodiment of the present disclosure, the flat surface of the first insulating layer may not have a step difference.

[0009] According to an embodiment of the present disclosure, a flat surface of the first insulating layer may face the second insulating layer.

[0010] According to an embodiment of the present disclosure, the first insulating layer may be directly disposed on the second gate electrode.

[0011] According to an embodiment of the present disclosure, the flat surface of the first insulating layer does not contact the second gate electrode.

[0012] According to an embodiment of the present disclosure, the first insulating layer may include silicon oxide, and the second insulating layer may include silicon nitride.

[0013] According to an embodiment of the present disclosure, the display device may further include an interlayer conductive layer disposed on the second insulating layer, and one surface and the other surface of the interlayer conductive layer may be flat.

[0014] According to an embodiment of the present disclosure, the interlayer conductive layer may include a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, and the first layer may contact the second insulating layer.

[0015] According to an embodiment of the present disclosure, the first layer and the third layer may include the same material, the second layer may include a material different from those of the first layer and the third layer, and the second layer may include aluminum.

[0016] According to an embodiment of the present disclosure, a method for manufacturing a display device may include patterning an active layer on a substrate layer, patterning a gate electrode on the active layer, depositing a pre-polished insulating layer on the gate electrode, polishing the pre-polished insulating layer to form a first insulating portion, and forming a second insulating portion on the first insulating portion. The first insulating portion and the second insulating portion may form a first insulating layer. Patterning the gate electrode on the active layer may include forming a first gate electrode and forming a second gate electrode on the first gate electrode. The first gate electrode and the second gate electrode may be spaced apart from the active layer. When the pre-polished insulating layer is deposited on the gate electrode, the pre-polished insulating layer may contact the second gate electrode.

[0017] According to an embodiment of the present disclosure, when the pre-polished insulating layer is polished to form the first insulating portion, the pre-polished insulating layer may be polished using a polishing device and a slurry, and the first insulating portion may form a flat polished surface.

[0018] According to an embodiment of the present disclosure, the method may further include forming a second insulating layer on the second insulating portion and forming an interlayer conductive layer on the second insulating layer. When the interlayer conductive layer is formed on the second insulating layer, the interlayer conductive layer may be etched by an etching solution including chlorine radicals.

[0019] According to an embodiment of the present disclosure, when a pre-polishing insulating layer is deposited on the gate electrode, the pre-polishing insulating layer may be deposited to have to Thickness.

[0020] According to an embodiment of the present disclosure, when the pre-polished insulating layer is polished to form the first insulating portion, the pre-polished insulating layer may be polished to form a flat polished surface, and the flat polished surface may be disposed on a different plane from one surface of the second gate electrode.

[0021] According to an embodiment of the present disclosure, the slurry may include silicon dioxide, and the pre-polished insulating layer may be polished within a predetermined polishing period.

[0022] According to an embodiment of the present disclosure, when the pre-polished insulating layer is polished to form the first insulating portion, the first insulating portion may be polished to have a thickness of 0.04mm in a region overlapping the first gate electrode and the second gate electrode. to Thickness.

[0023] According to an embodiment of the present disclosure, when the pre-polished insulating layer is polished to form the first insulating portion, the pre-polished insulating layer may be polished to form a flat polished surface, and the flat polished surface may be disposed on the same plane as one surface of the second gate electrode.

[0024] The slurry may include ceria.

[0025] The first insulating layer may include silicon oxide, and a ratio of selectivity of the slurry to the second gate electrode to selectivity of the slurry to the silicon oxide may be 1:30 to 1:50.

[0026] According to an embodiment of the present disclosure, a display device capable of reducing an etching depth for forming a contact hole structure and a method of manufacturing the display device may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a plan view schematically illustrating a display device according to an embodiment.

[0028] Figure 2 is a cross-sectional view schematically illustrating a display device according to an embodiment.

[0029] Figure 3 A schematic cross-sectional view for explaining a display device according to a first embodiment.

[0030] Figure 4 A schematic cross-sectional view for explaining the arrangement relationship between the interlayer conductive layer and the second insulating layer.

[0031] Figure 5 A flowchart for explaining a method of manufacturing a display device according to an embodiment.

[0032] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 Schematic cross-sectional views of each manufacturing process operation of the display device according to the first embodiment.

[0033] Fig.14 is a schematic cross-sectional view of a display device according to a second embodiment.

[0034] Fig.15 , Fig.16 and Fig.17 Schematic cross-sectional views of each manufacturing process operation of the display device according to the second embodiment. DETAILED DESCRIPTION

[0035] The present disclosure can be modified in various ways and have various forms. Therefore, specific embodiments will be illustrated in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific form disclosed, and the present disclosure includes all modifications, equivalents and alternatives within the spirit and technical scope of the present disclosure.

[0036] Terms such as "first" and "second" may be used to describe various components, but these components should not be limited by these terms. These terms are only used for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. In the following description, unless the context clearly indicates otherwise, a singular expression also includes a plural expression.

[0037] It should be understood in the present application that the terms "including" or "having" are used to indicate the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of pre-existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. In addition, the case where a portion of a layer, region, plate, etc. is referred to as "on" another portion not only includes the case where the portion is "directly on" another portion, but also includes the case where there is a further another portion between the portion and the other portion. In addition, in the present specification, when a portion of a layer, region, plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or in the lower direction. On the contrary, when a portion of a layer, region, plate, etc. is formed "below" another portion, this not only includes the case where the portion is "directly below" another portion, but also includes the case where there is a further another portion between the portion and the other portion.

[0038] The present disclosure relates to a display device and a method of manufacturing the display device. Hereinafter, a display device and a method of manufacturing the display device according to an embodiment are described with reference to the accompanying drawings.

[0039] Figure 1 is a plan view schematically illustrating a display device DD according to an embodiment. Figure 2 is a cross-sectional view schematically illustrating a display device DD according to an embodiment.

[0040] Below, reference Figure 1 and Figure 2, schematically describes a display device DD according to an embodiment of the present disclosure.

[0041] refer to Figure 1 , the display device DD is configured to emit light. The display device DD includes a light-emitting element. According to an embodiment of the present disclosure, the display device DD may be a device for displaying a moving image or a still image. The display device DD may be used as a display screen for various products (including not only portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebook computers, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs)), but also televisions, notebook computers, monitors, billboards, and Internet of Things (IOT) devices). However, the application field of the display device DD is not limited to specific examples.

[0042] The display device DD may be formed in a plane into a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The angle at which the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be formed into a rounded angle having a predetermined curvature, or may be formed into a right angle. The planar shape of the display device DD is not limited to a quadrilateral, and may be formed into another polygon, or may be formed into a circular shape (e.g., a circle or an ellipse). The display device DD may be formed to be flat, but is not limited thereto. For example, the display device DD may include a curved portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device DD may be flexibly formed to be twisted, curved, bent, folded, or rolled up.

[0043] In the present disclosure, the first direction DR1 may be a row direction of pixels PXL and may be a "horizontal" direction. The second direction DR2 may be a column direction of pixels PXL. The third direction DR3 may be a display direction of the display device DD or a normal direction of a plane on which the base layer BSL is disposed.

[0044] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may mean an area other than the display area DA. The non-display area NDA may surround at least a portion of the display area DA.

[0045] The display area DA may mean an area in which the pixels PXL are disposed. The non-display area NDA may mean an area in which no pixels PXL are disposed. A driving circuit unit, lines, and pads connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0046] According to an embodiment of the present disclosure, a pixel PXL (or a sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form a pixel unit PXU capable of emitting light of various colors. Figure 1 In the embodiment, an embodiment in which each pixel PXL includes three sub-pixels SPX1 , SPX2 , and SPX3 (ie, a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 ) is exemplified, but the embodiments of the present specification are not limited thereto.

[0047] According to an embodiment of the present disclosure, the The arrangement structure etc. arranges the pixels PXL (or sub-pixels SPX). However, the present disclosure is not necessarily limited thereto.

[0048] The first subpixel SPX1 may emit a first light, the second subpixel SPX2 may emit a second light, and the third subpixel SPX3 may emit a third light. Here, the first light may be light of a red wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600 nm to about 750 nm, the green wavelength band may be a wavelength band of about 480 nm to about 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to about 460 nm, but the embodiments of the present specification are not limited thereto.

[0049] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include an inorganic light emitting element (including an inorganic semiconductor) or an organic light emitting element (organic light emitting diode (OLED)) as a light emitting element emitting light. However, the present disclosure is not limited to specific examples.

[0050] refer to Figure 2 , the display device DD may include a pixel circuit layer PCL and a light emitting element layer LEL.

[0051] The pixel circuit layer PCL may be a layer including a pixel circuit for driving a light emitting element. The pixel circuit layer PCL may include a base layer BSL, a conductive layer for forming the pixel circuit, and an insulating layer disposed between the conductive layers.

[0052] The base layer BSL may form a base member of the display device DD. The base layer BSL may be a rigid substrate or a flexible substrate or a flexible film. For example, the base layer BSL may be a rigid substrate formed of glass (e.g., tempered glass), a flexible substrate (or film) formed of a plastic or metal material, or at least one insulating layer. According to an embodiment of the present disclosure, the base layer BSL may include silicon (Si). The material and / or physical properties of the base layer BSL are not specifically limited. According to an embodiment of the present disclosure, the base layer BSL may be substantially transparent. Here, "substantially transparent" may mean that light can be transmitted at one or more transmittances. In an embodiment, the base layer BSL may be translucent or opaque. In addition, the base layer BSL may include a reflective material according to an embodiment. For example, the reflective material may include at least one of Ag, Al, Au, Pt, and Ti. However, the present disclosure is not limited thereto.

[0053] According to an embodiment of the present disclosure, a pixel circuit may include a thin film transistor and may be electrically connected to a light emitting element to provide an electrical signal for the light emitting element to emit light.

[0054] The light emitting element layer LEL may be disposed on the pixel circuit layer PCL. The light emitting element included in the light emitting element layer LEL may include an inorganic light emitting element or an organic light emitting element. The light emitting element may be electrically connected to the pixel circuit included in the pixel circuit layer PCL.

[0055] Below, reference Figure 3 and Figure 4 A display device according to a first embodiment is described.

[0056] Figure 3 Schematic cross-sectional view for explaining the display device DD according to the first embodiment. Figure 3 2 may be a schematic cross-sectional view illustrating a pixel circuit layer PCL of a display device DD. Figure 4 A schematic cross-sectional view for explaining the arrangement relationship between the interlayer conductive layer SD and the second insulating layer IL2. Figure 4 To explain Figure 3 1 is a schematic enlarged view of an S1 region of FIG. 1 , and may be a diagram explaining an example of a stacking structure of an interlayer conductive layer SD.

[0057] refer to Figure 3 , the pixel circuit layer PCL may include a base layer BSL, an active layer ACT, a gate electrode GAT, a gate insulating layer GI, an insulating layer IL, an interlayer conductive layer SD, a contact hole CNT, and a capping layer VIA.

[0058] The active layer ACT may be disposed on the base layer BSL. According to another embodiment of the present disclosure, a buffer layer including an inorganic material may be disposed on the base layer BSL, and the active layer ACT may be disposed on the buffer layer.

[0059] According to an embodiment of the present disclosure, the active layer ACT may include one or more of an oxide semiconductor, an inorganic semiconductor, and an organic semiconductor. According to an embodiment of the present disclosure, the oxide semiconductor may include an oxide including at least one of the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). According to an embodiment of the present disclosure, the inorganic semiconductor may include amorphous silicon and polycrystalline silicon, etc. However, the present disclosure is not limited thereto.

[0060] The active layer ACT may include a source region electrically connected to the source electrode, a drain region electrically connected to the drain electrode, and a channel region between the source region and the drain region.

[0061] The active layer ACT may have to However, the present disclosure is not limited thereto. In the present disclosure, the thickness of the structure of the display device DD described below is not limited to the numerical range described in the present disclosure.

[0062] The gate insulating layer GI, the gate electrode GAT, and the insulating layer IL may be disposed on the active layer ACT. The gate insulating layer GI may include a first gate insulating layer GI1 and a second gate insulating layer GI2. The gate electrode GAT may include a first gate electrode GAT1 and a second gate electrode GAT2. The gate electrode GAT may be spaced apart from the active layer ACT. The insulating layer IL may include a first insulating layer IL1 and a second insulating layer IL2.

[0063] The first gate insulating layer GI1 may be disposed on the active layer ACT. The first gate insulating layer GI1 may be disposed between the active layer ACT and the first gate electrode GAT1. The first gate insulating layer GI1 may contact the active layer ACT. The first gate insulating layer GI1 may completely cover the active layer ACT.

[0064] The first gate insulating layer GI1 may include an inorganic material. For example, the first gate insulating layer GI1 may include silicon oxide (SiO x ). The first gate insulating layer GI1 may have a thickness thicker than that of the active layer ACT. For example, the first gate insulating layer GI1 may have a thickness of to The thickness is within the range of .

[0065] The first gate electrode GAT1 may be disposed on the first gate insulating layer GI1. The first gate electrode GAT1 may contact the first gate insulating layer GI1. In a plan view, the first gate electrode GAT1 may overlap at least a portion of the first gate insulating layer GI1.

[0066] The first gate electrode GAT1 may be formed as a single layer or a plurality of layers formed of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and / or oxides thereof and / or alloys thereof.

[0067] The first gate electrode GAT1 may have to The thickness is within the range of .

[0068] The second gate insulating layer GI2 may be disposed on the first gate electrode GAT1. The second gate insulating layer GI2 may contact the first gate electrode GAT1 and the first gate insulating layer GI1. The second gate insulating layer GI2 may completely cover the first gate electrode GAT1 and the first gate insulating layer GI1.

[0069] The second gate insulating layer GI2 may include an inorganic material. The second gate insulating layer GI2 may include a material different from that of the first gate insulating layer GI1. For example, the second gate insulating layer GI2 may include silicon nitride (SiN x ). The second gate insulating layer GI2 may have a thickness thicker than that of the active layer ACT. For example, the second gate insulating layer GI2 may have a thickness of to The thickness is within the range of .

[0070] The second gate electrode GAT2 may be disposed on the second gate insulating layer GI2. The second gate electrode GAT2 may contact the second gate insulating layer GI2. In a plan view, the second gate electrode GAT2 may overlap at least a portion of the second gate insulating layer GI2.

[0071] The second gate electrode GAT2 may be formed as a single layer or a plurality of layers formed of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and / or oxides thereof and / or alloys thereof.

[0072] The second gate electrode GAT2 may have to However, the present disclosure is not limited thereto.

[0073] The first insulating layer IL1 may be disposed on the second gate electrode GAT2. The first insulating layer IL1 may contact the second gate electrode GAT2 and the second gate insulating layer GI2. The first insulating layer IL1 may completely cover the second gate electrode GAT2 and the second gate insulating layer GI2.

[0074] The first insulating layer IL1 may include a flat surface (e.g., an upper surface). For example, an upper surface of the first insulating layer IL1 adjacent to the second insulating layer IL2 (as one surface of the first insulating layer IL1) may be substantially flat. For example, one surface of the first insulating layer IL1 (e.g., a surface that does not contact the second gate electrode GAT2) may be flat. One surface of the first insulating layer IL1 may not have a step difference.

[0075] The first insulating layer IL1 may include an inorganic material. For example, the first insulating layer IL1 may include silicon oxide (SiO x ).

[0076] The first insulating layer IL1 may include a first insulating portion P1 and a second insulating portion P2. The first insulating portion P1 and the second insulating portion P2 may be portions including the same material and may offset a step difference formed by an electrode pattern layer (eg, a gate electrode GAT and a gate insulating layer GI) in the pixel circuit layer PCL. According to an embodiment of the present disclosure, the first insulating portion P1 and the second insulating portion P2 may be formed in different processes. Figure 6 This is described in the following figures.

[0077] The first insulating portion P1 may have a first thickness d1. The first thickness d1 may be a thickness defined in a partial region of the first insulating layer IL1, and may be a thickness of a region of the first insulating portion P1 that overlaps both the first gate electrode GAT1 and the second gate electrode GAT2 in a plan view. According to an embodiment of the present disclosure, the first thickness d1 may be to

[0078] The second insulating portion P2 may have a second thickness d2. The second thickness d2 may be a thickness defined in a partial region of the first insulating layer IL1, and may be a thickness of a region of the second insulating portion P2 overlapping both the first gate electrode GAT1 and the second gate electrode GAT2 in a plan view. The second thickness d2 may be greater than the first thickness d1. According to an embodiment of the present disclosure, the second thickness d2 may be to

[0079] The second insulating portion P2 and the first insulating portion P1 may be defined based on a virtual surface. The virtual surface may be defined during a process. The virtual surface may be a polishing surface Q (refer to Figure 8 The virtual surface may be a flat surface. The virtual surface may be parallel to one surface (eg, an upper surface) of the second gate electrode GAT2.

[0080] The polishing surface Q according to the first embodiment may be disposed on a plane different from one surface of the second gate electrode GAT2.

[0081] The second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may contact the first insulating layer IL1. The second insulating layer IL2 may completely cover the first insulating layer IL1. The second insulating layer IL2 may include one surface and another surface that are flat. The second insulating layer IL2 may completely contact the first insulating layer IL1. In a plan view, the second insulating layer IL2 may completely overlap the first insulating layer IL1. One surface of the first insulating layer IL1 may face the second insulating layer IL2.

[0082] The second insulating layer IL2 may include an inorganic material. The second insulating layer IL2 may include an inorganic material different from that of the first insulating layer IL1. For example, the second insulating layer IL2 may include silicon nitride (SiN x ). The second insulating layer IL2 may have to Thickness.

[0083] The interlayer conductive layer SD may be disposed on the second insulating layer IL2. The interlayer conductive layer SD may contact the second insulating layer IL2. In a plan view, the interlayer conductive layer SD may overlap at least a portion of the second insulating layer IL2.

[0084] Because the other surface of the second insulating layer IL2 is flat, the interlayer conductive layer SD disposed on the second insulating layer IL2 may include a flat one surface, that is, a flat surface. The interlayer conductive layer SD may include a flat other surface, that is, another flat surface. For example, the surface of the interlayer conductive layer SD contacting the second insulating layer IL2 may be flat. The surface of the interlayer conductive layer SD spaced apart from the second insulating layer IL2 may be flat.

[0085] According to experiments, when the interlayer conductive layer SD is deposited on an uneven surface, the interlayer conductive layer SD may be formed to a non-uniform thickness. According to experiments, when the thickness of the interlayer conductive layer SD is non-uniform, the line width roughness of the interlayer conductive layer SD may be increased. On the other hand, since the interlayer conductive layer SD according to the present disclosure is deposited on the flat second insulating layer IL2, the interlayer conductive layer SD may have a uniform thickness. The interlayer conductive layer SD may form a substantially uniform step difference. Accordingly, the interlayer conductive layer SD of the display device DD according to the present disclosure may reduce the line width roughness.

[0086] The interlayer conductive layer SD may include a source electrode and a drain electrode. The interlayer conductive layer SD may be formed as a single layer or multiple layers formed of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) and / or oxides thereof and / or alloys thereof.

[0087] At least a portion of the interlayer conductive layer SD may be electrically connected to the active layer ACT through the contact hole CNT of the pixel circuit layer PCL. At least a portion of the interlayer conductive layer SD may be electrically connected to the active layer ACT through the contact hole CNT passing through the first insulating layer IL1, the second insulating layer IL2, the first gate insulating layer GI1, and the second gate insulating layer GI2.

[0088] The capping layer VIA may be disposed on the interlayer conductive layer SD. The capping layer VIA may completely cover the interlayer conductive layer SD. The capping layer VIA may contact the interlayer conductive layer SD.

[0089] The capping layer VIA may include an organic material. For example, the organic material may include one or more of the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0090] The display device DD according to the embodiment of the present disclosure may include a pixel circuit layer PCL with a reduced stack thickness. As the stack thickness of the pixel circuit layer PCL is reduced, the etching depth of the hole H for forming the contact hole CNT of the pixel circuit layer PCL may be reduced. Figure 6 This is described in the following figures.

[0091] refer to Figure 4 According to an embodiment of the present disclosure, the interlayer conductive layer SD may have a multi-layer structure including a first layer L1, a second layer L2, and a third layer L3.

[0092] The first layer L1 and the third layer L3 may include the same material. The first layer L1 and the third layer L3 may include a material different from that of the second layer L2. For example, the first layer L1 may include titanium (Ti), the second layer L2 may include aluminum (Al), and the third layer L3 may include titanium (Ti).

[0093] However, the present disclosure is not limited to the above examples. Hereinafter, for convenience of description, the present disclosure is described based on an embodiment in which the interlayer conductive layer SD includes: a first layer L1 including titanium (Ti), a second layer L2 including aluminum (Al), and a third layer L3 including titanium (Ti).

[0094] The first layer L1 may contact the second insulating layer IL2. A lower surface of the first layer L1 may contact an upper surface of the second insulating layer IL2. The first layer L1 may be disposed in the hole H.

[0095] The second layer L2 may be spaced apart from the second insulating layer IL2. The second layer L2 may not contact the second insulating layer IL2. One surface (e.g., upper surface) of the second layer L2 may not contact the first layer L1. Another surface (e.g., lower surface) of the second layer L2 may contact the first layer L1. The second layer L2 may not be disposed in the hole H.

[0096] The third layer L3 may be spaced apart from the second insulating layer IL2. The third layer L3 may not contact the second insulating layer IL2. One surface (e.g., upper surface) of the third layer L3 may not contact the second layer L2. Another surface (e.g., lower surface) of the third layer L3 may contact the second layer L2. The third layer L3 may not be disposed in the hole H.

[0097] Below, reference Figures 5 to 13 A method of manufacturing the display device according to the first embodiment is described. The contents overlapping with the above contents are not described repeatedly or are briefly described.

[0098] Figure 5 A flowchart for explaining a method of manufacturing a display device DD according to an embodiment. Figures 6 to 13 Schematic cross-sectional views of each manufacturing process operation of the display device DD according to the first embodiment. Figures 6 to 13 FIG. 5 is a diagram illustrating the pixel circuit layer PCL of the display device DD in more detail.

[0099] refer to Figure 5 , the method of manufacturing the display device DD may include patterning a gate electrode and a gate insulating layer on the active layer in operation S100, depositing a pre-polished insulating layer on the gate electrode in operation S200, forming a first insulating portion of a first insulating layer by polishing the pre-polished insulating layer in operation S300, forming a second insulating portion of the first insulating layer on the first insulating portion in operation S400, forming a second insulating layer on the second insulating portion in operation S500, and forming an interlayer conductive layer on the second insulating layer in operation S600.

[0100] refer to Figure 5 and Figure 6 When the gate electrode and the gate insulating layer are patterned on the active layer in operation S100, a base layer BSL may be prepared. The active layer ACT may be patterned on the base layer BSL, and the gate electrode GAT and the gate insulating layer GI may be formed on the active layer ACT.

[0101] Forming the gate electrode GAT may include forming first and second gate electrodes GAT1 and GAT2 spaced apart from the active layer ACT on the active layer ACT. Forming the gate insulating layer GI may include forming first and second gate insulating layers GI1 and GI2.

[0102] A first gate insulating layer GI1 may be formed on the active layer ACT. The first gate insulating layer GI1 may be deposited on the active layer ACT to completely cover the active layer ACT. In an embodiment, one or more of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be used as a process for depositing the structure of the display device DD. However, the embodiment is not limited to a specific example.

[0103] The first gate electrode GAT1 may be formed on the first gate insulating layer GI1. The first gate electrode GAT1 may be deposited and etched on the first gate insulating layer GI1. In an embodiment, one or more of wet etching and dry etching may be used as a process of etching the structure of the display device DD. However, the embodiment is not limited to a specific example.

[0104] A second gate insulating layer GI2 may be formed on the first gate electrode GAT1. The second gate insulating layer GI2 may be deposited to completely cover the first gate electrode GAT1 and the first gate insulating layer GI1.

[0105] The second gate electrode GAT2 may be formed on the second gate insulating layer GI2. The second gate electrode GAT2 may be deposited and etched on the second gate insulating layer GI2.

[0106] When the pre-polishing insulating layer is deposited on the gate electrode in operation S200, the pre-polishing insulating layer 50 may be deposited on the second gate electrode GAT2. The pre-polishing insulating layer 50 may be deposited to completely cover the second gate electrode GAT2 and the second gate insulating layer GI2. The pre-polishing insulating layer 50 may be directly deposited on the second gate electrode GAT2. The pre-polishing insulating layer 50 may contact the second gate electrode GAT2.

[0107] The pre-polishing insulating layer 50 may be deposited on the second gate electrode GAT2 to have a substantially uniform pre-polishing thickness d3. The pre-polishing thickness d3 may correspond to a step difference between the active layer ACT and the second gate electrode GAT2. For example, the pre-polishing thickness d3 may be a distance from a surface (e.g., an upper surface) of the pre-polishing insulating layer 50 that does not contact the second gate insulating layer GI2 to a surface (e.g., an upper surface) of the second gate insulating layer GI2 that does not contact the first gate insulating layer GI1 in the third direction DR3. As another example, the pre-polishing thickness d3 may be a distance from a surface (e.g., an upper surface) of the pre-polishing insulating layer 50 that does not contact the second gate electrode GAT2 to a surface (e.g., a lower surface) of the second gate electrode GAT2 that overlaps with the first gate electrode GAT1 and does not contact the second gate insulating layer GI2 in the third direction DR3. According to an embodiment of the present disclosure, the pre-polishing thickness d3 may be to

[0108] The pre-polished insulating layer 50 may be polished to form a portion of the first insulating layer IL1 (eg, a first insulating portion P1) (refer to Figure 8 ). A portion of the pre-polished insulating layer 50 may form a portion of the first insulating layer IL1. In the present disclosure, before a chemical mechanical polishing (CMP) process is performed, the pre-polished insulating layer 50 may be defined as the first insulating layer IL1.

[0109] The pre-polishing insulating layer 50 may include an inorganic material. The pre-polishing insulating layer 50 may include the same material as the first insulating layer IL1. For example, the pre-polishing insulating layer 50 may include silicon oxide (SiO x ).

[0110] refer to Figure 5 , Figure 7 and Figure 8 When the first insulating portion of the first insulating layer is formed by polishing the pre-polished insulating layer in operation S300 , the pre-polished insulating layer 50 may be polished by the polishing apparatus 100 and the first slurry SLR1 .

[0111] The polishing device 100 may determine the polishing endpoint of the polishing process by adjusting the polishing time, etc. The first slurry SLR1 may assist the polishing of the polishing device 100. For example, the first slurry SLR1 may include abrasive particles, and when the abrasive particles contact the structure of the display device DD, friction is generated to mechanically polish the structure of the display device DD. Alternatively, the abrasive particles may chemically react with some structures in the display device DD to chemically polish the structure of the display device DD.

[0112] The pre-polished insulating layer 50 may be polished to have a first thickness d1 in a partial region (eg, in a region overlapping with both the first gate electrode GAT1 and the second gate electrode GAT2). The first thickness d1 may be to The pre-polishing insulating layer 50 may be polished to form a flat polishing surface Q. The pre-polishing insulating layer 50 may be planarized. The polishing surface Q may be spaced apart from the second gate electrode GAT2.

[0113] The pre-polished insulating layer 50 may be polished to form the first insulating portion P1 of the first insulating layer IL1. In the display device DD according to an embodiment of the present disclosure, the pre-polished insulating layer 50 may be directly disposed on the second gate electrode GAT2, and a structure directly disposed on the second gate electrode GAT2 (eg, the pre-polished insulating layer 50) may be polished.

[0114] In a conventional display structure, an additional unpolished insulating layer is directly disposed on the second gate electrode GAT2, and a pre-polished insulating layer 50 as a subject of a polishing process is disposed on the unpolished insulating layer. Accordingly, the thickness of the pixel circuit layer PCL is increased, and the etching depth for forming the hole H in the pixel circuit layer PCL is increased.

[0115] In addition, in a conventional display structure, the insulating layer disposed under the pre-polishing insulating layer 50 is formed at the outermost portion to determine the end point of the polishing process of the polishing device 100, and includes a polishing auxiliary layer including silicon nitride (SiN xFor example, the polishing slurry used to manufacture conventional display structures includes silicon oxide (SiO x ) is more selective than layers including silicon nitride (SiN x ) layers. When polishing a layer including silicon oxide (SiO x ) of the pre-polished insulating layer 50 and then exposing the silicon nitride (SiN x ), the polishing apparatus 100 senses a change in frictional force caused by the polishing slurry, or an optical sensor that may be included in the polishing apparatus 100 senses an interference shape of a wavelength according to a change in thickness of a film on which the polishing process is performed. At this time, polishing is stopped. For example, when the pre-polishing insulating layer 50 is polished and then the silicon nitride (SiN x ), the friction force applied to the polishing device 100 is increased. Accordingly, when the current for driving the polishing device 100 is increased, the change in the current is sensed, and polishing is stopped. In addition, for example, when the polishing device 100 further includes an optical sensor, the optical sensor is based on the silicon nitride (SiN x )'s thickness change between the polishing assist layer and the pre-polishing insulating layer 50 senses the interference shape of the reflected wavelength, and so the polishing is stopped.

[0116] In order to expose silicon nitride (SiN x ) polishing auxiliary layer, and provide conventional polishing slurry as a polishing auxiliary layer with silicon nitride (SiN x ) compared to silicon oxide (SiO x ) has a relatively high selectivity functional slurry. And the functional slurry has a relatively high selectivity for silicon nitride (SiN x ) selectivity and functional slurry for silicon oxide (SiO x ) has a selectivity ratio of 1:30 to 1:50.

[0117] In the display device DD according to the embodiment of the present disclosure, the pre-polishing insulating layer 50 may be directly disposed on the second gate electrode GAT2, and the polishing auxiliary layer may not be disposed between the second gate electrode GAT2 and the pre-polishing insulating layer 50. Since the polishing auxiliary layer is not disposed, the pre-polishing insulating layer 50 may be polished by adjusting the polishing time of the polishing device 100, etc. For example, the pre-polishing insulating layer 50 may be polished within a predetermined polishing period of time.

[0118] In addition, since the polishing auxiliary layer is not provided under the pre-polishing insulating layer 50, the first slurry SLR1 used in manufacturing the display device DD according to the embodiment of the present disclosure may not be provided as a functional slurry. For example, the first slurry SLR1 may not be considered to have any effect on silicon oxide (SiO x) other than the first slurry SLR1 can polish a large amount of silicon oxide (SiO x ), and can polish large or small amounts of silicon nitride (SiN x ). Because the first slurry SLR1 does not consider the effect of silicon oxide (SiO x ), the polishing apparatus 100 may not require additional time to sense changes in frictional force, thereby reducing the polishing process time.

[0119] According to an embodiment of the present disclosure, the first slurry SLR1 may include cerium dioxide (CeO 2 ) and silicon dioxide (SiO 2 ) is one or more of the group consisting of. However, the present disclosure is not limited thereto.

[0120] refer to Figure 5 , Fig. 9 and Fig.10 When the second insulating portion of the first insulating layer is formed on the first insulating portion in operation S400 , the second insulating portion P2 of the first insulating layer IL1 may be deposited on the first insulating portion P1 of the first insulating layer IL1 .

[0121] As the second insulating portion P2 of the first insulating layer IL1 is further deposited, the first insulating layer IL1 can separate the second gate electrode GAT2 and the interlayer conductive layer SD (refer to Fig.12 ) are separated by an appropriate distance, and the second gate electrode GAT2 may be insulated from the interlayer conductive layer SD. When the second insulating portion P2 is not further deposited, the distance between the second gate electrode GAT2 and the interlayer conductive layer SD may be too close, and the second gate electrode GAT2 and the interlayer conductive layer SD may not be insulated.

[0122] Since the second insulating portion P2 is deposited after the pre-polished insulating layer 50 is planarized to form the first insulating portion P1, the second insulating portion P2 may include a flat surface. For example, one surface of the second insulating portion P2 (e.g., an upper surface or surface that does not contact the first insulating portion P1) and another surface (e.g., a lower surface or surface that contacts the first insulating portion P1) may be flat.

[0123] The second insulating portion P2 may be deposited to have a substantially uniform second thickness d2. The second thickness d2 may be thicker than the first thickness d1. For example, the second thickness d2 may be to Since the second thickness d2 is thicker than the first thickness d1, the second gate electrode GAT2 and the interlayer conductive layer SD may be separated by an appropriate distance, and the second gate electrode GAT2 and the interlayer conductive layer SD may be insulated.

[0124] When forming the second insulating layer on the second insulating portion in operation S500, the second insulating layer IL2 may be formed on the second insulating portion P2 of the first insulating layer IL1. The second insulating layer IL2 may be deposited on the second insulating portion P2 of the first insulating layer IL1. The second insulating layer IL2 may completely cover the second insulating portion P2.

[0125] Since the second insulating portion P2 includes a flat surface, the second insulating layer IL2 deposited on the second insulating portion P2 may also include a flat surface. For example, one surface (e.g., an upper surface or surface that does not contact the first insulating layer IL1) and another surface (e.g., a lower surface or surface that contacts the first insulating layer IL1) of the second insulating layer IL2 may be flat.

[0126] refer to Fig.11 , when the interlayer conductive layer is formed on the second insulating layer in operation S600, a hole H may be formed. The hole H may be formed by etching at least a portion of the pixel circuit layer PCL. The hole H may be formed to pass through the second insulating layer IL2, the first insulating layer IL1, the second gate insulating layer GI2, and the first gate insulating layer GI1. At least a portion of the second insulating layer IL2, the first insulating layer IL1, the second gate insulating layer GI2, and the first gate insulating layer GI1 may be etched. The depth of the hole H may be the same as the distance from the upper surface of the active layer ACT to the upper surface of the second insulating layer IL2. Therefore, as the thickness of the pixel circuit layer PCL increases, the depth of the hole H may increase. As the depth of the hole H increases, the necessity of further etching the pixel circuit layer PCL may increase.

[0127] In the display device DD according to the present disclosure, the pre-polished insulating layer 50 (refer to Figure 6 ) may be directly disposed on the second gate electrode GAT2, and a pixel circuit layer PCL having a reduced stack thickness may be provided. As the thickness of the pixel circuit layer PCL is reduced, the necessity of deep etching the pixel circuit layer PCL to form the hole H may be reduced. Accordingly, the hole H may be formed as a region intended to appropriately expose the active layer ACT, and the hole H may be connected to the exposed active layer ACT.

[0128] refer to Figure 5 and Fig.12 When the interlayer conductive layer is formed on the second insulating layer in operation S600, after the hole H is formed, the interlayer conductive layer SD may be formed. The interlayer conductive layer SD may be stably electrically connected to the active layer ACT through the contact hole CNT.

[0129] The interlayer conductive layer SD may include a first layer L1, a second layer L2, and a third layer L3. The first layer L1 and the third layer L3 may include the same material, and the first layer L1 and the third layer L3 may include a material different from that of the second layer L2. For example, the first layer L1 may include titanium (Ti), the second layer L2 may include aluminum (Al), and the third layer L3 may include titanium (Ti). The first layer L1 may be deposited on the second insulating layer IL2, the second layer L2 may be deposited on the first layer L1, and the third layer L3 may be deposited on the second layer L2.

[0130] The interlayer conductive layer SD may be etched using an etching solution 30. According to an embodiment of the present disclosure, the etching solution 30 may include chlorine radicals (Cl radicals). According to experiments, when the interlayer conductive layer SD is etched with silicon nitride (SiN x ) rather than silicon oxide (SiO x ) reaction, the etching solution 30 including chlorine radicals may be more consumed. When the etching solution 30 is not consumed, etching may be excessively performed.

[0131] For example, refer to Fig.13 , the interlayer conductive layer SD may be etched to expose the second insulating layer IL2, and at this time, in a conventional display structure, when silicon oxide (SiO x ) is disposed directly below the first layer L1, the etching solution 30 may not be consumed, and the etching solution 30 may remain in the layer including silicon oxide (SiO x The remaining etching solution 30 may splash onto one side of the second layer L2 and over-etch the second layer L2 including aluminum (Al).

[0132] In the display device DD according to the embodiment of the present disclosure, silicon nitride (SiN x ) may be disposed directly below the first layer L1. Therefore, the etching solution 30 may be consumed, and the second layer L2 may not be excessively etched.

[0133] Below, we will refer to Figures 14 to 17 as well as Figure 5 A display device and a method of manufacturing the display device according to a second embodiment are described. Contents overlapping with the above contents are not repeated.

[0134] Fig.14 is a schematic cross-sectional view of a display device DD according to a second embodiment. Figures 15 to 17 Schematic cross-sectional views of each manufacturing process operation of the display device DD according to the second embodiment. Figures 15 to 17 FIG. 5 is a diagram illustrating the pixel circuit layer PCL of the display device DD in more detail.

[0135] The second embodiment is different from the first embodiment in that when the first insulating portion P1 is formed by etching the pre-polished insulating layer 50 , the pre-polished insulating layer 50 is etched until the second gate electrode GAT2 is exposed.

[0136] refer to Fig.14 , the first insulating portion P1 of the display device DD according to the second embodiment may not completely cover the second gate electrode GAT2. For example, the first insulating portion P1 may cover the side surface of the second gate electrode GAT2, and may not cover the upper surface of the second gate electrode GAT2. The first insulating portion P1 may expose one surface (for example, the upper surface) of the second gate electrode GAT2 so that the one surface contacts another structure of the display device DD.

[0137] The first insulating portion P1 may have the same step difference as the second gate electrode GAT2. One surface (eg, upper surface) of the first insulating portion P1 and one surface (eg, upper surface) of the second gate electrode GAT2 may be disposed on the same plane.

[0138] The second insulating portion P2 may contact at least a portion of the second gate electrode GAT2. The second insulating portion P2 may contact one surface of the second gate electrode GAT2.

[0139] refer to Figure 5 , Fig.15 and Fig.16 When the first insulating portion of the first insulating layer is formed by polishing the pre-polished insulating layer according to the second embodiment in operation S300 , the pre-polished insulating layer 50 may be polished by the polishing apparatus 100 and the second slurry SLR2 .

[0140] The second slurry SLR2 may include zirconium oxide (ZrO 2 ) and cerium dioxide (CeO 2 ). The second slurry SLR2 may have a relatively high selectivity for inorganic materials compared to metals. The second slurry SLR2 may have a high selectivity for the first insulating layer IL1 compared to the second gate electrode GAT2. For example, the second slurry SLR2 may have a high selectivity for silicon oxide (SiO x ) has a relatively high selectivity. For example, the selectivity of the second slurry SLR2 to the second gate electrode GAT2 is related to the selectivity of the slurry to silicon oxide (SiO x ) has a selectivity ratio of 1:30 to 1:50.

[0141] The pre-polished insulating layer 50 may be polished by the polishing apparatus 100 and the second slurry SLR2 to form a first insulating portion P1 of the first insulating layer IL1. The first insulating portion P1 may form a flat polishing surface Q. The polishing surface Q may be disposed on the same plane as one surface (eg, upper surface) of the second gate electrode GAT2.

[0142] The pre-polished insulating layer 50 may be polished to expose one surface (e.g., upper surface) of the second gate electrode GAT2. The pre-polished insulating layer 50 may be polished to form a first insulating portion P1 so that the second gate electrode GAT2 and the first insulating portion P1 have the same step difference. The first insulating portion P1 may not be formed in a region where the first gate electrode GAT1 and the second gate electrode GAT2 overlap.

[0143] Compared with metal, the second slurry SLR2 has a x ) has a relatively high selectivity, so the pre-polishing insulating layer 50 may be polished, and then the polishing may be stopped when the second gate electrode GAT2 is exposed.

[0144] refer to Fig.17 After forming the first insulating portion P1, a second insulating portion P2 may be formed on the polished first insulating portion P1. After forming the second insulating portion P2, a second insulating layer IL2 may be formed. After forming the second insulating layer IL2, a hole H for electrically connecting the interlayer conductive layer SD and the active layer ACT may be formed.

[0145] When the pre-polished insulating layer 50 is polished to expose the second gate electrode GAT2, in the display device DD according to the second embodiment, the pixel circuit layer PCL may have a thickness less than that of the case where the pre-polished insulating layer 50 is polished without exposing the gate electrode GAT2. Accordingly, in the display device DD according to the second embodiment, the etching depth of the pixel circuit layer PCL for forming the hole H may be reduced.

[0146] As described above, although the present disclosure has been described with reference to the above embodiments, those skilled in the art or those with common knowledge in the art will understand that various modifications and changes may be made to the present disclosure without departing from the spirit and technical field of the present disclosure described in the claims.

[0147] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims

1. A display device, comprising: Active layer; a gate electrode disposed on the active layer; A first insulating layer disposed on the gate electrode, completely covering the gate electrode and including a flat surface; as well as a second insulating layer disposed on the first insulating layer and comprising a flat surface, The first insulating layer and the second insulating layer include inorganic materials different from each other.

2. The display device according to claim 1, wherein the active layer and the gate electrode are spaced apart from each other, The display device further includes a first gate insulating layer and a second gate insulating layer disposed on the active layer, and The gate electrode includes a first gate electrode disposed on the first gate insulating layer and a second gate electrode disposed on the second gate insulating layer. The display device according to claim 2 , wherein the flat surface of the first insulating layer has no step difference. The display device according to claim 3 , wherein the flat surface of the first insulating layer faces the second insulating layer. The display device according to claim 3 , wherein the first insulating layer is directly disposed on the second gate electrode. The display device according to claim 3 , wherein the flat surface of the first insulating layer does not contact the second gate electrode.

7. The display device according to claim 5, wherein the first insulating layer comprises silicon oxide, and The second insulating layer includes silicon nitride.

8. The display device according to claim 1, further comprising: an interlayer conductive layer disposed on the second insulating layer, One surface and the other surface of the interlayer conductive layer are flat.

9. The display device according to claim 8, wherein the interlayer conductive layer comprises: First floor; a second layer disposed on the first layer; as well as a third layer disposed on the second layer, and The first layer contacts the second insulating layer.

10. The display device according to claim 9, wherein the first layer and the third layer comprise the same material, The second layer includes a material different from that of the first layer and the third layer, and The second layer includes aluminum.

11. A method for manufacturing a display device, the method comprising: patterning an active layer on the base layer; patterning a gate electrode and a gate insulating layer on the active layer; depositing a pre-polished insulating layer on the gate electrode; polishing the pre-polished insulating layer to form a first insulating portion; as well as forming a second insulating portion on the first insulating portion, wherein the first insulating portion and the second insulating portion form a first insulating layer, Wherein patterning the gate electrode on the active layer comprises: forming a first gate electrode; as well as forming a second gate electrode on the first gate electrode, wherein the first gate electrode and the second gate electrode are spaced apart from the active layer, and When the pre-polished insulating layer is deposited on the gate electrode, the pre-polished insulating layer contacts the second gate electrode.

12. The method according to claim 11, wherein in the polishing of the pre-polished insulating layer to form the first insulating portion, the pre-polished insulating layer is polished using a polishing device and a slurry, and The first insulating portion forms a flat polished surface.

13. The method according to claim 12, further comprising: forming a second insulating layer on the second insulating portion; as well as forming an interlayer conductive layer on the second insulating layer, When the interlayer conductive layer is formed on the second insulating layer, the interlayer conductive layer is etched by an etching solution including chlorine radicals.

14. The method according to claim 13, wherein when depositing the pre-polishing insulating layer on the gate electrode, the pre-polishing insulating layer is deposited to have to Thickness.

15. The method according to claim 12, wherein in the polishing of the pre-polished insulating layer to form the first insulating portion, the pre-polished insulating layer is polished to form the flat polishing surface, and The flat polished surface is disposed on a different plane from one surface of the second gate electrode.

16. The method of claim 15, wherein the slurry comprises silicon dioxide, and The pre-polished insulating layer is polished within a predetermined polishing period.

17. The method according to claim 16, wherein in the polishing of the pre-polished insulating layer to form the first insulating portion, the first insulating portion is polished to have a thickness of to Thickness.

18. The method according to claim 12, wherein in said polishing said pre-polished insulating layer to form said first insulating portion, said pre-polished insulating layer is polished to form said flat polished surface, and The flat polished surface is disposed on the same plane as one surface of the second gate electrode.

19. The method of claim 18, wherein the slurry comprises ceria.

20. The method of claim 19, wherein the first insulating layer comprises silicon oxide, and A ratio of the selectivity of the slurry to the second gate electrode to the selectivity of the slurry to the silicon oxide is 1:30 to 1:50.

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