Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a plurality of pixel units arranged on a substrate body, at least one pixel unit comprises a plurality of light-emitting elements stacked in the third direction, and the light-emitting elements stacked in the third direction comprise a charge generation layer arranged on the substrate body; the first light-emitting layer is arranged on one side, close to the substrate, of the charge generation layer; the second light-emitting layer is arranged on one side, far away from the substrate, of the charge generation layer; the at least one testing assembly is arranged on the substrate and located in the testing assembly area, the at least one testing assembly comprises a plurality of testing elements, and the testing elements are arranged in the testing assembly area in an array mode in the first direction and the second direction. The plurality of test elements includes a first test element and a second test element, the first test element includes the same material as the first light emitting layer, the second test element includes the same material as the second light emitting layer, and the first test element and the second test element are located in two rows.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices have attracted much attention due to their advantages such as self-luminescence, rich colors, fast response speed, wide viewing angle, light weight, thin thickness, low power consumption, and flexible display. The core components of OLED products are OLED light-emitting devices, and the characteristics of OLED light-emitting devices such as luminous efficiency and life span directly determine the core competitiveness of the product.

[0003] With the development of OLED display technology, OLED light-emitting devices with a tandem structure (i.e., a series structure or a stacked structure) have begun to attract the attention of researchers. In an OLED light-emitting device with a tandem structure, stacking multiple electroluminescent elements can improve the luminous efficiency and life of the OLED light-emitting device. How to design and manufacture OLED display products with a tandem structure is one of the important topics for researchers. Summary of the invention

[0004] According to one aspect of the present disclosure, a display substrate is provided, comprising: a substrate substrate, the substrate substrate comprising a display area and a test component area; a plurality of pixel units disposed on the substrate substrate, the plurality of pixel units being arranged in an array in the display area along a first direction and a second direction, at least one of the pixel units comprising a plurality of light-emitting elements stacked along a third direction, the plurality of light-emitting elements stacked along the third direction comprising: a charge generation layer disposed on the substrate substrate; a first light-emitting layer disposed on a side of the charge generation layer close to the substrate substrate; and a second light-emitting layer disposed on a side of the charge generation layer away from the substrate substrate, wherein the first direction and the second direction intersect, the third direction is perpendicular to the first direction and the second direction; and a plurality of light-emitting layers disposed on the substrate substrate. At least one test component on the base substrate, the at least one test component is located in the test component area, the at least one test component includes a plurality of test elements, the plurality of test elements are arranged in an array along a first direction and a second direction in the test component area, wherein the plurality of test elements include a first test element and a second test element, the first test element and the first light-emitting layer include the same material, the second test element and the second light-emitting layer include the same material, and the first test element and the second test element are located in two rows; and the display substrate also includes a first calibration mark arranged on the base substrate, the first calibration mark is located in the test component area, and the first calibration mark is located between two adjacent rows of test elements.

[0005] According to some exemplary embodiments, the first light-emitting layer includes a first sub-light-emitting layer of multiple colors, the at least one test component includes a first test element of multiple colors, and the first test element of multiple colors and the first sub-light-emitting layer of multiple colors include the same material; the second light-emitting layer includes a second sub-light-emitting layer of multiple colors, the at least one test component includes a second test element of multiple colors, and the second test element of multiple colors and the second sub-light-emitting layer of multiple colors include the same material; and the test component area has a rectangular shape, the test component area has a first dimension along the first direction and a second dimension along the second direction, the first dimension is smaller than the second dimension, and in the same test component, the first test element and the second test element of the same color are located in two columns arranged along the first direction, and the first test element and the second test element of the same color are located in a row extending along the first direction.

[0006] According to some exemplary embodiments, in the same test assembly, the first test elements of different colors are located in the same column extending along the second direction; and / or, in the same test assembly, the second test elements of different colors are located in the same column extending along the second direction.

[0007] According to some exemplary embodiments, the plurality of light-emitting elements stacked along a third direction further include: a first compensation layer disposed on a side of the first light-emitting layer close to the base substrate; and a second compensation layer disposed on a side of the second light-emitting layer close to the base substrate; and the plurality of test elements further include a third test element and a fourth test element, the third test element and the first compensation layer include the same material, the fourth test element and the second compensation layer include the same material, and the third test element and the fourth test element are located in two rows.

[0008] According to some exemplary embodiments, the first compensation layer and the second compensation layer are of the same color, and the third test element and the fourth test element are located in the same row extending along the first direction.

[0009] According to some exemplary embodiments, in the same test assembly, the first test element and the third test element of different colors are located in the same column extending along the second direction; and / or, in the same test assembly, the second test element and the fourth test element of different colors are located in the same column extending along the second direction.

[0010] According to some exemplary embodiments, the display substrate further comprises a reference mark disposed on the base substrate, the reference mark being located in the test component area, and the reference mark being located between two adjacent columns of test elements in the first direction.

[0011] According to some exemplary embodiments, the reference mark is located between two adjacent rows of test elements in the second direction.

[0012] According to some exemplary embodiments, the display substrate further includes a second calibration mark disposed on the base substrate, the second calibration mark is located in the test component area, the second calibration mark extends along a second direction, and the second calibration mark is located between two adjacent rows of test elements in the second direction.

[0013] According to some exemplary embodiments, at least one of the test components includes q columns of test elements arranged along the first direction and n rows of test elements arranged along the second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4.

[0014] According to some exemplary embodiments, in the same test component, a first spacing distance between two adjacent columns of test elements arranged along a first direction is greater than or equal to 150 microns; and / or, in the same test component, a first spacing distance between two adjacent columns of test elements arranged along the first direction is less than or equal to 390 microns.

[0015] According to some exemplary embodiments, the reference mark includes a first reference mark portion extending along a first direction and a second reference mark portion extending along a second direction, the first reference mark portion and the second reference mark portion intersect at a reference point; and a first imaginary straight line extends along the second direction and passes through the reference point, a second imaginary straight line extends along the second direction and passes through the centers of at least two test elements in a column of test elements, a third imaginary straight line extends along the second direction and passes through the centers of at least two test elements in another column of test elements, and a ratio of a first distance between the second imaginary straight line and the first imaginary straight line in the first direction to a second distance between the third imaginary straight line and the first imaginary straight line in the first direction is between 0.8 and 1.2.

[0016] According to some exemplary embodiments, a fourth imaginary straight line extends along the first direction and passes through the reference point, a fifth imaginary straight line extends along the first direction and passes through the center of a row of test elements adjacent to the reference mark, a sixth imaginary straight line extends along the first direction and passes through the center of another row of test elements adjacent to the reference mark, and a ratio of a third distance between the fifth imaginary straight line and the fourth imaginary straight line in the second direction to a fourth distance between the sixth imaginary straight line and the fourth imaginary straight line in the second direction is between 0.8 and 1.2.

[0017] According to some exemplary embodiments, the display substrate includes n first calibration marks, and in the first direction, the i-th first calibration mark is located between the first test element and the second test element in the i-th row of test elements, where 1≤i≤n and i is a positive integer.

[0018] According to some exemplary embodiments, the display substrate includes q second calibration marks, and one second calibration mark among the q second calibration marks is located between two first test elements in the first column in the second direction.

[0019] According to some exemplary embodiments, the n rows of test elements include a kth row of test elements and a k+1th row of test elements adjacent to the reference mark, the kth row of test elements and the k+1th row of test elements having a second spacing distance in the second direction, wherein 1≤k≤n-1 and k is a positive integer; the pth row of test elements and the p+1th row of test elements have a third spacing distance in the second direction, wherein 1≤p≤n-1 and p is a positive integer, and p is not equal to k; and the second spacing distance is greater than the third spacing distance.

[0020] According to some exemplary embodiments, the second spacing distance is more than twice the third spacing distance.

[0021] According to some exemplary embodiments, the display area of ​​the display substrate includes a first side, a second side, a third side, a fourth side, a first corner, a second corner, a third corner and a fourth corner, and the first corner, the second corner, the third corner and the fourth corner are respectively located at the connection between two adjacent sides of the first side, the second side, the third side and the fourth side; and the display substrate includes a plurality of the test components, and the plurality of the test components are respectively arranged adjacent to the first side, the second side, the third side, the fourth side, the first corner, the second corner, the third corner and the fourth corner.

[0022] According to some exemplary embodiments, the display substrate includes a driving chip disposed adjacent to the first side edge, and at least one of the test components disposed adjacent to the first side edge is located between the driving chip and the first side edge of the display area.

[0023] According to some exemplary embodiments, the display substrate includes a driving chip disposed adjacent to the first side, and at least one of the testing components disposed adjacent to the first side is located on a side of the driving chip away from the first side of the display area.

[0024] According to some exemplary embodiments, the display substrate includes two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a first direction; and / or, the display substrate includes two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a second direction.

[0025] According to another aspect of the present disclosure, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above contents and other purposes, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0028] Figure 2 According to some exemplary embodiments of the present disclosure, the display substrate Figure 1 A schematic cross-sectional view taken along line AA' in FIG.

[0029] Figure 3 is a partial enlarged view of a test component area in a display substrate according to some exemplary embodiments of the present disclosure;

[0030] Figure 4 The structure diagram of the mask plate used in the evaporation process according to some exemplary embodiments of the present disclosure is schematically shown;

[0031] Figure 5 is a schematic plan view of a display substrate according to some other exemplary embodiments of the present disclosure;

[0032] Figure 6 According to some other exemplary embodiments of the present disclosure, the display substrate is Figure 5 A schematic cross-sectional view taken along line BB';

[0033] Figure 7 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0034] Figure 8 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0035] Fig. 9 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure;

[0036] Fig. 10A and Fig. 10BThey are respectively partial enlarged views of a test component area in a display substrate according to some further exemplary embodiments of the present disclosure;

[0037] Fig.11 is a schematic plan view of a display substrate according to some further exemplary embodiments of the present disclosure; and

[0038] Fig.12 is a schematic structural diagram of a testing device for detecting pixel position accuracy of a display substrate according to some exemplary embodiments of the present disclosure.

[0039] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0042] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by ordinary technicians in the field. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0043] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the device, element or component referred to must have a specific orientation, be constructed or operate in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the present disclosure.

[0044] It should be noted that, in this article, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. Usually, multiple elements, components, structures and / or parts located in the "same layer" have approximately the same thickness.

[0045] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0046] In this document, directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, for example, the longitudinal direction and the transverse direction of a pixel unit, or the row direction and the column direction of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not limitations of the present disclosure.

[0047] In the preparation process of OLED display devices, vacuum thermal evaporation can be used to form OLED light-emitting devices. The vacuum thermal evaporation method has moderate complexity in the preparation process, and the life of the OLED light-emitting devices produced is long, so it has been widely used. In this preparation method, FMM (Fine Metal Mask, i.e., high-precision metal mask) is a key structure to ensure that the organic light-emitting material is accurately evaporated to the designed position. FMM includes an evaporation opening corresponding to the display area. During the evaporation process, the heated and evaporated organic material molecules will pass through the openings in the FMM and deposit on the openings of the pixel definition layer (Pixel Define Layer, PDL) of the backplane, thereby forming a predetermined pattern.

[0048] The FMM structure is delicate, with openings of only tens of microns, so it is necessary to use TEG (Test Element Group) to accurately test and align the vapor deposition pattern to prevent poor color mixing caused by poor alignment and ensure the final display effect. Each layer of the vapor deposition pattern usually corresponds to a mask plate, and the mask plate is provided with a pixel position alignment test element group (Pixel Position Align TEG, referred to as PPA TEG). Through PPA TEG, the pixel position accuracy in the display screen can be monitored and improved, thereby improving the yield of display products and ensuring good display effects.

[0049] Figure 1 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure, Figure 2 According to some exemplary embodiments of the present disclosure, the display substrate Figure 1 A schematic cross-sectional view taken along line AA' in FIG. Figure 3 is a partial enlarged view of a test component area in a display substrate according to some exemplary embodiments of the present disclosure.

[0050] Combined with reference Figures 1 to 3 The display substrate 100' includes: a base substrate 1', the base substrate includes a display area AA and a test assembly area TGA; a plurality of pixel units P disposed on the base substrate 1', the plurality of pixel units P are arranged in an array in the display area AA along a first direction D1 and a second direction D2; and at least one test assembly 2' disposed on the base substrate 1', the at least one test assembly 2' is located in the test assembly area TGA, the at least one test assembly 2' includes a plurality of test elements 3', and the plurality of test elements 3' are arranged in the test assembly area TGA along the first direction D1 or the second direction D2.

[0051] like Figure 2 As shown, in the display area AA, the display substrate 100' includes: a first electrode 4', a second electrode 6' and a light-emitting functional layer 5' disposed on the base substrate 1. For example, the light-emitting functional layer 5' may include a hole injection layer 51', a hole transport layer 52', a light-emitting layer 53', an electron transport layer 54' and an electron injection layer 55'.

[0052] The light emitting layer 53' may include a plurality of sub-light emitting layers, for example, a first sub-light emitting layer 53'R, a second sub-light emitting layer 53'G and a third sub-light emitting layer 53'B. The first sub-light emitting layer 53'R, the second sub-light emitting layer 53'G and the third sub-light emitting layer 53'B may emit red light, green light and blue light respectively.

[0053] In this embodiment, a pixel unit P may include at least three sub-pixels SP1, SP2, SP3, which are red, green and blue sub-pixels respectively, and the sub-pixels SP1, SP2, SP3 include a first sub-light emitting layer 53'R, a second sub-light emitting layer 53'G and a third sub-light emitting layer 53'B respectively.

[0054] It should be noted that the embodiments of the present disclosure do not impose any particular restrictions on the design of the pixel unit P. For example, although the accompanying drawings schematically show that the pixel unit P includes three sub-pixels, in other embodiments, a pixel unit P may also include a smaller or larger number of sub-pixels. In addition, the arrangement of the sub-pixels within a pixel unit P may adopt various arrangements known in the art, and the embodiments of the present disclosure do not impose any particular restrictions.

[0055] Continue to refer to Figure 2 , the hole injection layer 51', the hole transport layer 52', the light emitting layer 53', the electron transport layer 54' and the electron injection layer 55' are sequentially arranged on the side of the first electrode 4' away from the base substrate 1'. In this embodiment, the first electrode 4' may be an anode, and the second electrode 6' may be a cathode. The holes provided by the first electrode 4' are assisted by the hole injection layer 51' and the hole transport layer 52' ​​to be transported to the light emitting layer 53', and the electrons provided by the second electrode 6' are assisted by the electron injection layer 55' and the electron transport layer 54' to be transported to the light emitting layer 53', and the holes and electrons are recombined in the light emitting layer 53' to excite the light emitting layer 53' to emit light of corresponding colors.

[0056] Optionally, the light-emitting functional layer 5 ′ may further include an electron blocking layer disposed between the first electrode 4 ′ and the light-emitting layer 53 ′, and a hole blocking layer disposed between the second electrode 6 ′ and the light-emitting layer 53 ′.

[0057] Since the wavelengths of red light, green light and blue light are different, the losses when passing through the structure above the light-emitting layer are different. The longer the wavelength, the greater the loss. In order to make each pixel unit P have the same display effect under the same conditions, in some embodiments of the present disclosure, the luminous intensity of the red sub-pixel and / or the green sub-pixel can be increased to offset the loss during transmission. In other words, a compensation layer can be added under the sub-light-emitting layer of the red sub-pixel and the green sub-pixel.

[0058] Continue to refer to Figure 2 The light emitting functional layer 5' may further include a compensation layer 56'. For example, the compensation layer 56' may include a sub-compensation layer 56'R located in the first sub-pixel SP1 and / or a sub-compensation layer 56'G located in the second sub-pixel SP2.

[0059] The sub-compensation layer 56'R is located below the first sub-light emitting layer 53'R, or in other words, the sub-compensation layer 56'R is located between the first sub-light emitting layer 53'R and the first electrode 4'. For example, the thickness of the sub-compensation layer 56'R is greater than the thickness of the first sub-light emitting layer 53'R. When the holes transmitted by the first electrode 4' and the electrons transmitted by the second electrode 6' are recombined in the sub-compensation layer 56'R, the sub-compensation layer 56'R is excited to emit red light, so as to enhance the intensity of the red light emitted by the first sub-pixel SP1.

[0060] The sub-compensation layer 56'G is located below the second sub-light emitting layer 53'G, or in other words, the sub-compensation layer 56'G is located between the second sub-light emitting layer 53'G and the first electrode 4'. For example, the thickness of the sub-compensation layer 56'G is greater than the thickness of the second sub-light emitting layer 53'G. When the holes transmitted by the first electrode 4' and the electrons transmitted by the second electrode 6' are recombined in the sub-compensation layer 56'G, the sub-compensation layer 56'G is excited to emit green light, so as to enhance the intensity of the green light emitted by the second sub-pixel SP2.

[0061] Reference Figures 1 to 3 The display area AA of the display substrate 100' includes a first side AA1, a second side AA2, a third side AA3, a fourth side AA4, a first corner AC1, a second corner AC2, a third corner AC3 and a fourth corner AC4, and the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4 are respectively located at the connection between two adjacent sides of the first side AA1, the second side AA2, the third side AA3 and the fourth side AA4.

[0062] In some embodiments, the display substrate 100' may include a plurality of the test components 2', which are respectively disposed adjacent to the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4.

[0063] Figure 3 A partial enlarged view of a test component area is schematically shown, such as Figure 3 As shown, in at least one test component area TGA, a test component 2' is provided, and the test component 2' may include a plurality of test elements 3'. For example, the plurality of test elements 3' may be test elements of a plurality of colors, and for the convenience of description, the test elements of a plurality of colors are respectively marked as test elements 3'R, 3'G, 3'B, 3"R, 3"G.

[0064] The test elements 3'R, 3'G, 3'B, 3"R, and 3"G of multiple colors respectively correspond to the first sub-light-emitting layer 53'R, the second sub-light-emitting layer 53'G, the third sub-light-emitting layer 53'B, the sub-compensation layer 56'R, and the sub-compensation layer 56'G formed by the evaporation process. Specifically, in the preparation process of the display substrate 100', the first sub-light-emitting layer 53'R, the second sub-light-emitting layer 53'G, the third sub-light-emitting layer 53'B, the sub-compensation layer 56'R, and the sub-compensation layer 56'G are formed by multiple evaporation processes. It should be noted that the "multiple evaporation processes" here means that in the multiple evaporation processes, different FMMs are used to form each evaporated film layer, or, although the same FMM is used, different evaporation process parameters are used to form each evaporated film layer.

[0065] In this embodiment, the test element 3'R and the first sub-light emitting layer 53'R are formed by the same evaporation process, the test element 3'G and the second sub-light emitting layer 53'G are formed by the same evaporation process, the test element 3'B and the third sub-light emitting layer 53'B are formed by the same evaporation process, the test element 3"R and the sub-compensation layer 56'R are formed by the same evaporation process, and the test element 3"G and the sub-compensation layer 56'G are formed by the same evaporation process. In this way, by detecting the position accuracy of the test element 3'R, the pixel position accuracy of the first sub-light emitting layer 53'R can be correspondingly determined, by detecting the position accuracy of the test element 3'G, the pixel position accuracy of the second sub-light emitting layer 53'G can be correspondingly determined, by detecting the position accuracy of the test element 3'B, the pixel position accuracy of the third sub-light emitting layer 53'B can be correspondingly determined, by detecting the position accuracy of the test element 3"R, the pixel position accuracy of the sub-compensation layer 56'R can be correspondingly determined, and by detecting the position accuracy of the test element 3"G, the pixel position accuracy of the sub-compensation layer 56'G can be correspondingly determined.

[0066] like Figure 3 As shown, a test assembly area TGA has a first size X1 in the first direction D1 and a second size Y1 in the second direction D2. A plurality of test elements are arranged in a row along the second direction D2 and arranged in the test assembly area TGA. For example, test elements 3'R, 3'G, 3'B, 3"R, 3"G are arranged in a row in sequence along the second direction D2.

[0067] It should be noted that in Figure 3 In the figure, the shape of the orthographic projection of each test element on the substrate 1' is schematically shown, and its shape is schematically shown as a square. However, the embodiments of the present disclosure are not limited to this. The shape of the orthographic projection of each test element on the substrate 1' may include but is not limited to a rectangle, a circle, an ellipse, an approximate circle, a triangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and the like.

[0068] Continue to refer to Figure 3 The display substrate 100' may further include a reference mark 7', a first calibration mark 8' and a second calibration mark 9' disposed on the base substrate 1'. The reference mark 7', the first calibration mark 8' and the second calibration mark 9' are all located in the test assembly area TGA.

[0069] The reference mark 7' may include a first reference mark portion 71' extending along the first direction D1 and a second reference mark portion 72' extending along the second direction D2, the first reference mark portion 71' and the second reference mark portion 72' intersecting at a reference point. The first calibration mark 8' extends along the first direction D1. The second calibration mark 9' extends along the second direction D2.

[0070] For example, the reference mark 7' may have a cross shape, and the first calibration mark 8' and the second calibration mark 9' may have a straight shape, respectively.

[0071] In the embodiment of the present disclosure, only one reference mark 7 ′ is provided in one test component area TGA, and the reference mark 7 ′ is used to mark the position of the test component area TGA.

[0072] In some embodiments, in the display area AA, m' evaporated film layers are provided, where m' is a positive integer greater than or equal to 1. For example, in the illustrated embodiment, m' is 5, and the 5 evaporated film layers are respectively the first sub-light emitting layer 53'R, the second sub-light emitting layer 53'G, the third sub-light emitting layer 53'B, the sub-compensation layer 56'R and the sub-compensation layer 56'G. Accordingly, in the test assembly area TGA, a test assembly includes m' test elements, which correspond to the m' evaporated film layers, respectively, and are respectively used to detect the pixel position accuracy of the m' evaporated film layers.

[0073] In the test assembly area TGA, m' first calibration marks 8' are arranged, and the m' first calibration marks 8' correspond to the m' test elements respectively, and are used to detect the position accuracy of the m' test elements in the second direction D2.

[0074] The number of the second calibration marks 9' provided in the test assembly area TGA is consistent with the number of columns of the m' test elements. For example, in this embodiment, the m' test elements are arranged in a column, and accordingly, one second calibration mark 9' is provided in the test assembly area TGA. The second calibration mark 9' is used to detect the position accuracy of the m' test elements arranged in a column in the first direction D1.

[0075] It should be noted that the purpose of calibration or positioning using the reference mark 7', the first calibration mark 8' and the second calibration mark 9' will be further described in detail below in conjunction with the detection process.

[0076] Return to reference Figure 2 In some embodiments, the first sub-light emitting layer 53 'R, the second sub-light emitting layer 53 'G, and the third sub-light emitting layer 53 'B can be formed by an evaporation process using different FMMs, respectively.

[0077] In the display area AA, the sub-compensation layer 56'R is located below the first sub-light emitting layer 53'R, and the positions of the sub-compensation layer 56'R and the first sub-light emitting layer 53'R in the first direction D1 and the second direction D2 are consistent, so the same FMM can be used to form the sub-compensation layer 56'R and the first sub-light emitting layer 53'R. It should be noted that in the process of forming the sub-compensation layer 56'R and the first sub-light emitting layer 53'R, the evaporation process parameters are different, so the evaporation processes for forming the sub-compensation layer 56'R and the first sub-light emitting layer 53'R are different evaporation processes. Similarly, the sub-compensation layer 56'G is located below the second sub-light emitting layer 53'G, and the positions of the sub-compensation layer 56'G and the second sub-light emitting layer 53'G in the first direction D1 and the second direction D2 are consistent, so the same FMM can be used to form the sub-compensation layer 56'G and the second sub-light emitting layer 53'G. It should be noted that, in the process of forming the compensation sub-layer 56'G and the second light-emitting sub-layer 53'G, the evaporation process parameters are different, so the evaporation processes for forming the compensation sub-layer 56'G and the second light-emitting sub-layer 53'G are different evaporation processes.

[0078] Figure 4 The structure diagram of a mask plate used in an evaporation process according to some exemplary embodiments of the present disclosure is schematically shown.

[0079] like Figure 4 As shown, the mask plate 20 includes an evaporation area 21 and a test area 22 located around the evaporation area 21. An evaporation opening 211 is provided in the evaporation area 21 for the target material to pass through and reach the graphic area of ​​the backplane, so as to form a pattern of the light-emitting layer or the compensation layer in the display area AA. A test hole 221 is provided in the test area 22 for the target material to pass through and reach the test component area of ​​the backplane, so as to form a pattern of the test element in the test component area TGA.

[0080] In practical applications, the mask plate 20 is fixed in the chamber, a target material is arranged below the mask plate 20, and the backplane to be evaporated is arranged above the mask plate 20. By setting appropriate process conditions in the chamber, it is ensured that the target material is evaporated to the predetermined position on the backplane through the evaporation opening and the test hole in the mask plate 20. For example, the mask plate 20 can be FMM. During evaporation, the heated and evaporated organic material molecules will pass through the evaporation opening 211 on the FMM and deposit on the opening of the pixel definition layer of the backplane to form a pattern of the light-emitting layer or the compensation layer in the display area AA; at the same time, the organic material molecules will pass through the test hole 221 on the FMM and deposit on the test component area of ​​the backplane to form a pattern of the test element in the test component area TGA. The multiple test elements arranged in the test component area TGA form a position test mark, which is used to accurately test and align the evaporation pattern formed by FMM evaporation. Each evaporation pattern corresponds to a test element to ensure the correctness and accuracy of the evaporation pattern.

[0081] Figure 5 is a schematic plan view of a display substrate according to some other exemplary embodiments of the present disclosure, Figure 6 According to some other exemplary embodiments of the present disclosure, the display substrate is Figure 5 A schematic cross-sectional view taken along line BB' in FIG. Figure 7 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure.

[0082] Combined with reference Figures 5 to 7 The display substrate 100 includes: a base substrate 1, the base substrate includes a display area AA and a test component area TGA; a plurality of pixel units P arranged on the base substrate 1, the plurality of pixel units P are arranged in an array in the display area AA along a first direction D1 and a second direction D2; and at least one test component 2 arranged on the base substrate 1, the at least one test component 2 is located in the test component area TGA, the at least one test component 2 includes a plurality of test elements 3, the plurality of test elements 3 are arranged in an array in the test component area TGA along the first direction D1 and the second direction D2.

[0083] In this embodiment, at least one of the pixel units P includes a plurality of light-emitting elements stacked along a third direction D3, and the plurality of light-emitting elements stacked along the third direction D3 include: a charge generation layer CGL arranged on the base substrate 1; a first light-emitting layer arranged on the side of the charge generation layer CGL close to the base substrate 1; and a second light-emitting layer arranged on the side of the charge generation layer CGL away from the base substrate 1, wherein the first direction D1 and the second direction D2 intersect, and the third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0084] like Figure 5As shown, in the display area AA, the display substrate 100 includes: a first electrode 4, a second electrode 6, and a first light-emitting layer, a charge generation layer CGL, and a second light-emitting layer sandwiched between the first electrode 4 and the second electrode 6, which are arranged on the base substrate 1. In the third direction D3, the first light-emitting layer is located between the first electrode 4 and the charge generation layer CGL, and the second light-emitting layer is located between the charge generation layer CGL and the second electrode 6.

[0085] That is, in at least one pixel unit P, the OLED light-emitting device includes two light-emitting elements connected in series, so that the OLED light-emitting device is formed as a Tandem device. For example, the light-emitting element 32 located above includes: a second electrode 6, an electron injection layer EIL, an electron transport layer ETL, a hole blocking layer HBL2, a second light-emitting layer EML2, a hole transport layer HTL2 and a charge generation layer CGL. The light-emitting element 31 located below includes: a charge generation layer CGL, a hole blocking layer HBL1, a first light-emitting layer EML1, a hole transport layer HTL1, a hole injection layer HIL and a first electrode 4.

[0086] For example, the charge generation layer CGL may include an N-type charge generation layer CGL1 and a P-type charge generation layer CGL2. The N-type charge generation layer CGL1 is located on the side of the P-type charge generation layer CGL2 close to the first electrode 4, that is, the N-type charge generation layer CGL1 is paired with the first electrode 4 to excite the light-emitting element located below to emit light; the P-type charge generation layer CGL2 is paired with the second electrode 6 to excite the light-emitting element located above to emit light.

[0087] For example, the constituent materials of the N-type charge generation layer CGL1 may include: organic electron transport materials doped with metal materials, with a doping concentration of ≤1%. The constituent materials of the P-type charge generation layer CGL2 may include: organic hole transport materials doped with PD (p-dopant, P-type luminescent dopant), with a doping concentration of about 10%.

[0088] That is to say, Figure 6As shown, the display substrate 100 includes: a first electrode 4 disposed on a substrate 1; a hole injection layer HIL disposed on a side of the first electrode 4 away from the substrate; a first hole transport layer HTL1 disposed on a side of the hole injection layer HIL away from the substrate; a first light-emitting layer EML1 disposed on a side of the first hole transport layer HTL1 away from the substrate; a first hole blocking layer HBL1 disposed on a side of the first light-emitting layer EML1 away from the substrate; an N-type charge generation layer CGL1 disposed on a side of the first hole blocking layer HBL1 away from the substrate; and a first hole transport layer HTL1 disposed on a side of the first hole transport layer HTL1 away from the substrate. A P-type charge generating layer CGL2 on one side of the base substrate; a second hole transport layer HTL2 arranged on the side of the P-type charge generating layer CGL2 away from the base substrate; a second light-emitting layer EML2 arranged on the side of the second hole transport layer HTL2 away from the base substrate; a second hole blocking layer HBL2 arranged on the side of the second light-emitting layer EML2 away from the base substrate; an electron transport layer ETL arranged on the side of the second hole blocking layer HBL2 away from the base substrate; an electron injection layer EIL arranged on the side of the electron transport layer ETL away from the base substrate; and a second electrode 6 arranged on the side of the electron injection layer EIL away from the base substrate.

[0089] In some embodiments of the present disclosure, the first light-emitting layer EML1 includes a plurality of first sub-light-emitting layers of colors, for example, the plurality of first sub-light-emitting layers of colors may include sub-light-emitting layers 51R, 51G, and 51B. The second light-emitting layer EML2 includes a plurality of second sub-light-emitting layers of colors, for example, the plurality of second sub-light-emitting layers of colors may include sub-light-emitting layers 52R, 52G, and 52B.

[0090] In this embodiment, the OLED light-emitting device is formed as a Tandem device, and two or more light-emitting elements are connected in series through a charge generation layer to form a stacked device. As the number of light-emitting layers increases, and the charge generation layer reduces the driving voltage and generates new carriers, stacking multiple light-emitting elements can multiply the luminous efficiency of the device and greatly improve the luminous efficiency of the device. At the same brightness, the current density of the Tandem device is reduced, thereby significantly increasing the life of the device.

[0091] For example, the sub-light emitting layers 51R, 51G, and 51B can emit red light, green light, and blue light, respectively. The sub-light emitting layers 52R, 52G, and 52B can emit red light, green light, and blue light, respectively.

[0092] In this embodiment, one pixel unit P may include at least three sub-pixels SP1, SP2, and SP3, and the sub-pixels SP1, SP2, and SP3 are red, green, and blue sub-pixels, respectively. The sub-pixel SP1 includes a stacked sub-light-emitting layer 51R and a stacked sub-light-emitting layer 52R, the sub-pixel SP2 includes a stacked sub-light-emitting layer 51G and a stacked sub-light-emitting layer 52G, and the sub-pixel SP3 includes a stacked sub-light-emitting layer 51B and a stacked sub-light-emitting layer 52B.

[0093] It should be noted that the embodiments of the present disclosure do not impose any particular restrictions on the design of the pixel unit P. For example, although the accompanying drawings schematically show that the pixel unit P includes three sub-pixels, in other embodiments, a pixel unit P may also include a smaller or larger number of sub-pixels. In addition, the arrangement of the sub-pixels within a pixel unit P may adopt various arrangements known in the art, and the embodiments of the present disclosure do not impose any particular restrictions.

[0094] In some exemplary embodiments of the present disclosure, at least one light emitting element stacked along the third direction may further include: a first compensation layer arranged on a side of the first light emitting layer EML1 close to the base substrate; and a second compensation layer arranged on a side of the second light emitting layer EML2 close to the base substrate.

[0095] Since the wavelengths of red light, green light and blue light are different from each other, the loss of passing through the structure above the light-emitting layer is different. The longer the wavelength, the greater the loss. In order to make each pixel unit P have the same display effect under the same conditions, in some embodiments of the present disclosure, the luminous intensity of the red sub-pixel and / or the green sub-pixel can be increased to offset the loss during transmission. In other words, a compensation layer can be added under the sub-light-emitting layer of the red sub-pixel and / or the green sub-pixel.

[0096] For example, in Figure 6 In the illustrated embodiment, at least one light-emitting element located in the first sub-pixel SP1 may include a compensation layer, that is, including: a first sub-compensation layer 561R arranged on the side of the first light-emitting layer EML1 close to the base substrate; and a second sub-compensation layer 562R arranged on the side of the second light-emitting layer EML2 close to the base substrate.

[0097] The first sub-compensation layer 561R is located below the sub-light emitting layer 51R, or in other words, the first sub-compensation layer 561R is located between the sub-light emitting layer 51R and the first electrode 4. For example, the thickness of the first sub-compensation layer 561R is greater than the thickness of the sub-light emitting layer 51R. When the holes transmitted by the first electrode 4 and the electrons transmitted by the N-type charge generation layer CGL1 are recombined in the first sub-compensation layer 561R, the first sub-compensation layer 561R is excited to emit red light, so as to enhance the intensity of the red light emitted by the first sub-pixel SP1.

[0098] Reference Figures 5 to 7 The display area AA of the display substrate 100 includes a first side AA1, a second side AA2, a third side AA3, a fourth side AA4, a first corner AC1, a second corner AC2, a third corner AC3 and a fourth corner AC4, and the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4 are respectively located at the connection between two adjacent sides of the first side AA1, the second side AA2, the third side AA3 and the fourth side AA4.

[0099] In some embodiments, the display substrate 100 may include a plurality of the test components 2, which are respectively arranged adjacent to the first side AA1, the second side AA2, the third side AA3, the fourth side AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4.

[0100] Figure 7 A partial enlarged view of a test component area is schematically shown, such as Figure 7 As shown, in at least one test component area TGA, a test component 2 is provided, and the test component 2 may include a plurality of test elements 3. For example, the plurality of test elements 3 may be test elements of a plurality of colors, and for the convenience of description, the test elements of a plurality of colors are respectively marked as test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R.

[0101] The test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R of multiple colors correspond to the sub-light-emitting layer 51R, sub-light-emitting layer 52R, sub-light-emitting layer 51G, sub-light-emitting layer 52G, sub-light-emitting layer 51B, sub-light-emitting layer 52B, the first sub-compensation layer 561R, and the second sub-compensation layer 562R formed by the evaporation process, respectively. Specifically, in the preparation process of the display substrate 100, the sub-light-emitting layer 51R, sub-light-emitting layer 52R, sub-light-emitting layer 51G, sub-light-emitting layer 52G, sub-light-emitting layer 51B, sub-light-emitting layer 52B, the first sub-compensation layer 561R, and the second sub-compensation layer 562R are formed by multiple evaporation processes, respectively. It should be noted that the "multiple evaporation processes" here means that in the multiple evaporation processes, different FMMs are used to form each evaporated film layer, or, although the same FMM is used, different evaporation process parameters are used to form each evaporated film layer.

[0102] In this embodiment, the test element 31R and the sub-light-emitting layer 51R are formed by the same evaporation process, the test element 32R and the sub-light-emitting layer 52R are formed by the same evaporation process, the test element 31G and the sub-light-emitting layer 51G are formed by the same evaporation process, the test element 32G and the sub-light-emitting layer 52G are formed by the same evaporation process, the test element 31B and the sub-light-emitting layer 51B are formed by the same evaporation process, the test element 32B and the sub-light-emitting layer 52B are formed by the same evaporation process, the test element 33R and the first sub-compensation layer 561R are formed by the same evaporation process, and the test element 34R and the second sub-compensation layer 562R are formed by the same evaporation process. In this way, by detecting the position accuracy of the test element 31R, the pixel position accuracy of the sub-light-emitting layer 51R can be correspondingly determined; by detecting the position accuracy of the test element 32R, the pixel position accuracy of the sub-light-emitting layer 52R can be correspondingly determined; by detecting the position accuracy of the test element 31G, the pixel position accuracy of the sub-light-emitting layer 51G can be correspondingly determined; by detecting the position accuracy of the test element 32G, the pixel position accuracy of the sub-light-emitting layer 52G can be correspondingly determined; by detecting the position accuracy of the test element 31B, the pixel position accuracy of the sub-light-emitting layer 51B can be correspondingly determined; by detecting the position accuracy of the test element 32B, the pixel position accuracy of the sub-light-emitting layer 52B can be correspondingly determined; by detecting the position accuracy of the test element 33R, the pixel position accuracy of the first sub-compensation layer 561R can be correspondingly determined; by detecting the position accuracy of the test element 34R, the pixel position accuracy of the second sub-compensation layer 562R can be correspondingly determined.

[0103] In the embodiments of the present disclosure, the test element located in the test component area and the light-emitting layer or sub-light-emitting layer located in the display area are formed by the same evaporation process, so that the test element and the light-emitting layer or sub-light-emitting layer formed by the same evaporation process include the same material, and the two have substantially the same thickness. It should be noted that the "substantially the same thickness" here can be understood as: the test element and the light-emitting layer or sub-light-emitting layer formed by the same evaporation process have approximately the same thickness in their respective middle parts, and the thickness in their respective edge parts may be slightly different due to different diffusion areas.

[0104] like Figure 7 As shown, a test assembly area TGA has a first size X1 in the first direction D1 and a second size Y1 in the second direction D2.

[0105] It should be noted that, in the embodiments of the present disclosure, the expression "test component area" refers to the area where the test component is placed, and its size is limited by the field of view of the image acquisition sensor (such as CCD) of the test equipment.

[0106] For example, Figure 5-7 In the embodiment shown, the first size and the second size of the single test component area TGA are respectively equal to Figure 1-3 The embodiment shown has a first size and a second size for a single test assembly area TGA.

[0107] It should also be noted that, in the embodiment of the present disclosure, the test assembly area TGA has a rectangular shape, and the first size X1 of the test assembly area TGA is smaller than the second size Y1. The embodiment of the present disclosure is not limited thereto, and the test assembly area TGA may also have other shapes, such as polygonal, circular, etc.

[0108] like Figure 7 As shown, in one test assembly area TGA, test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R are arranged in an array along a first direction D1 and a second direction D2 in the test assembly area TGA.

[0109] Exemplarily, the test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, and 34R are respectively located in two columns arranged along the first direction. Figure 7 , the column of test elements on the left is recorded as the first column, and the column of test elements on the right is recorded as the second column. The test elements corresponding to the light-emitting layer and / or compensation layer of the light-emitting element 31 below the Tandem structure can be located in the first column, and the test elements corresponding to the light-emitting layer and / or compensation layer of the light-emitting element 32 above the Tandem structure can be located in the second column. Specifically, the test elements 31R, 31G, 31B, and 33R are located in the first column, and the test elements 32R, 32G, 32B, and 34R are located in the second column.

[0110] In the embodiments of the present disclosure, the number of film layers formed by the evaporation process in the display substrate of the tandem structure increases, and accordingly, the number of test elements that need to be arranged in the test component area also increases. Figure 5-7 In the embodiment shown, the number of film layers formed by the evaporation process in the display area is increased to 8, and the number of test elements set in the test component area is increased to 8. When the number of test elements increases, the arrangement of the test elements is changed from a single-column arrangement to a multi-column arrangement, so that the pixel position accuracy detection of the display substrate with a Tandem structure can be achieved without changing the size of a single test component area.

[0111] It should be noted that in Figure 7In the figure, the shape of the orthographic projection of each test element on the substrate 1 is schematically shown, and its shape is schematically shown as a square. However, the embodiments of the present disclosure are not limited to this. The shape of the orthographic projection of each test element on the substrate 1 may include but is not limited to a rectangle, a circle, an ellipse, an approximate circle, a triangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon and the like.

[0112] It should be noted that, in this article, for the convenience of description, the test elements 31R, 31G, and 31B corresponding to the light-emitting layer of the light-emitting element 31 below the Tandem structure are called first test elements, the test elements 32R, 32G, and 32B corresponding to the light-emitting layer of the light-emitting element 32 above the Tandem structure are called second test elements, the test element 33R corresponding to the compensation layer of the light-emitting element 31 below the Tandem structure is called the third test element, and the test element 34R corresponding to the compensation layer of the light-emitting element 32 above the Tandem structure is called the fourth test element.

[0113] Reference Figure 7 , in the same test assembly, the first test element and the second test element of the same color are located in two columns arranged along the first direction D1, and the first test element and the second test element of the same color are located in a row extending along the first direction D1. Specifically, the first test element 31R and the second test element 32R of the same color are located in two columns arranged along the first direction D1, and the first test element 31R and the second test element 32R of the same color are located in a row extending along the first direction D1. The first test element 31G and the second test element 32G of the same color are located in two columns arranged along the first direction D1, and the first test element 31G and the second test element 32G of the same color are located in a row extending along the first direction D1. The first test element 31B and the second test element 32B of the same color are located in two columns arranged along the first direction D1, and the first test element 31B and the second test element 32B of the same color are located in a row extending along the first direction D1.

[0114] In the same test assembly, first test elements of different colors are located in the same column extending along the second direction. For example, first test elements 31R, 31G, 31B of different colors are located in the same column extending along the second direction D2. Additionally or alternatively, in the same test assembly, second test elements of different colors are located in the same column extending along the second direction. For example, second test elements 32R, 32G, 32B of different colors are located in the same column extending along the second direction D2.

[0115] The third test elements 33R and the fourth test elements 34R of the same color are located in two columns arranged along the first direction D1 , and the third test elements 33R and the fourth test elements 34R of the same color are located in a row extending along the first direction D1 .

[0116] Continue to refer to Figure 7 The display substrate 100 may further include a reference mark 7, a first calibration mark 8 and a second calibration mark 9 disposed on the base substrate 1. The reference mark 7, the first calibration mark 8 and the second calibration mark 9 are all located in the test assembly area TGA.

[0117] The reference mark 7 may include a first reference mark portion 71 extending along the first direction D1 and a second reference mark portion 72 extending along the second direction D2 , and the first reference mark portion 71 and the second reference mark portion 72 intersect at a reference point 7O.

[0118] The first alignment mark 8 extends along the first direction D1 , and the second alignment mark 9 extends along the second direction D2 .

[0119] For example, the reference mark 7 may have a cross shape, and the first alignment mark 8 and the second alignment mark 9 may have a straight shape, respectively.

[0120] In some embodiments, in the display area AA, m evaporated film layers are provided, where m is a positive integer greater than or equal to 1. Figure 5-7 In the embodiment shown, m is 8, and the 8 evaporated film layers are respectively the sub-light emitting layer 51R, the sub-light emitting layer 52R, the sub-light emitting layer 51G, the sub-light emitting layer 52G, the sub-light emitting layer 51B, the sub-light emitting layer 52B, the first sub-compensation layer 561R, and the second sub-compensation layer 562R. Accordingly, in the test assembly area TGA, one test assembly includes m test elements, and the m test elements correspond to the m evaporated film layers, respectively, and are respectively used to detect the pixel position accuracy of the m evaporated film layers.

[0121] In an embodiment of the present disclosure, at least one test assembly includes q columns of test elements arranged along a first direction D1 and n rows of test elements arranged along a second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. Figure 7 In the embodiment shown, q = 2 and n = 4. It should be understood that m = q x n.

[0122] In the embodiment of the present disclosure, only one reference mark 7 is provided in one test component area TGA, and the reference mark 7 is used to calibrate the position of the test component area TGA.

[0123] In at least one test assembly area TGA, n first calibration marks 8 are arranged, that is, the number of first calibration marks 8 is consistent with the number of test element rows. The n first calibration marks 8 correspond to n rows of test elements respectively, and are used to detect the position accuracy of the n rows of test elements in the second direction D2.

[0124] In at least one test assembly area TGA, q second calibration marks 9 are arranged, that is, the number of second calibration marks 9 is consistent with the number of test element columns. The q second calibration marks 9 correspond to q columns of test elements respectively, and are used to detect the position accuracy of the q columns of test elements in the first direction D1.

[0125] Exemplarily, the reference mark 7 is located approximately at the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0126] The n first calibration marks 8 correspond one-to-one with the n rows of test elements in position. Specifically, the n first calibration marks 8 are respectively located between two adjacent columns of test elements in the first direction D1. That is to say, in the first direction D1, the i-th first calibration mark 8 is located between the first test element and the second test element in the i-th row of test elements, where 1≤i≤n and i is a positive integer. Through such an arrangement, the position accuracy of multiple test elements in a row can be detected by using one first calibration mark, and at the same time, a close arrangement of multiple test elements and first calibration marks can be achieved.

[0127] like Figure 7 As shown, in a test assembly area TGA, four first calibration marks 8 are arranged, wherein two first calibration marks 8 are located above the reference mark 7 in the second direction, and the other two first calibration marks 8 are located below the reference mark 7 in the second direction.

[0128] The q second calibration marks 9 correspond one-to-one with the q columns of test elements in position. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Wherein, 1≤j≤q and j is a positive integer. With such an arrangement, the position accuracy of multiple test elements in a column can be detected by using one second calibration mark, and at the same time, a close arrangement of multiple test elements and second calibration marks can be achieved.

[0129] like Figure 7As shown, in a test component area TGA, two second calibration marks 9 are arranged, wherein, in the second direction D2, the two second calibration marks 9 are located between the second row of test elements and the third row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0130] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0131] like Figure 7 As shown, a test component area TGA has a first size X1 in the first direction D1 and a second size Y1 in the second direction D2. The first size X1 and the second size Y1 are designed to meet the following requirements: when the CCD of the test equipment takes a picture of the test component area TGA, the image of the entire test component area TGA can be captured by one shot.

[0132] Due to the limitation of the processing accuracy of the evaporation process using FMM, each test element needs to be a certain distance away from each side of the test element TGA during design, that is, a certain margin needs to be formed. Figure 7 As shown, the test elements 31R and 32R located in the top row need to be at a certain distance from the upper side of the test element TGA, which is recorded as the upper margin; the test elements 33R and 34R located in the bottom row need to be at a certain distance from the lower side of the test element TGA, which is recorded as the upper margin; the test elements located in the leftmost first column need to be at a certain distance from the left side of the test element TGA, which is recorded as the left margin; the test elements located in the rightmost second column need to be at a certain distance from the right side of the test element TGA, which is recorded as the right margin. For example, any two of the upper margin, the lower margin, the left margin, and the right margin are substantially equal to each other, or the ratio of any two of the upper margin, the lower margin, the left margin, and the right margin is between 0.8 and 1.2. For example, any one of the upper margin, the lower margin, the left margin, and the right margin is above 20 microns.

[0133] Continue to refer to Figure 7In the same test component, that is, in a single test component area TGA, the first spacing distance W1 of two columns of test elements arranged along the first direction D1 along the first direction D1 needs to meet certain design requirements. Specifically, when each test element is formed by utilizing the evaporation process of FMM, due to factors such as processing accuracy, a single test element has a certain processing accuracy error, and a single margin deviation needs to be reserved on each side for each test element. Based on this, the first spacing distance W1 can be greater than or equal to 150 microns, so that it can be ensured that the adjacent test elements on both sides do not overlap. Furthermore, the first spacing distance W1 can be less than or equal to 390 microns, so that it can be ensured that the two columns of test elements can be arranged within the range of a single test component area TGA.

[0134] Continue to refer to Figure 7 , the n rows of test elements include the kth row of test elements and the k+1th row of test elements adjacent to the reference mark 7, or the kth row of test elements and the k+1th row of test elements adjacent to the second calibration mark 9. The kth row of test elements and the k+1th row of test elements have a second spacing distance H2 in the second direction D2, where 1≤k≤n-1 and k is a positive integer. For example, Figure 7 In the embodiment of , k=2, that is, the test elements in the second row and the test elements in the third row have a second spacing distance H2 in the second direction D2.

[0135] The test elements in the pth row and the test elements in the p+1th row have a third spacing distance H3 in the second direction D2, where 1≤p≤n-1 and p is a positive integer, and p is not equal to k. Figure 7 In the embodiment, p may be equal to 1, that is, the test elements in the first row and the test elements in the second row have a third spacing distance H3 in the second direction D2; p may be equal to 3, that is, the test elements in the third row and the test elements in the fourth row have a third spacing distance H3 in the second direction D2.

[0136] In the embodiment of the present disclosure, the second spacing distance H2 is greater than the third spacing distance H3. Specifically, the second spacing distance H2 is more than twice the third spacing distance H3. Through such a design, on the one hand, a relatively large space can be provided for arranging a row of second calibration marks 9, and on the other hand, each row of test elements can be arranged relatively compactly in the second direction, which is conducive to arranging multiple rows of test elements in the test assembly area TGA.

[0137] Continue to refer to Figure 7, the first imaginary straight line L1 extends along the second direction D2 and passes through the reference point 7O, the second imaginary straight line L2 extends along the second direction D2 and passes through the centers of at least two test elements in a column of test elements (for example, the first column of test elements on the left), and the third imaginary straight line L3 extends along the second direction D2 and passes through the centers of at least two test elements in another column of test elements (for example, the second column of test elements on the right).

[0138] In an embodiment of the present disclosure, a first distance WD1 between the second imaginary straight line L2 and the first imaginary straight line L1 in the first direction D1 is substantially equal to a second distance WD2 between the third imaginary straight line L3 and the first imaginary straight line L1 in the first direction D1, or in other words, a ratio of the first distance WD1 to the second distance WD2 is between 0.8 and 1.2.

[0139] Continue to refer to Figure 7 , the fourth imaginary straight line L4 extends along the first direction D1 and passes through the reference point 7O, the fifth imaginary straight line L5 extends along the first direction D1 and passes through the center of a row of test elements adjacent to the reference mark 7 (for example, the second row of test elements), and the sixth imaginary straight line L6 extends along the first direction D1 and passes through the center of another row of test elements adjacent to the reference mark 7 (for example, the third row of test elements).

[0140] In an embodiment of the present disclosure, the third distance WD3 between the fifth imaginary straight line L5 and the fourth imaginary straight line L4 in the second direction D2 is substantially equal to the fourth distance WD4 between the sixth imaginary straight line L6 and the fourth imaginary straight line L4 in the second direction D2, or in other words, the ratio of the third distance WD3 to the fourth distance WD4 is between 0.8 and 1.2.

[0141] Figure 8 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure.

[0142] like Figure 8 As shown, at least one test assembly includes q columns of test elements arranged along the first direction D1 and n rows of test elements arranged along the second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. For example, q=2, n=5.

[0143] For example, in some embodiments, the first sub-compensation layer disposed on the side of the first light-emitting layer EML1 close to the base substrate may be located in the first sub-pixel SP1 and the second sub-pixel SP2. The second sub-compensation layer disposed on the side of the second light-emitting layer EML2 close to the base substrate may be located in the first sub-pixel SP1 and the second sub-pixel SP2. In other words, the luminous intensity of the red sub-pixel and the green sub-pixel may be increased to offset the loss during transmission.

[0144] exist Figure 8 In the illustrated embodiment, the plurality of test elements 3 may be test elements of a plurality of colors, and for the convenience of description, the test elements of a plurality of colors are marked as test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, 34R, 33G, and 34G, respectively. The test elements 31R, 32R, 31G, 32G, 31B, 32B, 33R, 34R, 33G, and 34G correspond to the sub-light-emitting layer 51R, the sub-light-emitting layer 52R, the sub-light-emitting layer 51G, the sub-light-emitting layer 52G, the sub-light-emitting layer 51B, the sub-light-emitting layer 52B, the first sub-compensation layer portion located in the first sub-pixel, the second sub-compensation layer portion located in the first sub-pixel, the first sub-compensation layer portion located in the second sub-pixel, and the second sub-compensation layer portion located in the second sub-pixel, respectively.

[0145] Combined with reference Figure 7 and Figure 8 , the size of the test assembly area TGA, the size of the test element itself, and the spacing distance between the test elements can remain unchanged.

[0146] The reference mark 7 is located approximately at the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0147] The five first calibration marks 8 correspond to the five rows of test elements in position. Specifically, the five first calibration marks 8 are respectively located between two adjacent columns of test elements in the first direction D1. That is, in the first direction D1, the i-th first calibration mark 8 is located between the first test element and the second test element in the i-th row of test elements, where 1≤i≤5 and i is a positive integer. With such an arrangement, the position accuracy of multiple test elements in a row can be detected using one first calibration mark, and at the same time, a close arrangement of multiple test elements and first calibration marks can be achieved.

[0148] like Figure 8 As shown, in a test assembly area TGA, five first calibration marks 8 are arranged, wherein three first calibration marks 8 are located above the reference mark 7 in the second direction, and the other two first calibration marks 8 are located below the reference mark 7 in the second direction.

[0149] The two second calibration marks 9 correspond to the two columns of test elements in position. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Wherein, 1≤j≤2 and j is a positive integer. With such an arrangement, the position accuracy of multiple test elements in a column can be detected by using one second calibration mark, and at the same time, a close arrangement of multiple test elements and second calibration marks can be achieved.

[0150] like Figure 8 As shown, in a test component area TGA, two second calibration marks 9 are arranged, wherein, in the second direction D2, the two second calibration marks 9 are located between the third row of test elements and the fourth row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0151] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0152] Fig. 9 is a partial enlarged view of a test component area in a display substrate according to some other exemplary embodiments of the present disclosure.

[0153] like Fig. 9 As shown, at least one test assembly includes q columns of test elements arranged along the first direction D1 and n rows of test elements arranged along the second direction D2, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4. For example, q=2, n=6.

[0154] Combined with reference Figure 7 , Figure 8 and Fig. 9 , compared to Figure 7 and Figure 8 , Fig. 9 The size of the test component area TGA remains unchanged, and at least a portion of the size of the test element itself and the spacing distance between the test elements can be reduced, so that multiple elements arranged in 6 rows and 2 columns can be arranged in a single test component area TGA with unchanged size.

[0155] The reference mark 7 is located approximately at the center of the test assembly area TGA. In the first direction D1, the reference mark 7 is located between two adjacent columns of test elements; in the second direction D2, the reference mark 7 is located between two adjacent rows of test elements.

[0156] The six first calibration marks 8 correspond to the six rows of test elements in position. Specifically, the six first calibration marks 8 are located between two adjacent columns of test elements in the first direction D1. That is, in the first direction D1, the i-th first calibration mark 8 is located between the first test element and the second test element in the i-th row of test elements, where 1≤i≤6 and i is a positive integer. With such an arrangement, the position accuracy of multiple test elements in a row can be detected using one first calibration mark, and at the same time, a close arrangement of multiple test elements and first calibration marks can be achieved.

[0157] like Fig. 9 As shown, in a test assembly area TGA, six first calibration marks 8 are arranged, wherein three first calibration marks 8 are located above the reference mark 7 in the second direction, and the other three first calibration marks 8 are located below the reference mark 7 in the second direction.

[0158] The two second calibration marks 9 correspond to the two columns of test elements in position. Specifically, in the first direction D1, the jth second calibration mark 9 is aligned with the jth column of test elements; in the second direction D2, the jth second calibration mark 9 is located between two adjacent test elements in the jth column of test elements. Wherein, 1≤j≤2 and j is a positive integer. With such an arrangement, the position accuracy of multiple test elements in a column can be detected by using one second calibration mark, and at the same time, a close arrangement of multiple test elements and second calibration marks can be achieved.

[0159] like Fig. 9 As shown, in a test component area TGA, two second calibration marks 9 are arranged, wherein, in the second direction D2, the two second calibration marks 9 are located between the third row of test elements and the fourth row of test elements; in the first direction D1, one second calibration mark 9 is located on the left side of the reference mark 7, and the other second calibration mark 9 is located on the right side of the reference mark 7.

[0160] In an embodiment of the present disclosure, multiple test elements are prepared by utilizing the evaporation process of FMM, and the test elements need to be within the field of view of the CCD of the test equipment when in use. Based on this, while the size of a single test component area TGA remains unchanged, the arrangement, size, and spacing distance of the multiple test elements in the test component area TGA need to be designed.

[0161] Fig. 10A and Fig. 10B They are respectively partial enlarged views of a test component area in a display substrate according to further exemplary embodiments of the present disclosure.

[0162] In the case where a single test assembly includes a large number of test elements, a plurality of test assembly areas may be provided for arranging the large number of test elements.

[0163] like Fig. 10A As shown, the display substrate 100 includes two adjacent test assembly areas TGA, and the test assemblies in the two test assembly areas TGA are arranged side by side along the first direction D1. For example, the arrangement of the multiple test elements in each test assembly area TGA can refer to the above-mentioned Figure 7 , Figure 8 and Fig. 9 The description will not be repeated here.

[0164] like Fig. 10B As shown, the display substrate 100 includes two adjacent test assembly areas TGA, and the test assemblies in the two test assembly areas TGA are arranged side by side along the second direction D1. For example, the arrangement of the multiple test elements in each test assembly area TGA can refer to the above-mentioned Figure 7 , Figure 8 and Fig. 9 The description will not be repeated here.

[0165] Fig.11 1 is a schematic plan view of a display substrate according to some further exemplary embodiments of the present disclosure.

[0166] In the embodiment of the present disclosure, the plurality of test components 2 are respectively disposed adjacent to the first side edge AA1, the second side edge AA2, the third side edge AA3, the fourth side edge AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4. Figure 5 and Fig.11 , schematically showing 8 test components 2. One test component 2 is arranged adjacent to the first side edge AA1, and one test component 2 is respectively arranged near the first side edge AA1, the second side edge AA2, the third side edge AA3, the fourth side edge AA4, the first corner AC1, the second corner AC2, the third corner AC3 and the fourth corner AC4.

[0167] like Figure 5 As shown, the display substrate 100 includes a driver chip IC disposed adjacent to the first side AA1, and at least one test component 2 disposed adjacent to the first side AA1 is located between the driver chip IC and the first side AA1 of the display area. The inventor has found through research that the closer the distance between the test component and the display area, the closer the evaporation condition of the test component is to the evaporation condition of each film layer in the display area. In this embodiment, each test component 2 is closer to the display area AA, which can achieve more accurate detection of the pixel position accuracy in the display area.

[0168] Alternatively, if Fig.11 As shown, at least one of the test components 2 disposed adjacent to the first side AA1 is located on a side of the driver chip IC away from the first side AA1 of the display area AA.

[0169] Fig.12 is a schematic structural diagram of a testing device for detecting pixel position accuracy of a display substrate according to some exemplary embodiments of the present disclosure.

[0170] like Fig.12 As shown, the testing device 200 may include a white light source 210 and an ultraviolet light source 220. Exemplarily, the testing method may be performed according to the following steps.

[0171] In step S110 , the testing device 200 is moved above the testing component area TGA of the display substrate 100 , and the white light source 210 is turned on to illuminate the testing component area TGA, so as to obtain a first image of the testing component area TGA under the illumination of white light.

[0172] Specifically, in the process of moving the test device 200 above the test component area TGA, the test device 200 may be aligned with the reference mark 7 in the test component area TGA to calibrate the position of the test device 200 through the reference mark 7 .

[0173] In this step, the first image may be subjected to grayscale processing to obtain the contour of each test element.

[0174] In step S120 , the white light source 210 of the testing device 200 is turned off.

[0175] In step S130, the test component area TGA is illuminated. For example, the ultraviolet light source 220 on the test device 200 is turned on to activate the test element to emit light under the irradiation of ultraviolet light, and a second image of the test component area under the irradiation of ultraviolet light is obtained, and the contour pattern of the test element can be obtained in the second image.

[0176] In step S140 , the pixel position accuracy of the display substrate 100 is detected according to the first image and the second image.

[0177] Combined with reference Figures 7 to 10B Specifically, an image processing algorithm may be used to obtain the contours of the first calibration mark 7, the second calibration mark 8, and the test element 3 in the figure. Figure 7Take the test element 31R in as an example. The imaginary straight lines 7L and 8L extending toward the test element 31R are obtained respectively for the outline of the first calibration mark 7 and the outline of the second calibration mark 8, and the intersection O1 of the imaginary straight lines 7L and 8L is the theoretical center position of the test element 31R. Then, the two symmetry axes AX1 and AX2 of the outline of the test element 31R are obtained, and the intersection O2 of the two symmetry axes AX1 and AX2 is the actual center position of the test element 31R. Since the test device 200 is aligned with the reference mark 7, the reference mark 7 can be selected as the coordinate origin to establish a Cartesian coordinate system, and the coordinate values ​​of the intersection O1 and the intersection O2 can be obtained. On this basis, the offset ΔX and ΔY of the intersection O2 relative to the intersection O1 in the horizontal and vertical coordinates can be obtained, that is, the offset of the test element. The larger the offset of the test element, the lower the pixel position accuracy; the smaller the offset of the test element, the higher the pixel position accuracy.

[0178] The embodiments of the present disclosure further provide a display device, which may include the display substrate described in any of the above embodiments. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0179] It should be understood that the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, and the beneficial effects of the display device are the same as the beneficial effects of the above-mentioned display substrate, which will not be repeated here.

[0180] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a test component area; A plurality of pixel units are provided on the substrate, the plurality of pixel units are arranged in an array in the display area along a first direction and a second direction, at least one of the pixel units comprises a plurality of light emitting elements stacked along a third direction, the plurality of light emitting elements stacked along the third direction comprises: a charge generation layer provided on the substrate; a first light emitting layer provided on a side of the charge generation layer close to the substrate; and a second light emitting layer provided on a side of the charge generation layer away from the substrate, wherein the first direction intersects with the second direction, and the third direction is perpendicular to the first direction and the second direction; and At least one test component is disposed on the substrate, the at least one test component is located in the test component area, the at least one test component includes a plurality of test elements, and the plurality of test elements are arranged in an array in the test component area along a first direction and a second direction, wherein the plurality of test elements include a first test element and a second test element, the first test element and the first light-emitting layer include the same material, the second test element and the second light-emitting layer include the same material, and the first test element and the second test element are located in two rows; and The display substrate further includes a first calibration mark disposed on the base substrate, the first calibration mark is located in the test component area, and the first calibration mark is located between two adjacent rows of test elements.

2. The display substrate according to claim 1, wherein: The first light-emitting layer includes a first sub-light-emitting layer of multiple colors, the at least one test component includes a first test element of multiple colors, and the first test element of multiple colors and the first sub-light-emitting layer of multiple colors include the same material; The second light-emitting layer includes a second sub-light-emitting layer of a plurality of colors, the at least one test component includes a second test element of a plurality of colors, and the second test element of the plurality of colors and the second sub-light-emitting layer of the plurality of colors include the same material; and The test component area has a rectangular shape, and has a first dimension along a first direction and a second dimension along a second direction, the first dimension is smaller than the second dimension, and in the same test component, the first test element and the second test element of the same color are located in two columns arranged along the first direction, and the first test element and the second test element of the same color are located in a row extending along the first direction.

3. The display substrate according to claim 2, wherein: In the same test assembly, the first test elements of different colors are located in the same column extending along the second direction; and / or, In the same test assembly, the second test elements of different colors are located in the same column extending along the second direction.

4. The display substrate according to any one of claims 1 to 3, characterized in that: The plurality of light emitting elements stacked along the third direction further include: a first compensation layer disposed on a side of the first light emitting layer close to the base substrate; and a second compensation layer disposed on a side of the second light emitting layer close to the base substrate; and The plurality of test elements further include a third test element and a fourth test element, the third test element and the first compensation layer include the same material, the fourth test element and the second compensation layer include the same material, and the third test element and the fourth test element are located in two rows.

5. The display substrate according to claim 4, wherein: The first compensation layer and the second compensation layer are of the same color, and the third test element and the fourth test element are located in the same row extending along the first direction.

6. The display substrate according to any one of claims 2 to 5, characterized in that: In the same test assembly, the first test element and the third test element of different colors are located in the same column extending along the second direction; and / or, In the same test assembly, the second test elements and the fourth test elements of different colors are located in the same column extending along the second direction.

7. The display substrate according to any one of claims 1 to 6, characterized in that: The display substrate further comprises a reference mark disposed on the base substrate, wherein the reference mark is located in the test component area and is located between two adjacent columns of test elements in a first direction.

8. The display substrate according to claim 7, wherein: The reference mark is located between two adjacent rows of test elements in the second direction.

9. The display substrate according to claim 7, wherein: The display substrate further includes a second calibration mark disposed on the base substrate, the second calibration mark is located in the test component area, the second calibration mark extends along a second direction, and the second calibration mark is located between two adjacent rows of test elements in the second direction.

10. The display substrate according to claim 1, wherein: At least one of the test components includes q columns of test elements arranged along the first direction and n rows of test elements arranged along the second direction, wherein q is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 4.

11. The display substrate according to claim 10, wherein: In the same test assembly, a first spacing distance between two adjacent columns of test elements arranged along the first direction is greater than or equal to 150 micrometers; and / or, In the same test assembly, a first spacing distance between two adjacent columns of test elements arranged along the first direction is less than or equal to 390 micrometers.

12. The display substrate according to claim 10 or 11, characterized in that: The reference mark includes a first reference mark portion extending along a first direction and a second reference mark portion extending along a second direction, wherein the first reference mark portion and the second reference mark portion intersect at a reference point; as well as A first imaginary straight line extends along the second direction and passes through the reference point, a second imaginary straight line extends along the second direction and passes through the centers of at least two test elements in a column of test elements, a third imaginary straight line extends along the second direction and passes through the centers of at least two test elements in another column of test elements, and a ratio of a first distance in the first direction between the second imaginary straight line and the first imaginary straight line to a second distance in the first direction between the third imaginary straight line and the first imaginary straight line is between 0.8 and 1.

2.

13. The display substrate according to claim 12, wherein: A fourth imaginary straight line extends along the first direction and passes through the reference point, a fifth imaginary straight line extends along the first direction and passes through the center of a row of test elements adjacent to the reference mark, a sixth imaginary straight line extends along the first direction and passes through the center of another row of test elements adjacent to the reference mark, and a ratio of a third distance between the fifth imaginary straight line and the fourth imaginary straight line in the second direction to a fourth distance between the sixth imaginary straight line and the fourth imaginary straight line in the second direction is between 0.8 and 1.

2.

14. The display substrate according to any one of claims 10 to 13, characterized in that: The display substrate includes n first calibration marks, and in a first direction, the i-th first calibration mark is located between the first test element and the second test element in the i-th row of test elements, wherein 1≤i≤n and i is a positive integer.

15. The display substrate according to claim 14, wherein: The display substrate includes q second calibration marks, and one of the q second calibration marks in the second direction is located between two first test elements in the first column.

16. The display substrate according to claim 14, wherein: The n rows of test elements include a kth row of test elements and a k+1th row of test elements adjacent to the reference mark, and the kth row of test elements and the k+1th row of test elements have a second spacing distance in the second direction, wherein 1≤k≤n-1 and k is a positive integer; The test elements in the pth row and the test elements in the p+1th row have a third spacing distance in the second direction, wherein 1≤p≤n-1 and p is a positive integer, and p is not equal to k; and The second spacing distance is greater than the third spacing distance.

17. The display substrate according to claim 16, wherein: The second spacing distance is more than twice the third spacing distance.

18. The display substrate according to any one of claims 1 to 17, characterized in that: The display area of ​​the display substrate includes a first side, a second side, a third side, a fourth side, a first corner, a second corner, a third corner and a fourth corner, wherein the first corner, the second corner, the third corner and the fourth corner are respectively located at the connection of two adjacent sides among the first side, the second side, the third side and the fourth side; as well as The display substrate includes a plurality of the test components, and the plurality of the test components are respectively disposed adjacent to the first side, the second side, the third side, the fourth side, the first corner, the second corner, the third corner, and the fourth corner.

19. The display substrate according to claim 18, wherein: The display substrate includes a driving chip disposed adjacent to the first side edge, and at least one of the testing components disposed adjacent to the first side edge is located between the driving chip and the first side edge of the display area.

20. The display substrate according to claim 18, wherein: The display substrate includes a driving chip disposed adjacent to the first side, and at least one of the testing components disposed adjacent to the first side is located on a side of the driving chip away from the first side of the display area.

21. The display substrate according to any one of claims 1 to 20, characterized in that: The display substrate comprises two adjacent test component areas, and the test components in the two test component areas are arranged side by side along a first direction; and / or, The display substrate includes two adjacently arranged test component areas, and the test components in the two test component areas are arranged side by side along the second direction.

22. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 21.

Images