A method and circuit for suppressing temperature drift of a charge and discharge capacitor detection circuit

Abstract

The present invention discloses a temperature drift suppression method and circuit for a charge and discharge capacitor detection circuit, and belongs to the technical field of electronic circuits. The circuit includes: a first GPIO interface, one end of which is connected to a capacitor to be measured through a first resistor; a first analog switch, one end of which is connected to the capacitor to be measured; a second GPIO interface, one end of which is connected to the negative power supply terminal of the first analog switch, and a third GPIO interface, one end of which is connected to the output end of the first analog switch; and a second analog switch, the input end of which is connected to the output end of the first analog switch, and the output end of which is connected to the first capacitor; and the input end of the second analog switch can be grounded through the third GPIO interface; in the charging stage, the capacitor to be measured can be charged through the first resistor and the high level output by the first GPIO interface, and the second GPIO interface also outputs a high level to reduce the potential difference between the positive and negative electrodes of the first analog switch.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a method and circuit for suppressing temperature drift of a charge and discharge capacitor detection circuit. Background Art

[0002] The charge and discharge capacitor detection circuit is a circuit used to measure the capacitance value, which is usually composed of a fixed voltage source, a capacitor to be measured, an analog switch, a resistor, and a reference capacitor. During the detection process, the charge and discharge state of the capacitor to be measured is controlled by the analog switch, thereby realizing the detection of the capacitance signal. The charge and discharge capacitor detection circuit has a wide range of applications in the fields of electronic measurement, automatic control, etc. For example, in the electronic manufacturing process, this circuit can be used to detect whether the capacitor elements on the circuit board meet the design requirements; in the automatic control system, this circuit can be used to monitor the state of the capacitor sensor, thereby realizing precise control of the system.

[0003] However, in practical applications, analog switches, as key components for controlling the charging and discharging of capacitors, usually contain complex semiconductor structures inside. These structures have parasitic effects, the most notable of which are junction capacitance and leakage current. Junction capacitance is a capacitive effect that exists in both the on and off states of the switch. It will cause voltage fluctuations when the switch is in action, thereby affecting the charging and discharging process of the capacitor. Leakage current is the flow of tiny currents caused by the internal characteristics of semiconductor materials when the switch is in the off state. It will gradually change the charge state of the capacitor over a long period of time, thus posing a threat to the accuracy and stability of the circuit. In particular, these effects will intensify when the temperature changes, resulting in the so-called "temperature drift" phenomenon, which seriously affects the accuracy and stability of the circuit. Summary of the invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to apply for a temperature drift suppression method and circuit for a charging and discharging capacitor detection circuit, which uses four universal input and output ports to output specific signals to charge the capacitor instead of a fixed power supply voltage, and completes the control of the analog switch, effectively solving the temperature drift problem in the prior art and improving the stability of the circuit. At the same time, it charges the capacitor more quickly and accurately, thereby improving the efficiency of the circuit.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0006] A first aspect of the present invention relates to a temperature drift suppression circuit for a charge and discharge capacitor detection circuit, comprising:

[0007] A first GPIO interface, one end of which is connected to the capacitor to be measured via a first resistor;

[0008] A first analog switch, one end of which is connected to the capacitor to be measured;

[0009] A second GPIO interface, one end of which is connected to the negative power supply terminal of the first analog switch,

[0010] A third GPIO interface, one end of which is connected to the output end of the first analog switch;

[0011] and a second analog switch, wherein the input end is connected to the output end of the first analog switch, and the output end is connected to the first capacitor; and the input end of the second analog switch can be grounded through a third GPIO interface;

[0012] In the charging stage, the capacitor to be measured can be charged through the first resistor and the high level output by the first GPIO interface, and the second GPIO interface outputs a high level to reduce the potential difference between the positive and negative electrodes of the first analog switch.

[0013] Optionally, the first analog switch and the second analog switch are respectively provided with a fourth GPIO interface and a fifth GPIO interface, which are respectively used to control the on and off of the first analog switch and the second switch.

[0014] Optionally, the first capacitance is more than 1000 times the capacitance of the capacitance to be measured.

[0015] Optionally, the first capacitor has a capacitance greater than 1000 times the junction capacitance of the first analog switch.

[0016] A second aspect of the present invention relates to a capacitance detection circuit, comprising the above-mentioned temperature drift suppression circuit for a charging and discharging capacitance detection circuit, and an operational amplifier; the non-phase input terminal of the operational amplifier is connected to a second resistor, the first capacitor, and the output terminal of the second analog switch, and the inverting input terminal of the operational amplifier is short-circuited with its output terminal.

[0017] A third aspect of the present invention relates to a method for suppressing temperature drift of a charge and discharge capacitor detection circuit, comprising the following steps:

[0018] Constructing the above-mentioned temperature drift suppression circuit for the charge and discharge capacitor detection circuit;

[0019] During the charging phase, the capacitor to be tested is connected through the resistor R 1 The first GPIO interface is charged with a high level output, and the second GPIO interface also outputs a high level, thereby reducing the potential difference between the positive and negative electrodes of the first analog switch;

[0020] In the discharge stage, the first GPIO interface is switched to a high impedance state, and the second GPIO interface is controlled to output a low level, and the third GPIO interface is switched to a high impedance state;

[0021] The first analog switch and the second analog switch are turned on so that the capacitor to be tested charges the first capacitor.

[0022] Optionally, a delay time T1 is provided between the step of converting the first GPIO interface to a high impedance state and the step of controlling the second GPIO interface to output a low level.

[0023] Optionally, a delay time T2 is set between the step of controlling the second GPIO interface to output a low level and the step of converting the third GPIO interface to a high impedance state.

[0024] Optionally, a delay time T3 is provided between the step of converting the third GPIO interface to a high-impedance state and the step of turning on the first analog switch and the second analog switch.

[0025] More specifically, the method and circuit for suppressing temperature drift in a charge and discharge capacitor detection circuit of the present invention include a capacitor to be tested C x , the first resistor R 1 , first GPIO interface, second GPIO interface, first analog switch S1, third GPIO interface, second analog switch S2, fourth GPIO interface, fifth GPIO interface, first capacitor C 1 , the second resistor R 2 And components such as operational amplifier A1. Among them, the capacitor to be measured C x One end is regarded as virtual ground, and the other end is connected to the first resistor R 1 and one end of the first analog switch S1. The first resistor R 1 The other end of the first analog switch S1 is connected to the first GPIO interface, and the output end of the first analog switch S1 is connected to the input end of the second analog switch S2 and the third GPIO interface. In addition, the negative power supply end of the first analog switch S1 is connected to the second GPIO interface, and the output end of the second analog switch S2 is connected to the first capacitor. C 1 One end of the second resistor R 2 and the non-inverting input terminal of the operational amplifier A1. C 1 The other end of the second resistor R 2 The other end of is grounded, and the inverting input terminal and output terminal of the operational amplifier A1 are short-circuited. The fourth GPIO interface is responsible for controlling the on-off of the first analog switch S1, and the fifth GPIO interface is responsible for controlling the on-off of the second analog switch S2.

[0026] Furthermore, a method for suppressing temperature drift of a charge and discharge capacitor detection circuit comprises the following steps:

[0027] In the charging stage, the capacitor to be tested is charged by outputting a high level through the first GPIO interface, and the second GPIO interface is controlled to output a high level at the same time, so that the potential difference between the positive and negative electrodes of the power supply of the first analog switch is smaller than that in the normal working state, so as to eliminate the charging of the junction capacitance of the input terminal of the first analog switch;

[0028] In the discharge stage, the first GPIO interface is first turned into a high-impedance state, and then the second GPIO interface is controlled to output a low level, so that the first analog switch enters a normal working state, and then the fourth GPIO interface and the fifth GPIO interface are controlled to output a high level to turn on the first analog switch and the second analog switch, so that the capacitor to be tested charges the first capacitor through the two switches;

[0029] During the discharge process, the input end of the second analog switch is grounded through the third GPIO interface to isolate the surge current and guide it into the ground to prevent it from being coupled to the first capacitor through the input end of the second analog switch.

[0030] Furthermore, the capacitor to be tested C x During discharge:

[0031] During the discharge process, the first GPIO interface is first switched to a high impedance state, delaying the time T1 to ensure that the charging process is completed, and then the second GPIO interface is controlled to output a low level to enable the first analog switch S1 to enter a normal working state.

[0032] The third GPIO interface and the input end of the second analog switch S2 are grounded, so that the surge current that may be generated by the first analog switch S1 is introduced into the ground line to prevent coupling to the first capacitor C 1 middle.

[0033] After the first analog switch S1 enters the normal working state, it delays for T2 time to ensure that its working state is stable, and then controls the fourth GPIO interface and the fifth GPIO interface to output a high level, so that the first analog switch S1 and the second analog switch S2 are turned on, so that the capacitor to be measured C x The first capacitor is connected to the C 1 Charge.

[0034] Furthermore, the first capacitor C 1 The capacitance value is much larger than the junction capacitance of the capacitor to be measured and the analog switch. During the discharge process, the junction capacitance of the input and output terminals of the first analog switch S1 and the second analog switch S2 can be ignored.

[0035] A fourth aspect of the present invention relates to a capacitance detection sensor, comprising the above-mentioned temperature drift suppression circuit for a charging and discharging capacitance detection circuit, or the above-mentioned capacitance detection circuit.

[0036] Beneficial effects of the present invention:

[0037] The circuit and control method of the present invention, during the charging process of the capacitor to be tested, maintain a small potential difference between the positive and negative poles of the first analog switch through the first GPIO interface and the second GPIO interface, thereby avoiding charging the junction capacitance. On the other hand, during the discharge process, the surge current generated by the first analog switch when the second GPIO interface is in a low level state is isolated by the second analog switch. At the same time, the second analog switch is grounded through the third GPIO interface to export the generated surge current. In summary, the present invention suppresses the temperature drift phenomenon caused by the junction capacitance and leakage current of the analog switch through a specific circuit design and control method, thereby improving the accuracy and stability of capacitance detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described below in conjunction with the accompanying drawings.

[0039] Figure 1 Schematic diagram of the charge and discharge capacitor detection circuit for suppressing temperature drift for the present application;

[0040] Figure 2 This is a signal output timing diagram of the five GPIO interfaces in this application.

[0041] Explanation of the accompanying drawings: 1. First GPIO interface; 2. Second GPIO interface; 3. Third GPIO interface; 4. Fourth GPIO interface; 5. Fifth GPIO interface. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Example 1

[0044] like Figure 1 As shown, a temperature drift suppression circuit for a charge and discharge capacitor detection circuit includes a capacitor to be tested C x , the first resistor R 1, first GPIO interface 1, second GPIO interface 2, first analog switch S1, third GPIO interface 3, second analog switch S2, fourth GPIO interface 4, fifth GPIO interface 5, first capacitor C 1 , the second resistor R 2 And components such as operational amplifier A1.

[0045] In this embodiment, the capacitor to be measured C x As a capacitive sensor, one end is regarded as a virtual ground, and the other end is connected to the first resistor R 1 and one end of the first analog switch S1. The first resistor R 1 The other end of the first analog switch S1 is connected to the first GPIO interface 1, and the output end of the first analog switch S1 is connected to the input end of the second analog switch S2 and the third GPIO interface 3. In addition, the negative power supply terminal of the first analog switch S1 is connected to the second GPIO interface 2, and the output end of the second analog switch S2 is connected to the first capacitor C 1 One end of the second resistor R 2 and the non-inverting input terminal of the operational amplifier A1. The first capacitor C 1 The other end of the second resistor R 2 The other end of each is grounded, and the inverting input terminal and the output terminal of the operational amplifier A1 are short-circuited. The fourth GPIO interface 4 is responsible for controlling the on-off of the first analog switch S1, and the fifth GPIO interface 5 is responsible for controlling the on-off of the second analog switch S2.

[0046] During the charging phase, the capacitor to be tested C x Through the first resistor R 1 The first GPIO interface 1 outputs a high level to charge. At this time, the second GPIO interface 2 also outputs a high level, so that the potential difference between the positive and negative electrodes of the power supply of the first analog switch S1 is smaller than its normal working state, thereby eliminating the charging process on the junction capacitance of the first analog switch input terminal. C p1 charging.

[0047] After entering the discharge phase, the first GPIO interface 1 is first turned into a high impedance state and waits for T1 time (T1 is a preset delay time, used to ensure that the charging process is completed). Subsequently, the second GPIO interface 2 outputs a low level, so that the first analog switch S1 enters a normal working state. After waiting for T2 time (T2 is another preset delay time, used to ensure that the first analog switch S1 works stably), the third GPIO interface 3 is also turned into a high impedance state. After continuing to wait for T3 time (T3 is another preset delay time, used to ensure that the circuit state is stable), the fourth GPIO interface 4 and the fifth GPIO interface 5 output a high level to turn on the first analog switch S1 and the second analog switch S2, so that the capacitor to be tested C x Through these two switches, the first capacitor C 1 At this time, the output of operational amplifier A1 will produce a corresponding voltage output, which is consistent with the capacitor to be measured. C x is proportional to the capacitance value.

[0048] During the discharge process, since the first analog switch S1 generates a surge current when the second GPIO interface 2 outputs a low level, the present invention isolates this influence by adding a second analog switch S2. At the same time, the input end of the second analog switch S2 is grounded through the third GPIO interface 3 to further guide the surge current to the ground, thereby preventing it from being coupled to the first capacitor through the input end of the second analog switch S2. C 1 middle.

[0049] In the above process, the signal output timing diagram of each GPIO interface is as follows: Figure 2 shown.

[0050] At the same time, the first capacitor C 1 The capacitance is set to 2.2nF. During the discharge process, since its capacitance is much larger than the junction capacitance C of the input and output terminals of the two analog switches, p1 and C p2 , so the analog switch junction current can be ignored.

[0051] In summary, the present invention effectively suppresses the temperature drift phenomenon caused by junction capacitance and leakage current of the analog switch in the charge and discharge capacitance detection circuit by optimizing the control logic and circuit design of the analog switch, thereby improving the accuracy and stability of capacitance detection.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0053] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A method for suppressing temperature drift of a charge and discharge capacitor detection circuit, characterized in that: The following steps are involved: Construct a temperature drift suppression circuit for a charge and discharge capacitor detection circuit, including: A first GPIO interface, one end of which is connected to the capacitor to be measured via a first resistor; A first analog switch, one end of which is connected to the capacitor to be measured; A second GPIO interface, one end of which is connected to the negative power supply terminal of the first analog switch, A third GPIO interface, one end of which is connected to the output end of the first analog switch; and a second analog switch, wherein the input end is connected to the output end of the first analog switch, and the output end is connected to the first capacitor; and the input end of the second analog switch can be grounded through a third GPIO interface; In the charging stage, the capacitor to be tested can be charged through the first resistor and the high level output by the first GPIO interface, and the second GPIO interface outputs a high level, reducing the potential difference between the positive and negative electrodes of the first analog switch; In the discharge stage, the first GPIO interface is switched to a high impedance state, and the second GPIO interface is controlled to output a low level, and the third GPIO interface is switched to a high impedance state; The first analog switch and the second analog switch are turned on so that the capacitor to be tested charges the first capacitor.

2. The method for suppressing temperature drift of a charge and discharge capacitor detection circuit according to claim 1, characterized in that: A delay time T1 is provided between the step of the first GPIO interface being changed to a high impedance state and the step of controlling the second GPIO interface to output a low level.

3. The temperature drift suppression method for a charge and discharge capacitor detection circuit according to claim 1, characterized in that: A delay time T2 is set between the step of controlling the second GPIO interface to output a low level and the step of converting the third GPIO interface to a high impedance state.

4. The method for suppressing temperature drift of a charge and discharge capacitor detection circuit according to claim 1, characterized in that: A delay time T3 is provided between the step of converting the third GPIO interface into a high impedance state and the step of turning on the first analog switch and the second analog switch.

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