A method for automatically calculating alignment chip coordinate values in a photolithographic pattern

Abstract

This invention discloses a method for automatically calculating the coordinate values ​​of aligned chips in a photolithographic pattern. The method includes the following steps: S1, obtaining the size of a single chip, the number of rows and columns of chips in a cell domain; forming a wafer drawing, defining the center point coordinates of the cell domain pattern as (0,0); S2, designing and arranging aligned chip pattern templates in the cell domain pattern; S3, automatically identifying the base point coordinates of each aligned chip pattern template, and calculating the differences in the X and Y directions between the base point coordinates of different aligned chip pattern templates and the center point coordinates of the cell domain pattern; these differences are the coordinate values ​​of the aligned chip patterns. Using the method described in this invention, the coordinate values ​​of aligned chip patterns can be automatically calculated, effectively avoiding various human errors, greatly improving the accuracy of the drawings, avoiding rework, and maximizing delivery time and cost savings.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a method for automatically calculating the coordinate values ​​of aligned chips in a photolithographic pattern. Background Technology

[0002] With the continuous development of packaging technology, in the field of photolithography, packaging processes such as eWLB (embedded Wafer Level BGA), FOCT-S (FANOUT-Connected Tech-silicon), and FOCT-R (FANOUT-Connected Tech-RDL) all require exposure alignment by inputting the coordinate values ​​of the alignment chip (mark) pattern, as long as no actual wafer is used during exposure.

[0003] A single cell field contains 2 to 4 alignment chips, and each alignment chip contains more than 2 alignment patterns. Each alignment pattern requires coordinate values.

[0004] In conventional design, designers need to first draw a cell field graphic and a mark graphic, and manually annotate the distance between the mark graphic and the cell field, recording it in a table. Therefore, it's necessary to measure and read the coordinate values ​​of different mark graphics in each layer of the mask within a cell field from the CAD drawing. During conventional measurement, in the CAD drawing interface, click "Annotation" - "Linear," move the mouse to the center point of the mark graphic and confirm, then move the mouse again to the center point of the field and confirm. This allows you to extract the distance values ​​in the X / Y directions, which you can then manually enter.

[0005] The above manual operation is prone to errors in identifying the center point. The slight error in the selection of the center point cannot be detected by the naked eye unless magnified. In addition, there is a certain probability of error when manually inputting values.

[0006] Due to the uncontrollable nature of manual operation, errors are prone to occur, leading to exposure deviations during the exposure process, resulting in unqualified products and rework.

[0007] Therefore, there is an urgent need to provide a method that can automatically calculate the coordinate values ​​of the aligned chip in the lithographic pattern. Summary of the Invention

[0008] To address the aforementioned issues, this invention provides a method for automatically calculating the coordinate values ​​of aligned chips in a photolithography pattern. This method can automatically calculate the coordinate values ​​of aligned chip patterns, effectively avoiding various human errors, greatly improving the accuracy of drawings, avoiding rework, and maximizing delivery time and cost savings.

[0009] To achieve the above objectives, this invention discloses a method for automatically calculating the coordinate values ​​of aligned chips in a photolithographic pattern, the method comprising the following steps:

[0010] S1. Obtain the X-direction dimension step_X and Y-direction dimension step_Y of a single chip, the number of chip rows ReticleX_F1 and the number of chip columns ReticleY_F1 in the cell domain; and form a wafer drawing, which includes a cell domain graphic, and define the center point coordinates of the cell domain graphic as (0,0);

[0011] S2. Design the chip alignment template in the cell domain graphic. The specific method is as follows:

[0012] a. Each layer of mask pattern in the unit domain pattern contains at least two aligned chip pattern templates, and the distance between the aligned chip pattern templates in adjacent mask patterns is at least 150μm.

[0013] b. Create blocks and name the different alignment chip graphic templates separately. The naming format is: layer-alignment chip number-alignment chip graphic template number, and use the center point of each alignment chip graphic template as the base point coordinate.

[0014] S3. Automatically identify the base point coordinates of each aligned chip graphic template, and calculate the difference in the X and Y directions between the base point coordinates of different aligned chip graphic templates and the center point coordinates of the unit domain graphic; the difference is the coordinate value of the aligned chip graphic.

[0015] In some implementations, the mask pattern file has multiple layers, and the distance between adjacent mask patterns and the alignment chip pattern templates is at least 150 μm to ensure accurate identification of each alignment chip pattern template.

[0016] In some implementations, different alignment chip graphic templates are collected to form a template library, and the templates are called according to their names.

[0017] In some implementations, in step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

[0018] In some implementations, the above method further includes step S4: compiling all the measurement values ​​from the previous step into a form and outputting them as needed.

[0019] In some implementations, the verification step is as follows: if the spacing between the alignment chip graphic templates does not exceed the specified value, a form is output; otherwise, no form is output.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] This invention establishes alignment chip pattern templates for various common packaging products. For products that do not use actual wafers during exposure, it is only necessary to draw the cell domain pattern once according to the cell domain pattern layout set by the FAB plant. However, the alignment chip pattern does not need to be drawn repeatedly and the corresponding alignment chip pattern template can be directly applied.

[0022] The method described in this invention can automatically calculate the coordinate values ​​of the aligned chip pattern, effectively avoiding various human errors, greatly improving the accuracy of the drawings, avoiding rework, and maximizing delivery time and cost savings. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the center point of the unit domain graphic in this invention;

[0024] Figure 2 This is a schematic diagram of arranging the aligned chip graphic template in the unit domain graphic in this invention;

[0025] Figure 3 This is a schematic diagram of some common alignment chip patterns in this invention. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0027] The method for automatically calculating the alignment chip coordinates in a lithographic pattern disclosed in this invention relies on the Visual Basic macro language. The corresponding program function is written in VBA according to the above method, and then applied to CAD to achieve the required function.

[0028] Example 1

[0029] This embodiment discloses a method for automatically calculating the coordinate values ​​of aligned chips in a photolithographic pattern. The method includes the following steps:

[0030] S1. Obtain the X-axis dimension step_X and Y-axis dimension step_Y of a single chip, as well as the number of rows (ReticleX_F1) and columns (ReticleY_F1) of the chip in the cell domain; and generate a wafer drawing, which includes a cell domain graphic, defining the center point coordinates of the cell domain graphic as (0,0). Figure 1 The geometric center point in;

[0031] S2. Design and align the chip pattern template in the cell domain graphic. The specific layout diagram is as follows: Figure 2 As shown, Figure 2 The numbers 1-4 represent four corresponding chip graphic templates;

[0032] The specific arrangement method is as follows:

[0033] a. Each layer of mask pattern in the unit domain pattern contains at least two aligned chip pattern templates, and the distance between the aligned chip pattern templates in adjacent mask patterns is at least 150μm.

[0034] b. Create blocks and name the different alignment chip graphic templates separately. The naming format is: layer-alignment chip number-alignment chip graphic template number, and use the center point of each alignment chip graphic template as the base point coordinate.

[0035] S3. Automatically identify the base point coordinates of each aligned chip graphic template, and calculate the difference in the X and Y directions between the base point coordinates of different aligned chip graphic templates and the center point coordinates of the unit domain graphic; the difference is the coordinate value of the aligned chip graphic.

[0036] The mask pattern file has multiple layers, and the distance between adjacent mask patterns and the corresponding chip pattern templates is at least 150μm to ensure accurate identification of each corresponding chip pattern template.

[0037] In step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

[0038] The above method also includes step S4: after verifying all the measurement values ​​in the previous step, organize them in a form and output them as needed.

[0039] The verification steps are as follows: if the spacing between the alignment chip graphic templates does not exceed the specified value, the form is sorted and output; otherwise, the form is not output.

[0040] This specified value refers to the different alignment pattern coordinate spacing values ​​corresponding to different chip sizes. When the chip size is determined, the alignment pattern coordinate spacing is also determined accordingly.

[0041] If the spacing between the alignment chip graphic templates matches the alignment graphic coordinate spacing corresponding to the current chip size, the result is considered correct and a form is output; if the spacing between the alignment chip graphic templates does not match the alignment graphic coordinate spacing corresponding to the current chip size, the result is considered incorrect and no form is output.

[0042] This invention enables the creation of alignment chip pattern templates for various common packaging products, and the collection of different alignment chip pattern templates to form a template library. These templates can be called upon based on their names. Specifically, for products that do not use actual wafers during exposure, only the cell domain pattern needs to be drawn once according to the cell domain pattern layout defined by the FAB (Fabrication Equipment) plant. However, the alignment chip pattern does not need to be drawn repeatedly; the corresponding alignment chip pattern template in the template library can be directly applied. Then, the steps for automatically calculating the coordinate values ​​of the alignment chip pattern as described in this invention are utilized.

[0043] Some common alignment chip patterns, such as Figure 3 As shown, alignment can be used in the exposure process depending on the different alignment patterns.

[0044] The method described in this invention can automatically calculate the coordinate values ​​of the aligned chip pattern, effectively avoiding various human errors, greatly improving the accuracy of the drawings, avoiding rework, and maximizing delivery time and cost savings.

[0045] The above descriptions are merely some embodiments of the present invention. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for automatically calculating alignment chip coordinate values in a photolithographic pattern, characterized by, The method includes the following steps: S1. Obtain the X-direction dimension step_X and Y-direction dimension step_Y of a single chip, the number of chip rows ReticleX_F1 and the number of chip columns ReticleY_F1 in the cell domain; and form a wafer drawing, which includes a cell domain graphic, and define the center point coordinates of the cell domain graphic as (0,0); S2. Design the chip alignment template in the cell domain graphic. The specific method is as follows: a. Each layer of mask pattern in the unit domain pattern contains at least two aligned chip pattern templates, and the distance between the aligned chip pattern templates in adjacent mask patterns is at least 150μm. b. Create blocks and name the different alignment chip graphic templates separately. The naming format is: layer-alignment chip number-alignment chip graphic template number, and use the center point of each alignment chip graphic template as the base point coordinate. S3. Automatically identify the base point coordinates of each aligned chip graphic template, and calculate the difference in the X and Y directions between the base point coordinates of different aligned chip graphic templates and the center point coordinates of the unit domain graphic; the difference is the coordinate value of the aligned chip graphic.

2. The method of claim 1, wherein, The mask image file has multiple layers, and the distance between adjacent mask images and the corresponding chip image templates is at least 150μm to ensure accurate identification of each corresponding chip image template.

3. The method of claim 2, wherein the method further comprises: Collect different alignment chip graphic templates to form a template library, and call the templates according to their names.

4. The method of claim 3, wherein the method further comprises: In step S3, the center point of each alignment chip graphic template is automatically identified using CAD software.

5. The method of claim 4, wherein the method further comprises the step of: It also includes step S4: After verifying all the measurement values ​​in the previous steps, organize them in a form and output them as needed.

6. The method of claim 5, wherein the method further comprises: The verification steps are as follows: if the spacing between the alignment chip graphic templates does not exceed the specified value, the form is sorted and output; otherwise, the form is not output.

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