Shared cache data management method and storage system with dynamic management strategy determination

Abstract

The present invention provides a shared cache data management method and storage system for dynamically determining management strategies. The method includes: configuring a shared cache in the memory of a host system, and a storage device is used to perform preset operations based on data cached in the shared cache; tracking the type of target mapping table items cached in the shared cache; determining the target management strategy for the target mapping table items based on the tracking results; obtaining target count information corresponding to the target mapping table items; and retaining the target mapping table items in the shared cache or removing the target mapping table items from the shared cache based on the target management strategy and the target count information. In this way, the performance of the storage device or the entire storage system can be effectively improved without affecting the operating performance of the host system itself as much as possible.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a shared cache data management method and storage system for dynamically determining a management strategy. Background Art

[0002] NAND flash memory is a non-volatile memory technology widely used in various storage devices. It stores charge by using floating gate transistors, each transistor represents a storage unit. NAND flash memory cells usually organize data in the form of pages, each page contains multiple bytes, and multiple pages form a block. Data is read and programmed in pages, while erase operations are performed in blocks. This organization makes NAND flash memory very suitable for large-capacity storage and has a high write speed.

[0003] However, as the storage capacity of storage devices continues to increase, the amount of management data used to manage the storage devices also continues to increase, resulting in the small capacity memory of the storage devices themselves being insufficient. Summary of the invention

[0004] The present invention provides a shared cache data management method and storage system with a dynamically determined management strategy, which can effectively improve the performance of a storage device or the entire storage system without affecting the operating performance of a host system as much as possible.

[0005] An embodiment of the present invention provides a shared cache data management method for dynamically determining a management strategy, which is used in a storage system, wherein the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache data management method for dynamically determining a management strategy includes: configuring a shared cache in the memory of the host system, wherein the storage device is used to perform preset operations based on data cached in the shared cache; tracking the type of target mapping table entries cached in the shared cache to obtain tracking results; determining a target management strategy for the target mapping table entry from multiple candidate management strategies based on the tracking results; obtaining target count information corresponding to the target mapping table entry; and retaining the target mapping table entry in the shared cache or removing the target mapping table entry from the shared cache based on the target management strategy and the target count information.

[0006] An embodiment of the present invention further provides a storage system, which includes a host system and a storage device. The storage device is connected to the host system. The host system is used to: configure a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on the data cached in the shared cache area; track the type of the target mapping table entry cached in the shared cache area to obtain a tracking result; determine a target management policy for the target mapping table entry from a plurality of candidate management policies based on the tracking result; obtain target count information corresponding to the target mapping table entry; and retain the target mapping table entry in the shared cache area or remove the target mapping table entry from the shared cache area based on the target management policy and the target count information.

[0007] Based on the above, a shared cache area can be configured in the memory of the host system, and the storage device can perform preset operations based on the data cached in the shared cache area. When the storage system is operating, the type of the target mapping table item cached in the shared cache area can be tracked to obtain a tracking result. According to the tracking result, the target management policy for the target mapping table item can be determined from a plurality of candidate management policies. On the other hand, the target count information corresponding to the target mapping table item can be obtained. Thereafter, according to the target management policy and the target count information, the target mapping table item can be retained in the shared cache area or removed from the shared cache area. Thus, the performance of the storage device or the entire storage system can be effectively improved without affecting the operating performance of the host system itself as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a flow chart of a shared cache data management method for dynamically determining a management strategy according to an embodiment of the present invention;

[0012] Figure 5 It is a flowchart of a shared cache data management method for dynamically determining a management strategy according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a schematic diagram of a storage system according to an embodiment of the present invention. Figure 1 , the storage system (also called data storage system) 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The host system 11 includes a processor 111 and a memory 112. The processor 111 is responsible for the overall or partial operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices.

[0016] The memory 112 is connected to the processor 111 and used to cache data. For example, the memory 112 may include a random access memory (RAM) or a similar volatile storage device. It should be noted that the memory 112 is disposed in the host system 11 (for example, disposed on the motherboard of the host system 11 or directly disposed in the processor 111), rather than disposed in the storage device 12.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (embedded Multi-Media Card, eMMC), a universal flash storage (Universal Flash Storage, UFS), a fast peripheral component interconnect (Peripheral Component Interconnect Express, PCIExpress), a fast non-volatile memory (Non-Volatile Memory Express, NVM express), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a universal serial bus (Universal Serial Bus, USB) or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (for example, exchange signals, instructions and / or data).

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0021] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0025] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile storage of data.

[0026] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0027] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0028] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0029] In one embodiment, a physical erase unit may include a plurality of physical programming units. A plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to a plurality of physical programming units in the physical erase unit to change the threshold voltage of at least a portion of the storage cells in these physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared. In one embodiment, a physical erase unit may be regarded as a physical block.

[0030] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0031] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0032] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0034] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0036] In one embodiment, the processor 111 can configure a shared cache area 101 in the memory 112. By utilizing the memory resources of the host system 11 (e.g., the shared cache area 101), the processor 111 provides an efficient temporary data exchange space for the storage device 12, which not only reduces the delay caused by frequent access to the flash memory, but also significantly improves the performance of random read and write operations. Specifically, based on the data in the shared cache area 101, the storage device 12 can perform preset operations related to the memory module 122, such as at least one of the following operations: ① Command scheduling optimization: Allow the memory control circuit 23 to temporarily store multiple I / O requests from the host system 11 in the shared cache area 101 in advance, thereby optimizing the execution order of these requests, reducing unnecessary addressing time and page switching, and improving the overall response speed. ② Address mapping management: The shared cache area 101 can be used to store and update the logical to physical address mapping table (L2P Mapping Table) to speed up the search process for data locations, especially for random read operations, greatly improving efficiency. And perform sorting operations on multiple mapping table entries cached in the shared cache area 101 according to the sorting algorithm to obtain operations such as sorting queues. ③ Data cache: When reading data from the memory module 122, if the data has been loaded into the shared cache area 101, it can be directly obtained from it to avoid accessing the slower memory module 122 again, thereby speeding up the data reading speed. Similarly, when writing new data, the data can be temporarily saved in the shared cache area 101, and then the background optimization strategy is used to decide when and how to persist it to the memory module 122. ④ Metadata processing: In addition to user data, it can also be used to cache key metadata such as file allocation table (FAT) and wear leveling information to ensure efficient data management and access mode even under high load conditions.

[0037] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the memory device 12. For example, the memory control circuit 23 may perform a handshake operation with the host system 11. The handshake operation is used to exchange information related to the establishment of the connection between the host system 11 and the memory device 12, such as clock information and / or voltage information.

[0038] In one embodiment, the memory control circuit 23 may establish a connection between the host system 11 and the storage device 12 according to the result of the handshake operation. Thereafter, the memory control circuit 23 may access (also referred to as access) the shared cache area 101 through the connection.

[0039] In one embodiment, the memory control circuit 23 may store the management data in the shared cache area 101. During access to the memory module 122, the memory control circuit 23 may query or update (i.e., modify) the management data in the shared cache area 101 accordingly. For example, the management data may include part of the data in the logic-to-physical mapping table (also referred to as a mapping table entry). The mapping table entry may carry mapping information (e.g., logic-to-physical mapping information). The mapping information may reflect the mapping relationship between at least one logical unit and at least one physical unit.

[0040] In one embodiment, when the host system 11 wants to read data belonging to a certain logical unit (also referred to as a first logical unit) from the storage device 12, the processor 111 may store read information corresponding to the first logical unit in the shared cache area 101. For example, the read information may include a read instruction indicating to read data belonging to the first logical unit. For example, the read instruction may include a random read instruction and / or a continuous read instruction. The random read instruction is used to indicate to read data from a single logical unit or multiple non-continuous logical units. The continuous read instruction is used to indicate to read data from multiple continuous logical units. The memory control circuit 23 may access the shared cache area 101 to obtain the read information.

[0041] After obtaining the read information, the memory control circuit 23 may confirm whether the mapping table entry associated with the first logical unit has been cached in the shared cache area 101. If the mapping table entry associated with the first logical unit is not cached in the shared cache area 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 into the shared cache area 101.

[0042] If the mapping table entry related to the first logical unit has been cached in the shared cache area 101 (or after the mapping table entry is loaded from the memory module 122 to the shared cache area 101), the memory control circuit 23 can query the mapping table entry in the shared cache area 101 to obtain the mapping relationship between the first logical unit and the physical unit (also referred to as the first physical unit) in the memory module 122. Then, the memory control circuit 23 can read data (also referred to as the first data) from the first physical unit in the memory module 122 according to the mapping relationship. Then, the memory control circuit 23 can return the read first data to the host system 11 in response to the read information.

[0043] In one embodiment, when the host system 11 wants to store data (also referred to as second data) belonging to a certain logical unit (also referred to as the second logical unit) into the storage device 12, the processor 111 may store write information corresponding to the second logical unit in the shared cache area 101. For example, the write information may include a write instruction indicating to update the data belonging to the second logical unit. For example, the write instruction may include a random write instruction and / or a continuous write instruction. The random write instruction is used to indicate to update the data belonging to a single logical unit or a plurality of discontinuous logical units. The continuous write instruction is used to indicate to update the data belonging to a plurality of continuous logical units. The memory control circuit 23 may access the shared cache area 101 to obtain the write information.

[0044] After obtaining the write information, the memory control circuit 23 may store the second data into the physical unit (also referred to as the second physical unit) in the memory module 122 according to the write information. On the other hand, the memory control circuit 23 may confirm whether the mapping table entry related to the second logical unit has been cached in the shared cache area 101. If the mapping table entry related to the second logical unit is not cached in the shared cache area 101, the memory control circuit 23 may load the mapping table entry from the memory module 122 to the shared cache area 101. If the mapping table entry related to the second logical unit has been cached in the shared cache area 101 (or after the mapping table entry is loaded from the memory module 122 to the shared cache area 101), the memory control circuit 23 may update the mapping table entry in the shared cache area 101 to establish a mapping relationship between the second logical unit and the second physical unit. Then, the memory control circuit 23 may notify the host system 11 to complete the write operation in response to the write information.

[0045] In one embodiment, the memory control circuit 23 may also store other types of management data in the shared cache area 101 (for example, load it from the memory module 122 into the shared cache area 101). For example, the management data may include valid count management data, wear leveling management data, or bad block management data, etc., which are not limited by the present invention. The valid count management data is used to manage the valid data storage status of at least some physical units in the memory module 122. For example, the valid count management data may include a valid count corresponding to at least one physical unit in the memory module 122. The wear leveling management data is used to manage the wear status of at least some physical units in the memory module 122. For example, the wear leveling management data may include a read count, a write count, and / or an erase count corresponding to at least one physical unit in the memory module 122. The bad block management data is used to manage damaged physical units (also called bad blocks) in the memory module 122. For example, the bad block management data may be used to mark at least one physical unit in the memory module 122 as a bad block. Thereafter, the memory control circuit 23 may access or manage the memory module 122 according to the management data in the shared cache area 101.

[0046] It should be noted that the shared cache area 101 set in the memory 112 will occupy a part of the storage space of the memory 112, thereby reducing the capacity of the memory 112 that can be used by the host system 11 itself. For example, after setting the shared cache area 101, the remaining capacity of the memory 112 after deducting the shared cache area 101 is the memory space that can be used by the host system 11 itself. Therefore, if the capacity of the shared cache area 101 is larger, it may cause the operating performance of the host system 11 itself to decrease (due to the reduction of the memory space that can be used by the host system 11 itself). However, if the capacity of the shared cache area 101 is too small, it may reduce the performance of the storage device 12 (due to the reduction of the memory space that can be used by the storage device 12).

[0047] However, through the technical solution proposed in the embodiment of the present invention, when the capacity of the shared cache area 101 is not large (the capacity of the shared cache area 101 can even be reduced), the optimal management strategy for managing (e.g., sorting, adding and / or removing) the mapping table entries cached in the shared cache area 101 can be dynamically determined. In this way, the performance of the storage device 12 or the entire storage system 10 can be effectively improved without affecting the operating performance of the host system 11 itself as much as possible.

[0048] In other words, according to the technical solution provided by the embodiment of the present invention, while maintaining a relatively small capacity configuration (including but not limited to reducing its capacity requirements) in the shared cache area 101, it is possible to achieve fine management of the mapping table entries residing in the shared cache area 101, including but not limited to operations such as sorting, adding and removing. In this way, on the basis of ensuring that the operating efficiency of the host system 11 is not disturbed, the performance of the storage device 12 and even the entire storage system 10 is further enhanced, achieving the best balance between the processing capacity of the host system 11 and the response speed of the storage device 12, ensuring that both can operate in an ideal state without affecting each other.

[0049] In particular, this solution is particularly suitable for scenarios that improve random read and write performance. Traditionally, in order to maximize the performance of random reads and writes, all mapping table entries should theoretically be loaded into the buffer memory 24. However, under the limitations of current product design - for example, the buffer memory 24 usually has a fixed capacity of 256KB, while the amount of data in the mapping table entries may reach 1GB or more (taking 1TB capacity as an example), which makes it impossible to load all the mapping table entries at once, resulting in the need to frequently load the mapping table entries in batches, thereby increasing latency and affecting the reading speed of the storage device 12. By using a shared cache area 101 to efficiently manage these mapping table entries, not only this challenge is solved, but also independent and undisturbed optimization of the performance of the host system 11 and the storage device 12 is achieved.

[0050] Specifically, this solution allows the storage system 10 to maintain high data access speed and low latency characteristics when processing a large number of mapping table entries, thereby ensuring the performance indicators of random read and write. At the same time, it also avoids the cost increase caused by adding additional hardware resources, as well as the possible increase in system complexity and decrease in stability. In short, this innovative technical solution provides a feasible and efficient way to solve the challenges of high-performance storage systems.

[0051] In one embodiment, one or more mapping table entries may be cached in the shared cache area 101. After the memory control circuit 23 caches at least one mapping table entry in the shared cache area 101, the processor 111 may track the type of a mapping table entry (also referred to as a target mapping table entry) cached in the shared cache area 101 to obtain a tracking result. In other words, the tracking result may reflect the type of the target mapping table entry currently cached in the shared cache area 101.

[0052] In one embodiment, the processor 111 may obtain identification information corresponding to the target mapping table entry. The identification information may reflect the type of the target mapping table entry. Then, the processor 111 may determine the type of the target mapping table entry according to the identification information.

[0053] In one embodiment, when the target mapping table entry is cached in the shared cache area 101, an identification information may be associated with the target mapping table entry according to the application to which the target mapping table entry belongs. For example, assuming that the application to which the target mapping table entry belongs is application A, the identification information A corresponding to application A may be associated with the target mapping table entry. Alternatively, assuming that the application to which the target mapping table entry belongs is application B, the identification information B corresponding to application B may be associated with the target mapping table entry.

[0054] In one embodiment, the processor 111 may query the management table according to the identification information corresponding to the target mapping table item to obtain the query result. The management table may record multiple types (also referred to as candidate types) corresponding to multiple identification information (also referred to as candidate identification information). Then, the processor 111 may determine the type of the target mapping table item from the multiple candidate types according to the query result. For example, according to the query result, the processor 111 may determine the candidate type matching the identification information in the management table as the type of the target mapping table item.

[0055] In one embodiment, the type of a mapping table entry may reflect that the mapping table entry belongs to at least one of an active foreground application, an inactive foreground application, and a background application. In one embodiment, it is assumed that the current processor 111 runs applications A and B. Among them, application A runs in the foreground of the operating system (OS), and application B runs in the background of the operating system. At this time, the processor 111 may classify application A as an active foreground application and application B as a background application. It should be noted that those skilled in the art should know how the processor runs different applications in the foreground and background of the operating system, and will not be elaborated here.

[0056] In one embodiment, assume that another application C is switched to the foreground of the operating system. In response to application C being switched to the foreground of the operating system, the processor 111 may classify application C as an active foreground application. At the same time, the processor 111 may reclassify (e.g., downgrade) application A, which was originally an active foreground application, as an inactive foreground application, and maintain application B as a background application.

[0057] In one embodiment, the identification information corresponding to the target mapping table entry may reflect that the target mapping table entry belongs to an active foreground application, an inactive foreground application, or a background application. In addition, when the type of the target mapping table entry changes, the processor 111 may update the identification information of the target mapping table entry accordingly. The updated identification information may reflect the current type of the target mapping table entry. For example, when the target mapping table entry is switched from originally belonging to an inactive foreground application to belonging to an active foreground application, the processor 111 may update the identification information of the target mapping table entry accordingly, so that the updated identification information reflects that the target mapping table entry currently belongs to an active foreground application.

[0058] In one embodiment, according to the tracking result (i.e., the type of the target mapping table entry), the processor 111 may determine a management policy (also referred to as a target management policy) for the target mapping table entry from a plurality of management policies (also referred to as candidate management policies). Thereafter, the processor 111 may manage the target mapping table entry based on the target management policy. For example, the processor 111 may retain the target mapping table entry in the shared cache 101 or remove the target mapping table entry from the shared cache 101 based on the target management policy.

[0059] In one embodiment, if the tracking result reflects that the type of the target mapping table item is a certain type (also referred to as the first type), the processor 111 may determine a certain management policy (also referred to as the first management policy) among the multiple candidate management policies as the target management policy. Alternatively, if the tracking result reflects that the type of the target mapping table item is another type (also referred to as the second type), the processor 111 may determine another management policy (also referred to as the second management policy) among the multiple candidate management policies as the target management policy. The first management policy is different from the second management policy. Alternatively, if the tracking result reflects that the type of the target mapping table item is another type (also referred to as the third type), the processor 111 may determine another management policy (also referred to as the third management policy) among the multiple candidate management policies as the target management policy. For example, the first type, the second type, and the third type may correspond to active foreground applications, inactive foreground applications, and background applications, respectively.

[0060] In one embodiment, the plurality of candidate management strategies correspond to a plurality of sorting algorithms (also referred to as candidate sorting algorithms). For example, a first management strategy may correspond to a sorting algorithm (also referred to as a first sorting algorithm) among the plurality of candidate sorting algorithms. A second management strategy may correspond to another sorting algorithm (also referred to as a second sorting algorithm) among the plurality of candidate sorting algorithms. A third management strategy may correspond to another sorting algorithm (also referred to as a third sorting algorithm) among the plurality of candidate sorting algorithms. The plurality of candidate sorting algorithms are different from each other.

[0061] In one embodiment, the processor 111 may also obtain counting information corresponding to the target mapping table entry (also referred to as target counting information). For example, the target counting information may reflect the number of times, frequency, or time point at which the target mapping table entry has been accessed in the past period of time. For example, the processor 111 may monitor the access status of the target mapping table entry cached in the shared cache area 101 in the past period of time to obtain a monitoring result. For example, this monitoring result may reflect the access status of the target mapping table entry cached in the shared cache area 101 in the past period of time. Then, the processor 111 may update the target counting information according to this monitoring result.

[0062] In one embodiment, the processor 111 may configure at least one counter for each mapping table entry in the shared cache area 101. The processor 111 may obtain counting information corresponding to each mapping table entry according to the output of the counter.

[0063] In one embodiment, in response to each access of the target mapping table entry, the processor 111 may update the target counting information accordingly. The updated target counting information may reflect the latest access status of the target mapping table entry cached in the shared cache area 101 in the current or past period of time (e.g., the number of times the target mapping table entry has been accessed, the frequency of the latest access, or the time point of the latest access).

[0064] In one embodiment, the target counting information may include one or more count values. This count value may reflect the number of times, frequency or time point at which the target mapping table item is accessed in the past period of time. In one embodiment, this count value may be positively correlated to the number of times and / or frequency at which the target mapping table item is accessed in the past period of time. That is, if this count value is larger, it means that the number of times and / or frequency at which the target mapping table item is accessed in the past period of time is more. Or, in one embodiment, this count value may also be negatively correlated to the number of times and / or frequency at which the target mapping table item is accessed in the past period of time.

[0065] In one embodiment, the count value may be positively correlated to the time difference between the time point at which the target mapping table entry was last accessed within the past period of time and the current system time. That is, the larger the count value is, the farther the time point at which the target mapping table entry was last accessed within the past period of time is from the current system time. Alternatively, in one embodiment, the count value may also be negatively correlated to the time difference between the time point at which the target mapping table entry was last accessed within the past period of time and the current system time.

[0066] In one embodiment, the processor 111 may retain the target mapping table entry in the shared cache area 101 or remove the target mapping table entry from the shared cache area 101 according to the target management policy and the target count information. For example, the target management policy may be one of the first management policy, the second management policy, and the third management policy.

[0067] In one embodiment, after determining the target management strategy, the processor 111 may bring the target count information into a sorting algorithm (also referred to as a target sorting algorithm) corresponding to the target management strategy to obtain a sorting result corresponding to the target mapping table item. For example, this sorting result may reflect the sorting of the target mapping table item among multiple mapping table items of the same type cached in the shared cache area 101. For example, assuming that the type of the target mapping table item is the first type, this sorting result may reflect the sorting of the target mapping table item among multiple mapping table items of the same first type cached in the shared cache area 101. Alternatively, assuming that the type of the target mapping table item is the second type, this sorting result may reflect the sorting of the target mapping table item among multiple mapping table items of the same second type cached in the shared cache area 101. Alternatively, assuming that the type of the target mapping table item is the third type, this sorting result may reflect the sorting of the target mapping table item among multiple mapping table items of the same third type cached in the shared cache area 101. Then, the processor 111 may retain the target mapping table entry in the shared cache area 101 or remove the target mapping table entry from the shared cache area 101 according to the sorting result.

[0068] In one embodiment, the target counting information includes first-class counting information, second-class counting information and / or third-class counting information. The first-class counting information reflects the number of times the target mapping table entry has been accessed in the past period of time. The second-class counting information reflects the frequency of the target mapping table entry being accessed in the past period of time. The third-class counting information reflects the time difference between the time point when the target mapping table entry was most recently accessed in the past period of time and the current system time. In one embodiment, the processor 111 may bring at least one of the first-class counting information, the second-class counting information and the third-class counting information into the target sorting algorithm to obtain the sorting result. Thereafter, the processor 111 may remove one or more mapping table entries from the shared cache area 101 in sequence according to the sorting result.

[0069] In one embodiment, the processor 111 may bring at least one of the first type of counting information, the second type of counting information, and the third type of counting information into the target sorting algorithm to obtain the sorting result. For example, when it is desired to sort a plurality of mapping table entries belonging to a specific type, the processor 111 may bring at least one of the predetermined first type of counting information, the second type of counting information, and the third type of counting information into the target sorting algorithm according to the specific type to obtain the sorting result.

[0070] In one embodiment, when the target sorting algorithm used is the first sorting algorithm, the processor 111 may bring at least one counting information (also referred to as the first target counting information) into the target sorting algorithm to obtain the sorting result. For example, the first target counting information may include at least one of the first type of counting information, the second type of counting information, and the third type of counting information. In one embodiment, when the target sorting algorithm used is the second sorting algorithm, the processor 111 may bring at least one target counting information (also referred to as the second target counting information) into the target sorting algorithm to obtain the sorting result. For example, the first target counting information may include at least one of the first type of counting information, the second type of counting information, and the third type of counting information. In one embodiment, when the target sorting algorithm used is the third sorting algorithm, the processor 111 may bring at least one target counting information (also referred to as the third target counting information) into the target sorting algorithm to obtain the sorting result. For example, the third target counting information may include at least one of the first type of counting information, the second type of counting information, and the third type of counting information. It should be noted that the types of counting information included in the first target counting information, the second target counting information and the third target counting information may be completely the same, partially the same or completely different.

[0071] In one embodiment, when the target sorting algorithm used is adjusted from a certain sorting algorithm to another sorting algorithm, the processor 111 may dynamically adjust the type of counting information to be brought into the target sorting algorithm. For example, when the target sorting algorithm used is adjusted from a first sorting algorithm to a second sorting algorithm, the processor 111 may adjust the counting information originally used to be brought into the target sorting algorithm from the first target counting information to the second target counting information.

[0072] In one embodiment, in the target sorting algorithm, the processor 111 may sort the multiple mapping table entries of the same type as the target mapping table entry in the shared cache area 101 according to the first type of counting information to obtain the sorting result. For example, the sorting result may reflect the number of times the multiple mapping table entries have been accessed in the past period of time from large to small or from small to large. Thereafter, the processor 111 may remove one or more mapping table entries from the shared cache area 101 in sequence, starting from the mapping table entry with the least number of accesses in the past period of time, according to the sorting result.

[0073] In one embodiment, in the target sorting algorithm, the processor 111 may sort the multiple mapping table entries of the same type as the target mapping table entry in the shared cache area 101 according to the second type of counting information to obtain the sorting result. For example, the sorting result may reflect the frequency of access to the multiple mapping table entries in the past period of time from low to high or from high to low. Thereafter, the processor 111 may remove one or more mapping table entries from the shared cache area 101 in sequence, starting from the mapping table entry with the lowest frequency of access in the past period of time among the multiple mapping table entries according to the sorting result.

[0074] In one embodiment, in the target sorting algorithm, the processor 111 may sort the multiple mapping table entries of the same type as the target mapping table entry in the shared cache area 101 according to the third type of counting information to obtain the sorting result. For example, the sorting result may reflect the time difference between the time point when the multiple mapping table entries were most recently accessed in the past period of time and the current system time from large to small or from small to large. Thereafter, the processor 111 may, according to the sorting result, sequentially remove one or more mapping table entries from the shared cache area 101, starting from the mapping table entry with the largest time difference between the time point when the multiple mapping table entries were most recently accessed in the past period of time and the current system time.

[0075] In one embodiment, in the target sorting algorithm, the processor 111 may also simultaneously consider at least two of the first type of counting information, the second type of counting information, and the third type of counting information to obtain the sorting result. In one embodiment, by considering at least two of the first type of counting information, the second type of counting information, and the third type of counting information to sort multiple mapping table entries of the same type as the target mapping table entry in the shared cache 101, the accuracy of managing the mapping table entries in the shared cache 101 can be improved.

[0076] In one embodiment, the processor 111 may configure a weight parameter (also referred to as a first weight parameter) for the first type of counting information. In one embodiment, the processor 111 may configure a weight parameter (also referred to as a second weight parameter) for the second type of counting information. In one embodiment, the processor 111 may configure a weight parameter (also referred to as a third weight parameter) for the third type of counting information. The first weight parameter, the second weight parameter, and the third weight parameter may be used to adjust the influence of the first type of counting information, the second type of counting information, and the third type of counting information on the sorting result, respectively. For example, the sum of the first weight parameter, the second weight parameter, and the third weight parameter may be "1".

[0077] In one embodiment, when the target sorting algorithm used is adjusted from a certain sorting algorithm to another sorting algorithm, the processor 111 may dynamically adjust at least one of the first weight parameter, the second weight parameter, and the third weight parameter to change the influence of different types of counting information on the target sorting algorithm (or sorting result). For example, if you want to increase the influence of the first type of counting information on the sorting result (equivalent to reducing the influence of the second type of counting information and the third type of counting information on the sorting result), the processor 111 may increase the value of the first weight parameter and correspondingly reduce the values ​​of the second weight parameter and the third weight parameter. Thereafter, based on the target sorting algorithm, the processor 111 may sort multiple mapping table entries of a specific type in the shared cache area 101 according to the first type of counting information (and the first weight parameter), the second type of counting information (and the second weight parameter) and / or the third type of counting information (and the third weight parameter) to obtain the sorting result.

[0078] In one embodiment, for different sorting algorithms, the type of counting information brought into the sorting algorithm and / or the setting method of the weight parameter may be different. In one embodiment, for different sorting algorithms, in addition to the different types of counting information brought into the sorting algorithm, the different sorting algorithms themselves may also have different operation logics for processing the one or more types of counting information.

[0079] In one embodiment, the processor 111 may detect the data storage capacity of at least one of the memory 112 and the shared cache area 101. For example, this data storage capacity may reflect how much data is currently stored in at least one of the memory 112 and the shared cache area 101. In one embodiment, the processor 111 may detect whether the data storage capacity has reached a critical value. When the data storage capacity reaches the critical value, the processor 111 may perform the aforementioned sorting operation according to the target management policy and the target count information to determine the priority order in which each type of mapping table entry in the shared cache area 101 is removed and / or retained. Then, the processor 111 may sequentially remove one or more mapping table entries from the shared cache area 101 according to the determined order. However, if the data storage capacity does not reach the critical value, the processor 111 may temporarily not perform the aforementioned operation of removing the mapping table entry from the shared cache area 101.

[0080] In one embodiment, when the data storage capacity of at least one of the memory 112 and the shared cache area 101 is relatively large (e.g., reaches the critical value), data with relatively low access rate is preferentially removed according to the type of data and the sorting order managed for each type of data, so that additional memory space can be released for use by the host system 11 (and the storage device 12). In this way, the performance of the host system 11 and the storage device 12 can be improved.

[0081] It should be noted that, in one embodiment, the type of at least one mapping table entry cached in the shared cache area 101 can also be configured or adjusted according to practical needs, and is not limited to the above-mentioned active foreground applications, inactive foreground applications and / or background applications. In addition, in one embodiment, the sorting algorithm and sorting method used for different types of mapping table entries can also be adjusted according to practical needs, and the present invention is not limited thereto.

[0082] Figure 4 is a flow chart of a shared cache data management method for dynamically determining a management strategy according to an embodiment of the present invention. Figure 4 In step S401, a shared cache area is configured in the memory of the host system, wherein a storage device is used to perform a preset operation based on the data cached in the shared cache area. In step S402, the type of at least one mapping table entry cached in the shared cache area is tracked to obtain a tracking result. In step S403, based on the tracking result, a target management policy for a target mapping table entry is determined from a plurality of candidate management policies. In step S404, target count information corresponding to the target mapping table entry is obtained. In step S405, based on the target management policy and the target count information, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area.

[0083] Figure 5 is a flow chart of a shared cache data management method for dynamically determining a management strategy according to an embodiment of the present invention. Figure 5 , in step S501, determine the type of the target mapping table entry currently cached in the shared cache area. In step S502, determine whether the target mapping table entry belongs to an active foreground application. If the target mapping table entry belongs to an active foreground application, in step S503, determine the first management policy as the target management policy. If the target mapping table entry does not belong to an active foreground application, in step S504, determine whether the target mapping table entry belongs to an inactive foreground application. If the target mapping table entry belongs to an inactive foreground application, in step S505, determine the second management policy as the target management policy. In addition, if the target mapping table entry does not belong to an inactive foreground application, in step S506, determine the third management policy as the target management policy.

[0084] However, Figure 4 and Figure 5 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 4 and Figure 5 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 4 and Figure 5 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0085] In summary, the shared cache data management method and storage system for dynamically determining management strategies proposed in the embodiments of the present invention can dynamically determine the best management strategy for managing (e.g., sorting, adding and / or removing) the mapping table entries cached in the shared cache when the capacity of the shared cache for use by the storage device inside the host system is not large (the capacity of the shared cache can even be reduced). In this way, the performance of the storage device or the entire storage system can be effectively improved without affecting the operating performance of the host system itself as much as possible.

[0086] In one embodiment, the aforementioned management and / or sorting mechanism for mapping table entries may also be used to manage and / or sort other types of data. For example, in one embodiment, the aforementioned mapping table entries may be replaced by various instructions, valid count management data, wear leveling management data, bad block management data, or other types of custom data, which will not be repeated here.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shared cache data management method for dynamically determining a management strategy, characterized in that: For a storage system, the storage system includes a host system and a storage device, the host system is connected to the storage device, and the shared cache area data management method of dynamically determining the management strategy includes: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Tracking the type of the target mapping table entry cached in the shared cache area to obtain a tracking result; Determining a target management strategy for the target mapping table entry from a plurality of candidate management strategies according to the tracking result; Obtaining target count information corresponding to the target mapping table entry; and According to the target management policy and the target counting information, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area.

2. The shared cache data management method of dynamically determining a management strategy according to claim 1, wherein the step of tracking the type of the target mapping table entry cached in the shared cache comprises: Obtaining identification information corresponding to the target mapping table entry; as well as The type of the target mapping table entry is determined according to the identification information.

3. The shared cache data management method for dynamically determining a management strategy according to claim 2, wherein the step of determining the type of the target mapping table entry according to the identification information comprises: According to the identification information, querying a management table to obtain a query result, wherein the management table records a plurality of candidate types corresponding to a plurality of candidate identification information respectively; as well as According to the query result, the type of the target mapping table entry is determined from the multiple candidate types.

4. The shared cache data management method for dynamically determining management policies according to claim 1, wherein the step of determining the target management policy for the target mapping table entry from the plurality of candidate management policies according to the tracking result comprises: If the tracking result reflects that the type of the target mapping table entry is the first type, determining a first management policy among the multiple candidate management policies as the target management policy; If the tracking result reflects that the type of the target mapping table entry is the second type, a second management policy among the multiple candidate management policies is determined as the target management policy, wherein the first management policy is different from the second management policy.

5. A shared cache data management method for dynamically determining management strategies according to claim 4, wherein the first management strategy corresponds to a first sorting algorithm, the second management strategy corresponds to a second sorting algorithm, and the first sorting algorithm is different from the second sorting algorithm.

6. The shared cache data management method for dynamically determining management strategies according to claim 1, wherein the plurality of candidate management strategies correspond to a plurality of candidate sorting algorithms respectively, and the step of retaining the target mapping table entry in the shared cache or removing the target mapping table entry from the shared cache according to the target management strategy and the target counting information comprises: Bringing the target counting information into the target sorting algorithm corresponding to the target management policy among the multiple candidate sorting algorithms to obtain a sorting result corresponding to the target mapping table entry; as well as According to the sorting result, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area.

7. The shared cache data management method for dynamically determining management strategies according to claim 1, wherein the type of the target mapping table entry reflects that the target mapping table entry belongs to one of an active foreground application, an inactive foreground application, and a background application.

8. The shared cache data management method for dynamically determining management strategies according to claim 1, wherein the target counting information reflects the number of times, frequency or time point at which the target mapping table entry is accessed within a past period of time.

9. The shared cache data management method of dynamically determining management strategies according to claim 1, further comprising: In response to each time the target mapping table entry is accessed, the target count information is correspondingly updated.

10. A storage system, characterized in that: include: Host system; as well as a storage device, connected to the host system, The host system is used to: configuring a shared cache area in the memory of the host system, wherein the storage device is used to perform a preset operation based on data cached in the shared cache area; Tracking the type of the target mapping table entry cached in the shared cache area to obtain a tracking result; Determining a target management strategy for the target mapping table entry from a plurality of candidate management strategies according to the tracking result; Obtaining target count information corresponding to the target mapping table entry; as well as According to the target management policy and the target counting information, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area.

11. The storage system according to claim 10, wherein the operation of tracking the type of the target mapping table entry cached in the shared cache area comprises: Obtaining identification information corresponding to the target mapping table entry; as well as The type of the target mapping table entry is determined according to the identification information.

12. The storage system according to claim 11, wherein the operation of determining the type of the target mapping table entry according to the identification information comprises: According to the identification information, querying a management table to obtain a query result, wherein the management table records a plurality of candidate types corresponding to a plurality of candidate identification information respectively; as well as According to the query result, the type of the target mapping table entry is determined from the multiple candidate types.

13. The storage system according to claim 10, wherein the operation of determining the target management policy for the target mapping table entry from the plurality of candidate management policies according to the tracking result comprises: If the tracking result reflects that the type of the target mapping table entry is the first type, determining a first management policy among the multiple candidate management policies as the target management policy; If the tracking result reflects that the type of the target mapping table entry is the second type, a second management policy among the multiple candidate management policies is determined as the target management policy, wherein the first management policy is different from the second management policy. 14 . The storage system according to claim 13 , wherein the first management policy corresponds to a first sorting algorithm, the second management policy corresponds to a second sorting algorithm, and the first sorting algorithm is different from the second sorting algorithm.

15. The storage system according to claim 10, wherein the plurality of candidate management strategies correspond to a plurality of candidate sorting algorithms respectively, and according to the target management strategy and the target count information, the operation of retaining the target mapping table entry in the shared cache area or removing the target mapping table entry from the shared cache area comprises: Bringing the target counting information into the target sorting algorithm corresponding to the target management policy among the multiple candidate sorting algorithms to obtain a sorting result corresponding to the target mapping table entry; as well as According to the sorting result, the target mapping table entry is retained in the shared cache area, or the target mapping table entry is removed from the shared cache area. 16 . The storage system of claim 10 , wherein the type of the target mapping table entry reflects that the target mapping table entry belongs to one of an active foreground application, an inactive foreground application, and a background application. 17 . The storage system according to claim 10 , wherein the target counting information reflects the number of times, frequency or time point at which the target mapping table entry is accessed within a past period of time.

18. The storage system according to claim 10, wherein the host system is further configured to: In response to each time the target mapping table entry is accessed, the target count information is correspondingly updated.

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