Embedded control circuit, embedded mainboard and embedded equipment

Abstract

The embodiment of the invention provides an embedded control circuit, an embedded mainboard and embedded equipment, relates to the technical field of embedded development, and solves the problem that the programming or debugging process of a microprocessor is easily interrupted by a watchdog circuit in the related technology. According to the technical scheme, a dog feeding signal is provided for the watchdog chip, so that the timing requirement of the watchdog chip during programming or debugging of the microprocessor is met, the microprocessor is prevented from being reset, the programming or debugging process can be smoothly carried out, the stability of a system can be maintained, and the stability of the system is improved.

Description

Technical Field

[0001] The present application relates to the field of embedded development technology, and in particular to an embedded control circuit, an embedded mainboard and an embedded device. Background Art

[0002] Embedded devices are widely used in fields such as industrial control, medical equipment, and consumer electronics. The systems of embedded devices usually use watchdog circuits to monitor the operating status of the system. Among them, the watchdog circuit is a hardware timer. When the system is abnormal or has no operation for a long time, the watchdog circuit will automatically reset the system to restore normal operation.

[0003] However, the hardware watchdog circuit needs to input a periodic dog feeding signal, such as the dog feeding signal provided by the microprocessor of the embedded device. However, when the microprocessor is being programmed or debugged, since the microprocessor is not in normal operation, it cannot output a normal dog feeding signal, causing the watchdog circuit to overflow due to the lack of the dog feeding signal and output a reset signal, causing the microprocessor to be reset, thereby interrupting the programming or debugging process. Summary of the invention

[0004] The present application provides an embedded control circuit, an embedded mainboard and an embedded device, which solve the problem in the related art that the programming or debugging process of the microprocessor is easily interrupted by the watchdog circuit. The present solution can ensure the smooth progress of the programming or debugging process of the microprocessor, and effectively avoid the overflow of the watchdog circuit due to the lack of a feeding signal.

[0005] In a first aspect, the present application provides an embedded control circuit, which includes a microcontroller, a watchdog chip and a signal input module.

[0006] Wherein, the reset pin of the microcontroller is connected to the reset output pin of the watchdog chip, the signal output pin of the microcontroller is connected to the first input end of the signal input module, and the serial input pin of the microcontroller is connected to the test port, and the test port is used to access the debugging data signal; The second input end of the signal input module is connected to the test port, and the output end of the signal input module is connected to the signal input pin of the watchdog chip. The signal input module is used to output the output signal provided by the signal output pin of the microcontroller as a dog feeding signal to the signal input pin of the watchdog chip when the microcontroller is in normal operation, and the signal input module is also used to output the debugging data signal connected to the test port as a dog feeding signal to the signal input pin of the watchdog chip when the microcontroller is in the programming or debugging process.

[0007] On the basis of the above embodiment, the signal input module includes a pull-up resistor, a first diode and a second diode. The first end of the pull-up resistor is connected to the working voltage, and the second end of the pull-up resistor is connected to the signal input pin of the watchdog chip; the anode end of the first diode is connected to the second end of the pull-up resistor, and the cathode end of the first diode is connected to the signal output pin of the microcontroller; the anode end of the second diode is connected to the second end of the pull-up resistor, and the cathode end of the second diode is connected to the test port.

[0008] Based on the above embodiment, the first diode and the second diode are both Schottky diodes.

[0009] On the basis of the above embodiment, the circuit further includes a filter capacitor, a first end of the filter capacitor is connected to a power pin of the watchdog chip, and a second end of the filter capacitor is grounded.

[0010] On the basis of the above embodiment, the test port is a JTAG interface. In the case where the test port is a JTAG interface, the debug data signal is a TDI signal provided by a TDI pin of the JTAG interface.

[0011] On the basis of the above embodiment, the test port is a SWD interface. In the case where the test port is a SWD interface, the debug data signal is a SWDIO signal provided by a SWDIO pin of the SWD interface.

[0012] Based on the above embodiment, the signal period of the dog feeding signal output by the signal output pin of the microcontroller is less than or equal to the timer period of the watchdog chip, and the timer period of the watchdog chip is greater than the minimum reset duration of the microcontroller.

[0013] On the basis of the above embodiment, the data pulse width of the debugging data signal is less than or equal to the signal period of the dog feeding signal.

[0014] In a second aspect, the present application also provides an embedded mainboard, which includes the embedded control circuit provided in the first aspect above.

[0015] In a third aspect, the present application also provides an embedded device, which includes the embedded mainboard provided in the second aspect above.

[0016] The present application scheme can utilize the debugging data signal during the programming or debugging process to provide a feeding signal for the watchdog chip to meet the timing requirements of the watchdog chip when the microprocessor is being programmed or debugged, thereby ensuring that the microprocessor will not be reset, allowing the programming or debugging process to proceed smoothly, helping to maintain system stability, and improving system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A principle block diagram of an embedded control circuit provided in one embodiment of the present application.

[0018] Figure 2 A schematic diagram of the circuit structure of a signal input module provided in one embodiment of the present application.

[0019] Figure 3 A schematic diagram of the circuit structure of an embedded control circuit provided in one embodiment of the present application.

[0020] Figure 4 A schematic diagram of a waveform of a dog feeding signal output by a microcontroller according to an embodiment of the present application.

[0021] Figure 5 A waveform diagram of a debugging data signal provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only the parts related to the embodiments of the present application rather than all structures are shown in the accompanying drawings, and those skilled in the art should be able to think of it after reading the specification of this application that as long as the technical features do not contradict each other, any combination of the technical features can constitute an optional implementation method.

[0023] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally represents that the objects associated before and after are in an "or" relationship. In the description of the present application, "multiple" means two or more, and "several" means one or more.

[0024] Embedded devices are devices that integrate dedicated hardware and software. They are widely used in various fields, such as industrial control, medical equipment, consumer electronics, etc. In order to ensure the reliability and stability of embedded devices, watchdog circuits are usually used to monitor the operating status of the device. The watchdog circuit is a hardware timer. When the device is abnormal or has no operation for a long time, the watchdog circuit will automatically reset the system and restore the device to normal operation.

[0025] Microprocessors are the core components of embedded devices and are usually programmed and debugged using Serial Wire Debug (SWD) or Joint Test Action Group (JTAG). Both SWD and JTAG are debugging interface standards developed by the Institute of Electrical and Electronics Engineers (IEEE), which enable non-intrusive, full-rate debugging of microprocessors.

[0026] In the related art, the WDI (Watchdog Input) pin of the watchdog circuit is used to receive the dog feeding signal from the microprocessor. When the microprocessor is operating normally, it will periodically output a fixed periodic signal (such as a pulse signal) to the WDI pin to keep the watchdog timer counter reset to zero, so that the watchdog timer will not overflow and will not output a reset signal. However, when the microprocessor is being programmed or debugged, since the microprocessor is not in normal operation, it is impossible to output a normal dog feeding signal to the WDI pin, and then the watchdog timer will overflow due to the lack of a dog feeding signal, and output a reset signal, causing the microprocessor to be reset, thereby interrupting the programming or debugging process.

[0027] In this regard, an embodiment of the present application provides an embedded control circuit, which can be applied to an embedded mainboard and can provide a corresponding dog feeding signal when the microprocessor is programmed or debugged to ensure that the microprocessor will not be reset. Figure 1 The principle block diagram of the embedded control circuit provided in one embodiment of the present application is shown in the figure, and the embedded control circuit includes a microcontroller 101, a watchdog chip 102 and a signal input module 103. Among them, the reset pin of the microcontroller 101 is connected to the reset output pin of the watchdog chip 102, the signal output pin of the microcontroller 101 is connected to the first input end of the signal input module 103, the serial input pin of the microcontroller 101 is connected to the test port 104, the second input end of the signal input module 103 is connected to the test port 104, and the output end of the signal input module 103 is connected to the signal input pin of the watchdog chip 102.

[0028] The test port 104 is used to access the debug data signal. For example, the debug data signal imported according to the SWD or JTAG interface standard is accessed to the embedded device through the test port 104, and the test port 104 is not only connected to the microcontroller 101, but also connected to the signal input module 103. In this regard, the imported debug data signal can be accessed to the microcontroller 101 and the signal input module 103 through the test port 104. Optionally, in one embodiment, the test port 104 is a JTAG interface, and accordingly, the debug data signal accessed through the test port 104 of the JTAG interface is a TDI signal provided by the TDI pin of the JTAG interface. Optionally, in another embodiment, the test port 104 is a SWD interface, and accordingly, the debug data signal accessed through the test port 104 of the SWD interface is a SWDIO signal provided by the SWDIO pin of the SWD interface.

[0029] When the microcontroller 101 is in normal operation, the signal input module 103 outputs the output signal provided by the signal output pin of the microcontroller 101 as a dog feeding signal to the signal input pin of the watchdog chip 102 through the first input terminal thereof. When the microcontroller 101 is in the programming or debugging process, the signal input module 103 outputs the debugging data signal connected to the test port 104 as a dog feeding signal to the signal input pin of the watchdog chip 102 through the second input terminal thereof.

[0030] It is understandable that this solution utilizes the debug data signal introduced into the microprocessor, and when the microprocessor is programmed or debugged, the debug data signal generated in the process is utilized as the watchdog chip 102's feeding signal. In this regard, even if the microprocessor cannot output a normal feeding signal to the watchdog chip 102, this solution can ensure that the watchdog chip 102 will not overflow and output a reset signal, thereby preventing the microprocessor from being reset and interrupting the programming or debugging process.

[0031] It can be seen from the above scheme that this scheme can utilize the debugging data signal during the programming or debugging process to provide a dog feeding signal for the watchdog chip to meet the timing requirements of the watchdog chip when the microprocessor is programmed or debugged, thereby ensuring that the microprocessor will not be reset, so that the programming or debugging process can proceed smoothly, which helps to maintain system stability and improve the stability of the system.

[0032] Figure 2 A circuit structure diagram of a signal input module provided for an embodiment of the present application. In one embodiment, the signal input module includes a pull-up resistor R1, a first diode D1 and a second diode D2. The signal input module can provide two paths for accessing the dog feeding signal for the watchdog chip, thereby being able to provide the watchdog chip with a dog feeding signal when the microcontroller is being programmed or debugged.

[0033] Specifically, Figure 2 As shown, the first end of the pull-up resistor R1 is connected to the working voltage, the second end of the pull-up resistor R1 is connected to the signal input pin of the watchdog chip, the anode end of the first diode D1 is connected to the second end of the pull-up resistor R1, the cathode end of the first diode D1 is connected to the signal output pin of the microcontroller, the anode end of the second diode D2 is connected to the second end of the pull-up resistor R1, and the cathode end of the second diode D2 is connected to the test port.

[0034] It can be understood that the first diode D1 and the second diode D2 provide two paths for the access of the dog feeding signal. When the cathode end of any diode is connected to the corresponding signal, the diode is turned on so that the signal input pin of the watchdog chip is connected to the dog feeding signal. When the microprocessor is in normal operation, the first diode D1 is turned on, and the microcontroller can output a periodic signal accordingly to provide it to the signal input pin of the watchdog chip as a dog feeding signal; when the microcontroller is in the programming or debugging process, the test port is connected to the debug data signal, in response to which the second diode D2 is turned on so that the debug data signal is used as the dog feeding signal and provides the signal input pin of the watchdog chip.

[0035] Therefore, the signal input module can provide two signals as dog feeding signals for the watchdog chip, so that when the microcontroller is in normal or programming debugging state, the circuit can provide dog feeding signals so that the watchdog chip will not overflow and output a reset signal, which helps to maintain system stability.

[0036] It should be noted that, in one embodiment, the first diode and the second diode are both Schottky diodes, so that signal isolation is achieved through the two Schottky diodes to prevent another signal from interfering with the microcontroller.

[0037] In some embodiments, the embedded control circuit also includes a filter capacitor, a first end of which is connected to the power pin of the watchdog chip, and a second end of which is grounded. In this regard, the filter capacitor can filter the voltage signal connected to the watchdog chip, thereby improving the power supply quality of the watchdog chip.

[0038] Figure 3 A schematic diagram of the circuit structure of an embedded control circuit provided in an embodiment of the present application is shown in the figure. Figure 3The first chip U1 represents a microprocessor, the second chip U2 represents a watchdog chip, and the interface J1 represents a test port, which can be used for programming and debugging of the microcontroller, that is, to access the corresponding debugging data signal. In one embodiment, taking the test port as a JTAG interface as an example, the reset pin nRST of the first chip U1 (i.e., the microprocessor) is connected to the reset output pin RESET of the second chip U2 (i.e., the watchdog chip), the power pin VCC of the second chip U2 is connected to the working voltage, and it is also connected to the grounded filter capacitor C1.

[0039] The signal output pin GPIO of the first chip U1 is connected to the cathode end of the first diode D1, and the anode end of the first diode D1 is connected to one end of the pull-up resistor R1. The other end of the pull-up resistor R1 is connected to the working voltage, and the anode end of the first diode D1 is also connected to the signal input pin WDI of the second chip U2. In addition, the serial input pin JTAG_TDI of the first chip U1 is connected to the cathode end of the second diode D2, and the anode end of the second diode D2 is connected to the anode end of the first diode D1. The pull-up resistor R1 serves as a pull-up resistor for the signal input pin WDI, and its purpose is to determine the level state of the signal input pin WDI, and to form corresponding control logic with the first diode D1 and the second diode D2.

[0040] Moreover, the interface J1 is used as a test port, and the pin for accessing the debug data signal is connected to the serial input pin JTAG_TDI of the above-mentioned first chip U1. In addition, the other pins on the interface J1 are connected one-to-one to the pins on the first chip U1 (such as the clock pin TCK, the mode selection pin TMS, the data output pin TDO, etc.).

[0041] It can be understood that when the first chip U1 is in normal operation and the interface J1 is not connected, the signal output pin GPIO will output a periodic signal to the signal input pin WDI as a dog feeding signal. When the signal output pin GPIO outputs a high level (such as 3.3V), that is, the cathode end of the first diode D1 is a high level. Due to the unidirectional conductivity of the diode and the existence of the pull-up resistor R1, the cathode end of the first diode D1 is also pulled up to 3.3V at this time. In this regard, the signal input pin WDI recognizes a high level. When the signal output pin GPIO outputs a low level (such as 0V), that is, the cathode end of the first diode D1 is a low level. Due to the unidirectional conductivity of the diode, the anode end of the first diode D1 is 0.4~0.7V (corresponding to the voltage drop of the diode) at this time, and the signal input pin WDI recognizes a low level.

[0042] Exemplarily, in one embodiment, the timer period is 1.6s. Figure 4The waveform diagram of the dog-feeding signal output by the microcontroller provided in one embodiment of the present application, the horizontal direction in the figure corresponds to the time axis, and each grid in this direction corresponds to 1ms. In this regard, the signal period of the dog-feeding signal output by the signal output pin GPIO of the microcontroller (i.e., the first chip U1) is less than or equal to the timer period of the watchdog chip (i.e., the second chip U2), so that the dog-feeding signal can be provided in time before overflow. And the timer period of the watchdog chip is greater than the minimum reset time of the microcontroller, and the minimum reset time is the shortest time required to recover from the reset state to the normal working state. Therefore, after the microcontroller is reset, the corresponding dog-feeding signal can be provided in time to ensure that the watchdog chip will not overflow.

[0043] When the first chip U1 is connected to the interface J1 and the first chip U1 is in the debugging state, during the debugging process, the state of the signal output pin GPIO may be one of the high impedance state, weak pull-up state or weak pull-down state, and the dog feeding signal cannot be output. In addition, due to the existence of the first diode D1 and the second diode D2, the state of the signal output pin GPIO will not affect the serial input pin JTAG_TDI. Therefore, in the debugging state, the serial input pin JTAG_TDI is connected to the debugging data signal. The principle is as described above. When the serial input pin JTAG_TDI is connected to a high level, the cathode end of the second diode D2 is a high level. When the serial input pin JTAG_TDI is connected to a low level, the cathode end of the second diode D2 is 0.4~0.7V.

[0044] It can be imagined that the data pulse width of the debugging data signal is less than or equal to the signal period of the dog feeding signal. Figure 5 A waveform diagram of a debug data signal provided for an embodiment of the present application, wherein the horizontal direction in the figure corresponds to the time axis, and each grid in this direction corresponds to 1 ms. As shown in the figure, in one embodiment, the data pulse width of the connected debug data signal satisfies the condition of being less than or equal to the signal period of the watchdog signal, and will not cause a timeout. Furthermore, during the entire debugging process, the serial input pin JTAG_TDI has a debug data signal connected, that is, the debug data signal acts as the watchdog signal of the signal input pin WDI, and the reset output pin RESET of the second chip U2 (i.e., the watchdog chip) will not generate a low-level reset signal, thereby effectively avoiding interrupting the programming and debugging process of the microcontroller.

[0045] An embodiment of the present application also provides an embedded mainboard, which includes the embedded control circuit provided in the above embodiment. The embedded mainboard can use the debugging data signal in the programming or debugging process to provide a dog feeding signal for the watchdog chip thereon, so that the programming or debugging process can also proceed smoothly, thereby effectively improving the stability of the mainboard and facilitating the application of the mainboard in embedded devices.

[0046] An embodiment of the present application also provides an embedded device, which includes the embedded mainboard provided by the above embodiment. The embedded device can utilize the debugging data signal during the programming or debugging process, which can effectively solve the problem of the watchdog timer overflowing and outputting a reset signal due to the lack of a dog feeding signal during the programming or debugging process of the microprocessor, so that the microcontroller can be debugged smoothly during the programming or debugging process, thereby improving the reliability and stability of the embedded device, while reducing the workload of developers, improving the work efficiency of programming or debugging, and facilitating the widespread application of embedded devices.

[0047] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0048] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. An embedded control circuit, characterized in that: Including microcontroller, watchdog chip and signal input module; The reset pin of the microcontroller is connected to the reset output pin of the watchdog chip, the signal output pin of the microcontroller is connected to the first input end of the signal input module, and the serial input pin of the microcontroller is connected to the test port, and the test port is used to access the debugging data signal; The second input end of the signal input module is connected to the test port, and the output end of the signal input module is connected to the signal input pin of the watchdog chip. The signal input module is used to output the output signal provided by the signal output pin of the microcontroller as a dog feeding signal to the signal input pin of the watchdog chip when the microcontroller is in normal operation, and is also used to output the debugging data signal connected to the test port as a dog feeding signal to the signal input pin of the watchdog chip when the microcontroller is in a programming or debugging process.

2. The embedded control circuit according to claim 1, characterized in that: The signal input module includes a pull-up resistor, a first diode and a second diode; The first end of the pull-up resistor is connected to the working voltage, and the second end of the pull-up resistor is connected to the signal input pin of the watchdog chip; An anode end of the first diode is connected to the second end of the pull-up resistor, and a cathode end of the first diode is connected to a signal output pin of the microcontroller; An anode terminal of the second diode is connected to the second end of the pull-up resistor, and a cathode terminal of the second diode is connected to the test port.

3. The embedded control circuit according to claim 2, characterized in that: The first diode and the second diode are both Schottky diodes.

4. The embedded control circuit according to any one of claims 1 to 3, characterized in that: It also includes a filter capacitor, a first end of the filter capacitor is connected to the power pin of the watchdog chip, and a second end of the filter capacitor is grounded.

5. The embedded control circuit according to claim 1, characterized in that: The test port is a JTAG interface. In the case where the test port is the JTAG interface, the debug data signal is a TDI signal provided by a TDI pin of the JTAG interface.

6. The embedded control circuit according to claim 1, characterized in that: The test port is a SWD interface. In the case where the test port is the SWD interface, the debug data signal is a SWDIO signal provided by a SWDIO pin of the SWD interface.

7. The embedded control circuit according to claim 1, characterized in that: The signal period of the dog feeding signal output by the signal output pin of the microcontroller is less than or equal to the timer period of the watchdog chip, and the timer period of the watchdog chip is greater than the minimum reset duration of the microcontroller.

8. The embedded control circuit according to any one of claims 5 to 7, characterized in that: The data pulse width of the debugging data signal is less than or equal to the signal period of the dog feeding signal.

9. An embedded motherboard, characterized in that: Comprising the embedded control circuit as described in any one of claims 1-8.

10. An embedded device, characterized in that: Comprising the embedded mainboard as claimed in claim 9.

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