Simple parallel communication system and method between CPUs
By using data bus and read and write signal lines in inter-CPU parallel communication system, combining GPIO signal analog bus and signal lines, and adding fault-tolerant signal lines, the existing inter-CPU communication methods are slow, poor real-time and high hardware cost. The problem is to achieve efficient and reliable data interaction between CPUs.
Patent Information
- Application Number
- CN202411535195.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-18
AI Technical Summary
The existing inter-CPU communication methods have problems such as slow communication speed, poor real-time performance, high hardware costs and lack of suitable communication interfaces, which are difficult to meet the needs of fast data interaction.
A simple inter-CPU parallel communication system and method is adopted to realize fast data transmission between CPUs through the data bus and read and write signal lines, and use GPIO signals to simulate bus and signal lines, and add fault-tolerant signal lines to achieve data verification.
It realizes fast and accurate signal transmission and data interaction between CPUs, improves communication reliability and real-time performance, reduces hardware costs, and is suitable for data interaction in multiprocessor systems.
Smart Images
Figure CN119473991A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of communication systems, and in particular relates to a simple parallel communication system and method between CPUs. Background Art
[0002] In a multi-processor system, different CPUs need to communicate with each other to coordinate tasks / share data or implement parallel computing, so the use of parallel port single-frame communication between CPUs can be used to quickly and reliably transmit data between processors. In embedded systems, parallel port single-frame communication between CPUs can achieve efficient data transmission without increasing system complexity. Different processor modules can share memory or perform data processing through parallel port communication.
[0003] A parallel port connection is an interface in which each bit of data is transmitted simultaneously. In inter-CPU parallel port communication, multiple data bits can be transmitted simultaneously on different lines, thereby achieving a relatively high data transfer rate.
[0004] At present, there are many ways of communication between CPUs, such as serial communication, CAN bus communication, Ethernet communication, etc. The main problems are: 1. For low-speed communication interfaces, the communication speed is slow and the real-time performance is poor; 2. Additional communication interface hardware is required, which increases hardware costs; 3. When the CPU may not have a suitable communication interface but requires fast interactive data, the existing communication methods cannot fully meet the needs. Summary of the invention
[0005] To solve the above problems, the purpose of the present invention is to provide a simple parallel communication system and method between CPUs, a new communication method between CPUs, which has the advantages of fast response speed, high efficiency and simplicity. In the communication between CPUs, one party needs to send a read / write signal and send the data content through the data bus Data[0:x]. The other party receives RD / WE and reads the data on the data bus Data. It realizes fast and accurate signal transmission and reception between CPUs and realizes data interaction.
[0006] A simple parallel communication system between CPUs includes CPU1, CPU2, a data bus, and a read / write signal line. The CPU1 and CPU2 are connected via the data bus, and a read / write signal line is provided between the CPU1 and CPU2. Data is transmitted between CPU1 and CPU2 via the data bus and the read / write signal line. Small CPUs do not have a dedicated data bus due to limited resources, and use GPIO (general purpose input / output port) to simulate the bus to achieve data transmission.
[0007] Furthermore, two fault-tolerant signal lines are added between the CPU1 and the CPU2. The fault-tolerant signal line is the GPIO signal of the CPU, and the input or output state can be set according to different uses. The fault-tolerant line plays a role of supplementary verification.
[0008] Furthermore, the data bus can be replaced by a GPIO signal of the CPU.
[0009] Furthermore, the read / write signal line is a GPIO signal of the CPU, and the input or output state can be set according to different uses.
[0010] Furthermore, the data bus Data[0:x] can realize data transmission of 0~x bits. In read and write operations, data will be transmitted or stored within this range. CPU1 and CPU2 are connected via a data bus. The data bus is used to transmit data between CPU1 and CPU2. It can be a set of parallel lines, each line representing a data bit.
[0011] Furthermore, two read / write signal lines are provided between the CPU1 and the CPU2. The read / write signal of the CPU1 is connected to the read / write signal of the CPU2 through the read / write signal lines, so as to realize unidirectional / bidirectional data transmission.
[0012] A simple method for parallel communication between CPUs, the specific steps are: S1 CPU1 sends a read or write signal to CPU2; The S2 read or write signal triggers the interrupt of CPU2; If S3 is a write signal, CPU2 receives the data on the data bus in the interrupt; If S4 is a read signal, CPU2 sends the data to the data bus in the interrupt and drives the write signal. The write signal triggers the interrupt of CPU1, and CPU1 receives the data on the data bus in the interrupt.
[0013] Furthermore, after reading the data, fault tolerance measures are used to confirm that the data is correct. The specific steps include: The receiver reads the data twice in succession and compares the two results. If they are consistent, it is considered that the data communication result is correct, otherwise it is wrong. The states of the two fault-tolerant signal lines are different when communicating and when not communicating. If the state of the fault-tolerant signal line meets the state characteristics during communication, it is considered that the data communication result is correct, otherwise it is wrong; The communication data has a check bit. If the value of the check bit conforms to the rules, the result of this data communication is considered correct, otherwise it is wrong.
[0014] The present invention provides a simple parallel communication method between CPUs. The sender only needs to send a read / write signal, which triggers the interruption of the receiver. The software controls the receiver to read the data on the data bus Data[0:x] in its interruption without going through the address bus Add[0:x]. The read / write signal line and the data bus together constitute the communication channel between CPU1 and CPU2. The write signal line is used to trigger data transmission, the read signal line is used to confirm data reception, and the data bus is responsible for the actual data transmission. This connection relationship enables the two CPUs to perform single-frame data communication in a relatively simple and efficient manner, which is suitable for application scenarios that achieve communication speed and real-time, simple and reliable communication methods.
[0015] 1. This method provides an efficient solution for data interaction in multi-processor systems and can improve the communication reliability between CPUs.
[0016] 2. This method takes into account signal stability, timeliness of interrupt processing and data consistency.
[0017] 3. When CPU1 sends a read / write signal, it successfully triggers the interrupt of CPU2. The signal transmission mechanism is effective and can promptly notify CPU2 that there is data to be processed.
[0018] 4.CPU2 can accurately read the data on the data bus Data [0:x] during the interrupt. Through software control, CPU2 can process and store the read data according to specific needs.
[0019] 5. This mechanism implements asynchronous communication between CPU1 and CPU2, and improves the parallel processing capability of the system. For example, CPU1 does not need to wait for CPU2 to complete data reading and can continue to execute other tasks.
[0020] Instruction Manual Figure 1 It is a connection diagram of the present invention.
[0021] Figure 2 It is a timing diagram of the present invention. DETAILED DESCRIPTION
[0022] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Example
[0023] like Figure 1As shown, a simple parallel communication system between CPUs includes CPU1, CPU2, a data bus, and a read-write signal line. CPU1 and CPU2 are connected via the data bus, and a read-write signal line is provided between CPU1 and CPU2. Data is transmitted between CPU1 and CPU2 via the data bus and the read-write signal line.
[0024] There are two read / write signal lines between CPU1 and CPU2, and the read / write signal of CPU1 is connected to the read / write signal of CPU2 through the read / write signal lines, realizing unidirectional / bidirectional data transmission.
[0025] Two fault-tolerant signal lines are added between CPU1 and CPU2. The fault-tolerant signal lines are GPIO signals of the CPU, and the input or output status can be set according to different uses.
[0026] The data bus can be replaced by the CPU's GPIO signal.
[0027] The read and write signal lines are the GPIO signals of the CPU, and the input or output status can be set according to different uses.
[0028] Data bus Data[0:x], the data range is from 0 to X. In read and write operations, data will be transmitted or stored within this range. Example
[0029] like Figure 2 As shown, a simple method for parallel communication between CPUs is implemented by using the system of Example 1, and the specific steps are as follows: S1 CPU1 sends a read or write signal to CPU2; The S2 read or write signal triggers the interrupt of CPU2; If S3 is a write signal, CPU2 receives the data on the data bus in the interrupt; If S4 is a read signal, CPU2 sends the data to the data bus in the interrupt and drives the write signal. The write signal triggers the interrupt of CPU1, and CPU1 receives the data on the data bus in the interrupt.
[0030] After reading the data, fault-tolerant measures are used to confirm that the data is correct. The specific steps include: The receiver reads the data twice in succession and compares the two results. If they are consistent, it is considered that the data communication result is correct, otherwise it is wrong.
[0031] The states of the two fault-tolerant signal lines are different when communicating and when not communicating. If the states of the fault-tolerant signal lines meet the state characteristics during communication, it is considered that the result of this data communication is correct, otherwise it is wrong.
[0032] The communication data has a check bit. If the value of the check bit conforms to the rules, the result of this data communication is considered correct, otherwise it is wrong.
[0033] The above are only preferred technical solutions of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements without departing from the principles of the present invention. These improvements should also be regarded as the protection scope of the present invention.
Claims
1. A simple parallel communication system between CPUs, characterized by: It includes CPU1, CPU2, data bus, and read / write signal lines. The CPU1 and CPU2 are connected via the data bus. A read / write signal line is provided between the CPU1 and CPU2. Data is transmitted between the CPU1 and CPU2 via the data bus and the read / write signal line.
2. The system according to claim 1, characterized in that: Two fault-tolerant signal lines are added between the CPU1 and the CPU2. The fault-tolerant signal lines are GPIO signals of the CPU and can be set to input or output states according to different uses.
3. The system as claimed in claim 2, characterized in that: The data bus can be replaced by the GPIO signal of the CPU.
4. The system as claimed in claim 2, characterized in that: The read / write signal line is the GPIO signal of the CPU, and the input or output state can be set according to different uses.
5. The system according to claim 1, characterized in that: The data bus Data[0:x] has a data range from 0 to X. In read and write operations, data will be transmitted or stored within this range.
6. The system according to claim 1, characterized in that: Two read / write signal lines are provided between the CPU1 and the CPU2, and the read / write signal of the CPU1 is connected to the read / write signal of the CPU2 through the read / write signal lines.
7. A simple parallel communication method between CPUs, characterized by: The following steps are included S1 CPU1 sends a read or write signal to CPU2; The S2 read or write signal triggers the interrupt of CPU2; If S3 is a write signal, CPU2 receives the data on the data bus in the interrupt; If S4 is a read signal, CPU2 sends the data to the data bus in the interrupt and drives the write signal. The write signal triggers the interrupt of CPU1, and CPU1 receives the data on the data bus in the interrupt.
8. The method according to claim 7, characterized in that: After reading the data, fault-tolerant measures are used to confirm that the data is correct. The specific steps include: S1 The receiver reads the data twice in succession and compares the two results. If they are consistent, it is considered that the data communication result is correct, otherwise it is wrong; S2 The states of the two fault-tolerant signal lines are different when communicating and when not communicating. If the state of the fault-tolerant signal line meets the state characteristics during communication, it is considered that the data communication result is correct, otherwise it is wrong; The data of S3 communication has a check bit. If the value of the check bit conforms to the rules, the result of this data communication is considered correct, otherwise it is wrong.