Processor, chip system and related request service quality configuration method

Abstract

The embodiment of the invention discloses a processor, a chip system and a related request service quality configuration method, the processor comprises a first control unit and N processor cores, a target processor core in the N processor cores comprises a first mapping unit and a plurality of execution units, and the plurality of execution units comprise a target execution unit. The first control unit is used for receiving a target memory access request sent by the first mapping unit, the target memory access request comprises first service quality, and the first service quality is used for indicating the priority of the memory access request corresponding to the target execution unit; adjusting the first service quality based on the current system information to obtain second service quality corresponding to the target memory access request in the current state; and accessing the memory through the second service quality based on the target memory access request. By adopting the embodiment of the invention, the scheduling priority of the memory access request sent by the processor can be indicated more accurately, so that the execution performance of the key task is ensured, and the performance of the processor is improved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular to a method for configuring the quality of service of a processor, a chip system, and related requests. Background Art

[0002] Since the 1960s, processor performance has been developing rapidly in accordance with Moore's Law. As the integration of single-chip transistors becomes higher and higher, problems such as chip power consumption, line transmission delay, and leakage current are becoming increasingly serious. It is very difficult to improve processor performance simply by increasing the main frequency, and the return on investment of developing instruction-level parallelism using traditional superscalar and forward-looking technologies is also getting lower and lower. Developing higher-level process-level parallelism and task-level parallelism has become an inevitable trend to continuously improve processor performance. Advanced architectures represented by multi-core processors have become the dominant design structure in the current high-performance computing field. Today, multi-core processors have been used in many fields such as servers, notebooks, game platforms, and high-performance multimedia applications.

[0003] With the rapid development of processor architecture and the continuous improvement of production process level, the working efficiency of processors and memory systems has been continuously improved. However, the working efficiency of processors and memory systems has not increased at the same rate. The performance improvement rate of processors is significantly higher than that of memory systems. The gap between processor memory access speed and computing speed is becoming more and more significant. Memory access performance has become an important factor affecting processor performance, and memory access performance optimization has become a key factor in improving processor performance.

[0004] In a traditional single-core processor system, the memory system only needs to provide data for one processor core. On a multi-core processor platform, the memory system needs to provide data for multiple processor cores at the same time, and the memory access requests of multiple processes interfere with each other. The memory access competition of multiple processes leads to an increase in the average memory access latency, which has a significant negative impact on the processor performance. At the same time, in the processor core, the memory system needs to provide data for multiple processing sub-units (such as arithmetic logic units, memory read and write units, etc.) in the processor core at the same time, and the memory access requests of multiple processing sub-units interfere with each other. The memory access competition of multiple processing sub-units leads to an increase in the average memory access latency, which also has a significant negative impact on the processor performance. Summary of the invention

[0005] The embodiments of the present application provide a method for configuring the quality of service of a processor, a chip system and related requests, which can more accurately indicate the scheduling priority of a memory access request sent by the processor to ensure the execution performance of key tasks, thereby improving processor performance.

[0006] In a first aspect, an embodiment of the present application provides a processor, the processor comprising a first control unit and N processor cores, a target processor core among the N processor cores comprising a first mapping unit and multiple execution units, N being an integer greater than 0, and the multiple execution units comprising a target execution unit, wherein the first control unit is used to: receive a target memory access request corresponding to the target execution unit sent by the first mapping unit, the target memory access request comprising a first quality of service, and the first quality of service is used to indicate the priority of the memory access request corresponding to the target execution unit; adjust the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information comprises one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a temperature of the current processor, and an available bandwidth of the memory; and access the memory through the second quality of service based on the target memory access request.

[0007] In an embodiment of the present application, a control unit in a processor receives a memory access request sent by a processor core, and the memory access request corresponds to an initial service quality, and the initial service quality is used to indicate the initial scheduling priority of the memory access request. For example, the higher the initial service quality, the higher the scheduling priority of the memory access request, and then the processor can give priority to scheduling memory access requests with high service quality to ensure the execution performance of key tasks. In the prior art, the control unit accesses the memory based on the initial service quality. In the present application, the control unit can adjust the initial service quality (i.e., the first service quality) of the memory access request based on the current system state to obtain the final service quality (i.e., the second service quality). Then, the control unit accesses the memory based on the final service quality. Compared with accessing the memory with the initial service quality, the adjusted service quality can more accurately indicate the scheduling priority of the memory access request to ensure the execution performance of key tasks, thereby improving the processor performance. In addition, when adjusting the initial service quality, the control unit can be based on multiple information, such as the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, etc., to configure the service quality of the memory access request from multiple dimensions, so that the adjusted service quality can more accurately indicate the scheduling priority of the memory access request.

[0008] In some embodiments, each execution unit among the multiple execution units corresponds to a hardware service quality, and the first mapping unit is used to: determine the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit among the multiple execution units, and determine the hardware service quality corresponding to the target memory access request as the first service quality.

[0009] In an embodiment of the present application, since the functions of the multiple execution units in the processor core are different, the importance of the memory access requests issued by different execution units is different, so the hardware service quality of the execution unit can be used as the first service quality (i.e., the initial service quality) to indicate the scheduling priority of the memory access request. For example, the memory access request initiated by the instruction acquisition unit (an execution unit) is to obtain the operation instruction, and the memory access request initiated by the operation logic unit (another execution unit) is to obtain the operation data. The importance of obtaining the operation instruction is higher than the importance of obtaining the operation data. Therefore, the memory access request initiated by the instruction acquisition unit is more important than the memory access request initiated by the operation logic unit. Further, the hardware priorities of multiple execution units can be preset in advance. When mapping the hardware service quality for the memory access request, it can be determined according to the hardware priority of the execution unit to indicate the importance of the memory access request initiated by the corresponding execution unit, so that the memory access request with higher hardware service quality can be processed preferentially to improve the utilization of the memory, reduce access delay, and improve processor performance.

[0010] In some embodiments, each of the N processor cores runs a thread, the target processor core runs a target thread, one thread corresponds to a software service quality, the target memory access request includes the software service quality corresponding to the target thread, the software service quality corresponding to the target thread is used to indicate the priority of the memory access request corresponding to the target thread, and the first mapping unit is used to: determine the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit among multiple execution units; determine the first service quality based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target memory access request.

[0011] In the embodiment of the present application, since the functions of the multiple execution units in the processor core are different, the importance of memory access requests issued by different execution units is different. At the same time, since the threads running on the different execution units are different and different threads correspond to different tasks, the importance of memory access requests initiated by the threads is also different. Therefore, the first service quality (i.e., initial service quality) can be determined based on the hardware service quality and software service quality of the execution unit, so that memory access requests with higher hardware service quality and software service quality can be processed preferentially to improve the utilization of the memory, reduce access delay, and improve processor performance.

[0012] In some embodiments, the first mapping unit stores a first mapping table, which is used to record the mapping relationship between the first service quality and the software service quality and the hardware service quality. The first mapping unit is specifically used to: determine the first service quality from the first mapping table based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread.

[0013] In an embodiment of the present application, the first mapping unit can be composed of registers, and a mapping table can be stored in advance at the first mapping unit, which can record the mapping relationship between the software service quality corresponding to the memory access request and the hardware service quality corresponding to the memory access request and the first service quality, so as to facilitate the comprehensive decision-making of the first service quality of the target memory access request, so that memory access requests with higher hardware service quality and software service quality can be given priority to improve memory utilization, reduce access latency, and enhance processor performance.

[0014] In some embodiments, the first control unit is specifically used to: obtain current system information, and analyze and process the current system information based on a preset algorithm to determine a current system status score, where the current system status score is used to indicate current processor performance and / or current memory performance; based on the current system status score, adjust the first service quality to obtain a second service quality.

[0015] In the embodiment of the present application, when the control unit adjusts the initial service quality, the control unit can analyze and process various information, such as the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, etc., to obtain the current system status score. Furthermore, the initial service quality can be adjusted based on the current system status score to obtain the final service quality, so as to configure the service quality of the memory access request from multiple dimensions, so that the adjusted service quality can more accurately indicate the scheduling priority of the memory access request.

[0016] In some embodiments, the first control unit is specifically used to: if the current system status score is greater than a threshold, determine the first service quality as the second service quality; if the current system status score is less than or equal to the threshold, increase the first service quality to obtain the second service quality.

[0017] In the embodiment of the present application, the initial service quality can be adjusted based on the current system status score. If the current system status score is greater than the threshold, it can be indicated that the current system status is normal, and the initial service quality can be adjusted without adjusting, and the initial service quality can be directly used as the final service quality. If the current system status score is less than or equal to the threshold, it can be indicated that the current system status is poor (i.e., the system is busy), and the initial service quality can be increased to obtain the final service quality, so as to configure the service quality of the memory access request from multiple dimensions, so that the adjusted service quality can more accurately indicate the scheduling priority of the memory access request.

[0018] In a second aspect, the present application provides a method for configuring a requested quality of service, which is applied to a processor, wherein the processor includes a first control unit and N processor cores, wherein a target processor core among the N processor cores includes a first mapping unit and multiple execution units, N is an integer greater than 0, and the multiple execution units include a target execution unit. The method includes: receiving, through the first control unit, a target memory access request corresponding to the target execution unit sent by the first mapping unit, the target memory access request including a first quality of service, and the first quality of service is used to indicate the priority of the memory access request corresponding to the target execution unit; adjusting the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a temperature of the current processor, and an available bandwidth of the memory; and accessing the memory through the second quality of service based on the target memory access request.

[0019] In some embodiments, each execution unit in a plurality of execution units corresponds to a hardware service quality, and the method further includes: determining, through a first mapping unit, the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit in the plurality of execution units, and determining the hardware service quality corresponding to the target memory access request as the first service quality.

[0020] In some embodiments, each of the N processor cores runs a thread, the target processor core runs a target thread, one thread corresponds to a software service quality, the target memory access request includes the software service quality corresponding to the target thread, and the software service quality corresponding to the target thread is used to indicate the priority of the memory access request corresponding to the target thread. The method also includes: determining, through a first mapping unit, the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit among multiple execution units; determining the first service quality based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target memory access request.

[0021] In some embodiments, the first mapping unit stores a first mapping table, which is used to record the mapping relationship between the first service quality and the software service quality and the hardware service quality, and determines the first service quality based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread, including: determining the first service quality from the first mapping table based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread through the first mapping unit.

[0022] In some embodiments, a first quality of service is adjusted based on current system information to obtain a second quality of service corresponding to a target memory access request in a current state, including: obtaining current system information through a first control unit, and analyzing and processing the current system information based on a preset algorithm to determine a current system state score, wherein the current system state score is used to indicate current processor performance and / or current memory performance; based on the current system state score, adjusting the first quality of service to obtain a second quality of service.

[0023] In some embodiments, based on the current system status score, the first service quality is adjusted to obtain the second service quality, including: if the current system status score is greater than a threshold, the first service quality is determined as the second service quality by the first control unit; if the current system status score is less than or equal to the threshold, the first service quality is increased by the first control unit to obtain the second service quality.

[0024] In a third aspect, the present application provides a chip system, wherein the system on chip includes a processor and a memory, and a controller, wherein the processor includes a first control unit and N processor cores, wherein a target processor core among the N processor cores includes a first mapping unit and multiple execution units, N is an integer greater than 0, and the multiple execution units include a target execution unit, wherein the first control unit of the processor is used to: receive a target memory access request corresponding to the target execution unit sent by the first mapping unit, the target memory access request includes a first quality of service, and the first quality of service is used to indicate the priority of the memory access request initiated by the target execution unit; adjust the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, and the available bandwidth of the memory; send the target memory access request to the controller based on the second quality of service; the controller is used to: receive and respond to the target memory access request, and access the memory according to the second quality of service.

[0025] In a fourth aspect, the present application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, it implements the method described in any one of the second aspects above.

[0026] In a fifth aspect, the present application provides a chip system, which includes a processor for supporting an electronic device to implement the functions involved in the second aspect, for example, generating or processing the information involved in the quality of service configuration method requested above. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the electronic device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0027] In a sixth aspect, the present application provides a computer program product, characterized in that the computer program includes instructions, and when the computer program is executed by a computer, the computer executes any one of the methods described in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a chip system provided by an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of the structure of a processor provided in an embodiment of the present application.

[0030] Figure 3 A schematic diagram of analyzing and processing current system information provided in an embodiment of the present application.

[0031] Figure 4 A schematic diagram of the structure of another processor provided in an embodiment of the present application.

[0032] Figure 5 A schematic diagram of a data table provided in an embodiment of the present application.

[0033] Figure 6 A schematic diagram of the structure of another processor provided in an embodiment of the present application.

[0034] Figure 7 A flowchart of a method for configuring quality of service of a request provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] The chip system involved in the embodiment of the present application is introduced below:

[0039] The present application embodiment provides a chip system. Figure 1 , Figure 1 1 is a schematic diagram of a chip system provided by an embodiment of the present invention, and the chip system may include but is not limited to a system on chip 101 (System on chip, Soc), an internal memory 102, and an external memory 103. The chip system can be integrated in any electronic device, such as a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart car or a smart home appliance, and the chip system can work under the necessary software driver.

[0040] System on chip 101 (System on chip, Soc) refers to a technology that integrates a complete system on a single chip and groups all or part of the necessary electronic circuits. System on chip 101 may include multiple processing units and a controller 1014. Among them, the multiple processing units may include one or more of a central processing unit 1011 (Central Processing Unit, CPU), a modem processing unit, a graphics processing unit 1012 (graphics processing unit, GPU), an image signal processing unit (image signal processor, ISP), a video codec unit, a digital signal processing unit (digital signal processor, DSP), a baseband processing unit and a neural network processing unit 1013 (neural-network processing unit, NPU). Optionally, different processing units can communicate with each other through a primary bus, and the processing units can also communicate with the controller 1014 through the primary bus.

[0041] In some embodiments, the central processing unit 1011 (also referred to as a central processing unit, or processor) may be a multi-core processor, that is, multiple processor cores are integrated in one chip. Multiple processor cores are short for processor cores, also known as kernels, and are the most important components of a central processing unit (CPU). They are made of single crystal silicon using a certain production process. All CPU calculations, command reception or command storage, and data processing are performed by the processor core. Each of the multiple processor cores can load instructions or data stored in an external memory 103 (such as a disk, etc.) into an internal memory 102, and call the instructions or data that need to be calculated to the processor core for calculation. After the calculation is completed, the processor core temporarily stores the result in the internal memory 102, and stores the instructions or data that need to be stored for a long time in the external memory 103 through the controller 1014. The processor core can run an operating system, a file system (such as a flash file system F2FS) or an application program, etc., to control multiple hardware or software components connected to the processor, and can process various data and perform operations. Each of the multiple processor cores can include multiple processing subunits ( Figure 1 Only processing subunit a, processing subunit b, processing subunit n) and the first mapping unit newly added in the present application are shown. The first mapping unit may be a register built into the processor core, and may map a quality of service for a memory access request issued by the processing subunit to indicate the scheduling priority of the memory access request.

[0042] It is understandable that multiple processor cores can send memory access requests (such as read / write requests) to the internal memory 102 through the controller 1014. On a multi-core processor platform, the memory system needs to provide data to multiple processor cores at the same time, and the memory access requests of multiple processes interfere with each other. The memory access competition of multiple processes leads to an increase in the average memory access delay, which has a great negative impact on the performance of the multi-core processor. At the same time, in each processor core, the memory system also needs to provide data to multiple processing sub-units (such as arithmetic logic units, memory read and write units, etc.) in the processor core at the same time, and the memory access requests of multiple processing sub-units interfere with each other. The memory access competition of multiple processing sub-units leads to an increase in the average memory access delay, which also has a great negative impact on the processor performance. Therefore, in the present application, the controller 1014 can access the internal memory 102 based on the scheduling priority corresponding to each memory access request, which can improve the utilization rate of the internal memory 102, reduce the memory access delay, and improve the processor performance.

[0043] In addition, in the present application, after the memory access request initiated by the processor core is mapped to a scheduling priority at the first mapping unit, the scheduling priority can be adjusted based on the current system status, so that the scheduling priority of the memory access request can be more accurately indicated to ensure the execution performance of key tasks, thereby improving processor performance.

[0044] Optionally, the memory of the central processing unit 1011 can be a cache memory (Cache). The Cache can include one or more of a first-level cache (L1 Cache), a second-level cache (L2 Cache), a third-level cache (L3 Cache), etc. The Cache can save instructions or data that the central processing unit 1011 has just used or cyclically used. If the central processing unit 1011 needs to use the instruction or data again, it can be directly called from the Cache. Repeated access is avoided, the waiting time of the processor core is reduced, and the efficiency of the processor is improved. It can be understood that the processor core can communicate with other processor cores through a secondary bus.

[0045] Optionally, there are heterogeneous processing cores among the multiple processor cores, that is, the structures of the processor cores are different, and the processor cores can be divided into large cores, medium cores, small cores, etc. according to performance. The types of processor cores may include performance cores (also called large cores), energy efficiency cores (also called medium cores), and low power cores (also called small cores), etc. Among them, the performance core can provide high performance, high throughput and low latency, which can be used to ensure the high performance scenario of the processor; the energy efficiency core can provide the best energy efficiency ratio, which can be used to ensure the better performance and lower energy consumption scenario of the processor; the low power core can provide the lowest power consumption, which can be used to ensure the lowest power consumption scenario of the processor.

[0046] In some embodiments, the central processing unit 1011 may be a single-core processor, that is, it includes only one processor core. The function and structure of the processor core are similar to those of the processor core in the multi-core processor described above, and are not repeated here.

[0047] The internal memory 102 (Memory), referred to as memory for short, can be located outside the system on chip 101, and is usually a power-off volatile memory, which will lose the content stored thereon when the power is off, and can also be called the main memory. The internal memory 102 in the present application includes a readable and writable operating memory, which is used to temporarily store the operation data of one or more processor cores, and to exchange data with the external memory 103 or other external memories, and can be used as a storage medium for temporary data of the operating system or other running programs.

[0048] The internal memory 102 may include one or more of a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), etc. Among them, DRAM includes double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), referred to as DDR, second generation double data rate synchronous dynamic random access memory (DDR2), third generation double data rate synchronous dynamic random access memory (DDR3), fourth generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 4, LPDDR4) and fifth generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 5, LPDDR5), etc.

[0049] The controller 1014 can be used to manage and control the communication between the central processing unit 1011 and the external memory 103 (such as a disk, etc.), and provide a standardized interface (such as the universal flash storage UFS standard) for the communication between the central processing unit 1011 and the external storage device. The controller 1014 can also be used to manage and control the communication between the central processing unit 1011 and the internal memory 102. It can also be understood that one or more processor cores can send a memory access request (such as a read / write request) to the internal memory 102 through the controller 1014, and one or more processor cores can also send a memory access request (such as a read / write request) to the external memory 103 through the controller 1014. Specifically, the controller 1014 can access the internal memory 102 or the external memory 103 according to the scheduling priority of the memory access request to improve the utilization of the internal memory 102 or the external memory 103, reduce access latency, and improve processor performance. It will be described in detail later how to determine the scheduling priority of different memory access requests in this application to ensure the execution performance of key tasks, which will not be described in detail here.

[0050] In some embodiments, the controller 1014 can receive read / write requests issued by the central processing unit 1011, transmit commands (e.g., write, read, erase, etc.) and data to the external storage device according to the scheduling priority, and feedback events (e.g., command completion events, command status events, hardware error events, etc.) to the central processing unit 1011 according to the results of reading / writing data of the storage device. For commands or data issued from the central processing unit 1011, the controller 1014 can convert the commands or data into data packets supporting a certain protocol by encapsulation, and for data received by the central processing unit 1011, the controller 1014 performs the reverse operation.

[0051] The external memory 103 is a non-volatile memory, and its stored contents will not be lost after power failure. The external memory 103 can be used for long-term storage of instructions and data involved in the operation of the central processing unit 1011, such as startup programs, operating systems, applications and data. Since the central processing unit 1011 cannot directly read instructions and data in the external memory 103 or directly write instructions or data to the external memory 103, when the central processing unit 1011 executes a read (or load) instruction, it actually temporarily loads the contents to be read (including instructions and / or data) stored in the external memory 103 into the internal memory 102 through the controller 1014, and then the central processing unit 1011 reads it from the internal memory 102; and when executing a write (i.e. store) instruction, it actually temporarily writes the data to be stored (including instructions and / or data) into the internal memory 102 by the central processing unit 1011, and then stores it from the internal memory 102 to the external memory 103 through the controller 1014.

[0052] The external memory 103 may include one or more of Flash flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash storage (UFS), embedded multimedia card eMMC, universal flash storage multi-chip package uMCP memory, embedded multimedia card multi-chip package eMCP memory, solid-state drive (SSD), etc.

[0053] Understandably, Figure 1 The chip systems in the embodiments are just some exemplary implementations provided by the embodiments of the present invention. The chip systems in the embodiments of the present invention include but are not limited to the above implementations.

[0054] The following is an introduction to a processor involved in an embodiment of the present application:

[0055] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a processor provided in an embodiment of the present application. The processor 20 can be used as the central processing unit 1011. Figure 2 The processor 20 in the embodiment may be a single-core processor, and the processor 20 may include a processor core 201, and a first control unit 202 newly added in the present application. The processor core 201 may include a first mapping unit 2016 newly added in the present application and multiple processing sub-units, and the multiple processing sub-units may include but are not limited to an instruction scheduling unit 2011, at least one general-purpose operation unit 2012 (such as 2012A, 2012B, 2012C, 2012D), a result write-back unit 2013, an instruction acquisition unit 2014, and one or more of an instruction decoding unit 2015. In some embodiments, the processing sub-unit may also be referred to as an execution unit.

[0056] The instruction acquisition unit 2014 and the instruction decoding unit 2015 run in the instruction fetch pipeline stage and the decoding pipeline stage respectively, and complete the corresponding instruction fetch and instruction decoding functions.

[0057] In some embodiments, the instruction fetch unit 2014 may initiate a memory access request to fetch instructions from a memory unit.

[0058] The at least one general purpose computing unit 2012 may specifically include one or more of a memory read / write unit (LSU) 2012A, a floating point computing unit (FPU) 2012B, a vector computing unit (SIMD) 2012C, and an arithmetic logic unit (ALU) 2012D. The above-mentioned multiple general purpose computing units (including 2012A, 2012B, 2012C, and 2012D) are all connected to the instruction scheduling unit 2011, and run in the execution pipeline stage as the execution unit (EU) of the processor 20. The above-mentioned execution units respectively receive different types of instructions scheduled by the instruction scheduling unit 2011, and then execute the computing tasks of the types they are good at based on their own different hardware structures.

[0059] In some embodiments, before executing a computing task, multiple general-purpose computing units may initiate a memory access request to obtain the required data. For example, the memory read / write unit (LSU) initiates a memory access request to read and write data from a memory unit (memory), and this process runs in the memory access pipeline stage. Optionally, the processor core 201 also includes a result write-back unit 2013, which runs in the write-back pipeline stage and is responsible for writing the calculation result of the instruction back to the destination register.

[0060] Optionally, when the memory unit is located outside the processor 20, the memory unit may be the above Figure 1 When the memory unit is located inside the processor 20, the memory unit is the above-mentioned cache memory.

[0061] Next, we will combine the above Figure 2 , explains how to determine the service quality of different memory access requests in a single-core processor scenario to indicate the scheduling priority of different memory access requests.

[0062] When the processor 20 runs an application, since the processor 20 is a single-core processor, the processor core 201 cannot run multiple threads in parallel, so the multiple processing sub-units in the processor core 201 are used to run one thread.

[0063] The target processing sub-unit among the multiple processing sub-units is used to send a first memory access request to the first mapping unit 2016.

[0064] The first mapping unit 2016 is configured to receive a first memory access request initiated by a target processing subunit, and determine a first quality of service of the first memory access request.

[0065] In some embodiments, the first memory access request may also be referred to as a target memory access request.

[0066] In some embodiments, the first mapping unit 2016 determines the hardware quality of service (HW-QOS) of the first memory access request based on the hardware priority of the target processing subunit among the multiple processing subunits, and determines the hardware quality of service as the first quality of service.

[0067] Specifically, the hardware service quality is used to indicate the importance of the memory access request initiated by the target processing sub-unit. Since different processing sub-units have different functions, the importance of the memory access requests issued by different processing sub-units is different. For example, the memory access request initiated by the instruction acquisition unit 2014 is to obtain operation instructions, and the memory access request initiated by the arithmetic logic unit (ALU) 2012D is to obtain operation data. The importance of obtaining operation instructions is higher than that of obtaining operation data. Therefore, the memory access request initiated by the instruction acquisition unit 2014 is more important than the memory access request initiated by the arithmetic logic unit (ALU) 2012D.

[0068] Optionally, the hardware priority of each of the multiple processing sub-units is preset, such as the hardware priority of the instruction acquisition unit 2014 is higher than the hardware priority of the general operation unit 2012. Furthermore, when the first mapping unit 2016 maps the HW-QOS for the memory access request, it can be determined according to the hardware priority of the processing sub-unit to indicate the importance of the memory access request initiated by the corresponding processing sub-unit.

[0069] In some embodiments, the first mapping unit 2016 maps HW-QOS to the memory access request based on the hardware priority of the processing subunit, and the mapping relationship can be customized according to actual needs. For example, the higher the hardware priority of the processing subunit, the higher the corresponding HW-QOS, which can indicate that the importance of the memory access request initiated by the processing subunit is higher; the lower the hardware priority of the processing subunit, the lower the corresponding HW-QOS, which can indicate that the importance of the memory access request initiated by the processing subunit is lower. Furthermore, when processing the memory access request initiated by the processing subunit, the memory access request with a higher HW-QOS can be processed preferentially to improve the utilization of the memory unit, reduce access latency, and improve processor performance.

[0070] In some embodiments, for the same processing sub-unit, different requests initiated by the processing sub-unit may correspond to different hardware service qualities. For example, if the processing sub-unit is an LSU, the LSU may dynamically adjust the hardware service quality based on whether the issued request has a dependency relationship with other requests. For example, if a subsequent request or calculation requires the result of this request, then this request may be a critical request, and a higher hardware priority may be set for the critical request.

[0071] The first mapping unit 2016 is further configured to send a first memory access request to the first control unit 202, wherein the first memory access request includes a first quality of service.

[0072] The first control unit 202 is used to receive a first memory access request corresponding to the target processing subunit sent by the first mapping unit 2016, and adjust the first service quality based on the current system information to obtain a second service quality corresponding to the first memory access request in the current state.

[0073] Specifically, the current system information may include but is not limited to the response delay of the memory access request of the current processor 20, the memory access bandwidth of the memory access request of the current processor 20, the temperature of the current processor 20, the available bandwidth of the current memory unit, etc.

[0074] In some embodiments, the first control unit 202 analyzes the current system information, adjusts the first service quality, and obtains the second service quality. Assume that the current system information includes the response delay of the memory access request of the current processor 20, the memory access bandwidth of the memory access request of the current processor 20, the temperature of the current processor 20, and the available bandwidth of the current memory unit.

[0075] The following will be combined Figure 3 How the first control unit 202 analyzes the current system information to obtain the second service quality is described. Figure 3As shown, feature 1, feature 2, ..., feature n can correspond to indicators in the current system information respectively, such as feature 1 can be the response delay of the memory access request of the current processor 20, feature 2 can be the memory access bandwidth of the memory access request of the current processor 20, feature 3 can be the temperature of the current processor 20, and feature 4 can be the available bandwidth of the current memory unit. Further, different thresholds can be preset for different features (the threshold can be obtained by pre-training through a preset algorithm), such as setting threshold 1 for feature 1, and then comparing the response delay of the memory access request of the current processor 20 with threshold 1, and mapping the comparison result through index1 function and weight table 1 (recording the mapping relationship between the comparison result and the weight) to obtain weight 1. Similarly, weight 2 corresponding to feature 2, weight 3 corresponding to feature 3, and weight 4 corresponding to feature 4 can be obtained. Then, the obtained multiple weights are summed to obtain a comprehensive weight (i.e., the current system state score), and the comprehensive weight is compared with the judgment threshold (tact).

[0076] It should be noted that the decision threshold can also be obtained by pre-training through a preset algorithm; the comprehensive weight can be used to indicate the current processor performance and / or the current memory (such as a memory unit) performance. Finally, based on the comparison result, the first service quality is adjusted to obtain the second service quality, such as increasing the first service quality to obtain the second service quality, or not adjusting the first service quality and directly using the first service quality as the second service quality, or lowering the first service quality to obtain the second service quality.

[0077] It should also be noted that if the response delay of the memory access request of the current processor 20 exceeds the first threshold, it can indicate that the current system state is in a congested state and the efficiency is low; if the memory access bandwidth of the memory access request of the current processor 20 exceeds threshold 2, it can also indicate that the current system state is in a congested state and the efficiency is low; if the temperature of the current processor 20 exceeds threshold 3, it can also indicate that the current system state is in a congested state and the efficiency is low; if the available bandwidth of the current memory unit is less than threshold 4, it can also indicate that the current system state is in a congested state and the efficiency is low. Therefore, the current system state score can be obtained through multiple indicator analysis, and the first service quality can be adjusted based on the current system state score to obtain the second service quality, so as to configure the service quality of the memory access request from multiple dimensions, and can more accurately indicate the scheduling priority of the memory access request to ensure the execution performance of key tasks, thereby improving the processor performance.

[0078] For example, the first control unit 202 analyzes the current system information and finds that the current system state is poor (such as being in a congested state), that is, the current system state score is lower than a threshold (the threshold can be the above-mentioned decision threshold), and the first service quality can be increased to obtain the second service quality; if the current system state is normal, that is, the current system state score is equal to the threshold, you can choose not to adjust the first service quality, and directly use the first service as the second service quality.

[0079] In some embodiments, the first control unit 202 may be composed of an artificial intelligence sensor, wherein the artificial intelligence sensor may be composed of a plurality of comparators, a plurality of adders and other devices, and has the advantages of light load and low overhead (power consumption, area).

[0080] In some embodiments, the first control unit 202 may be composed of a logic circuit with fixed conditions.

[0081] The first control unit 202 is further configured to access the memory unit through the second quality of service based on the first memory access request.

[0082] In some embodiments, the first control unit 202 can receive memory access requests initiated by multiple processing sub-units, and each memory access request corresponds to a second quality of service. The first control unit 202 can access the memory unit according to the scheduling priority corresponding to the second quality of service to ensure the execution performance of key tasks, thereby improving processor performance.

[0083] In summary, in this application, not only the service quality of memory access requests is determined based on hardware priority, but the current system status is also obtained by analyzing multiple indicators, and the service quality of memory access requests is adjusted based on the current system status, thereby configuring the service quality of memory access requests from multiple dimensions. It can more accurately indicate the scheduling priority of memory access requests to ensure the execution performance of key tasks, thereby improving processor performance.

[0084] Another processor involved in the embodiment of the present application is introduced below:

[0085] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of another processor provided in an embodiment of the present application. The processor 30 can be used as the central processing unit 1011. Figure 4 The processor 30 in the embodiment may be a multi-core processor. Figure 2Compared with the processor 20 in the embodiment of the present invention, the processor 30 includes more processor cores. Specifically, the processor 30 may include multiple processor cores (such as processor core 301, processor core 302, etc.), and a first control unit 303 newly added in the present application. The internal structures of multiple processor cores are similar. The processor core 301 is used as an example for explanation. The processor core 301 may include a first mapping unit 3016 newly added in the present application (each processor core has a corresponding first mapping unit) and multiple processing sub-units. The multiple processing sub-units may include but are not limited to an instruction scheduling unit 3011, at least one general-purpose operation unit 3012 (such as 3012A, 3012B, 3012C, 3012D), a result write-back unit 3013, an instruction acquisition unit 3014, and one or more of an instruction decoding unit 3015. The structure of the processor core 302 is similar to that of the processor core 301, and will not be repeated.

[0086] It should be noted that the multiple processing sub-units included in the processor core 301 are Figure 2 The structures of the processing sub-units in the processor core 201 are similar and will not be described again here.

[0087] Next, we will combine the above Figure 4 , explains how to determine the service quality of different memory access requests in a multi-core processor scenario to indicate the scheduling priority of different memory access requests.

[0088] When the processor 30 runs an application, since the processor 30 is a multi-core processor, the processor 30 can run multiple threads in parallel, and each thread can run on one processor core.

[0089] The target processing sub-unit among the multiple processing sub-units is used to send a first memory access request to the first mapping unit 3016.

[0090] Specifically, the first memory access request includes software service quality. Software service quality (Software Quality Of Service, SW-QOS) is used to indicate the importance of the memory access request initiated by the thread.

[0091] In some embodiments, N applications are respectively run on N processes, and the multiple threads running in parallel by the processor 30 belong to different processes, that is, different threads correspond to different applications, and N is an integer greater than 1. In this case, since different applications have different requirements for execution performance, the importance of memory access requests initiated by different threads is different. For example, take two applications as examples, namely, a game application and a chat application. Compared with chat, games have higher requirements for real-time performance (that is, higher requirements for execution performance), and it is necessary to ensure that the game interface runs smoothly and does not drop frames as much as possible. Therefore, the software priority of the game application is higher than that of the chat application, that is, the memory access request initiated by the game application is more important than the memory access request initiated by the chat application.

[0092] Optionally, the software priority of each of the multiple applications is pre-set, such as the software priority of the game application is higher than the software priority of the chat application. Furthermore, when the system issues a task, it can map a SW-QOS to the thread according to the software priority of the application. When the thread initiates a memory access request, the request can carry the SW-QOS to indicate the importance of the memory access request initiated by the corresponding thread.

[0093] Optionally, when the system maps SW-QOS to threads based on the software priority of the application, the mapping relationship can be customized according to actual needs. For example, the higher the software priority of the application, the higher the corresponding SW-QOS, which can indicate that the memory access request initiated by the thread is more important; the lower the software priority of the application, the lower the corresponding SW-QOS, which can indicate that the memory access request initiated by the thread is less important. Furthermore, when scheduling memory access requests, memory access requests with higher SW-QOS can be scheduled first to improve the utilization of memory units, reduce access latency, and improve processor performance.

[0094] In some embodiments, an application runs on a process, a process includes multiple threads, and the multiple threads running in parallel by the processor 30 belong to the same process. In this case, since multiple tasks included in an application can run on multiple threads, and the importance of different tasks is different. For example, in a game application, the logic task and the screen rendering task are of higher urgency, and the urgency of other tasks is lower. In general, the software priority of the task with higher urgency (i.e., the main task) is higher than the software priority of the task with lower urgency (sub-task), that is, the memory access request initiated by the main task is more important than the memory access request initiated by the sub-task.

[0095] Optionally, the software priority of each task in multiple tasks is pre-set, such as the software priority of the main task in a game application is higher than the software priority of the secondary task. Furthermore, when the system issues a task, it can map a SW-QOS to the thread according to the software priority of the task. When the thread initiates a memory access request, the request can carry the SW-QOS to indicate the importance of the memory access request initiated by the corresponding thread.

[0096] Optionally, when the system maps SW-QOS to threads based on the software priority of the task, the mapping relationship can be customized according to actual needs. For example, the higher the software priority of the task, the higher the corresponding SW-QOS, which can indicate that the memory access request initiated by the thread is more important; the lower the software priority of the thread, the lower the corresponding SW-QOS, which can indicate that the memory access request initiated by the thread is less important. Furthermore, when processing memory access requests initiated by threads, memory access requests with higher SW-QOS can be given priority to improve the utilization of memory units, reduce access latency, and improve processor performance.

[0097] The first mapping unit 3016 is configured to receive a first memory access request initiated by a target processing subunit, and determine a first quality of service of the first memory access request.

[0098] In some embodiments, the first mapping unit 3016 determines the hardware quality of service (HW-QOS) corresponding to the first memory access request based on the hardware priority of the target processing subunit among the multiple processing subunits, and determines the first quality of service based on the hardware quality of service and software quality of service corresponding to the first memory access request. Optionally, the first mapping unit 3016 maps the HW-QOS to the memory access request based on the hardware priority of the processing subunit, and the mapping relationship can be customized according to actual needs.

[0099] In some embodiments, the first mapping unit stores a first mapping table, which is used to record the mapping relationship between the first service quality and the software service quality and the hardware service quality. The first mapping unit is specifically used to: determine the first service quality from the first mapping table based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread.

[0100] Specifically, the first mapping unit can be composed of registers, and a mapping table can be stored in advance at the first mapping unit, which can record the mapping relationship between the software service quality corresponding to the memory access request and the hardware service quality corresponding to the memory access request and the first service quality, so as to facilitate the comprehensive decision-making of the first service quality of the target memory access request, so that memory access requests with higher hardware service quality and software service quality can be given priority to improve memory utilization, reduce access latency, and enhance processor performance.

[0101] For example, the first mapping unit 3016 may pre-store a Figure 5 The data table shown in the figure records the mapping relationship between the software quality of service and the hardware quality of service and the first quality of service. For example, the software quality of service of a memory access request is 7, and the hardware quality of service is 7. Through the mapping relationship in the data table, it can be determined that the first quality of service is 7. It should be noted that the mapping relationship between the hardware quality of service and the software quality of service and the first quality of service in this application includes but is not limited to Figure 5 The mapping relationship shown.

[0102] The first mapping unit 3016 is further configured to send a first memory access request to the first control unit 303, wherein the first memory access request includes a first quality of service.

[0103] The first control unit 303 is configured to receive the first memory access request sent by the first mapping unit 3016, and adjust the first quality of service based on the current system information to obtain a second quality of service corresponding to the first memory access request in the current state.

[0104] Specifically, the current system information may include but is not limited to the response delay of the memory access request of the current processor 30, the memory access bandwidth of the memory access request of the current processor 30, the temperature of the current processor 30, the available bandwidth of the current memory unit, etc.

[0105] In some embodiments, the first control unit 303 analyzes the current system information, adjusts the first quality of service, and obtains the second quality of service.

[0106] It should be noted that, for a detailed description of how the first control unit 303 analyzes the current system information to obtain the second service quality, please refer to the above description of Figure 3 The relevant description will not be repeated here.

[0107] The first control unit 303 is further configured to access the memory unit through the second quality of service based on the first memory access request.

[0108] In some embodiments, the first control unit 303 can receive memory access requests initiated by multiple processing sub-units in multiple processor cores, and each memory access request corresponds to a second quality of service. The first control unit 303 can access the memory unit according to the scheduling priority corresponding to the second quality of service to ensure the execution performance of key tasks, thereby improving processor performance.

[0109] In summary, in this application, not only the service quality of memory access requests is determined based on hardware priority and software priority, but the current system status is also obtained by analyzing multiple indicators, and the service quality of memory access requests is adjusted based on the current system status, thereby configuring the service quality of memory access requests from multiple dimensions, and being able to more accurately indicate the scheduling priority of memory access requests to ensure the execution performance of key tasks, thereby improving processor performance.

[0110] Please see attached Figure 6 , an embodiment of the present application provides a processor, the processor 40 includes a first control unit 401 and N processor cores, a target processor core 402 among the N processor cores includes a first mapping unit and multiple execution units, N is an integer greater than 0, and the multiple execution units include a target execution unit. The first control unit 401 is used to receive a target memory access request corresponding to the target execution unit sent by the first mapping unit, the target memory access request includes a first quality of service, and the first quality of service is used to indicate the priority of the memory access request corresponding to the target execution unit; adjust the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, and the available bandwidth of the memory; based on the target memory access request, access the memory through the second quality of service.

[0111] It should be noted that the processor 40 may be the above Figure 2 The processor 20 in the embodiment may also be the above Figure 4 The processor 30 in the embodiment; the plurality of execution units may be the above-mentioned processing sub-units; the memory may be the above-mentioned memory unit, and the optional memory may also be an external memory. For the description of the first control unit 401, please refer to the above-mentioned description of the first control unit 202 or the first control unit 303, which will not be repeated here.

[0112] In the present application, a control unit in a processor receives a memory access request sent by a processor core, and the memory access request corresponds to an initial service quality, and the initial service quality is used to indicate the initial scheduling priority of the memory access request. For example, the higher the initial service quality, the higher the scheduling priority of the memory access request, and then the processor can give priority to scheduling memory access requests with high service quality to ensure the execution performance of key tasks. In some embodiments, the control unit accesses the memory based on the initial service quality. In the present application, the control unit can adjust the initial service quality (i.e., the first service quality) of the memory access request based on the current system state to obtain the final service quality (i.e., the second service quality). Then, the control unit accesses the memory based on the final service quality. Accessing the memory with the adjusted service quality, compared with accessing the memory with the initial service quality, the adjusted service quality can more accurately indicate the scheduling priority of the memory access request to ensure the execution performance of key tasks, thereby improving the performance of the processor. In addition, when adjusting the initial service quality, the control unit can be based on multiple information, such as the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, etc., to configure the service quality of the memory access request from multiple dimensions, so that the adjusted service quality can more accurately indicate the scheduling priority of the memory access request.

[0113] See also Figure 7 The embodiment of the present application provides a requested quality of service configuration method, which is applied to a processor, wherein the processor includes a first control unit and N processor cores, wherein a target processor core among the N processor cores includes a first mapping unit and a plurality of execution units, wherein N is an integer greater than 0, and the plurality of execution units includes a target execution unit, and the method includes:

[0114] Step S501: receiving, via a first control unit, a target memory access request corresponding to a target execution unit sent by a first mapping unit.

[0115] Specifically, the target memory access request includes a first quality of service, and the first quality of service is used to indicate the priority of the memory access request corresponding to the target execution unit;

[0116] Step S502: adjusting the first quality of service based on the current system information to obtain a second quality of service corresponding to the target memory access request in the current state.

[0117] Specifically, the current system information includes one or more of a memory access delay of a memory access request of a current processor, a memory access bandwidth of a memory access request of a current processor, a temperature of a current processor, and an available bandwidth of a memory.

[0118] Step S503: Based on the target memory access request, access the memory through the second quality of service.

[0119] In some embodiments, each execution unit in a plurality of execution units corresponds to a hardware service quality, and the method further includes: determining, through a first mapping unit, the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit in the plurality of execution units, and determining the hardware service quality as the first service quality.

[0120] In some embodiments, each of the N processor cores runs a thread, the target processor core runs a target thread, one thread corresponds to a software service quality, the target memory access request includes the software service quality corresponding to the target thread, and the software service quality corresponding to the target thread is used to indicate the priority of the memory access request corresponding to the target thread. The method also includes: determining, through a first mapping unit, the hardware service quality corresponding to the target memory access request based on the hardware priority of the target execution unit among multiple execution units; and determining the first service quality based on the software service quality and hardware service quality corresponding to the target thread.

[0121] In some embodiments, a first quality of service is adjusted based on current system information to obtain a second quality of service corresponding to a target memory access request in a current state, including: obtaining current system information through a first control unit, and analyzing and processing the current system information based on a preset algorithm to determine a current system state score, wherein the current system state score is used to indicate current processor performance and / or current memory performance; based on the current system state score, adjusting the first quality of service to obtain a second quality of service.

[0122] In some embodiments, the first mapping unit stores a first mapping table, which is used to record the mapping relationship between the first service quality and the software service quality and the hardware service quality, and determines the first service quality based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread, including: determining the first service quality from the first mapping table based on the software service quality corresponding to the target thread and the hardware service quality corresponding to the target thread through the first mapping unit.

[0123] In some embodiments, based on the current system status score, the first service quality is adjusted to obtain the second service quality, including: if the current system status score is greater than a threshold, the first service quality is determined as the second service quality by the first control unit; if the current system status score is less than or equal to the threshold, the first service quality is increased by the first control unit to obtain the second service quality.

[0124] In the present application, compared with accessing the memory with the initial quality of service, the adjusted quality of service can more accurately indicate the scheduling priority of the memory access request when accessing the memory with the adjusted quality of service, so as to ensure the execution performance of key tasks, thereby improving the processor performance. In addition, when the control unit adjusts the initial quality of service, the control unit can be based on various information, such as the memory access delay of the memory access request of the current processor, the memory access bandwidth of the memory access request of the current processor, the temperature of the current processor, etc., to configure the quality of service of the memory access request from multiple dimensions, so that the adjusted quality of service can more accurately indicate the scheduling priority of the memory access request.

[0125] The present application provides a chip system, wherein the system on chip includes a processor and a memory, and a controller, wherein the processor includes a first control unit and N processor cores, wherein a target processor core among the N processor cores includes a first mapping unit and multiple execution units, wherein N is an integer greater than 0, and wherein the multiple execution units include a target execution unit, wherein the first control unit of the processor is used to: receive a target memory access request corresponding to the target execution unit sent by the first mapping unit, wherein the target memory access request includes a first quality of service, and the first quality of service is used to indicate the priority of the memory access request initiated by the target execution unit; adjust the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a temperature of the current processor, and an available bandwidth of the memory; send the target memory access request to the controller based on the second quality of service; and the controller is used to: receive and respond to the target memory access request, and access the memory according to the second quality of service.

[0126] The present application provides a computer storage medium, characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, the service quality configuration method of any one of the above requests is implemented.

[0127] An embodiment of the present application provides an electronic device, the electronic device includes a processor, the processor is configured to support the electronic device to implement the corresponding function in any one of the above-mentioned service quality configuration methods. The electronic device may also include a memory, the memory is used to couple with the processor, and the memory stores the necessary program instructions and data of the electronic device. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

[0128] The present application provides a chip system, which includes a processor for supporting an electronic device to implement the functions involved above, for example, generating or processing information involved in the service quality configuration method of the above request. In a possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the electronic device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0129] The present application provides a computer program product, characterized in that the computer program includes instructions, and when the computer program is executed by a computer, the computer executes the above-mentioned service quality configuration method.

[0130] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0131] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0132] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0133] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0135] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0136] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processor, characterized in that: The processor includes a first control unit and N processor cores, a target processor core among the N processor cores includes a first mapping unit and a plurality of execution units, N is an integer greater than 0, and the plurality of execution units includes a target execution unit, wherein: The first control unit is used to: receiving a target memory access request corresponding to the target execution unit sent by the first mapping unit, wherein the target memory access request includes a first quality of service, and the first quality of service is used to indicate a priority of the memory access request corresponding to the target execution unit; adjusting the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a current temperature of the processor, and an available bandwidth of the memory; Based on the target memory access request, the memory is accessed through the second quality of service.

2. The processor according to claim 1, characterized in that Each of the plurality of execution units corresponds to a hardware quality of service, and the first mapping unit is configured to: Based on the hardware priority of the target execution unit among the multiple execution units, a hardware quality of service corresponding to the target memory access request is determined, and the hardware quality of service corresponding to the target memory access request is determined as the first quality of service.

3. The processor according to claim 1, wherein: Each of the N processor cores runs a thread, the target processor core runs a target thread, one thread corresponds to one software service quality, the target memory access request includes the software service quality corresponding to the target thread, and the software service quality corresponding to the target thread is used to indicate the priority of the memory access request corresponding to the target thread, and the first mapping unit is used to: Determining a hardware quality of service corresponding to the target memory access request based on a hardware priority of the target execution unit among the multiple execution units; The first quality of service is determined based on the software quality of service corresponding to the target thread and the hardware quality of service corresponding to the target memory access request.

4. The processor according to claim 3, characterized in that The first mapping unit stores a first mapping table, the first mapping table is used to record the mapping relationship between the first quality of service and the software quality of service and the hardware quality of service, and the first mapping unit is specifically used to: The first quality of service is determined from the first mapping table based on the software quality of service corresponding to the target thread and the hardware quality of service corresponding to the target thread.

5. The processor according to any one of claims 1 to 4, characterized in that: The first control unit is specifically used for: Acquire the current system information, and analyze and process the current system information based on a preset algorithm to determine a current system status score, where the current system status score is used to indicate the current processor performance and / or the current memory performance; Based on the current system status score, the first quality of service is adjusted to obtain the second quality of service.

6. The processor according to claim 5, characterized in that The first control unit is specifically used for: When the current system status score is greater than a threshold, determining the first quality of service as the second quality of service; When the current system status score is less than or equal to the threshold, the first service quality is increased to obtain the second service quality.

7. A method for configuring quality of service of a request, characterized in that: Applied to a processor, the processor includes a first control unit and N processor cores, a target processor core among the N processor cores includes a first mapping unit and a plurality of execution units, N is an integer greater than 0, the plurality of execution units include a target execution unit, the method includes: Receiving, by the first control unit, a target memory access request corresponding to the target execution unit sent by the first mapping unit, wherein the target memory access request includes a first quality of service, and the first quality of service is used to indicate a priority of the memory access request corresponding to the target execution unit; adjusting the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a current temperature of the processor, and an available bandwidth of the memory; Based on the target memory access request, the memory is accessed through the second quality of service.

8. The method according to claim 7, characterized in that Each of the plurality of execution units corresponds to a hardware quality of service, and the method further comprises: The hardware quality of service corresponding to the target memory access request is determined based on the hardware priority of the target execution unit among the multiple execution units through the first mapping unit, and the hardware quality of service corresponding to the target memory access request is determined as the first quality of service.

9. The method according to claim 7, characterized in that: Each of the N processor cores runs a thread, the target processor core runs a target thread, one thread corresponds to one software service quality, the target memory access request includes the software service quality corresponding to the target thread, and the software service quality corresponding to the target thread is used to indicate the priority of the memory access request corresponding to the target thread, and the method further includes: Determining, by the first mapping unit, a hardware quality of service corresponding to the target memory access request based on the hardware priority of the target execution unit among the multiple execution units; The first quality of service is determined based on the software quality of service corresponding to the target thread and the hardware quality of service corresponding to the target memory access request.

10. The method according to claim 9, characterized in that The first mapping unit stores a first mapping table, the first mapping table is used to record a mapping relationship between the first quality of service and the software quality of service and the hardware quality of service, and the determining the first quality of service based on the software quality of service corresponding to the target thread and the hardware quality of service corresponding to the target thread includes: The first quality of service is determined from the first mapping table by the first mapping unit based on the software quality of service corresponding to the target thread and the hardware quality of service corresponding to the target thread.

11. The method according to any one of claims 7 to 10, characterized in that: The adjusting the first quality of service based on the current system information to obtain the second quality of service corresponding to the target memory access request in the current state includes: Acquire the current system information through the first control unit, and analyze and process the current system information based on a preset algorithm to determine a current system status score, where the current system status score is used to indicate the current processor performance and / or the current memory performance; Based on the current system status score, the first quality of service is adjusted to obtain the second quality of service.

12. The method according to claim 11, characterized in that The adjusting the first quality of service to obtain the second quality of service based on the current system status score includes: When the current system status score is greater than a threshold, determining the first quality of service as the second quality of service by the first control unit; When the current system status score is less than or equal to the threshold, the first control unit increases the first service quality to obtain the second service quality.

13. A chip system, characterized in that: The system on chip includes a processor and a memory, a controller, the processor includes a first control unit and N processor cores, a target processor core among the N processor cores includes a first mapping unit and a plurality of execution units, N is an integer greater than 0, and the plurality of execution units includes a target execution unit, wherein, The first control unit of the processor is configured to: receiving a target memory access request corresponding to the target execution unit sent by the first mapping unit, wherein the target memory access request includes a first quality of service, and the first quality of service is used to indicate a priority of the memory access request initiated by the target execution unit; adjusting the first quality of service based on current system information to obtain a second quality of service corresponding to the target memory access request in the current state; the current system information includes one or more of a memory access delay of the memory access request of the current processor, a memory access bandwidth of the memory access request of the current processor, a current temperature of the processor, and an available bandwidth of the memory; sending the target memory access request to the controller based on the second quality of service; The controller is used to: The target memory access request is received and responded to, and the memory is accessed according to the second quality of service.

14. A computer storage medium, characterized in that: The computer storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 7 to 12.

15. A computer program product, characterized in that The computer program comprises instructions, and when the computer program is executed by a computer or a processor, the computer or the processor executes the method according to any one of claims 7 to 12.

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