Constant current driving method, constant current driving chip and LED display screen of LED display screen

Abstract

Embodiments of the present application disclose a constant current driving method, a constant current driving chip and an LED display screen. The constant current driving method comprises: sequentially receiving a plurality of groups of external input grayscale clock signals, each group of grayscale clock signals being composed of a plurality of grayscale clocks and a plurality of read data clocks; when a grayscale clock is currently received, outputting a corresponding constant current driving signal to a current target row of LED lamp beads based on first display data corresponding to a read data clock in a previous group of grayscale clock signals, so as to drive the LED lamp beads to display; when a read data clock is currently received, stopping outputting the constant current driving signal, and reading second display data, the second display data being used in the next scanning; in the process of receiving a plurality of continuous read data clocks, receiving a row switching signal, and determining a target row driven by a constant current driving signal corresponding to a next group of grayscale clock signals according to the row switching signal. The above method can solve the technical problem of limited brightness efficiency in driving the LED display in the related art.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of LED display screens, and in particular to a constant current driving method for an LED display screen, a constant current driving chip and an LED display screen. BACKGROUND

[0002] A light-emitting diode (LED) is a commonly used light-emitting device that can efficiently convert electrical energy into light energy, and is therefore widely used in display, lighting and other fields. In the display field, small-pitch LED display screens composed of LEDs are widely used in high-definition display scenarios.

[0003] In a small-pitch LED display screen, a constant current driving chip is usually used to accurately control the light-emitting diodes point by point. When controlling, one scan of the constant current driving chip can include three processes: 1. outputting a constant current driving signal for driving the LEDs in the corresponding row to display; 2. reading display data corresponding to the next scan output constant current driving signal; 3. line switching and blanking. After the three processes are executed in sequence, one scan of the constant current driving chip can be achieved.

[0004] In one scan process, the LED emits light in the on-time, and the brightness of the LED emission will be different when the on-time is different, that is, the brightness of the LED is related to the specific value of the on-time. In some technologies, the maximum value of the on-time of the LED in one scan can be understood as the brightness efficiency when driving the LED display, which is the ratio of the maximum value of the on-time of the LED in one scan to the total time required for one scan. However, the on-time of the LED is related to the constant current driving signal, that is, the maximum value of the on-time of the LED is related to the duration of the first process of outputting the constant current driving signal, and the ratio of the duration of the first process to the total time required for one scan is limited, which limits the brightness efficiency, that is, the display brightness of the LED when driving the LED display is limited. SUMMARY

[0005] An embodiment of the present application provides a constant current driving method for an LED display screen, a constant current driving chip and an LED display screen to solve the technical problem of limited brightness efficiency when driving the LED display in related technologies.

[0006] In a first aspect, an embodiment of the present application provides a constant current driving method for an LED display screen, comprising:

[0007] receiving a plurality of groups of external input grayscale clock signals in sequence, each group of grayscale clock signals being composed of a plurality of consecutive grayscale clocks and a plurality of consecutive read data clocks, and the grayscale clock in a group of grayscale clock signals being received before the read data clock;

[0008] In a case that the current received gray scale clock signal is a read data clock, the constant current driving signal is stopped from being outputted, and second display data is read, the constant current driving signal corresponding to the second display data being used for outputting in a gray scale clock in a next group of gray scale clock signals;

[0009] In a case that the current received gray scale clock signal is a read data clock, the constant current driving signal is stopped from being outputted, and second display data is read, the constant current driving signal corresponding to the second display data being used for outputting in a gray scale clock in a next group of gray scale clock signals;

[0010] In a process of receiving continuous multiple read data clocks, a row switching signal is received, and a target row corresponding to a constant current driving signal driven by a gray scale clock in a next group of gray scale clock signals is determined according to the row switching signal.

[0011] In a process of receiving continuous multiple read data clocks, a row switching signal is received, and a target row corresponding to a constant current driving signal driven by a gray scale clock in a next group of gray scale clock signals is determined according to the row switching signal.

[0012] In a process of receiving continuous multiple read data clocks, a row switching signal is received, and a target row corresponding to a constant current driving signal driven by a gray scale clock in a next group of gray scale clock signals is determined according to the row switching signal.

[0013] The logic chip is configured to sequentially send multiple groups of gray scale clock signals to the constant current driving chip, each group of the gray scale clock signals being composed of continuous multiple gray scale clocks and continuous multiple read data clocks, the gray scale clock in the group of the gray scale clock signals being sent before the read data clock, and the logic chip is further configured to send a switching clock signal to the row driving chip, the gray scale clock signal sent by the logic chip at a corresponding sending time of the switching clock signal being a read data clock.

[0014] The row driving chip is configured to send a row switching signal to the constant current driving chip according to the switching clock signal, each switching clock signal corresponding to one row switching signal.

[0015] The constant current driving chip is used for sequentially receiving a plurality of groups of grayscale clock signals inputted externally, in a case that the currently received grayscale clock signal is a grayscale clock, outputting a corresponding constant current driving signal to the LED lamp bead of the current target row based on the first display data corresponding to the reading data clock in the previous group of grayscale clock signals, so as to drive the LED lamp bead of the current target row to display, in a case that the currently received grayscale clock signal is a reading data clock, stopping outputting the constant current driving signal, and reading second display data, the constant current driving signal corresponding to the second display data being used for outputting in the grayscale clock in the next group of grayscale clock signals, in a process of receiving a plurality of continuous reading data clocks, receiving the row switching signal, and determining the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals according to the row switching signal.

[0016] In an embodiment of the present application, by sequentially receiving a plurality of groups of grayscale clock signals inputted externally, and in a case that the currently received grayscale clock signal is a grayscale clock, outputting a constant current driving signal to the LED lamp bead of the target row based on the first display data corresponding to the reading data clock in the previous group of grayscale clock signals, so as to drive the LED lamp bead to emit light, in a case that the currently received grayscale clock signal is a reading data clock, stopping outputting the constant current driving signal, and reading second display data, the second display data being used for the scanning process corresponding to the next group of grayscale clock signals, and in the process of receiving the reading data clock, the row switching signal is also received, the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals is determined according to the row switching signal, so as to output the corresponding constant current driving signal to the LED lamp bead of the target row when scanning based on the next group of grayscale clock signals, the technical means solves the technical problem that the brightness efficiency is limited when driving the LED display in the related art, by receiving the row switching signal in the process of receiving the reading data clock, the display data reading, line switching and blanking can be processed in parallel, so as to shorten the idle time period in one scanning, and then shorten the total time required for one scanning. When the total time required for one scanning is shortened, the proportion of the duration of the grayscale clock in the total time will increase, accordingly, the proportion of the conduction time of the LED when the LED is driven to emit light by the constant current driving signal under the grayscale clock in the total time will also increase, at this time, when the conduction time takes the maximum value, the proportion of the maximum value in the total time will also increase, that is, the brightness efficiency of the LED display is improved. In the process of receiving the reading data clock, the row switching signal is also received, which can also ensure the integrity of the LED lamp bead display in this scanning as much as possible. Moreover, by dividing the grayscale clock signal into the grayscale clock and the reading data clock, the constant current driving chip can more accurately perform the actions of outputting the constant current driving signal and reading the display data. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1A connection diagram of an LED in the related art;

[0018] Figure 2 A row scanning time composition diagram provided in the related art;

[0019] Figure 3 A signal transmission path diagram of a small-pitch LED display screen in an embodiment of the present application;

[0020] Figure 4 A structure diagram of a constant-current driving chip in an embodiment of the present application;

[0021] Figure 5 A flowchart of a constant-current driving method of an LED display screen in an embodiment of the present application;

[0022] Figure 6 A first diagram of a gray-scale clock signal in an embodiment of the present application;

[0023] Figure 7 A second diagram of a gray-scale clock signal in an embodiment of the present application;

[0024] Figure 8 A flowchart of another constant-current driving method of an LED display screen in an embodiment of the present application;

[0025] Figure 9 A third diagram of a gray-scale clock signal in an embodiment of the present application;

[0026] Figure 10 A first signal group diagram in an embodiment of the present application;

[0027] Figure 11 A fourth diagram of a gray-scale clock signal in an embodiment of the present application;

[0028] Figure 12 A first diagram of clock driving counting of a row switching signal in an embodiment of the present application;

[0029] Figure 13 A second diagram of clock driving counting of a row switching signal in an embodiment of the present application;

[0030] Figure 14 A structure diagram of an LED display screen in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The application will be further described below in detail with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are used to explain the application, but not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings, not all the structures.

[0032] The small-pitch LED display screen can be understood as an LED display screen with a small pitch (e.g., less than 2.5 mm). Currently, the LEDs in the small-pitch LED display screen are referred to as LED lamp beads. The red, green, and blue (optical primary colors) light-emitting diodes of each LED lamp bead are packaged on a lamp holder. The optical primary colors of the three types of light-emitting diodes are mixed to form each color that the LED lamp bead can display. At this time, one LED lamp bead can be considered as one pixel of the small-pitch LED display screen.

[0033] The LED lamp bead is driven and displayed by a driving chip. Generally, the driving chip at least includes a row driving chip and a constant current driving chip. For example, Figure 1 A schematic diagram of the connection of an LED in the related art. Figure 1 Taking one LED lamp bead as an example, and the LED lamp bead is represented by a light-emitting diode VD1. The LED lamp bead is driven and displayed by a driving chip. Generally, the driving chip at least includes a row driving chip and a constant current driving chip. For example, Figure 1 It can be known that the LED lamp bead is controlled by the row driving chip 10 and the constant current driving chip 11. The row driving chip is used to realize row gating, which can be understood as controlling the opening of the row channel of the LED lamp bead (i.e., controlling the opening of the row channel of one row of LED lamp beads) to achieve the function of selecting the display row in each row of LED lamp beads. The constant current driving chip is used to realize column gating, which can be understood as generating a constant current driving signal according to the corresponding display data and outputting the constant current driving signal to the LED lamp bead of the corresponding column. Among the LED lamp beads of the corresponding column, the LED lamp bead with the opened row channel can emit light based on the constant current driving signal. Therefore, based on the constant current driving signal, the opening (i.e., the light emission) and the closing of the LED lamp bead can be realized. When the LED emits light, the corresponding display data is displayed. At this time, based on the row driving chip, the LED lamp bead can be turned on row by row. Based on the constant current driving chip, the LED lamp bead of the corresponding column in the on row can be turned on to realize the light emission of the LED lamp bead row by row, i.e., the point-to-point accurate control of the LED lamp bead. The process of turning on the LED lamp bead of the corresponding row or multiple rows based on the indication of the row driving chip by the constant current driving chip can also be considered as one row scanning. Generally, one row scanning can be 1 / 2 scanning, 1 / 4 scanning, 1 / 8 scanning, or 1 / 16 scanning (also referred to as 2 scanning, 4 scanning, 8 scanning, and 16 scanning), etc. The scanning modes are technical means that have been realized, and are not described herein.

[0034] By quickly switching the light-emitting LED lamp beads (the human eye cannot distinguish the scanning process), the viewing effect of all LED lamp beads of the small-pitch LED display screen emitting light can be achieved, and the display of the small-pitch LED display screen can be realized.

[0035] It can be understood that, since the number of LED lamp beads of the small-pitch LED display screen is large, a plurality of constant current driving chips can be arranged, and each constant current driving chip controls different parts of the LED lamp beads. Similarly, a plurality of row driving chips can also be arranged, and the plurality of row driving chips and the plurality of constant current driving chips cooperate to realize point-to-point accurate control of each LED lamp bead.

[0036] The constant current driving signal output by the constant current driving chip is usually a pulse width modulation (PWM) signal, which can also be referred to as a PWM wave. The PWM signal can control the on / off time of the LED lamp bead. Specifically, when the PWM signal is high, the LED lamp bead is turned on, at which time the LED lamp bead is turned on (i.e., emits light). When the PWM wave is low, the LED lamp bead is turned off (i.e., does not emit light). By using the short-term visual persistence effect, the duration of the high level can be adjusted to adjust the on duration of the LED lamp bead, thereby adjusting the brightness of the LED lamp bead. Generally speaking, the longer the duration of the high level, the brighter the actual display brightness of the LED lamp bead. It can be understood that the ratio of the high level time to the PWM signal period in the PWM signal is called the duty cycle. Based on the foregoing description, it can be known that the duty cycle determines the brightness of the LED lamp bead.

[0037] Generally speaking, the brightness of the LED lamp bead can be represented by the gray scale, that is, the degree of brightness of the LED lamp bead is the gray scale of the LED display screen. At this time, when the constant current driving chip realizes column strobe, it can be considered as controlling the on duty cycle (i.e., the duty cycle of the PWM signal) of all channels during row strobe, which determines the gray scale of the LED lamp bead.

[0038] The constant current driving chip used in the small-pitch LED display screen has the functions of outputting a constant current driving signal, self-decoding, and data buffering, so that when the data processing amount of the constant current driving chip is large, the display data can still be transmitted in advance in a serial manner and the display process can be controlled in time division.

[0039] The self-decoding function can be understood as decoding the received display data to determine the on duty cycle in the constant current driving signal when driving the LED lamp bead to display the display data. The data buffering function refers to buffering the data in the constant current driving chip, such as buffering the display data required by the LED lamp bead for display, so as to output the corresponding constant current driving signal by the constant current driving chip.

[0040] Generally, a constant current driving chip is driven by a gray scale clock (GCLK) signal to control the display of an LED lamp bead. In one implementation, the constant current driving chip continuously receives multiple sets of gray scale clock signals during its operation, and each set of gray scale clock signals includes multiple gray scale clock signals. One set of gray scale clock signals corresponds to one row of scanning. Based on the control of the received gray scale clock signals, the constant current driving chip acquires display data and outputs a constant current driving signal corresponding to the display data. In addition, at the end of one row of scanning, line switching and blanking need to be performed. The line switching refers to determining the number of the row in which the LED lamp bead is located in the next row of scanning, which can generally be informed to the constant current driving chip by a row driving chip. The blanking can be simply understood as moving from the scanning end point in scanning one row to the scanning start point in scanning the next row, and the scanning end point and the scanning start point both refer to the LED lamp bead at the corresponding position. The line switching and the blanking also need time. At this time, each set of gray scale clock signals is followed by a period of spare time, which is used to implement the line switching and the blanking. By setting the period of spare time, the time required for the line switching can be hidden, thereby avoiding the misaligned display during scanning. In addition, the period of spare time can also provide a waiting time for the constant current driving chip to read and decode the display data of the next scan (i.e., the next row of scanning), so that the constant current driving signal corresponding to the read display data can be decoded and output in the next scan. At this time, the time required for scanning one row includes the duration of one set of gray scale clock signals and the period of spare time.

[0041] For example, Figure 2 A schematic diagram of the composition of a row scanning time in the related art is provided, in which the first row of data is the waveform of the gray scale clock signal, Figure 2 Three sets of gray scale clock signals are exemplarily shown in the table, in which the numbers above each gray scale clock signal represent the number of the gray scale clock signal in the group. The second row of data represents the number of the row scanned by each set of gray scale clock signals, and the time length thereof can be understood as the time length required for scanning one row. The third row of data represents the time interval corresponding to the period of spare time for line switching and blanking, Figure 2 which is recorded as the row blanking interval in the table. Based on Figure 2 It can be known that there is a period of spare time between adjacent sets of gray scale clock signals, and the period of spare time is the row blanking interval. That is, the time length required for scanning one row is composed of the duration of one set of gray scale clock signals and the period of spare time, and there is a period of spare time before and after one set of gray scale clock signals.

[0042] It can be understood that the LED lamp bead emits light based on the constant current driving signal. That is, Figure 2In the length of time required for scanning a row, the LED lamp bead only emits light in the high level time of the constant current driving signal, and does not emit light in the remaining time. However, the high level duration of the constant current driving signal (which can also be understood as the LED lamp bead conduction time) is limited, and the length of time required for scanning a row is also limited (the display row needs to be switched quickly), so the proportion of the LED lamp bead conduction time in the length of time required for scanning a row is also limited. Ideally (i.e. without considering the blanking period of the line feed), the duty cycle of the constant current driving signal driving the LED lamp bead to display the maximum gray scale level (i.e. the highest brightness) is the largest, and the LED lamp bead conduction time is the longest. At this time, the proportion of the LED lamp bead conduction time in the duration of a group of gray scale clock signals can be understood as the brightness efficiency, which is generally between 50% and 70%, i.e. the brightness efficiency is limited.

[0043] At this time, based on the limitation of the brightness efficiency, the maximum brightness that the LED lamp bead can reach when driving the LED lamp bead to emit light is limited. In the related art, if a higher brightness is required, the current of the constant current driving signal needs to be increased. However, when the current of the constant current driving signal is increased, the power supply of the LED display screen needs to output a higher instantaneous output power, thereby increasing the heat dissipation and power consumption of the LED display screen, and the ripple fluctuation of the power supply is larger, so that the stability of the LED display screen during display is lower. The display device (i.e. the LED lamp bead) is subjected to the large-current constant current driving signal, which causes wear. If the LED lamp bead is subjected to a large current for a long time, the wear and aging of the LED lamp bead will be serious, and the service life of the LED lamp bead will be reduced. In addition, the constant current driving chip also has a maximum current limit when outputting the constant current driving signal, and cannot meet the needs of all high-brightness displays.

[0044] Therefore, in the embodiments of the present application, a constant current driving method, a constant current driving chip and an LED display screen are provided to solve the technical problem of limited display brightness of the LED in the related art when driving the LED display, and the brightness of the LED lamp bead when the constant current driving signal drives the LED lamp bead to emit light is improved by improving the brightness efficiency, and the disadvantages caused by increasing the current of the constant current driving signal to improve the brightness of the LED lamp bead in the related art are avoided.

[0045] An embodiment of the present application provides a constant current driving method of an LED display screen, which can be executed by a constant current driving device of the LED display screen. The constant current driving device can be implemented in software and / or hardware. The constant current driving device can be composed of two or more physical entities, or can be composed of one physical entity. The constant current driving device has a data processing function. In an embodiment, the constant current driving device is taken as a constant current driving chip in the LED display screen, and the LED display screen is a small-pitch LED display screen.

[0046] The small-pitch LED display screen can be provided with one or more constant current driving chips. When a plurality of constant current driving chips are provided, the plurality of constant current driving chips all perform the constant current driving method. Therefore, in the embodiments, one constant current driving chip is taken as an example for description.

[0047] In order to facilitate understanding of the constant current driving method, the working process of the constant current driving chip is exemplarily described in the embodiments. Figure 3 A signal transmission path schematic diagram of the small-pitch LED display screen in display is provided for one embodiment of the present application. Referring to Figure 3 The small-pitch LED display screen includes a plurality of constant current driving chips 20. Each constant current driving chip 20 can drive part of LED lamp beads to emit light, and the LED lamp beads form all LED lamp beads of the small-pitch LED display screen.

[0048] It can be understood that the small-pitch LED display screen can be composed of a receiving part and a display part. The display part can also be referred to as an LED lamp panel. The LED lamp panel is provided with LED lamp beads, row driving chips for driving the LED lamp beads to conduct, constant current driving chips for driving the LED lamp beads to emit light, and the like.

[0049] The small-pitch LED display screen further includes an FPGA 30. The FPGA is installed in the receiving part. The receiving part refers to a receiving card, which can also be referred to as a receiving card, a board card, or a control board, and the like. The receiving card is provided with a plurality of chips. After cooperation of the chips, various functions of the small-pitch LED display screen can be realized. At present, the receiving card is provided with at least a logic chip, and the logic chip is taken as an example of a field programmable gate array (FPGA) (i.e. Figure 3 The FPGA 30 shown in the figure is only an exemplary description), and in actual application, the logic chip can also adopt other chips with data processing functions. The FPGA can receive display data sent by an external device, determine RGB values and other parameters of each LED lamp bead based on the display data, and control the LED lamp bead to display based on the RGB values and other parameters.

[0050] The small-pitch LED display screen further includes a buffer driver 40, which can also be understood as a data transceiver memory. The buffer driver 40 can be installed in the receiving part, and is used for enhancing (such as shaping) and distributing (i.e. multiplexing) the output signals.

[0051] In one embodiment, when the FPGA controls the LED lamp bead to display, at least display data, data clock signals, grayscale clock signals, and latch signals are sent to the constant current driving chip 20. The display data (referred to as DATA in the figure) is the RGB values and other parameters obtained after processing by the FPGA. The data clock signals (referred to as CLK in the figure) are used for indicating the display data. The grayscale clock signals (referred to as GRAY in the figure) are used for indicating the grayscale of the display data. The latch signals (referred to as LATCH in the figure) are used for indicating the display data. Figure 3 ​Figure 3 The latch signal (denoted as DCLK) is the clock cycle used to enable the constant current driver chip to receive display data. Figure 3 The signal denoted as LAT is the enable signal used to latch the display data received by the constant current drive chip. The function of the grayscale clock signal (GCLK) can be found in the relevant description above.

[0052] based on Figure 3 It can be seen that DATA, DCLK, LAT, and GCLK output by FPGA30 are first input to buffer driver 40. Then, buffer driver 40 shapes DATA, DCLK, LAT, and GCLK and sends them to each constant current driver chip 20 in a parallel manner. Figure 3 In this configuration, constant current driver chips located in the same row can simultaneously receive the same DCLK, LAT, and GCLK. Furthermore, constant current driver chips 20 located in the same row serially transmit corresponding DATA, while the buffer driver 40 only sends DATA to one constant current driver chip 20 in each row.

[0053] It should be noted that Figure 3 The relative positions of the constant current driver chips in the diagram are not the same as their actual relative positions during installation. Figure 3 The relative positions shown are merely illustrative representations for the purpose of understanding the signal transmission path.

[0054] The constant current driver chip operates based on the received DATA, DCLK, LAT, and GCLK. Figure 4 This is a schematic diagram of a constant current driving chip provided in one embodiment of this application. (Reference) Figure 4 The constant current drive chip 20 includes a FIFO 21, a control logic unit 22, a static random-access memory (SRAM) 23, a configurable register 24, a constant current source algorithm circuit 25, a current generator 26, and a constant current source channel 27.

[0055] Among them, FIFO (First Input First Output) 21, which can also be referred to as FIFO memory, adopts a first-in, first-out (FIFO) method. FIFO 21 has a serial data input terminal (i.e., SDI terminal) and a serial data output terminal (i.e., SDO terminal). At this time, the DATA transmitted serially is stored in the FIFO through the serial data input terminal for use by the constant current driver chip. The DATA in the FIFO is also transmitted to the next constant current driver chip connected in the same row through the serial data output terminal.

[0056] The control logic unit 22 can control the constant current driving chip. The control logic unit has a data clock signal (i.e., DCLK) input end, receives DCLK through the data clock signal input end, and then, based on the driving of DCLK, stores the display data into the FIFO. The control logic unit also has a latch signal input end (i.e., LE end), receives LAT through the LE end, and then, based on LAT, determines to latch the DATA stored in the FIFO.

[0057] The SRAM 23 is used to latch the DATA. When the control logic unit determines to latch the DATA based on LAT, the control logic unit controls the SRAM to obtain the DATA from the FIFO and latch the DATA.

[0058] The configurable register 24 is used to temporarily store the instructions generated by the control logic unit 22. For example, the configurable register 24 stores the instructions generated by the control logic unit 22 for indicating the implementation of a certain function during the working process of the constant current source algorithm circuit 25, and then sends the instructions to the constant current source algorithm circuit 25. For another example, the configurable register 24 stores the instructions generated by the control logic unit 22 for indicating the implementation of a certain function during the working process of the current generator 26, and then sends the instructions to the current generator 26.

[0059] The constant current source algorithm circuit 25 can read the display data and decode, and generate the corresponding constant current driving signal. The constant current source algorithm circuit 25 has a grayscale clock signal (i.e., GCLK) input end. GCLK is received through the grayscale clock signal input end. After the data of the constant current driving chip is updated (such as receiving a new row of display data), the constant current algorithm circuit can read the latched DATA from the SRAM based on the driving of GCLK, and then, based on the latched DATA, decode to obtain the on-time proportion of the LED lamp bead and output the corresponding constant current driving signal. In the embodiment, the constant current driving method of the LED display screen is mainly understood as being executed by the constant current source algorithm circuit 25 when the constant current driving chip executes the constant current driving method.

[0060] The current generator 26 is used to generate a current signal, which is modulated based on the constant current driving signal output by the constant current source algorithm circuit 25, to output the corresponding electrical signal of the constant current driving signal to the outside. The current generator 26 has an external resistance input end (REXT), and the resistance connected to the external resistance input end (located outside the current generator 26) can set the size of the current generated by the current generator 26.

[0061] The constant current source channel 27 is a channel that outputs the constant current driving signal. The constant current source channel 27 receives the constant current driving signal output by the constant current source algorithm circuit 25 and the current signal generated by the current generator 26, and then, based on the constant current driving signal, modulates the current signal to output the corresponding electrical signal of the constant current driving signal to the outside. It can be understood thatFigure 4 Taking the 16-channel constant current source channel 27 as an example, the 16-channel constant current source channel corresponds to the output terminals 0-15 (i.e., OUT0-15) respectively. The 16-channel constant current source channel can light up 16 LED lamp beads at the same time.

[0062] It should be noted that Figure 4 The hardware structure of each circuit, element and unit inside the constant current drive chip is not limited at present. In addition to the structure shown in the figure Figure 4 The constant current drive chip can also contain other circuits, elements and units, which are not limited at present.

[0063] It can be understood that the FPGA can also control the row drive chip to determine the number of rows of LED lamp beads that need to be turned on at present, and generate a row switching signal based on the number of rows and send it to the constant current drive chip, so that the constant current drive chip determines the number of rows of LED lamp beads that are turned on.

[0064] When the constant current drive chip is working, the constant current drive method of the LED display screen can be executed. Figure 5 A flowchart of a constant current drive method of an LED display screen provided by an embodiment of the present application is shown in the figure. Figure 5 The constant current drive method includes steps 110-140:

[0065] Step 110, sequentially receive a plurality of groups of externally input gray scale clock signals, each group of gray scale clock signals is composed of a plurality of continuous gray scale clocks and a plurality of continuous read data clocks, and the gray scale clock in a group of gray scale clock signals is received before the read data clock.

[0066] For example, the constant current drive chip needs to receive a group of gray scale clock signals every time it scans a row, that is, a group of gray scale clock signals is used to drive the constant current display chip to scan a row. By sequentially receiving a plurality of groups of gray scale clock signals, a plurality of row scans are realized.

[0067] In an embodiment, the gray scale clock signal includes two types of gray scale clock (which can be denoted as gray_clk) and read data clock (which can be denoted as data_clk), wherein the gray scale clock corresponds to the actual working time of the constant current source algorithm circuit, that is, the working time of decoding and outputting the constant current drive signal (i.e., the PWM signal), and the read data clock corresponds to the working time of reading the latched display data (DATA) from the SRAM. Wherein, decoding can be understood as the process of determining the proportion of LED lamp beads that need to be turned on when LED lamp beads display the display data, and the corresponding constant current drive signal can be obtained based on the proportion of LED lamp beads that need to be turned on. Decoding and outputting can be performed synchronously.

[0068] The group of gray scale clock signals can be combined by a plurality of continuous gray scale clocks and a plurality of continuous read data clocks, and the number of gray scale clocks and the number of read data clocks can be set according to actual needs. For a group of gray scale clocks, the gray scale clock is received before the read data clock.

[0069] In an embodiment, the plurality of continuous read data clocks is composed of an even number of read clocks and one operation clock. That is, the read data clock includes two types of read clock and operation clock, wherein the read clock corresponds to the working time of reading the latched display data from the SRAM, and the operation clock corresponds to the working time of transmitting the display data. Generally, the number of read clocks is even, and the number of operation clocks is one. That is, when receiving a plurality of continuous read data clocks, an even number of read clocks is received first, and then one operation clock is received. Optionally, the number of read clocks is related to the number of constant current driving signals output by the constant current driving chip during one scan, and can reflect the depth of reading the internal cache of the constant current driving chip each time, for example, the constant current driving chip shown in Figure 4 For example, the constant current driving chip outputs 16 constant current driving signals, and the 16 constant current driving signals correspond to 16 read clocks, so that the display data corresponding to the constant current driving signal of the corresponding path is read under each read clock.

[0070] It can be understood that the gray scale clock signals are generated by the FPGA and sent to the constant current driving chip. At this time, the number of clocks included in each group of gray scale clock signals is pre-set in the FPGA, and when a group of gray scale clock signals is sent at a pre-set frequency, the counting of the gray scale clock signals is synchronized, and when the pre-set number of clocks is reached, it is determined that a group of gray scale clock signals has been sent, and the counting is restarted. It can also be that the number of gray scale clocks and the number of read data clocks included in a group of gray scale clock signals are pre-set in the FPGA, and when a group of gray scale clock signals is sent at a pre-set frequency, the counting is started synchronously.

[0071] For the constant current driving chip, when a group of gray scale clock signals is received, the gray scale clock is received first, and after a plurality of gray scale clocks are continuously received, the read data clock is received instead of the gray scale clock, and after a plurality of read data clocks are continuously received, the read data clock is no longer received, and it is determined that the reception of a group of gray scale clock signals is completed. Optionally, the constant current driving chip pre-stores the number of gray scale clocks and the number of read data clocks in a group of gray scale clock signals, and then determines whether the currently received gray scale clock signal is a gray scale clock or a read data clock based on the number of currently received gray scale clock signals. Alternatively, the FPGA informs the constant current driving chip whether the currently sent is a gray scale clock or a read data clock. It can be understood that the constant current driving chip can also determine whether the currently received is a gray scale clock or a read data clock by other ways, and the embodiments do not limit this.

[0072] In step 120, when the currently received gray scale clock signal is a gray scale clock, the first display data corresponding to the reading under the reading data clock in the previous group of gray scale clock signals is output to the LED lamp bead of the current target row to drive the LED lamp bead of the current target row to display.

[0073] When the gray scale clock signal is received, the constant current driving chip outputs the constant current driving signal when it is determined that the currently received gray scale clock signal is a gray scale clock. The constant current driving signal can control the LED lamp bead of the corresponding row to emit light, thereby realizing the display of the LED lamp bead. In one embodiment, the row in which the LED lamp bead driven to emit light during one scan is recorded as a target row, and the LED lamp bead lit in the target row can be one or more, which is related to the number of constant current driving signals output by the constant current driving chip, and is not limited at present.

[0074] For example, the LED lamp bead conduction time ratio in the constant current driving signal output by the constant current driving chip during the present scan is obtained based on the display data read during the previous scan, that is, the LED lamp bead conduction time ratio in the constant current driving signal output under the driving of the gray scale clock in the current group of gray scale clock signals is determined based on the display data read under the driving of the reading data clock in the previous group of gray scale clock signals. Wherein, the LED lamp bead conduction time ratio can also be understood as the duty cycle of the PWM signal. In order to distinguish, the display data read under the driving of the reading data clock in the previous group of gray scale clock signals is recorded as the first display data. That is, the display of the LED lamp bead driven by the constant current driving chip during each scan is the display data read during the previous scan. Specifically, when the constant current driving chip receives the gray scale clock, the first display data read during the previous scan is obtained, and the LED lamp bead conduction time ratio required during the present scan is obtained based on the first display data, and then the corresponding constant current driving signal is output to drive the LED lamp bead in the target row with the current channel open to emit light. Wherein, the decoding process is not limited at present. Generally, when decoding, the brightness and the like of the LED lamp bead during display can be determined based on parameters such as RGB value, and then the LED lamp bead conduction time ratio of the constant current driving signal can be determined based on the required brightness and the like.

[0075] It can be understood that the target row with the current channel open can be determined based on the row driving chip.

[0076] It should be noted that the number of target rows driven to emit light by the constant current driving signal during each scan is not limited at present, and the technical means for driving each row of LED lamp bead to emit light is the same. Therefore, in the embodiment, only driving one row of LED lamp bead to emit light is taken as an example for description.

[0077] In step 130, when the currently received gray scale clock signal is a read data clock, the constant current driving signal is stopped from being output, and the second display data is read, and the constant current driving signal corresponding to the second display data is used to be output under the gray scale clock in the next group of gray scale clock signals.

[0078] When the gray scale clock signal is received, when the currently received gray scale clock signal is a read data clock, the constant current driving chip stops outputting the constant current driving signal, and reads the display data based on the continuously received multiple read data clocks. Optionally, when the currently received gray scale clock signal changes from a gray scale clock to a read data clock, the constant current driving chip can stop outputting the constant current driving signal, and the constant current driving chip will not output the constant current driving signal when the read data clock is continuously received thereafter.

[0079] Specifically, when the constant current driving chip starts to receive the read data clock, the currently latched display data is read, which is a row of display data to be displayed in the next scan (when multiple rows are scanned at a time, multiple rows of display data are read). The display data includes parameters such as RGB values of each pixel during display. In general, the display data of the LED display screen is in units of frames, and one frame of display data can generate an image for the LED display screen to display. When the constant current driving chip scans a frame of display data row by row (generally from top to bottom), a row of display data in the frame of display data is read each time.

[0080] It can be understood that latching display data and reading latched display data are both already implemented technical means, and are not limited at present.

[0081] At present, in order to distinguish, the display data read under the read data clock in the currently received group of gray scale clock signals is recorded as second display data. It can be understood that the second display data and the first display data correspond to different rows of LED lamp beads.

[0082] Optionally, when the received read data clock is a read clock, the latched second display data is read, and when the received read data clock is an operation clock, the display data is transmitted for subsequent use.

[0083] Optionally, after reading the second display data, the second display data is cached. Then, when the next scan starts, that is, a new group of gray scale clock signals is received, if a gray scale clock is received (that is, the gray scale clock is received again), the cached display data is decoded and the corresponding constant current driving signal is output, and the constant current driving signal can drive the LED lamp beads in the corresponding target row to emit light in the next scan. It can be understood that in the next scan, the latched display data is also read according to the read data clock, and the process is repeated, so that the display of the LED lamp beads can be realized.

[0084] Step 140, in the process of receiving continuous multiple read data clocks, a row switching signal is received, and a target row corresponding to a constant current driving signal driven by a gray scale clock in a next set of gray scale clock signals is determined according to the row switching signal.

[0085] Generally, there is a spare time period between two adjacent sets of gray scale clock signals, which is used for line switching and blanking. During line switching and blanking, the constant current driving chip receives the row switching signal (i.e., row_cut) sent by the row driving chip, which is used to determine which row the constant current driving signal is output to during scanning, i.e., to determine the target row in the next scanning. The constant current driving signal switches lines according to the row switching signal to output the constant current driving signal to the corresponding target row in the next scanning.

[0086] For example, Figure 6 The first schematic diagram of the gray scale clock signal provided by an embodiment of the present application, Figure 6 In the first row, the type corresponding to the gray scale clock signal at the corresponding position of the second row is indicated, the second row is the specific waveform of the gray scale clock signal, and the third row indicates the row switching signal. The row switching signal is high effective, i.e., when the high level is determined, the constant current driving chip receives the row switching signal. Referring to Figure 6 A set of gray scale clock signals is composed of gray scale clock 51 Figure 6 In which part of the continuous gray scale clock 51 is omitted, and read data clock 52, wherein the read data clock has 17 in total, the first 16 read data clocks can be considered as read clocks, and the last 1 read data clock can be considered as an operation clock. There are spare time periods in front of and behind a set of gray scale clock signals, and the row switching signal is generally generated in the spare time period. For example Figure 6 In the spare time period 53, the constant current driving chip receives the row switching signal 54. The row switching signal received in the spare time period behind a set of gray scale clock signals is used for the next scanning (i.e., the next set of gray scale clock signals).

[0087] It can be understood that in a set of gray scale clock signals, only during the time corresponding to the gray scale clock, the constant current driving chip can drive the LED lamp bead to light up, and only when the constant current driving signal is high, the LED lamp bead lights up, and during other time (at least including the spare time period and the working time corresponding to the read data clock) the LED lamp bead does not emit light. At this time, in the total time required for each scan, the effective time for controlling the LED lamp bead to light up is only related to the working time corresponding to the gray scale clock in the total time required for each scan, and the lighting degree is related to the proportion of the gray scale clock in the total time required for each scan. Therefore, in the embodiment, by increasing the proportion of the working time corresponding to the gray scale clock in the total time required for each scan, i.e., increasing the proportion of the effective time of the LED lamp bead lighting, the brightness efficiency of the LED lamp bead is improved.

[0088] In one embodiment, the row switching signal is received in the process of receiving the gray scale clock signal, i.e., the row switching signal is received in advance to conceal the time of receiving the row switching signal and responding to the row switching signal (i.e., line switching and blanking) in the idle time period, thereby shortening the length of the idle time period, i.e., realizing blanking in.

[0089] The row driving chip sends the row switching signal according to the indication of the FPGA, so that the time of sending the row switching signal by the row driving chip in the FPGA can be modified to realize the advance sending of the row switching signal, and thus the advance receiving of the row switching signal by the constant current driving chip. In one embodiment, the row switching signal is received in the process of receiving the plurality of read data clocks. That is, the row switching signal generation time is located in the working time corresponding to the plurality of read data clocks. Specifically, the FPGA sends a clock signal to the row driving chip, which is used to drive the row driving chip to send the row switching signal outward. At present, the clock signal is referred to as a switching clock signal. That is, the sending of the gray scale clock signal to the constant current driving chip and the sending of the row switching signal to the row driving chip are parallel processes. In one embodiment, the FPGA pre-sets the frequency of the switching clock signal. The frequency of the switching clock signal can be determined according to the frequency of the gray scale clock signal to ensure that the constant current driving chip receives the row switching signal in the process of receiving the read data clock during each scanning. Wherein, the FPGA starts to send the switching clock signal when sending the Nth gray scale clock signal in the first group of gray scale clock signals. The Nth gray scale clock signal is the read data clock, and the specific value of N can be set according to actual needs. At this time, the gray scale clock signal sent by the FPGA at the sending time of the switching clock signal is the read data clock to ensure that the constant current driving chip receives the row switching signal when receiving the read data clock.

[0090] After the constant current driving chip receives the row switching signal, the line switching and blanking are performed based on the row switching signal, i.e., the target line in the next scanning is determined, and the LED lamp beads of the target line are prepared for scanning. At the same time, since the read data clock is also received, the constant current driving chip also reads the display data in the next scanning. That is, the line switching and blanking and the reading of the display data are performed at the same time, thereby shortening the length of the idle time period.

[0091] It should be noted that in the time range corresponding to the received gray scale clock, the LED lamp bead of the target row may emit light due to the driving of the constant current driving signal. In this time range, if the row switching signal is received, the LED lamp bead that is emitting light will no longer emit light after the constant current driving chip responds to the row switching signal to perform row switching and blanking, that is, the row channel of the LED lamp bead that is emitting light has been closed by the row driving chip, and the row channel of another target row LED lamp bead has been opened. At this time, even if there is still un-displayed display data (for example, the constant current driving chip still outputs the constant current driving signal), the LED lamp bead with the closed row channel will not emit light any more, that is, the display data loss occurs. Therefore, the row switching signal is received when the read data clock is received, which can reduce the display data loss.

[0092] In an optional manner, the receiving time of the row switching signal corresponding to a group of gray scale clock signals is later than the receiving time of the third read data clock. It can be understood that when the constant current driving chip drives the LED lamp bead to emit light, the LED lamp bead may still emit light before the third read data clock in the group of gray scale clock signals is received, that is, the display is still based on the received constant current driving signal, and after the third read data clock is received, the LED lamp bead can display the display data corresponding to the current scanning, therefore, the sending time of the switching clock signal sent by the FPGA to the row driving chip corresponds to the Nth gray scale clock signal, which can be the third read data clock, or other read data clock after the third read data clock (generally not the last few read data clocks). At this time, the receiving time of the row switching signal received by the constant current driving chip should be later than the receiving time of the third read data clock, so as to ensure the display integrity of the display data in the current scanning. Optionally, the receiving time of the row switching signal is located in the receiving time of the front half of the read data clock (for example, when there are 17 read data clocks, the front half of the read data clock is the first 9 read data clocks), and generally after the receiving time of the third read data clock. It should be noted that generally, when the third read data clock is received, the LED lamp bead of the target row in the current scanning has displayed the display data that needs to be displayed at present, and even if the row channel of the LED lamp bead is closed, the display data loss will not occur. Therefore, the row switching signal is received after the third read data clock is received, which can ensure the display integrity of the LED lamp bead.

[0093] When receiving the read data clock, the row switching signal is received, the idle time period in one scanning process can be reduced, and the proportion of the gray scale clock can be improved. It can be understood that the idle time period is reduced, the total time required for scanning one row is reduced, the working time of the gray scale clock is unchanged, and therefore the proportion of the working time of the gray scale clock in the total time is improved, and the constant current driving signal generated by the gray scale clock has a higher LED lamp bead conduction time proportion, and the gray scale level that can be reached when the constant current driving signal drives the LED lamp bead to emit light is improved. At this time, the frequency of the gray scale clock and the read data clock can be appropriately reduced, and the proportion of the working time of the gray scale clock in the total time required for scanning one row can be improved.

[0094] Based on this mode, the idle time period can be small (i.e., no need to wait for more time for line switching and blanking), and therefore the FPGA can send almost continuous groups of gray scale clock signals.

[0095] For example, Figure 7 The second schematic diagram of the gray scale clock signal provided for an embodiment of the application, Figure 7 In the first row, the first row is used to represent the type of the gray scale clock signal corresponding to the corresponding position of the second row, the second row is the specific waveform of the gray scale clock signal, and the third row represents the row switching signal. Referring to Figure 7 When the fifth read data clock 52 is received, the row switching signal 54 is received, that is, the receiving time of the row switching signal 54 is advanced from the original T1 time to the T2 time, and therefore the reading of the display data is performed at the same time as the line switching and blanking, and the idle time period 53 between the two groups of gray scale clock signals is significantly reduced.

[0096] It can be understood that, for the first group of gray scale clock signals, since there is no other group of gray scale clock signals before it, there is no display data read under the previous group of gray scale clock signals for use under the gray scale clock in the gray scale clock signal. At this time, in order to ensure that the constant current driving signal is output under the first group of gray scale clock signals, a plurality of read data clocks can be additionally set before the first group of gray scale clock signals. The constant current driving chip reads the display data that needs to be displayed at the beginning under the plurality of read data clocks additionally set, and then under the gray scale clock in the first group of gray scale clock signals, the corresponding constant current driving signal can be output to the LED lamp bead of the target row based on the display data that needs to be displayed at the beginning. It should be noted that, when initializing (i.e., preparing to start controlling the LED lamp bead to display), the first row is set as the target row by default, and the row channel of the LED lamp bead of the first row is controlled to be turned on. Then, under the plurality of read data clocks additionally set, the constant current driving chip reads the display data corresponding to the first row. Therefore, under the gray scale clock in the first group of gray scale clock signals, the constant current driving chip defaults to output the corresponding constant current driving signal to the LED lamp bead of the first row. It can be understood that the plurality of read data clocks additionally set can also be considered as belonging to the first group of gray scale clock signals, that is, the first group of gray scale clock signals has the plurality of read data clocks additionally set compared with other groups of gray scale clock signals. At this time, the first group of gray scale clock signals is composed of the plurality of read data clocks additionally set, the plurality of gray scale clocks and the plurality of read data clocks in turn according to the order of receiving time. And under the plurality of read data clocks additionally set, the row switching signal does not need to be received.

[0097] The technical scheme is characterized in that: the plurality of groups of gray scale clock signals inputted from outside are received in sequence, and in the case that the currently received gray scale clock signal is a read data clock, the first display data corresponding to the read data clock in the previous group of gray scale clock signals is read and outputted to the target row of LED lamp beads as a constant current driving signal to drive the LED lamp beads to emit light, and in the case that the currently received gray scale clock signal is a read data clock, the output of the constant current driving signal is stopped, and the second display data is read, the second display data being used for the scanning process corresponding to the next group of gray scale clock signals, and in the process of receiving the read data clock, the row switching signal is also received, the target row of LED lamp beads driven by the constant current driving signal corresponding to the gray scale clock in the next group of gray scale clock signals is determined according to the row switching signal, so that the corresponding constant current driving signal is outputted to the target row of LED lamp beads in the scanning based on the next group of gray scale clock signals. The technical scheme solves the technical problem of limited brightness efficiency in the related art when driving the LED display, and through receiving the row switching signal in the process of receiving the read data clock, the read display data, the line switching and the blanking can be processed in parallel, so as to shorten the idle time period in one scanning, and further shorten the total time required for one scanning. When the total time required for one scanning is shortened, the proportion of the duration of the gray scale clock in the total time is increased, and correspondingly, the proportion of the conduction time of the LED driven by the constant current driving signal under the gray scale clock in the total time is also increased. When the conduction time takes the maximum value, the proportion of the maximum value in the total time is also increased, that is, the brightness efficiency of the LED display is improved. The gray scale clock signal is divided into the gray scale clock and the read data clock, which can ensure that the constant current driving chip more accurately performs the actions of outputting the constant current driving signal and reading the display data. And in the process of receiving the read data clock, the row switching signal is also received, which can also ensure the integrity of the LED lamp bead display in this scanning as much as possible. The receiving time of the row switching signal is set to be after the receiving time of the third read data clock, which can further ensure the integrity of the display data when driving the LED lamp bead to display.

[0098] Figure 8 The flow chart of another constant current driving method of the LED display screen is provided for an embodiment of the present application. Figure 8 The constant current driving method shown is based on the foregoing constant current driving method, and the frequency of the read data clock is increased, the working time corresponding to the read data clock is shortened, and the proportion of the gray scale clock is increased.

[0099] Reference Figure 8 The constant current driving method comprises steps 210-240.

[0100] Step 210: a plurality of groups of gray scale clock signals inputted from outside are received in sequence, each group of gray scale clock signals being composed of a plurality of continuous gray scale clocks and a plurality of continuous read data clocks, and the gray scale clock in a group of gray scale clock signals is received earlier than the read data clock.

[0101] In step 220, when the currently received gray scale clock signal is a gray scale clock, the first display data corresponding to the reading under the read data clock in the previous group of gray scale clock signals is output to the LED lamp beads of the current target row based on the corresponding constant current driving signal to drive the LED lamp beads of the current target row to display.

[0102] In step 230, when the currently received gray scale clock signal is a read data clock, a multiple frequency read data clock is obtained based on the currently received read data clock, and the constant current driving signal is stopped based on the multiple frequency read data clock, and the second display data is read.

[0103] The multiple frequency read data clock is also a read data clock, but the frequency of the multiple frequency read data clock is higher than the frequency of the read data clock sent by the FPGA. In this way, the number of multiple frequency read data clocks is more at the same time, and the constant current driving chip can execute more content. For example, taking the multiple frequency as two times as an example. At this time, the frequency of the 8 read data clocks sent by the FPGA becomes two times, and 16 read data clocks can be obtained. The working time corresponding to the 8 read data clocks sent by the FPGA is consistent with the working time corresponding to the 16 two times read data clocks under two times frequency.

[0104] It can be understood that the constant current driving chip works based on the received clock. If 17 read data clocks are required in one scanning process, only 8.5 read data clocks need to be sent by the FPGA when using two times read data clock, so that the constant current driving chip can receive 17 two times read data clocks, and then complete the reading of the display data corresponding to 17 read data clocks in the original working time corresponding to 8.5 read data clocks (i.e. required for one scanning). In this way, the working time of reading display data is shortened, and the proportion of gray scale clock in one group of gray scale clock signals is further improved, that is, the brightness efficiency is improved.

[0105] For example, each gray scale clock signal generated by the FPGA has a uniform frequency, that is, the frequencies of the gray scale clock and the read data clock are consistent. At this time, the received read data clock can be processed by the constant current driving chip to obtain a multiple frequency read data clock. That is, the constant current driving chip receives the read data clock and performs multiple frequency processing at the same time.

[0106] Currently, taking the two times read data clock as an example, how the constant current driving chip generates the two times read data clock is described. When generating the two times read data clock, a double edge trigger mode is used. That is, before step 210, a double edge trigger mode can also be set.

[0107] It can be understood that a clock signal (such as a gray scale clock signal) corresponds to a waveform with two edges, which are of a rising edge (i.e., an edge changing to a high level) and a falling edge (i.e., an edge changing to a low level). The constant current driving chip can identify each received clock signal by identifying the edges in the signal.

[0108] When the constant current driving chip receives a clock signal, a single-edge trigger mode is usually used. In the single-edge trigger mode, the edge type at the beginning of the clock signal is specified. For example, when the edge type at the beginning of the clock signal is a rising edge, the constant current driving chip determines that a clock starts when it identifies that the waveform of the currently received signal is a rising edge, and determines that a clock ends when it identifies that the waveform of the currently received signal is a falling edge. In this way, each clock signal is identified. At this time, the clock signal is a high level signal.

[0109] In an embodiment, the constant current driving chip is set to a double-edge trigger mode. In the double-edge trigger mode, the edge type at the beginning or end of the clock signal is not limited. For example, when the constant current driving chip receives a clock signal, it identifies the first edge. Regardless of whether the edge is a rising edge or a falling edge, it determines that a clock starts. When it identifies the second edge, regardless of whether the edge is a rising edge or a falling edge, it determines that a clock ends. When it identifies the third edge, regardless of whether the edge is a rising edge or a falling edge, it determines that a clock starts. In this way, each clock signal is identified.

[0110] Optionally, the double-edge trigger mode is set by the control logic unit, and then the control logic unit stores the relevant data of setting the double-edge trigger mode in the configurable register. The constant current source algorithm circuit determines that the current is set to the double-edge trigger mode through the configurable register.

[0111] After the double-edge trigger mode is set, the continuous multiple read data clocks are changed to multiple frequency read data clocks in this step, which can include steps 231-232:

[0112] In step 231, the currently received read data clock is copied to obtain a copied read data clock. When copying, the edge signals of the read data clock and the copied read data clock are arranged at intervals in time sequence, and the distance between any two adjacent edge signals during the interval is equal.

[0113] For example, the constant current driving chip divides the currently received read data clock into two paths, one of which is the originally received read data clock, and the other of which is the read data clock obtained by copying the received read data clock. The copied read data clock is referred to as a copied read data clock. The waveform of the copied read data clock is the same as that of the read data clock, and the number of clocks is also the same.

[0114] It can be understood that the receiving and copying of the read data clock are performed simultaneously, that is, the read data clock is received and the currently received read data clock is copied at the same time. At this time, it can be considered that the constant current driving chip simultaneously receives the read data clock and the copied read data clock.

[0115] Since the constant current driving chip can identify the gray scale clock signal by identifying the edges of the received signal, in order to obtain the double-frequency read data clock, the edge signals of the read data clock and the edge signals of the copied read data clock can be arranged in time sequence. After the interval arrangement, when the constant current driving chip simultaneously receives the read data clock and the copied read data clock, the received edge signals are: the edge signal of the read data clock (such as the above edge signal), the edge signal of the copied read data clock (such as the above edge signal), the edge signal of the read data clock (such as the below edge signal), the edge signal of the copied read data clock (such as the below edge signal), and so on.

[0116] Among them, the technical means for realizing interval arrangement is not limited at present. For example, when the constant current driving chip obtains the copied read data clock, the copied read data clock is phase-shifted, and after phase-shifting, the edge signals of the read data clock and the copied read data clock are arranged in time sequence.

[0117] An optional way is that when the copied read data clock is phase-shifted by 90°, the position of the edge signal of the copied read data clock in time sequence is located in the middle of the two positions of the two adjacent edge signals of the read data clock in time sequence, so as to realize that the distance between adjacent edge signals is equal when the edge signals of the read data clock and the copied read data clock are arranged in time sequence. After the distance is equal, the double-frequency read data clock with regular waveform can be obtained based on the edge signals arranged in time sequence.

[0118] Optionally, the control logic unit in the constant current driving chip informs the constant current source algorithm circuit to copy the received read data clock and arrange in time sequence through a configurable register.

[0119] Step 232, according to the double-edge trigger mode, the double-frequency read data clock is obtained according to the edge signals arranged in time sequence.

[0120] Exemplarily, when the double-edge trigger mode is adopted, the constant current driving chip identifies the edge signals arranged in time sequence, and each time the identified edge signal is taken as the edge signal of the double-frequency read data clock, so as to obtain the double-frequency read data clock.

[0121] For example, the edges of the signals arranged at intervals are respectively: an edge of the read data clock (such as a rising edge), an edge of the copied read data clock (such as a rising edge), an edge of the read data clock (such as a falling edge), an edge of the copied read data clock (such as a falling edge), and so on. When the constant current driving signal identifies the first edge of the signals (the edge of the read data clock), it is considered that the edge of the first double frequency read data clock indicating the start of the clock is identified, when the constant current driving signal identifies the second edge of the signals (the edge of the copied read data clock), it is considered that the edge of the first double frequency read data clock indicating the end of the clock is identified, when the constant current driving signal identifies the third edge of the signals (the edge of the read data clock), it is considered that the edge of the second double frequency read data clock indicating the start of the clock is identified, and so on, so that all double frequency read data clocks can be obtained.

[0122] In one embodiment, when the double frequency read data clock is obtained, it is also necessary to determine whether the signal between adjacent edges is high or low. In one optional manner, the signals between the edges arranged at intervals are alternately arranged in high and low levels in advance. That is, the signal between the first and second edges arranged at intervals is high, the signal between the second and third edges is low, the signal between the third and fourth edges is high, and so on, so that all double frequency read data clocks can be obtained. In another optional manner, the exclusive or operation is used to determine whether the signal between adjacent edges is high or low.

[0123] For example, in the case of using the exclusive or operation to determine whether the signal between adjacent edges is high or low, the step can be specifically: based on the double edge trigger mode, the read data clock and the copied read data clock are subjected to the exclusive or operation based on the edges arranged at intervals, so that the double frequency read data clock is obtained.

[0124] The continuous clock signals are realized by alternating high and low signals. When the exclusive or operation is performed on two groups of continuous clock signals, the low signal is obtained based on two high (low) signals, and the high signal is obtained based on one high (low) signal and one low (high) signal.

[0125] On this basis, the read data clock and the copied read data clock are subjected to the exclusive or operation, and it is determined whether the signal between the edges of the double frequency read data clock is high or low based on the operation result.

[0126] For example, Figure 9 A third schematic diagram of the gray scale clock signal provided by one embodiment of the application, Figure 9In the table, the first row is used to represent the type of the gray scale clock signal corresponding to the position of the second row, the second and third rows are the specific waveforms of the gray scale clock signal, wherein the second row includes the specific waveform of the read data clock sent by the FPGA, the third row is the specific waveform of the copied read data clock, the fourth row is the specific waveform of the double frequency read data clock (i.e. the specific waveform of the read data clock actually used by the constant current driving chip), and the fifth row represents the row switching signal. Referring to Figure 9 The edge signals of the read data clock 521 and the copied read data clock 522 are arranged in intervals, and each interval-arranged edge signal is used as an edge signal of the double frequency read data clock 523. When the read data clock and the copied read data clock are subjected to XOR operation, only the high level signal of the read data clock is present in time sequence between the first two interval-arranged edge signals (corresponding to the rising edge signals of the read data clock and the copied read data clock), and therefore, the high level signal is retained, i.e. the high level signal is present between the first two interval-arranged edge signals. The high level signals of the read data clock and the copied read data clock are present in time sequence between the second interval-arranged edge signal (corresponding to the rising edge signal of the copied read data clock) and the third interval-arranged edge signal (corresponding to the falling edge signal of the read data clock), and therefore, it can be determined that the low level signal is present between the second interval-arranged edge signal and the third interval-arranged edge signal after XOR operation. In this way, the double frequency read data clock shown in the fourth row can be obtained after the read data clock and the copied read data clock are subjected to XOR operation.

[0127] In actual application, other methods can also be used to determine whether the signal between adjacent edge signals is a high level signal or a low level signal.

[0128] It can be understood that when the constant current driving chip is driven based on the double frequency read data clock, only half of the original number of read data clocks needs to be received from the FPGA. At this time, the FPGA can reset the number of gray scale clock signals in a group of gray scale clock signals (the number is obtained by adding the number of original gray scale clocks to half of the number of original read data clocks), and output the corresponding number of gray scale clock signals to the constant current driving chip based on the reset number. Optionally, the frequency of the gray scale clock signal generated by the FPGA can remain unchanged or be fine-tuned.

[0129] When the number of read data clocks is modified to half of the original number, the concept of half a clock will appear. For example, a plurality of continuous read data clocks are composed of an even number of read clocks and an operation clock, and when the number is modified by half, 0.5 read data clock will appear at the end. However, the FPGA cannot transmit only half a clock signal, and needs to transmit a complete clock signal. On this basis, a method needs to be found to eliminate the situation of transmitting half a clock signal by the FPGA during frequency doubling.

[0130] In one embodiment, each group of gray scale clock signals required for displaying one frame of display data is taken as a whole to eliminate the concept of half a clock in logic. At this time, each group of gray scale clock signals corresponding to one frame of display data forms a first signal group, and each group of gray scale clock signals in the first signal group is continuous in time sequence.

[0131] For example, the FPGA takes each group of gray scale clock signals required for displaying one frame of display data as a signal group, which is currently referred to as a first signal group. And the total number of gray scale clock signals required in the first signal group is set in units of the first signal group. The concept of half a clock is eliminated, for example, there are four groups of gray scale clock signals in the first signal group, and each group has 13.5 clocks, so the first signal group has 13.5x4=54 gray scale clock signals. At this time, there is no concept of half a gray scale clock.

[0132] For example, each group of gray scale clock signals in the first signal group is continuous in time sequence and has no spare time period to ensure that the constant current driving chip accurately identifies the gray scale clock and the read data clock. After that, the constant current driving chip continuously receives each gray scale clock signal in the first signal group, and becomes a double-frequency read data clock when the received gray scale clock signal is a read data clock. Since it is currently in double-edge trigger mode, the constant current driving chip only needs to identify the edge, and the situation of half a clock can be avoided.

[0133] For example, Figure 10 A first signal group schematic diagram provided for one embodiment of the application, Figure 10 In the embodiment, the first signal group has four groups of gray scale clock signals, each group of gray scale clock signals has 5.5 gray scale clock signals, the first signal group has 22 gray scale clock signals, and the constant current driving chip needs 2 gray scale clocks and 7 double-frequency read data clocks during one scan. Figure 10 In the embodiment, the first row represents the waveform of the gray scale clock signal of the first signal group output by the FPGA (which can also be understood as received by the constant current driving chip from the FPGA), the second row represents the waveform of the copied read data clock copied by the constant current driving chip, and the third row represents the waveform of the gray scale clock signal actually used by the constant current driving chip during scanning in the working time corresponding to the first signal group. Among them, the gray scale clock signal with low frequency is a gray scale clock, and the gray scale clock signal with high frequency is a read data clock (i.e. a double-frequency read data clock). Based on Figure 10 As shown in the clock signal, the concept of half a clock signal no longer appears in the gray scale clock signal corresponding to one frame of display data.

[0134] Generally speaking, when determining the gray scale clock signal as a whole for a frame of display data, the half clock signal can be effectively avoided. In a few cases, there may be a half clock signal in the first signal group, at this time, the half clock signal can be directly supplemented at the end of the gray scale clock signal of the first signal group to obtain an integer number of gray scale clock signals.

[0135] Optionally, there can be a spare time period between adjacent first signal groups. It can be understood that the time length required for a scanning process when the constant current driving chip drives the LED display screen to display is basically fixed, and correspondingly, the time length corresponding to the display of a frame of display data is also basically fixed. If the gray scale clock signals corresponding to a frame of display data are continuous, a spare time period may appear at the rear of the first signal group, that is, the spare time period originally between the adjacent two groups of gray scale clock signals is concentrated at the rear of the first signal group. When the spare time period appears, the constant current driving chip does not drive the display and does not read the display data. If the duration of the spare time period is relatively long, a large black field (LED lamp beads do not display) may appear, at this time, the user watching the LED display screen will have a flickering feeling of the display content, and when the black field is large, it will also cause a large load on the power supply of the LED display screen.

[0136] Therefore, in an embodiment, in order to avoid a long spare time period after each first signal group, the number of rows corresponding to an even number of continuous scanning times can also be taken as a whole, and the number of times of the even number of continuous times is less than the number of scanning times corresponding to a frame of display data. In this way, while eliminating the half clock signal, the situation of a long spare time period can also be avoided. At this time, the even number of continuous groups of gray scale clock signals form a second signal group, and the groups of gray scale clock signals in the second signal group are continuous in time sequence, and the number of groups of gray scale clock signals in the second signal group is less than the number of groups of gray scale clock signals corresponding to a frame of display data.

[0137] For example, the FPGA takes each group of gray scale clock signals required in an even number of continuous scanning times as a signal group, which is currently referred to as a second signal group. And the total number of gray scale clock signals required in the second signal group is set in units of second signal groups. It can be understood that the number of groups of gray scale clock signals contained in the second signal group is even, so as to eliminate the concept of half clock.

[0138] Optionally, the number of groups of gray scale clock signals contained in the second signal group is less than the number of groups of gray scale clock signals corresponding to a frame of display data (i.e. the number of groups of gray scale clock signals contained in the first signal group), at this time, the spare time period corresponding to the first signal group can be scattered and distributed between the second signal groups, this process can be realized by the FPGA, and the implementation means of the FPGA for scattering the spare time period in the related technology can be referred to. At this time, the spare time period between the second signal groups is small, which can avoid the black field of the LED display screen.

[0139] It is understandable that the processing method of the grayscale clock signal corresponding to the second signal group can refer to the processing method of the grayscale clock signal corresponding to the first signal group, and will not be elaborated here.

[0140] In one embodiment, the second signal group consists of two consecutive sets of grayscale clock signals to minimize the gaps in the time interval.

[0141] In one embodiment of this application, when eliminating the concept of a half-clock signal, besides treating multiple groups of grayscale clock signals as a whole and setting the total number of grayscale clock signals it contains, the idle time period between each group of grayscale clock signals continuously output by the FPGA can be set to alternate between high-level and low-level signals based on the characteristics of the dual-edge triggering mode. That is, the idle time period between each group of grayscale clock signals alternates between high-level and low-level signals in sequence, and the level signal of the idle time period is determined according to the adjacent preceding grayscale clock signal. At this time, the last grayscale clock signal (i.e., half of the read data clock) in a group of grayscale clock signals output by the FPGA has only one edge signal indicating the start. After that, the level of the idle time period after this group of grayscale clock signals is consistent with the level of the half-read data clock, until the next group of grayscale clock signals begins, when another edge signal appears. At this time, the idle time period between each group of grayscale clock signals will alternate between high-level and low-level signals in sequence.

[0142] It is understandable that the process of obtaining a doubled read data clock based on half of the read data clock and the corresponding half of the copied read data clock can be referred to the above content, and will not be repeated here.

[0143] For example, Figure 11 This is a fourth schematic diagram of a grayscale clock signal provided in one embodiment of this application. Figure 11 In the diagram, the first line indicates the type of the grayscale clock signal corresponding to the position in the second line; the second line shows the specific waveform of the grayscale clock signal, which is generated by the FPGA; and the third line represents the line switching signal. (Reference) Figure 11 The first set of grayscale clock signals ( Figure 11 The last half of the read data clock (showing only the last few read data clocks) is a low-level signal. During this time, the subsequent idle time period remains a low-level signal. For the FPGA, this can be considered as outputting an integer number of grayscale clock signals and then maintaining the same level before outputting the next set of grayscale clock signals. At the start of the next set of grayscale clock signals, the signal becomes high again based on the edge signal. The last half of the read data clock signal of the next set of grayscale clock signals is a high-level signal, and during this time, the subsequent idle time period remains a high-level signal, thus eliminating the FPGA's output of half a clock signal.

[0144] It should be noted that in the embodiments of the present application, the size of the spare time period in the schematic diagram of each gray scale clock signal is only used for exemplary description, and cannot indicate the size of the spare time period in actual application. When the size of the spare time period in different schematic diagrams is inconsistent, it also cannot indicate that the spare time periods are inconsistent in actual application.

[0145] In step 240, a row switching signal is received in the process of receiving the continuous multiple read data clocks, and a target row corresponding to the constant current driving signal in the next group of gray scale clock signals is determined according to the row switching signal.

[0146] It can be understood that the double-frequency read data clock is generated in the constant current driving chip, and at this time, the receiving time of the row switching signal should correspond to the working time corresponding to the double-frequency read data clock. In one embodiment, it is also necessary to modify the frequency and sending time of the switching clock signal corresponding to the row switching signal in the FPGA, so as to ensure that the constant current driving chip receives the row switching signal when the double-frequency read data clock is generated.

[0147] In one embodiment, when the concept of half clock signal generated when the double-frequency read data clock is generated is eliminated by using the first signal group or the second signal group, the frequency of the clock driving count of the row switching signal in the FPGA should be doubled, that is, the frequency of the clock driving count corresponding to the row switching signal is set to double frequency. It can be considered that the clock driving count is the count of the switching clock signal. It should be noted that for the FPGA, only the frequency of the count is doubled, but the frequency of the switching clock signal is not increased, that is, the switching clock signal is still sent to the row driving chip according to the current frequency. When the frequency of the count is doubled, the FPGA can consider that the row switching signal is received in the working time corresponding to half clock signal (the constant current driving chip actually does not receive the row switching signal), at this time, the FPGA can continue to work after half clock signal. It can be understood that the FPGA generates the gray scale clock signal, and also needs to generate the data clock signal, the latch signal and send the corresponding display data, etc., and the FPGA needs to work according to the complete clock period, and it is difficult to realize the working logic under half gray scale clock signal. Therefore, when the frequency of the count of the row switching signal is doubled, this problem can be avoided, that is, when half gray scale clock signal, by changing the count of the row switching signal, the FPGA can still work according to the complete clock period.

[0148] For example, Figure 12The first schematic diagram of clock driving count of row switching signal provided by one embodiment of the present application. It is the clock driving count of row switching signal in FPGA when using the first signal group, wherein the first row represents the vertical synchronization signal (also can be understood as the frame synchronization signal), the second row represents the first signal group, wherein the first signal group includes multiple groups of gray scale clock signals, and each group of gray scale clock signals includes a gray scale clock and a read data clock, and the blank part behind can be considered as the spare time period 53. The third row represents the clock driving count of row switching signal in FPGA, wherein at each arrow, the clock driving count is added by 1, based on Figure 12 It can be known that at the end of each read data clock (half clock signal), the clock driving count of FPGA is added by 1, so as to ensure the normal counting of FPGA when using the first signal group.

[0149] For example, Figure 13 The second schematic diagram of clock driving count of row switching signal provided by one embodiment of the present application. It is the clock driving count of row switching signal in FPGA when using the second signal group, wherein the first row VSYNC represents the vertical synchronization signal (also can be understood as the frame synchronization signal), the second row represents each second signal group corresponding to one frame of display data, wherein one second signal group includes two groups of gray scale clock signals, and each group of gray scale clock signals includes a gray scale clock 51 and a read data clock 52. The third row represents the clock driving count of row switching signal in FPGA, wherein at each arrow, the clock driving count is added by 1, based on Figure 13 It can be known that at the end of each read data clock (half clock signal), the clock driving count of FPGA is added by 1, so as to ensure the normal counting of FPGA when using the second signal group.

[0150] The above, by setting the double-edge trigger mode, and increasing the frequency of the read data clock in the double-edge trigger mode (that is, using a multiple frequency read data clock), the working time of reading display data corresponding to the read data clock can be shortened, the clock signal utilization rate of the non-display period is optimized, and the time required for scanning a row is shortened, so that in a group of gray scale clock signals, the proportion of the gray scale clock is further increased, and the brightness efficiency of the LED lamp bead display is improved. At this time, the brightness efficiency can be increased from 50%-70% to 79%-93%. For small-pitch LED display screens, higher brightness can be displayed with lower power consumption (without significantly increasing the current of the constant current driving signal), ensuring the temperature rise redundancy of the small-pitch LED display screen during operation. And, the implementation process is simple, and can be quickly popularized. And, when increasing the frequency of the read data clock, the total number of gray scale clock signals is set as a whole for a frame of display data, or the continuous even number of gray scale clock signals is set as a whole, avoiding the occurrence of half a clock, and ensuring the accurate operation of the constant current driving chip. By increasing the clock driving count frequency of the row switching signal, the normal counting of the FPGA is also ensured, and the normal operation of the constant current driving chip is further ensured.

[0151] In an embodiment of the present application, a constant current driving chip is also provided, which can be used to execute the constant current driving method provided by any of the above embodiments, has corresponding functions and advantages. Wherein, the constant current driving chip executes the constant current driving method provided by any of the above embodiments, and the structure and implementation process involved can refer to the related description of the foregoing embodiments.

[0152] In an embodiment of the present application, an LED display screen is also provided, which can be a separate display such as a billboard, etc., or can be integrated in an electronic device such as a mobile phone, a television, an interactive tablet, etc. The current LED display screen is a small-pitch LED display screen.

[0153] Figure 14 An embodiment of the present application provides a structural diagram of an LED display screen, which is referred to as Figure 14 The LED display screen 60 includes a receiving card 61 and an LED lamp panel 62, the receiving card 61 includes a logic chip 611, and the LED lamp panel 62 includes a plurality of LED lamp beads 621, at least one constant current driving chip 622, and at least one row driving chip 623, Figure 14 For example, four LED lamp beads 621, one constant current driving chip 622, and at least one row driving chip 623, and the logic chip 611 is taken as an FPGA.

[0154] The logic chip 611 is configured to sequentially send a plurality of groups of grayscale clock signals to the constant-current driving chip 622, each group of grayscale clock signals is composed of a plurality of continuous grayscale clocks and a plurality of continuous read data clocks, the grayscale clock in a group of grayscale clock signals is sent before the read data clock, and the logic chip 611 is also configured to send a switching clock signal to the row driving chip 623, the grayscale clock signal sent by the logic chip 611 at a corresponding sending moment of the switching clock signal is the read data clock.

[0155] The row driving chip 623 is configured to send a row switching signal to the constant-current driving chip 622 according to the switching clock signal, and each switching clock signal corresponds to one row switching signal.

[0156] The constant-current driving chip 622 is configured to sequentially receive a plurality of groups of externally input grayscale clock signals, in a case where the currently received grayscale clock signal is a grayscale clock, output a corresponding constant-current driving signal to the LED lamp bead 621 of a current target row based on first display data corresponding to the read data clock in the previous group of grayscale clock signals, so as to drive the LED lamp bead 621 of the current target row to display, in a case where the currently received grayscale clock signal is a read data clock, stop outputting the constant-current driving signal, and read second display data, the constant-current driving signal corresponding to the second display data is used to be output in the grayscale clock in the next group of grayscale clock signals, and in the process of receiving a plurality of continuous read data clocks, receive a row switching signal, and determine the target row driven by the constant-current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals according to the row switching signal.

[0157] In an embodiment of the present application, the constant-current driving chip 622 is configured to, in a case where the currently received grayscale clock signal is a read data clock, stop outputting the constant-current driving signal and read the second display data, and specifically configured to: in a case where the currently received grayscale clock signal is a read data clock, obtain a plurality of frequency-multiplied read data clocks based on the currently received read data clock, and stop outputting the constant-current driving signal and reading the second display data based on the plurality of frequency-multiplied read data clocks.

[0158] In an embodiment of the present application, the plurality of frequency-multiplied read data clocks is a two-frequency-multiplied read data clock, and the constant-current driving chip 622 is further configured to set a double-edge trigger mode before sequentially receiving a plurality of groups of externally input grayscale clock signals. The constant-current driving chip 622 is configured to, when obtaining a plurality of frequency-multiplied read data clocks based on the currently received read data clock, specifically configured to: copy the currently received read data clock to obtain a copied read data clock, and control the edge signals of the read data clock and the edge signals of the copied read data clock to be arranged at intervals in time sequence during copying, and the distance between any two adjacent edge signals during the interval arrangement is equal; obtain a two-frequency-multiplied read data clock based on the edge signals arranged at intervals according to the double-edge trigger mode.

[0159] In one embodiment of the present application, the constant current driving chip 622 is configured to obtain the double-frequency read data clock based on the double-edge trigger mode and the interval arrangement of the edge signals, and specifically configured to: perform XOR operation on the read data clock and the copied read data clock based on the double-edge trigger mode and the interval arrangement of the edge signals, to obtain the double-frequency read data clock.

[0160] In one embodiment of the present application, before the logic chip 611 sequentially sends the multiple groups of gray scale clock signals to the constant current driving chip, the logic chip 611 is further configured to: take each group of gray scale clock signals corresponding to a frame of display data as a first signal group, set the total number of the gray scale clock signals contained in the first signal group, and set each group of gray scale clock signals in the first signal group to be continuous in time sequence.

[0161] In one embodiment of the present application, before the logic chip 611 sequentially sends the multiple groups of gray scale clock signals to the constant current driving chip, the logic chip 611 is further configured to: take the continuous even-numbered groups of gray scale clock signals as a second signal group, set the total number of the gray scale clock signals contained in the second signal group, and set each group of gray scale clock signals in the second signal group to be continuous in time sequence, and the number of groups of gray scale clock signals in the second signal group is less than the number of groups of gray scale clock signals corresponding to a frame of display data.

[0162] In one embodiment of the present application, the second signal group is composed of two continuous groups of gray scale clock signals.

[0163] In one embodiment of the present application, when the logic chip 611 sends the switching clock signal to the row driving chip, the logic chip 611 is further configured to adjust the frequency of the clock driving count corresponding to the row switching signal to double frequency.

[0164] In one embodiment of the present application, when the logic chip 611 sequentially sends the multiple groups of gray scale clock signals to the constant current driving chip, the logic chip 611 is further configured to: set the spare time period between each group of gray scale clock signals to be alternately high and low, and the level signal of the spare time period is determined according to the adjacent previous gray scale clock signal.

[0165] In one embodiment of the present application, the receiving time of the row switching signal corresponding to one group of the gray scale clock signals in the constant current driving chip 622 is later than the receiving time of the third read data clock in the constant current driving chip 622.

[0166] In one embodiment of the present application, the continuous multiple read data clocks are composed of an even number of read clocks and one operation clock.

[0167] It can be understood that the LED display screen can further include a buffer driver and the like, and the embodiments will not be described here.

[0168] It should be noted that, Figure 14The elements contained in the LED display screen are only exemplary, and the mounting positions and relative positional relationships of the elements are not limited.

[0169] The LED display screen contains a constant current driving chip, which can be used to execute the constant current driving method provided by any of the above embodiments, and has corresponding functions and beneficial effects. Among them, the hardware involved in the LED display screen and the implementation process can refer to the related description of the foregoing embodiments.

[0170] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0171] Note that the above is only the preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A constant current driving method of an LED display screen, characterized in that, The method comprises the following steps: receiving a plurality of groups of external input grayscale clock signals in sequence, each group of the grayscale clock signals being composed of a plurality of continuous grayscale clocks and a plurality of continuous read data clocks, the grayscale clock in each group of the grayscale clock signals being received before the read data clock; in a case where the currently received grayscale clock signal is a grayscale clock, outputting a corresponding constant current driving signal to the LED lamp bead of the current target row based on the first display data corresponding to the read data clock in the previous group of grayscale clock signals, so as to drive the LED lamp bead of the current target row to display; in a case where the currently received grayscale clock signal is a read data clock, stopping outputting the constant current driving signal and reading second display data, the constant current driving signal corresponding to the second display data being used for outputting in the grayscale clock of the next group of grayscale clock signals; in the process of receiving the plurality of continuous read data clocks, receiving a row switching signal and determining the target row driven by the constant current driving signal corresponding to the grayscale clock in the next group of grayscale clock signals according to the row switching signal.

2. The constant current drive method according to claim 1, wherein in a case where the currently received grayscale clock signal is a read data clock, stopping outputting the constant current driving signal and reading second display data, comprising: in a case where the currently received grayscale clock signal is a read data clock, obtaining a plurality of frequency-multiplied read data clocks based on the currently received read data clock, and stopping outputting the constant current driving signal and reading second display data based on the plurality of frequency-multiplied read data clocks.

3. The constant current drive method according to claim 2, wherein the plurality of frequency-multiplied read data clocks are double frequency-multiplied read data clocks, before the step of receiving a plurality of groups of external input grayscale clock signals in sequence, comprising: setting a double-edge trigger mode; the step of obtaining a plurality of frequency-multiplied read data clocks based on the currently received read data clock, comprising: copying the currently received read data clock to obtain a copied read data clock, and controlling the edge signals of the read data clock and the edge signals of the copied read data clock to be arranged at intervals in time sequence during copying, and the distance between any two adjacent edge signals during the interval arrangement being equal; obtaining double frequency-multiplied read data clocks based on the edge signals arranged at intervals according to the double-edge trigger mode.

4. The constant current drive method according to claim 3, wherein the step of obtaining double frequency-multiplied read data clocks based on the edge signals arranged at intervals according to the double-edge trigger mode, comprising: performing exclusive OR operation on the read data clock and the copied read data clock based on the edge signals arranged at intervals according to the double-edge trigger mode to obtain double frequency-multiplied read data clocks.

5. The constant current drive method according to claim 3, wherein each group of grayscale clock signals corresponding to a frame of display data forms a first signal group, and each group of grayscale clock signals in the first signal group is continuous in time sequence.

6. The constant current drive method according to claim 3, wherein a second signal group is composed of a plurality of continuous even groups of grayscale clock signals, each group of grayscale clock signals in the second signal group is continuous in time sequence, and the number of groups of grayscale clock signals in the second signal group is less than the number of groups of grayscale clock signals corresponding to a frame of display data.

7. The constant current drive method according to claim 6, wherein the second signal group is composed of two continuous groups of grayscale clock signals.

8. The constant current drive method according to claim 5 or 6, wherein the frequency of the clock driving count corresponding to the row switching signal is set to double frequency.

9. The constant current drive method according to claim 3, wherein The spare time periods between the gray scale clock signals of each group are alternately high level signals and low level signals, and the level signals of the spare time periods are determined according to the previous gray scale clock signal.

10. The constant current drive method according to claim 1, wherein The receiving time of the row switching signal corresponding to the gray scale clock signal of each group is later than the receiving time of the third read data clock.

11. The constant current drive method according to claim 1, 5 or 6, wherein The continuous read data clocks are composed of an even number of read clocks and one operation clock.

12. A constant current driving chip for LED display screen, characterized in that, The constant current driving chip is used to perform the constant current driving method of the LED display screen as claimed in any one of claims 1-11.

13. An LED display screen, characterized by The LED display screen comprises a receiving card and an LED lamp panel, the receiving card comprises a logic chip, and the LED lamp panel comprises a plurality of LED lamp beads, at least one constant current driving chip and at least one row driving chip, The logic chip is used to sequentially send a plurality of groups of gray scale clock signals to the constant current driving chip, each group of the gray scale clock signals is composed of a plurality of continuous gray scale clocks and a plurality of continuous read data clocks, the gray scale clock in each group of the gray scale clock signals is sent before the read data clock, and the logic chip is also used to send a switching clock signal to the row driving chip, the gray scale clock signal sent by the logic chip at the sending time corresponding to the switching clock signal is a read data clock; The row driving chip is used to send a row switching signal to the constant current driving chip according to the switching clock signal, and each switching clock signal corresponds to one row switching signal; The constant current driving chip is used to sequentially receive a plurality of groups of externally input gray scale clock signals, in the case that the currently received gray scale clock signal is a gray scale clock, output a corresponding constant current driving signal to the LED lamp beads of the current target row based on the first display data corresponding to the read data clock in the previous group of gray scale clock signals, so as to drive the LED lamp beads of the current target row to display, in the case that the currently received gray scale clock signal is a read data clock, stop outputting the constant current driving signal, and read second display data, the constant current driving signal corresponding to the second display data is used to output in the gray scale clock of the next group of gray scale clock signals, and in the process of receiving a plurality of continuous read data clocks, receive the row switching signal, and determine the target row driven by the constant current driving signal corresponding to the gray scale clock in the next group of gray scale clock signals according to the row switching signal.

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