Apparatus and method for phase clock correction

Abstract

The invention relates to a phase clock correction apparatus and method. In some examples, clock correction may include two stages of duty cycle adjustment. In the first stage, the duty cycle of the plurality of clock signals may be adjusted. The clock signals may be based on an input clock signal and its inverse signal. The duty cycle adjustment provided to the clock signal during this phase may be based on the difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its inverse signal may be adjusted. The duty cycle adjustment provided to the input clock signal and / or its inverse signal may be based on a clock signal generated from the plurality of clock signals after its duty cycle has been adjusted.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the invention patent application with application date of March 30, 2020, application number 202010235418.6, and invention name “Device and method for phase clock correction”.

[0003] Cross-references

[0004] This patent application claims priority to U.S. patent application No. 16 / 371,414 filed by Brox et al. on April 1, 2019, entitled “PHASE CLOCK CORRECTION,” each of which is assigned to the assignee of this application and each of which is expressly incorporated herein by reference in its entirety.

[0005] The technical field relates to phase clock correction. Background Art

[0006] The following relates generally to systems including at least one memory device, and more specifically to phase clock correction.

[0007] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states (often represented by a logical 1 or a logical 0). In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (such as ferroelectric random access memory) can maintain its stored logic state for a long time even in the absence of external power. Volatile memory devices (such as dynamic random access memory) may lose their stored state when disconnected from the external power supply. Due to the use of ferroelectric capacitors as storage devices, ferroelectric random access memory may be able to achieve densities similar to volatile memory, but may have non-volatile characteristics.

[0009] Memory devices may use multiple clock signals to convey timing information for various operations. However, component imperfections may result in non-ideal phase offsets between clock signals. Techniques for correcting phase errors between multiple clock signals may be desirable. Summary of the invention

[0010] A method is described. The method may include: receiving a first set of clock signals; generating a plurality of clock signals that are offset in phase from one another based at least in part on the first set of clock signals; adjusting a duty cycle of at least one of the plurality of clock signals; receiving a second set of clock signals; and adjusting a duty cycle of at least one of the second set of clock signals based at least in part on the at least one clock signal having the adjusted duty cycle.

[0011] An apparatus is described. The apparatus may include: a first circuit coupled to an input of a clock divider circuit and operable to adjust a duty cycle of a set of clock signals; a second circuit coupled to an output of the clock divider circuit and operable to adjust a duty cycle of at least one of a plurality of clock signals output by the clock divider circuit; a third circuit coupled to the second circuit and operable to output two clock signals based at least in part on the plurality of clock signals, at least one of the plurality of clock signals having a duty cycle adjusted by the second circuit; and a control component coupled to the third circuit and operable to modify the duty cycle adjustment provided by the first circuit based at least in part on the two clock signals.

[0012] A device is described. The device may include: a first circuit operable to adjust the duty cycle of a first clock signal of two clock signals; a clock frequency dividing circuit operable to receive the two clock signals after adjusting the duty cycle of the first clock signal and generate four clock signals each shifted in phase; a second circuit operable to receive a first pair of the four clock signals and adjust the duty cycle of at least one of the first pair of clock signals; and a third circuit operable to receive a second pair of the four clock signals and adjust the duty cycle of at least one of the second pair of clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a system supporting phase clock correction according to examples disclosed herein is illustrated.

[0014] Figure 2 An example of a memory die supporting phase clock correction according to examples disclosed herein is illustrated.

[0015] Figure 3 An example of clock circuitry supporting phase clock correction according to examples disclosed herein is illustrated.

[0016] Figure 4 An example of a clock signal supporting phase clock correction according to examples disclosed herein is illustrated.

[0017] Figure 5 An example of clock circuitry supporting phase clock correction according to examples disclosed herein is illustrated.

[0018] Figure 6 An example of a clock signal supporting phase clock correction according to examples disclosed herein is illustrated.

[0019] Figure 7 An example of a duty cycle correction (DCC) controller supporting phase clock correction according to examples disclosed herein is illustrated.

[0020] Figure 8 An example of a circuit system supporting phase clock correction according to examples disclosed herein is illustrated.

[0021] Fig. 9 Examples of waveforms supporting phase clock correction according to examples disclosed herein are illustrated.

[0022] Fig.10 A flow chart illustrating one or more methods of supporting phase clock correction according to various examples disclosed herein is shown. DETAILED DESCRIPTION

[0023] The memory device may correct for phase shifts or variations in one or more clock signals by implementing a correction process, which may be a two-stage correction process. Such a process may include: adjusting the duty cycle of one or more clock signals (e.g., low-frequency clock signals); and using the adjusted one or more signals as a basis for adjusting the duty cycle of one or more incoming clock signals (e.g., high-frequency clock signals), from which other (e.g., low-frequency) clock signals are derived.

[0024] A memory device may use one or more clock signals (e.g., a high frequency clock signal) to time its operations. However, it may be difficult to distribute a clock signal (e.g., a high frequency clock signal) through a memory device due to the filter-like nature of the traces used. For example, the traces may act as a low pass filter that attenuates signals at a particular frequency (e.g., the cutoff frequency of the trace metallization). To overcome this problem, a memory device may use a clock signal (e.g., a high frequency clock signal) to generate multiple other (e.g., low frequency) clock signals that are offset in phase. These multiple other clock signals may represent the same information as the high frequency clock signal (e.g., the edges of the low frequency clock signals may be aligned with the edges of the high frequency clock), but may be propagated throughout the device without experiencing the same degradation as the one or more different (e.g., high frequency) clock signals.

[0025] In some instances, information from the high-frequency clock signal may be lost if the low-frequency clock has a non-ideal phase offset (e.g., an error or change in phase). Such an offset may be introduced by components used to generate one or more low-frequency clock signals, or may be caused by noise or duty cycle errors in the high-frequency clock signal (e.g., which may be used as a basis for or correlated with the low-frequency clock signal).

[0026] According to the technology described herein, a memory device can correct phase errors or changes by adopting a correction scheme, which can include two stages of duty cycle adjustment. The correction scheme can include generating multiple (e.g., four) low-frequency clock signals from a high-frequency clock signal and its inverse signal. The low-frequency clock signals can be evenly spaced apart in phase (e.g., offset by 90°), plus or minus phase errors in some cases. In the first duty cycle adjustment stage, as an example, the duty cycles of low-frequency clock signals with phases of 0° and 180° can be adjusted so that they match (e.g., both are 50%, so that the duration of the high phase is equal to the duration of the low phase). Similarly, the duty cycles of low-frequency clock signals with phases of 90° and 270° can be adjusted so that they match (e.g., both are 50%, so that the duration of the high phase is equal to the duration of the low phase). Therefore, at the end of stage one, the edges of the 0° and 180° clock signals can be aligned with each other, and the edges of the 90° and 270° clock signals can be aligned with each other. However, the two pairs of clock signals may still be incorrectly offset relative to each other.

[0027] In order to provide appropriate spacing between multiple sets of clock signals (e.g., 90° between all four low-frequency clock signals), a low-frequency clock signal with an adjusted duty cycle can be used to generate a clock signal and its inverse signal, both of which can have the same frequency as the high-frequency clock signal. If the clock signal and its inverse signal have different duty cycles, the difference between the duty cycles can be used as a basis for setting or adjusting the second duty cycle adjustment stage. In this stage, the duty cycle of the incoming high-frequency and / or its inverse signal can be adjusted. After implementing stage two, multiple (e.g., all four low-frequency) clock signals distributed by the device can be evenly spaced in the phase domain.

[0028] In the case of memory devices, systems and circuits supporting multi-phase clock correction, reference is made to Figure 1 and 2 The above disclosed features are further described. Figures 3 to 9 Describe specific examples, Figures 3 to 9 Circuitry for implementing clock correction and associated waveforms is illustrated. Fig.10 To further illustrate these and other features of the present disclosure, Fig.10 A flow chart for supporting multi-phase clock correction is illustrated.

[0029] Figure 1An example of a system 100 supporting phase clock correction according to examples disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of illustration, the one or more memory devices may be described as a single memory device 110.

[0030] System 100 may be an example of an electronic device (e.g., a computing device, a mobile computing device, a wireless device, or a graphics processing device). System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. Memory device 110 may be a component of a system configured to store data of one or more other components of system 100. In some examples, system 100 may be configured to perform two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0031] At least a portion of the system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host or a host device.

[0032] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide physical memory addresses / space for potential use or reference by system 100. In some instances, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0033] The memory device 110 may be configured to store data of components of the system 100. In some cases, the memory device 110 may be used as a slave-type device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0034] System 100 may also include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may use a bus 140 to electronically communicate with each other.

[0035] The processor 120 may be configured to control at least a portion of the control system 100. The processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In this case, the processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system on a chip (SoC), etc.

[0036] The BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of the system 100. The BIOS component 125 may also manage the data flow between the processor 120 and the various components of the system 100 (e.g., the peripheral components 130, the input / output controller 135, etc.). The BIOS component 125 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0037] Peripheral component 130 may be any input device or output device, or an interface to such devices, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0038] Input / output controller 135 may manage data communications between processor 120 and peripheral components 130, input 145, or output 150. Input / output controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, input / output controller 135 may represent a physical connection or port to an external peripheral component.

[0039] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with other devices or interfaces between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by input / output controller 135.

[0040] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by input / output controller 135.

[0041] The components of system 100 may be composed of general or special purpose circuitry designed to perform its functions. This may include various circuit elements (e.g., wires (e.g., traces or transmission lines), transistors, capacitors, inductors, transformers, resistors, amplifiers) or other active or passive elements configured to perform the functions set forth herein.

[0042] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0043] The memory device 110 may be an example of a two-dimensional (2D) memory cell array, or may be an example of a three-dimensional (3D) memory cell array. For example, a two-dimensional memory device may include a single memory die 160. A three-dimensional memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a three-dimensional memory device, multiple memory dies 160-N may be stacked on each other or adjacent to each other. In some cases, the memory dies 160-N in a three-dimensional memory device may be referred to as a level, a level, a layer, or a die. A three-dimensional memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). Compared to a single two-dimensional memory device, this may increase the number of memory cells that can be positioned on a substrate, which in turn may reduce production costs or improve the performance of the memory array, or both. In some three-dimensional memory devices, different levels can share at least one common access line, such that some levels can share at least one of a word line, a digit line, and / or a plate line.

[0044] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, the one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 will store specific data on behalf of a component of the system 100 (e.g., the processor 120) or a read command indicating that the memory device 110 will provide specific data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0045] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Additionally, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110, as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. As such, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0046] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may serve as a connection between components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 for the external memory controller 105 to satisfy. The external memory controller 105 may convert or translate communications exchanged between components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. The clock signal may control the timing of operations within the system 100. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0047] The system clock signal may be a first clock signal (e.g., a high frequency clock signal) having a frequency higher than the cutoff frequency of a trace used to transmit signals throughout the system 100. Thus, in some cases, the external memory controller 105 may use the system clock signal to generate multiple (e.g., four) clock signals having different (e.g., lower) frequencies (e.g., a frequency that is half the frequency of the system clock signal). The different (e.g., lower) frequency clock signals may convey the same information as the first clock signal (e.g., the high frequency system clock signal), but may be distributed throughout the system 100 without being degraded by the low pass filter quality of one or more components.

[0048] In some cases, the external memory controller 105 or other components of the system 100 described herein, or the functionality thereof, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functionality thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (either separate from or included in processor 120 ).

[0049] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115. Additional signal paths may be coupled to the terminals of a channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths leading to the interior of memory device 110 or a component thereof (e.g., leading to the interior of memory die 160)) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0050] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, channel 115 may be an aggregate channel and, therefore, may include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and the like. Signals conveyed through the channel may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on the rising edge of a clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. Signals conveyed through the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded for each clock cycle.

[0051] In some cases, the channel 115 may include one or more command and address (CA) channels 186. The command and address channels 186 may be configured to communicate commands between the external memory controller 105 and the memory device 110, the commands including control information associated with the commands (e.g., address information). For example, the command and address channel 186 may include a read command with an address of desired data. In some cases, the command and address channel 186 may be recorded on a rising clock signal edge and / or a falling clock signal edge. In some cases, the command and address channel 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0052] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The clock signal channel 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal path of the clock signal channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The clock signal channel 188 may include any number of signal paths. In some cases, the clock signal (CK) (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal (CK) may therefore be variously referred to as a control clock signal (CK), a command clock signal (CK), or a system clock signal (CK). The system clock signal (CK) may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.) In some cases, the system clock signal may be used as the basis for a lower frequency clock signal that represents the same information as the system clock signal.

[0053] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0054] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0055] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference for general access operations of the memory device 110 (e.g., a timing reference for both read operations and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The write clock signal channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal) and the signal path of the write clock signal channel may be configured accordingly. The write clock signal channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0056] In some cases, other channels 192 may include one or more error detection code (EDC) channels. Error detection code channels may be configured to pass error detection signals (eg, checksums) to improve system reliability. Error detection code channels may include any number of signal paths.

[0057] The channel 115 may couple the external memory controller 105 with the memory device 110 using a variety of different architectures. The various architecture examples may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer (e.g., a silicon interposer), or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0058] A variety of different modulation schemes may be used to modulate the signals communicated over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0059] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0060] As described above, system 100 may distribute some clock signals (e.g., low-frequency clock signals) derived from one or more other clock signals (e.g., higher-frequency clock signals). As an example, if appropriately offset in phase, the edges of the low-frequency clock signal may represent the same timing information as the higher-frequency clock signal. However, if non-ideal components of system 100 introduce phase errors into the low-frequency clock, the low-frequency clock may lose the timing information of the higher-frequency clock (e.g., the timing information may become distorted).

[0061] According to the techniques described herein, system 100 can correct phase errors in a low-frequency clock signal constructed based on a high-frequency clock signal. System 100 can first adjust the duty cycle of the low-frequency clock signal so that they match. After adjusting the duty cycle of the low-frequency clock, system 100 can use the low-frequency clock signal to construct a full-frequency clock signal (e.g., a clock signal having the same frequency as the high-frequency clock signal) and, in some instances, to construct its inverse signal. System 100 can also adjust the duty cycle of the high-frequency clock based on the duty cycle of the full-frequency clock signal and its inverse signal.

[0062] Figure 2An example of a memory die 200 supporting phase clock correction according to an example disclosed herein is shown. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is illustrated. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0063] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) representing digital data. In a ferroelectric random access memory architecture, the memory cell 205 may include a capacitor, which may include a ferroelectric material to store a charge and / or polarization representing a programmable state. In a dynamic random access memory architecture, the memory cell 205 may include a capacitor, which may include a dielectric material to store a charge representing a programmable state.

[0064] By activating or selecting access lines such as word lines 210, digit lines 215, and / or plate lines 220, operations such as reading and writing can be performed on memory cells 205. The timing of the operations can be controlled based on one or more clock signals. In some cases, digit lines 215 can also be referred to as bit lines. References to access lines, word lines, digit lines, plate lines, or the like are interchangeable without loss of understanding or operation. Activating or selecting word lines 210, digit lines 215, or plate lines 220 can include applying a voltage to the corresponding line.

[0065] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of the word lines 210, digit lines 215, and / or plate lines 220. By biasing the word lines 210, digit lines 215, and plate lines 220 (e.g., applying voltages to the word lines 210, digit lines 215, or plate lines 220), individual memory cells 205 may be accessed at their intersections.

[0066] Access to the memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from a local memory controller 265 and activate a word line 210 based on the received row address. The column decoder 230 may receive a column address from a local memory controller 265 and activate a digit line 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and may activate a plate line 220 based on the received plate address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M, a plurality of digit lines 215 labeled DL_1 to DL_N, and a plurality of plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating a word line 210, a digit line 215, and a plate line 220, such as WL_1, DL_3, and PL_1, a memory cell 205 at their intersection may be accessed. In a two-dimensional or three-dimensional configuration, the intersection of word line 210 and digit line 215 can be referred to as the address of memory cell 205. In some cases, the intersection of word line 210, digit line 215, and plate line 220 can be referred to as the address of memory cell 205.

[0067] The memory cell 205 may include a logic storage component, such as a capacitor 240, and a switch component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switch component 245 and a second node of the capacitor 240 may be coupled to the plate line 220. The switch component 245 may be an example of a transistor or any other type of switching device that selectively establishes or releases electronic communication between two components.

[0068] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the switch component 245. The capacitor 240 can be in electronic communication with the digital line 215 using the switch component 245. For example, when the switch component 245 is deactivated, the capacitor 240 can be isolated from the digital line 215, and when the switch component 245 is activated, the capacitor 240 can be coupled to the digital line 215. In some cases, the switch component 245 is a transistor and its operation is controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. In some cases, the switch component 245 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switch component 245 and the switch component 245 can be activated / deactivated based on the voltage applied to the word line 210.

[0069] The word line 210 may be a conductive line used to perform access operations on the memory cell 205 in electronic communication therewith. In some architectures, the word line 210 may be in electronic communication with the gate of the switch element 245 of the memory cell 205 and may be configured to control the switch element 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with the node of the capacitor of the memory cell 205 and the memory cell 205 may not include a switch element.

[0070] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the switching component 245 of the word line 210 and the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 and the digit line 215 of the memory cell 205. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0071] Plateline 220 may be a conductive line used to perform access operations on a memory cell 205 in electronic communication therewith. Plateline 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. Plateline 220 may be configured (e.g., along with digitline 215) to bias capacitor 240 during access operations of memory cell 205.

[0072] The sensing component 250 may be configured to determine a state (e.g., a polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. In some cases, the charge stored in the memory cell 205 may be extremely small. In this case, the sensing component 250 may include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sense amplifier may detect a small change in the charge of the digital line 215 during a read operation and may generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 may output a signal (e.g., discharge) to its corresponding digital line 215. The signal may cause the voltage of the digital line 215 to change.

[0073] The sensing component 250 may be configured to compare the signal received by the memory cell 205 at both ends of the digit line 215 with a reference signal 255 (e.g., a reference voltage). The sensing component 250 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 255, the sensing component 250 may determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 255, the sensing component 250 may determine that the storage state of the memory cell 205 is a logic 0.

[0074] The sensing component 250 may include various transistors or amplifiers to detect and amplify differences in one or more signals. The detected logic state of the memory cell 205 may be provided as an output of the sensing component 250 (e.g., to the input / output 260), and the detected logic state may be indicated to another component of the memory device 110 including the memory die 200, such as the device memory controller 155 (e.g., directly or using a local memory controller 265). In some cases, the sensing component 250 may be in electronic communication with the row decoder 225, the column decoder 230, the plate driver 235, or other components, or any combination thereof.

[0075] The local memory controller 265 may control the operation of the memory cell 205 through various components (eg, the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250). The local memory controller 265 may be a reference Figure 1 105. In some cases, one or more of the row decoder 225, column decoder 230, and plate driver 235, as well as the sensing component 250, may be co-located with the local memory controller 265. The local memory controller 265 may be configured to receive data from the external memory controller 105 (or reference 105). Figure 1 The local memory controller 265 may receive one or more commands and / or data, translate the commands and / or data into information that the memory die 200 may use, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. The local memory controller 265 may generate row, column, and / or plate line address signals to activate the target word lines 210, the target digit lines 215, and the target plate lines 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein may be adjustable or varied and may be different for the various operations discussed in operating the memory die 200.

[0076] In some cases, the local memory controller 265 can be configured to perform a precharge operation on the memory die 200. The precharge operation can include precharging one or more components and / or access lines of the memory die 200 to one or more voltage levels. In some cases, the memory cells 205 and / or portions of the memory die 200 can be precharged between different access operations. In some cases, the digit lines 215 and / or other components can be precharged prior to a read operation.

[0077] In some cases, the local memory controller 265 can be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 265 can identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 265 can identify a target word line 210, a target digit line 215, and / or a target plate line 220 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. During a write operation, the local memory controller 265 may apply a specific signal (e.g., voltage) to the digit line 215 and a specific signal (e.g., voltage) to the plate line 220 to store a specific state in the capacitor 240 of the memory cell 205, wherein the specific state indicates a desired logical state.

[0078] In some cases, the local memory controller 265 can be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 265 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 265 can identify the target word line 210, the target digit line 215, and / or the target plate line 220 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 can activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205.

[0079] The target memory cell 205 may send a signal to the sensing component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. The local memory controller 265 may activate the sensing component 250 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on this comparison, the sensing component 250 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 265 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller).

[0080] In some memory architectures, accessing a memory cell 205 may degrade or destroy the logical state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell may destroy the logical state stored in the ferroelectric capacitor. In another example, a read operation performed in a dynamic random access memory architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 265 may perform a rewrite operation or a refresh operation to return the memory cell to its original logical state. The local memory controller 265 may rewrite the logical state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line such as a word line 210 may interfere with the state stored in some memory cells that are in electronic communication with this access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not be accessed.

[0081] The timing of various operations of the memory die 200 may be controlled by or based on timing information conveyed by one or more clock signals. The clock signals may be low-frequency clock signals, which may be generated from a high-frequency clock signal (and, in some cases, its inverse). The memory die 200 may correct for phase errors in the low-frequency clock signal by adjusting the duty cycle of the low-frequency clock signal and then using the adjusted low-frequency clock signal as a basis for adjusting the duty cycle of the high-frequency clock signal (and, in some cases, its inverse).

[0082] Figure 3 An example of a clock circuit system 300 supporting phase clock correction according to an example disclosed herein is illustrated. The clock circuit system may include a receiving circuit 305, a clock divider 310, and a clock correction circuit system 315. The receiving circuit 305 may receive a high-frequency clock as an input and generate its inverse signal. The inverse signal of the signal may be a version of the signal that is shifted 180° in phase. A signal and its inverse signal may be referred to herein as differential signals, and the inverse signal version of the signal may be represented by a prime (e.g., the inverse signal version of signal A may be represented as A'). Therefore, the receiving circuit 305 may output a differential clock signal including a high-frequency clock signal (Clock) and its inverse signal (Clock').

[0083] The differential clock signal may be received by a clock divider 310, which may generate a plurality of (e.g., four) low-frequency clock signals based on Clock and Clock'. The low-frequency clock signal may have half the frequency of the high-frequency clock signal and may be offset in phase by 90° (e.g., in an ideal system) or close to 90° (e.g., in a non-ideal system). Thus, in a non-ideal system, the clock divider 310 may output a first clock signal having a phase offset of exactly or approximately 0°, a second clock signal having a phase offset of exactly or approximately 90°, a third clock signal having a phase offset of exactly or approximately 180°, and a fourth clock signal having a phase offset of exactly or approximately 270°. The difference between the ideal phase of the clock signal and its approximate phase may be referred to as a phase error or variation of the signal. Such an error or variation may be caused by irregularities in components of the receiving circuit 305, the clock divider 310, or irregularities caused by components of the receiving circuit 305, the clock divider 310, or by noise or duty cycle errors in the high-frequency clock.

[0084] According to the techniques described herein, clock correction circuit system 315 can correct phase errors by adjusting the duty cycle of the high-frequency clock signal and its inverse signal and the duty cycle of the low-frequency clock signal. Therefore, the output of clock correction circuit system 315 can be a low-frequency signal (e.g., a signal with a lower frequency than the other, high-frequency clock signal) with an ideal duty cycle and an ideal phase. Although shown as separate circuits, the components of clock correction circuit system 315 can be distributed throughout clock circuit system 300, or can be included or integrated in a single component.

[0085] Figure 4 An example of a clock signal 400 supporting phase clock correction according to an example disclosed herein is shown. The clock signal with a solid line may be as shown in FIG. Figure 3 4. The ideal clock signals (e.g., clock 0°, clock 90°, clock 180°, and clock 270°) output (or should be output) by the clock correction circuit system 315 are described. Therefore, the clock signal 400 may include clock signals with phases of 0°, 90°, 180°, and 270°. Each clock signal may have a period and a duty cycle. The period of a clock signal may be the duration between rising (or falling) edges of the signal. For example, the period of the ideal clock 0° may be period 405. The duty cycle of a clock signal may be the ratio of the phase (e.g., high phase) to the period. For example, the duty cycle of the ideal clock 0° may be duty cycle 410.

[0086] The dashed clock signal may represent a non-ideal clock signal, which may be output by the clock divider 310 in some instances. The non-ideal clock signal may have an incorrect duty cycle (e.g., a duty cycle different from 50%, as shown by the non-ideal clock signals corresponding to clock 0° and clock 180°), and / or may be delayed incorrectly (e.g., incorrectly offset in phase, as shown by the non-ideal clock signals corresponding to clock 90° and clock 270°). The difference between the edge of the clock signal output by the clock divider 310 and the edge of the ideal clock signal may represent a phase error or a delay error. If not corrected, the non-ideal clock signal may convey incorrect timing information due to the incorrect location of the rising and falling clock edges. Therefore, correcting the clock signal may improve the operation of a device that uses the clock signal to control the timing of its operations.

[0087] According to the techniques described herein, a duty cycle adjustment scheme may be used to correct for multiple non-ideal clock signals. In some examples, this scheme may include a two-stage duty cycle adjustment scheme. The first stage of duty cycle adjustment may correct the duty cycles of the clock signals so that they are equal (e.g., 50%, so that the duration of the high phase is half the cycle duration). The second stage of duty cycle adjustment may correct the phase offset between the clock signals. In some alternative embodiments, the correction of the phase offset between the clock signals may occur simultaneously or before the correction of the duty cycles of the clock signals so that they are equal.

[0088] Figure 5 An example of a clock circuit system 500 supporting phase clock correction according to an example disclosed herein is shown. The clock circuit system 500 may be a reference Figure 3 1. An example of clock circuit system 300 is described. Clock circuit system 500 may include receiving circuit 505, duty cycle correction (DCC) circuit 510, clock divider 515, duty cycle correction circuit 520, duty cycle correction controller 525, and discriminator 530. The components of clock circuit system 500 may be coupled via one or more traces (also referred to herein as transmission lines). Clock circuit system 500 may correct phase error through one or more duty cycle adjustment stages. In some examples, a first duty cycle adjustment stage may be implemented by duty cycle correction circuit 520, and a second duty cycle adjustment stage may be implemented by duty cycle correction circuit 510.

[0089] The receiving circuit 505 may receive a clock signal (clock_i) from another component (e.g., a component external to the clock circuit system 500). The clock signal clock_i may be referred to as a high-frequency clock signal because its frequency is higher than the clock signal generated by the clock divider 515. The receiving circuit 505 may generate an inverse signal (clock_i') for the clock signal and output both signals to the duty cycle correction circuit 510. The duty cycle correction circuit 510 may receive a differential pair of high-frequency clock signals and generate four clock signals that are offset from each other by the same phase (e.g., 90°) plus or minus one or more phase errors (e.g., x°). Thus, the duty cycle correction circuit 510 may generate and output the following clock signals: clock 0°, clock 90°, clock 180°, and clock 270°. The four clock signals may have the same frequency and may be referred to as low-frequency or half-frequency clock signals because their frequencies are lower than the frequency of the input clock (e.g., half). In addition to the phase error, the four clock signals may also have a duty cycle error (e.g., a duty cycle different from 50%).

[0090] The duty cycle correction circuits 520 may each receive a differential pair of low-frequency clock circuits (e.g., a pair of clock signals offset by approximately 180°). For example, the duty cycle correction circuit 520-a may receive clock 0° and clock 180°. And the duty cycle correction circuit 520-b may receive clock 90° and clock 270°. Each duty cycle correction circuit 520 may adjust the duty cycle of one or both of its input low-frequency clock signals. For example, the duty cycle correction circuit 520-a may adjust the duty cycle of clock 0° and / or clock 180°. And the duty cycle correction circuit 520-b may adjust the duty cycle of clock 90° and / or clock 270°. Although shown as separate components, the duty cycle correction circuit 520-a and the duty cycle correction circuit 520-b may be located at the same location or as part of the same component.

[0091] The duty cycle adjustment provided by the duty cycle correction circuit 520 may be based on a control signal (e.g., a digital control code) received from the duty cycle correction controller 525. The control signal may indicate to the duty cycle correction circuit 520 the amount by which to modify the duty cycle of the clock signal. The control signal may be based on a comparison of the duty cycles of the clock signals output by the duty cycle correction circuit 520. For example, the duty cycle correction circuit 520-a may output clock 0° and clock 180°, one or both of which may have an adjusted duty cycle. The duty cycle correction controller 525-a may compare the duty cycles of the output clock 0° and clock 180° to determine if there is a mismatch. If the duty cycles are different, the duty cycle correction controller 525-a may control the duty cycle correction circuit 520-a so that the duty cycle adjustment provided by the duty cycle correction circuit 520-a produces a clock signal with the same duty cycle (e.g., 50%). Duty cycle correction circuit 520 - b and duty cycle correction controller 525 - b may follow a similar process.

[0092] Adjusting the duty cycle of the low frequency clock signal may correct the duty cycle (e.g., so that they are both 50%). Additionally, the adjustment may shift the edges of the clock signal so that the edges of the differential clock pair are aligned (e.g., the rising edge of clock 0° may coincide with the falling edge of clock 180°, and vice versa). Thus, after adjustment by the duty cycle correction circuit 520, clock 0° and clock 180° may be aligned in phase (e.g., offset by 180°), and clock 90° and clock 270° may be aligned in phase (e.g., offset by 180°). However, the differential clock pairs may still be incorrectly offset from each other.

[0093] The low-frequency clock signal output by the duty cycle correction circuit 520 can be transmitted to components external to the clock circuit system 500 (e.g., for timing external operations) and the discriminator 530. Upon receiving the low-frequency clock signal, the discriminator 530 can generate a full-frequency clock signal (clock_f) and its inverse signal (clock_f') based on the low-frequency clock signal. The full-frequency clock and its inverse signal can have the same frequency as the high-frequency clock received by the duty cycle correction circuit 510. Therefore, the frequency of the full-frequency clock and its inverse signal may be twice that of the low-frequency clock signal.

[0094] The differential clock signal generated by the discriminator 530 can be transmitted to the duty cycle correction controller 525-c, which can compare the duty cycles of the clock signals. Based on the comparison, the duty cycle correction controller 525-c can generate a control signal (e.g., a control code) that instructs the duty cycle correction circuit 510 how to adjust the duty cycle of the incoming clock signals clock_i and clock_i'. Therefore, the duty cycle correction controller 525-c can control the duty cycle adjustment provided by the duty cycle correction circuit 510 based on the clock signals clock_f and clock_f', which in turn is based on the low-frequency clock signal. After the duty cycle correction circuit 510 has modified its duty cycle adjustment as instructed by the duty cycle correction controller 525-c, the differential clock signals (e.g., clock and clock') output by the duty cycle correction circuit 510 can be aligned in phase. The alignment of clock and clock′ results in an ideal offset between the differential pair clocks 0° / 180° and 90° / 270°, which enables the duty cycle correction circuit 520 to output an ideal low frequency clock signal (eg, a low frequency clock signal with a duty cycle and a phase).

[0095] In some cases, the clock circuit system 500 may include a duty cycle correction controller 525-d. The duty cycle correction controller 525-d may receive clock_i and clock_i' as inputs and output a control signal to the duty cycle correction circuit 510 based on the duty cycles of clock_i and clock_i'. The duty cycle correction controller 525-d may correct initial duty cycle errors in clock_i and clock_i'. If not corrected, these duty cycle errors may be severe enough to disrupt the operation of the clock divider 515.

[0096] Figure 6 An example of a clock signal 600 supporting phase clock correction according to examples disclosed herein is illustrated. Clock signal 600 may include clock signal 600-a, which may represent a low-frequency clock signal output by duty cycle correction circuit 520 after a first stage of duty cycle adjustment has occurred (e.g., after duty cycle correction circuit 520 has applied duty cycle adjustment, but before duty cycle correction circuit 510 has applied duty cycle adjustment). Clock signal 600 may also include clock signal 600-b, which in some examples may represent a low-frequency clock signal output by duty cycle correction circuit 520 after a second stage of duty cycle adjustment has occurred (e.g., after both duty cycle correction circuit 510 and duty cycle correction circuit 520 have applied duty cycle adjustment).

[0097] As shown in clock signal 600-a, after the first stage of duty cycle correction, the duty cycles of the low frequency clocks may be equal (e.g., 50%). Additionally, the edges of clock 0° and clock 180° may be aligned relative to each other, and the edges of clock 90° and clock 270° may be aligned relative to each other. However, the differential clock signal pairs may still be incorrectly offset from each other. For example, the edges of clock 90° and 270° may be offset from the midpoint of the high phase of clock 0° and from the midpoint of the low phase of clock 180°. Such offsets may be referred to as phase or delay errors.

[0098] After the second stage of duty cycle correction, the phase error may be reduced or eliminated. As shown in clock signal 600-b, after the second stage of duty cycle correction, the low frequency clock signal may be evenly dispersed in the phase domain (e.g., offset by 90°). Therefore, the timing information of the high frequency clock may be preserved.

[0099] Figure 7 An example of a duty cycle correction controller 700 supporting phase clock correction according to examples disclosed herein is illustrated. The duty cycle correction controller 700 can compare the duty cycles of two clock signals (e.g., a clock signal and its inverse signal) and output a control code (e.g., to the duty cycle correction circuit 520) based on the difference between the duty cycles. The duty cycle correction controller 700 can be as described in reference to Figure 5 An example of a duty cycle correction controller 525 is illustrated. The duty cycle correction controller 700 may include an integrator 705 and a control component 710. The control component may be one or more operational amplifiers (op amps), logic circuits, a digital engine, or a processor.

[0100] Each integrator 705 may include a resistive component, such as a resistor 715, and a capacitive component, such as a capacitor 720. The resistor 715 and the capacitor 720 may be coupled to each other (e.g., connected in series), and the capacitor may be coupled to a ground reference 725. The voltage at the node between the resistor 715 and the capacitor 720 may represent the output of the integration of the input clock signal. Thus, the voltage at node A may represent the output of the integration of clock_1, and the voltage at node B may represent the output of the integration of clock_1'. By comparing the voltages at nodes A and B, the control component 710 may determine whether the duty cycles of the clock signals are equal. This is because equal duty cycles will result in equal voltages at nodes A and B, while unequal duty cycles will result in a higher voltage at the node with the higher duty cycle.

[0101] For illustration, the duty cycle correction controller 700 can receive multiple clock signals as inputs. For example, the duty cycle correction controller 700 can receive clock_1 and clock_1', which can be differential clock signals output by the duty cycle correction circuit 520. The duty cycle correction controller 700 can integrate each signal (e.g., over a plurality of cycles, such as 100), and compare the results of each integration. For example, the control component 710 can compare the voltage on node A with the voltage on node B to determine the difference between the voltages.

[0102] If one of the voltages is higher than the other voltage, the control component 710 may output information (e.g., a code, an indication, one or more bits) indicating that the corresponding duty cycle correction circuit will adjust its configuration to provide a different duty cycle adjustment for one or both of the clock signals. For example, if the voltage on node A is higher than the voltage on node B, the code may indicate that the duty cycle correction circuit will reduce the duty cycle of clock_1 and / or increase the duty cycle of clock_1'. If there is no difference between the voltages, the duty cycle correction controller 700 may suppress the output code. Alternatively, the duty cycle correction controller 700 may output a code indicating that the corresponding duty cycle correction circuit will maintain its current configuration for duty cycle adjustment.

[0103] Figure 8 An example of a circuit system 800 supporting phase clock correction according to an example disclosed herein is illustrated. The circuit system 800 may include a plurality of nodes labeled A to F, which will be referred to as Fig. 9 The circuit system 800 may also include a discriminator 805 and a duty cycle correction controller 810. The discriminator 805 may be a reference Figure 5 The example of the discriminator 530 described above and the duty cycle correction controller 810 may be referred to as Figure 5 The example of duty cycle correction controller 525 described herein or with reference to Figure 7 An example of the duty cycle correction controller 700 is described. The discriminator 805 can generate a pair of differential clock signals (e.g., a full-frequency clock signal and its inverse signal) based on the low-frequency clock signal. Based on the duty cycle of the differential clock signal output by the discriminator 805, the duty cycle correction controller 810 can output (e.g., to the duty cycle correction circuit 520) a control code.

[0104] The discriminator 805 may include a plurality of logic gates, such as NAND gates 815. A set of NAND gates 815 (e.g., NAND gates 815-a, 815-b, 815-d, and 815-e) may receive a pair of low-frequency clock signals as inputs. For example, the NAND gate 815-a may receive clock 0° and clock 270°, the NAND gate 815-b may receive clock 180° and clock 90°, the NAND gate 815-d may receive clock 0° and clock 90°, and the NAND gate 815-e may receive clock 270° and clock 180°. Therefore, the NAND gates 815-a, 815-b, 815-d, and 815-e may each receive a unique combination of low-frequency inputs.

[0105] The outputs of NAND gates 815-a, 815-b, 815-d, and 815-e may be coupled to the inputs of other NAND gates 815. For example, NAND gates 815-a and 815-b may be coupled to NAND gate 815-c, and NAND gates 815-d and 815-e may be coupled to NAND gate 815-f. Thus, NAND gate 815-c may receive the results of two NAND gate operations from NAND gates 815-a and 815-b. Similarly, NAND gate 815-f may receive the results of two NAND gate operations from NAND gates 815-a and 815-b. 815-c may perform a NAND gate operation on its input and output the result (e.g., a full-frequency clock signal) to the first input of duty cycle correction controller 810. Similarly, 815 - f may perform a NAND operation on its inputs and output the result (eg, the inverted signal of the full frequency clock signal) to a second input of the duty cycle correction controller 810 .

[0106] As reference Figure 7 As discussed, the duty cycle correction controller 810 may integrate the clock signal received from the NAND gate 815-c and the clock signal received from the NAND gate 815-f. The voltage level generated by the integration may be input to the control component 820, which may be a reference Figure 7 An example of control component 710 is illustrated. Control component 820 can compare voltage levels to determine the duty cycle of the full frequency clock signal. Based on the comparison, duty cycle correction controller 810 can output a control code (eg, to a duty cycle correction circuit).

[0107] Although described with reference to a NAND gate, discriminator 805 may be implemented using any type of logic gate, including AND gates, OR gates, NOR gates, XOR gates, etc.

[0108] Fig. 9An example of a waveform 900 supporting phase clock correction according to an example disclosed herein is illustrated. Waveform 900 may represent input and output signals of various components of circuit system 800. For example, clock 0°, clock 90°, clock 180°, and clock 270° may represent low-frequency clock signals input to NAND gates 815-a, 815-b, 815-d, and 815-f. And waveforms A to G may represent signals present on nodes A to G, respectively. Waveform 900-a is an example of a waveform that appears when clock signals clock 90° and clock 270° are delayed (e.g., delayed or offset in the phase domain). Waveform 900-b is an example of a waveform that appears when the low-frequency clock signals have an ideal phase offset (e.g., 90° apart in the phase domain).

[0109] like Figure 8 As shown, the voltage on node A at any given time may be the result of a NAND operation on clock 0° and clock 270°, and the voltage on node B at any given time may be the result of a NAND operation on clock 90° and 180°. The voltage on node D at any given time may be the result of a NAND operation on clock 0° and clock 90°, and the voltage on node E at any given time may be the result of a NAND operation on clock 180° and 270°. In addition, the voltage on node C at any given time may be the result of a NAND operation on waveforms A and B. And the voltage on node F at any given time may be the result of a NAND operation on waveforms D and E. When considered in terms of time, the voltage on node C may represent the full frequency clock signal and the voltage on node F may represent the inverse signal of the full frequency clock signal.

[0110] As illustrated by waveform 900-a, an incorrect offset between the low frequency clock signals (e.g., a delay in clock 90° and clock 270°) results in a full frequency clock signal having a non-ideal duty cycle (e.g., a duty cycle different from 50%). For example, the waveform generated at node C may be a clock signal with a duty cycle greater than 50%, and its inverse signal, i.e., the waveform generated at node F, may be a clock signal with a duty cycle less than 50%.

[0111] Since the duty cycle of the full frequency clock signal is not 50%, integrating the waveforms at nodes C and F may result in voltages of different levels. For example, the voltage at node G may be greater than the voltage at node H. If the two voltages are not equal, the control component 820 may instruct (e.g., via control code) its associated duty cycle correction circuit (e.g., duty cycle correction circuit 510) to modify the duty cycle adjustment it provides. The new duty cycle adjustment may be based on the voltage difference at G and H (and therefore may be based on the duty cycle difference between the waveforms at C and F).

[0112] As illustrated by waveform 900-b, a low-frequency clock signal with an ideal phase generates a clock signal with a duty cycle of 50%. For example, the waveform generated on node C is a clock signal with a duty cycle of 50%. And the waveform generated on node F is the inverse signal of the waveform generated on C. The clock signal is a full-frequency clock signal because its frequency is twice that of the low-frequency clock signal. Therefore, when the low-frequency clock signal is evenly spaced in the phase domain, the circuit system 800 can output the full-frequency clock signal and its inverse signal with a 50% duty cycle.

[0113] Since the full frequency clock signal has a 50% duty cycle, integrating the waveforms at nodes C and F may produce voltages of the same level. For example, the voltage at node G may be equal to the voltage at node H. If the two voltages are equal, the control component 820 refrains from sending a control code to its associated duty cycle correction circuit (e.g., duty cycle correction circuit 510). Alternatively, the control component 820 may transmit a control code instructing the duty cycle correction circuit to maintain its current level of duty cycle adjustment.

[0114] Fig.10 A flow chart illustrating a method 1000 for supporting phase clock correction according to various examples disclosed herein is shown. The operations of the method 1000 may be implemented by the device or components thereof described herein. In some examples, a memory controller may execute a set of instructions to control functional elements of the device to implement the functions described below. Additionally or alternatively, the device may use dedicated hardware to implement the functions described below.

[0115] At 1005, the method may include receiving a first set of clock signals. The first set of clock signals may include two clock signals (e.g., Figure 5 The operation of 1005 can be performed according to the reference clock and clock'. Figures 3 to 9 In some examples, the operation of 1005 can be performed by referring to Figure 5 The duty cycle correction circuit 510 is described to implement this.

[0116] At 1010, the method may include generating a plurality of clock signals that are offset in phase from one another based at least in part on the first set of clock signals. The plurality of clock signals may include four clock signals (e.g., referring to Figures 3 to 9 The operation of 1010 can be performed according to the reference clock 0°, 90°, 180° and 270°. Figures 3 to 9 In some examples, the operation of 1010 can be performed by referring to Figure 3 and 5 This is done using the clock divider described above.

[0117] At 1015, the method may include adjusting a duty cycle of at least one of the plurality of clock signals. The operation of 1015 may be based on reference Figures 3 to 9 In some examples, the operation of 1015 can be performed by referring to Figure 5 The duty cycle correction circuit 520 is described to implement this.

[0118] At 1020, the method may include receiving a second set of clock signals. The first set of clock signals and the second set of clock signals may be received from the same source (e.g., a clock) via the same set of transmission lines. Thus, the first set of clock signals may be those signals received during a first time period, and the second set of clock signals may be those signals received during a second, later time period. In some examples, the first set of clock signals and the second set of clock signals have a first frequency (e.g., f1), and the plurality of clock signals have a second frequency (e.g., f1 / 2) different from the first frequency. The operation of 1020 may be based on reference Figures 3 to 9 In some examples, the operation of 1020 can be performed by referring to Figure 5 The duty cycle correction circuit 510 is described to implement this.

[0119] At 1025, the method may include adjusting the duty cycle of at least one of the second set of clock signals based at least in part on at least one clock signal having an adjusted duty cycle. The operation of 1025 may be based on reference Figures 3 to 9 In some examples, the operation of 1025 can be performed by referring to Figure 5 The duty cycle correction circuit 510 is described to implement this.

[0120] In some examples, the apparatus described herein may implement one or more methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a first set of clock signals; generating a plurality of clock signals offset in phase from one another based at least in part on the first set of clock signals; adjusting a duty cycle of at least one of the plurality of clock signals; receiving a second set of clock signals; and adjusting a duty cycle of at least one of the second set of clock signals based at least in part on at least one clock signal having an adjusted duty cycle.

[0121] In some examples, the apparatus described herein may implement one or more methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: determining a duty cycle difference between two of the plurality of clock signals after adjusting the duty cycle of the at least one clock signal; generating a new plurality of clock signals; and adjusting the duty cycle of at least one of the new plurality of clock signals based at least in part on the difference. In this case, the apparatus may also include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a third set of clock signals and adjusting the duty cycle of the third set of clock signals based at least in part on the new plurality of clock signals having the at least one adjusted duty cycle. The third set of clock signals may be received from the same source as the first set of clock signals and the second set of clock signals. Additionally or alternatively, the apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for integrating each of two of the plurality of clock signals, wherein a difference between the duty cycles is determined at least in part based on the integration.

[0122] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may also include operations, features, means, or instructions for: 1) generating a first clock signal (e.g., clock_f) and a second clock signal (e.g., clock_f') based at least in part on the plurality of clock signals; and 2) comparing a duty cycle of the first clock signal to a duty cycle of the second clock signal, wherein adjusting the duty cycle of the second set of clock signals is based at least in part on the comparison. In some cases, the first clock signal, the second clock signal, and the second set of clock signals have the same frequency.

[0123] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for adjusting the duty cycle of at least one of the clock signals by: 1) adjusting the duty cycle of a first clock signal that is offset in phase by 180 degrees from a second clock signal plus or minus a first phase error; and 2) adjusting the duty cycle of a third clock signal that is offset in phase by 180 degrees from a fourth clock signal plus or minus a second phase error. In some cases, the first set of clock signals and the second set of clock signals are received over the same set of transmission lines. In some cases, the first set of clock signals and the second set of clock signals have a first frequency and the plurality of clock signals have a second frequency that is different from the first frequency.

[0124] It should be noted that the above methods illustrate possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. In addition, steps of two or more methods may be combined.

[0125] In some examples, a device or apparatus may use general or special hardware to implement the functions described herein. The device or apparatus may include: a first circuit (e.g., duty cycle correction circuit 510) coupled to an input of a clock divider circuit (e.g., clock divider 515) and operable to adjust the duty cycle of a set of clock signals (e.g., clock_i and clock_i'); a second circuit (e.g., duty cycle correction circuit 520-a, duty cycle correction circuit 520-b, or a circuit including both) coupled to an output of the clock divider circuit and operable to adjust a plurality of clock signals (e.g., clock_i') output by the clock divider circuit 0°, 90°, 180° and / or 270°); a third circuit (e.g., discriminator 530) coupled to the second circuit and operable to output two clock signals based at least in part on the multiple clock signals, at least one of the multiple clock signals having a duty cycle adjusted by the second circuit; and a control component (e.g., duty cycle correction controller 525-c or a control component within duty cycle correction controller 525-c, such as control component 710) coupled to the third circuit and operable to modify the duty cycle adjustment provided by the first circuit based at least in part on the two clock signals.

[0126] In some cases, the clock division circuit is operable or configured to generate the plurality of clock signals based at least in part on the set of clock signals.

[0127] In some instances, the device or apparatus may include an integrator (e.g., an integrator within the duty cycle correction controller 525-a) coupled to the output of the second circuit and operable or configured to integrate a first clock signal (e.g., clock 0°) output by the second circuit. In this case, the device or apparatus may include a second control component (e.g., a control component within the duty cycle correction controller 525-a) coupled to the integrator and the input of the second circuit. In some instances, the device or apparatus may include a second integrator (e.g., a second integrator within the duty cycle correction controller 525-b) coupled to the second output of the second circuit and the input of the second control component (e.g., the control component within the duty cycle correction controller 525-a). The second integrator is operable or configured to integrate a second clock signal output (e.g., clock 180°) through the second circuit.

[0128] In some cases, the device or apparatus includes an integrator (e.g., an integrator within the duty cycle correction controller 525-c) coupled to the output of the third circuit and the input of the control component (e.g., the control component within the duty cycle correction controller 525-c). The integrator is operable or configured to integrate at least one of the two clock signals (e.g., clock_f and / or clock_f') output by the third circuit.

[0129] In some examples, the device or apparatus includes a circuit (e.g., receiving circuit 505) coupled to an input of the first circuit. The circuit is operable or configured to receive a first clock signal (e.g., clock_i) and provide the first clock signal and a second clock signal (e.g., clock_i') that is an inverse signal of the first clock signal to the first circuit. The set of clock signals may include the first clock signal and the second clock signal.

[0130] In some instances, the third circuit includes: 1) a first group of NAND gates (e.g., NAND gates 815-a, 815-b, and 815-c) operable or configured to output a first clock signal (e.g., clock_f) of the two clock signals to the control component; and 2) a second group of NAND gates (e.g., NAND gates 815-d, 815-e, and 815-f) operable to output a second clock signal (e.g., clock_f') of the two clock signals to the control component.

[0131] In some cases, the device or apparatus may include: a first circuit (e.g., duty cycle correction circuit 510) operable or configured to adjust the duty cycle of a first clock signal of two clock signals; a clock division circuit (e.g., clock divider 515) operable or configured to receive the two clock signals after adjusting the duty cycle of the first clock signal and generate four clock signals each offset in phase; a second circuit (e.g., duty cycle correction circuit 520-a) operable or configured to receive a first pair of the four clock signals and adjust the duty cycle of at least one of the first pair of clock signals; and a third circuit (e.g., duty cycle correction circuit 520-b) operable or configured to receive a second pair of the four clock signals and adjust the duty cycle of at least one of the second pair of clock signals.

[0132] In some cases, the apparatus or device may include a fourth circuit (e.g., discriminator 530) coupled to the second circuit and the third circuit. The fourth circuit is operable or configured to generate a third pair of clock signals based at least in part on the first pair and the second pair of the four clock signals. In these or other cases, the apparatus or device may include: a fifth circuit (e.g., a duty cycle correction controller 525-c or a combination of integrators 705-a and 705-b) operable or configured to integrate the third pair of clock signals; and a control component (e.g., a control component within the duty cycle correction controller 525-c) operable or configured to control the duty cycle adjustment provided by the first circuit based at least in part on the integration of the third pair of clock signals.

[0133] In some cases, the first pair of the four clock signals includes a first clock signal (e.g., clock 0°) having a first duty cycle adjusted by a second circuit (e.g., duty cycle correction circuit 520-a) and a second clock signal (e.g., clock 180°) having a second duty cycle. In these or other cases, the apparatus or device may include: a fourth circuit (e.g., duty cycle correction controller 525-a) operable or configured to compare the first duty cycle of the first clock signal with the second duty cycle of the second clock signal; and a control component (e.g., a control component within duty cycle correction controller 525-a) operable or configured to control the duty cycle adjustment provided by the second circuit based at least in part on the comparison. In some instances, the fourth circuit includes an integrator operable to integrate the clock signals in the first pair of clock signals.

[0134] In some cases, the second pair of the four clock signals includes a third clock signal having a third duty cycle adjusted by a third circuit (e.g., clock 90°) and a fourth clock signal having a fourth duty cycle (e.g., clock 270°). In these or other cases, the device or apparatus may include: a fifth circuit (e.g., a duty cycle correction controller 525-b) operable or configured to compare the third duty cycle of the third clock signal with the fourth duty cycle of the fourth clock signal; and a second control component (e.g., a control component within the duty cycle correction controller 525-b) operable or configured to control the duty cycle adjustment provided by the third circuit based at least in part on the comparison of the third duty cycle with the fourth duty cycle. In some instances, the fourth circuit includes: an integrator operable to integrate the first pair of clock signals of the four clock signals. In some instances, the first pair of clock signals and the second pair of clock signals of the four clock signals are offset in phase by 90 degrees plus or minus one or more phase errors.

[0135] It should be noted that the above methods illustrate possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. In addition, steps of two or more methods may be combined.

[0136] The information and signals described herein may be represented using a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0137] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. Virtual ground can be implemented using various electronic circuit elements (e.g., a voltage divider consisting of an operational amplifier and a resistor). Other implementations are also possible. "Virtual ground" or "virtually grounded" refers to being connected to approximately 0V.

[0138] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports a flow of signals between the components. Components are considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support a flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication (or conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device containing the connected components. The conductive paths between connected components may be direct conductive paths between the components, or the conductive paths between connected components may be indirect conductive paths that may include intermediate components (such as switches, transistors, or other components). In some cases, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as switches or transistors.

[0139] The term "coupling" refers to the situation of moving from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). When a component, such as a controller, couples other components together, the component initiates the change, allowing signals to flow between other components via conductive paths that previously did not allow signal flow.

[0140] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch located between the components are isolated from one another when a switch is open. When a controller isolates two components from one another, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously allowed a signal to flow.

[0141] The term "layer" as used herein refers to a stratum or sheet of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than one-third (e.g., a film). A layer may contain different elements, components, and / or materials. In some cases, a layer may be composed of two or more sublayers. In some drawings, two dimensions of a three-dimensional layer are depicted for purposes of illustration. However, a person skilled in the art will recognize that these layers are three-dimensional in nature.

[0142] As used herein, the term "substantially" means that the modified feature (eg, a verb or adjective modified by the term substantially) need not be absolute, but is close enough to achieve the advantage of the feature.

[0143] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components by activating a single intermediate component between the two components in question. For example, a first component shorted to a second component can exchange signals with the second component when a switch between the two components is closed. Thus, a short can be a dynamic operation that enables charge to flow between components (or lines) in electronic communication.

[0144] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or any other doping means.

[0145] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degraded) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the field effect transistor may be referred to as an n-type field effect transistor. If the channel is p-type (i.e., most carriers are holes), the field effect transistor may be referred to as a p-type field effect transistor. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type field effect transistor or a p-type field effect transistor, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate, the transistor may be "turned on" or "activated." A transistor may be “off” or “deactivated” when a voltage less than the transistor threshold voltage is applied to the transistor gate.

[0146] The descriptions presented herein in conjunction with the accompanying drawings set forth exemplary configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, case, or illustration" and not "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be performed without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0147] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0148] The information and signals described herein may be represented using a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0149] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or implemented with a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to implement the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other such configuration).

[0150] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the above functions may be implemented using software, hardware, firmware, hardware wiring, or any combination thereof executed by a processor. The features of the implementation functions may also be physically located at different locations, including being distributed so that parts of the functions are implemented at different physical locations. In addition, as used herein, included in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase (e.g., "at least one of ..." or "one or more of ...")) indicates a list of inclusions, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a set of closed conditions. For example, the exemplary steps described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0151] Computer-readable media include both non-transient computer storage media and communication media, and communication media include any medium that is convenient for transmitting a computer program from one place to another.Non-transient storage media can be any available medium accessible to a general or special-purpose computer.As an example, but not limited to, non-transient computer-readable media may include random access memory, read-only memory, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) read-only memory or other optical disk storage body, disk storage body or other magnetic storage device, or any other non-transient medium, which can be used to carry or store the desired program code means in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor.In addition, any connection is properly referred to as a computer-readable medium.For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc, laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc, where discs usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0152] The descriptions provided herein are intended to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs set forth herein, but rather conforms to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a first circuit coupled to an input of the clock divider circuit and operable to adjust a duty cycle of a set of clock signals; a second circuit coupled to the output of the clock divider circuit and operable to adjust a duty cycle of at least one of the plurality of clock signals output by the clock divider circuit; a third circuit coupled to the second circuit and operable to output two clock signals based at least in part on the plurality of clock signals, at least one of the plurality of clock signals having a duty cycle adjusted by the second circuit; as well as A control component is coupled to the third circuit and is operable to modify the adjustment of the duty cycle provided by the first circuit based at least in part on the two clock signals. 2 . The apparatus of claim 1 , wherein the clock division circuit is operable to generate the plurality of clock signals based at least in part on the set of clock signals.

3. The device according to claim 1, further comprising: an integrator coupled to the output of the second circuit and operable to integrate the first clock signal output by the second circuit; as well as A second control component is coupled to the integrator and an input of the second circuit.

4. The device according to claim 3, further comprising: A second integrator is coupled to the second output of the second circuit and the input of the second control component, and the second integrator is operable to integrate a second clock signal output by the second circuit.

5. The apparatus according to claim 1, further comprising: An integrator is coupled to the output of the third circuit and the input of the control component, the integrator being operable to integrate at least one of the two clock signals output by the third circuit.

6. The device according to claim 1, further comprising: A circuit is coupled to an input of the first circuit and is operable to receive a first clock signal and provide the first clock signal and a second clock signal which is an inverse signal of the first clock signal to the first circuit, wherein the set of clock signals includes the first clock signal and the second clock signal.

7. The apparatus of claim 1 , wherein the third circuit comprises: a first group of NAND gates operable to output a first clock signal of the two clock signals to the control component; as well as A second group of NAND gates is operable to output a second clock signal of the two clock signals to the control component.

8. A device comprising: a first circuit operable to adjust a duty cycle of a first clock signal of two clock signals; a clock frequency dividing circuit operable to receive the two clock signals after adjusting the duty cycle of the first clock signal and generate four clock signals each shifted in phase; a second circuit operable to receive a first pair of the four clock signals and adjust a duty cycle of at least one clock signal of the first pair; as well as A third circuit is operable to receive a second pair of the four clock signals and adjust a duty cycle of at least one clock signal of the second pair.

9. The device according to claim 8, further comprising: A fourth circuit is coupled to the second circuit and the third circuit, the fourth circuit being operable to generate a third pair of clock signals based at least in part on the first pair and the second pair of the four clock signals.

10. The device according to claim 9, further comprising: a fifth circuit operable to integrate the third pair of clock signals; as well as A control component is operable to control the adjustment of the duty cycle provided by the first circuit based at least in part on an integration of the third pair of clock signals.

11. The apparatus of claim 8, wherein the first pair of the four clock signals comprises a first clock signal having a first duty cycle adjusted by the second circuit and a second clock signal having a second duty cycle, the apparatus further comprising: a fourth circuit operable to compare the first duty cycle of the first clock signal with the second duty cycle of the second clock signal; as well as A control component is operable to control the adjustment of the duty cycle provided by the second circuit based at least in part on the comparison.

12. The apparatus of claim 11, wherein the second pair of the four clock signals comprises a third clock signal having a third duty cycle adjusted by the third circuit and a fourth clock signal having a fourth duty cycle, the apparatus further comprising: a fifth circuit operable to compare the third duty cycle of the third clock signal with the fourth duty cycle of the fourth clock signal; as well as A second control component is operable to control the adjustment of the duty cycle provided by the third circuit based at least in part on a comparison of the third duty cycle with the fourth duty cycle.

13. The apparatus of claim 11, wherein the fourth circuit comprises an integrator operable to integrate the first pair of the four clock signals.

14. The apparatus of claim 8, wherein a first pair of clock signals and a second pair of clock signals of the four clock signals are offset in phase by 90 degrees plus or minus one or more phase errors.

15. A method comprising: Using a first circuit to adjust a duty cycle of a clock signal in a first set of clock signals; outputting, by a clock divider circuit coupled to the first circuit, a second set of clock signals based at least in part on the first set of clock signals; adjusting a duty cycle of at least one clock signal in the second set of clock signals using a second circuit; outputting, by a third circuit and after adjusting a duty cycle of the at least one clock signal, two clock signals based at least in part on the second set of clock signals; as well as The first circuit is controlled based at least in part on the two clock signals.

16. The method of claim 15, wherein controlling the first circuit comprises adjusting an amount of duty cycle adjustment provided by the first circuit.

17. The method according to claim 15, further comprising: A difference between duty cycles of the two clock signals is determined, wherein the first circuit is controlled based at least in part on the difference.

18. The method according to claim 15, further comprising: determining a difference between a duty cycle of the at least one clock signal and a second clock signal in the second set of clock signals, the at least one clock signal and the second clock signal having different phases; and A duty cycle of at least one clock signal in a third set of clock signals output by the clock divider circuit is adjusted based at least in part on the difference.

19. The method according to claim 15, further comprising: A fourth circuit is used to adjust a duty cycle of a second clock signal in the second set of clock signals, wherein the two clock signals are based at least in part on the second clock signal.

20. The method according to claim 19, further comprising: A duty cycle difference between the second clock signal and a third clock signal in the second set of clock signals is determined, wherein the duty cycle of the second clock signal is adjusted based at least in part on the difference.

21. The method of claim 19, further comprising: using the second circuit to adjust a duty cycle of a fourth clock signal in the second set of clock signals; as well as The fourth circuit is used to adjust a duty cycle of a third clock signal in the second set of clock signals.

22. A method comprising: Using a first circuit to adjust a duty cycle of a first clock signal of two clock signals; The clock frequency dividing circuit receives the two clock signals after adjusting the duty cycle of the first clock signal and generates four clock signals that are respectively shifted in phase; receiving, by a second circuit, a first pair of the four clock signals and adjusting a duty cycle of at least one clock signal of the first pair; as well as A second pair of the four clock signals is received by a third circuit, and a duty cycle of at least one clock signal of the second pair is adjusted.

23. The method according to claim 22, further comprising: A third pair of clock signals is generated by a fourth circuit coupled to the second circuit and the third circuit based at least in part on the first pair and the second pair of the four clock signals.

24. The method according to claim 23, further comprising: integrating the third pair of clock signals using a fifth circuit; as well as The adjustment of the duty cycle provided by the first circuit is controlled using a control component based at least in part on an integration of the third pair of clock signals.

25. The method of claim 22, wherein the first pair of the four clock signals comprises a first clock signal having a first duty cycle and a second clock signal having a second duty cycle adjusted by the second circuit, the method further comprising: using a fourth circuit to compare the first duty cycle of the first clock signal with the second duty cycle of the second clock signal; as well as The adjustment of the duty cycle provided by the second circuit is controlled using a control component based at least in part on the comparison.

26. The method of claim 25, wherein the second pair of the four clock signals comprises a third clock signal having a third duty cycle regulated by the third circuit and a fourth clock signal having a fourth duty cycle, the method further comprising: using a fifth circuit to compare the third duty cycle of the third clock signal with the fourth duty cycle of the fourth clock signal; as well as The adjustment of the duty cycle provided by the third circuit is controlled using a second control component based at least in part on comparing the third duty cycle to the fourth duty cycle.

27. The method of claim 25, wherein the fourth circuit comprises an integrator operable to integrate the clock signal of the first pair of the four clock signals.

28. The method of claim 22, wherein the clock signal of the first pair and the clock signal of the second pair of the four clock signals are offset in phase by 90 degrees plus or minus one or more phase errors.

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