Line speed streaming test method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a line-speed streaming test method and device, electronic equipment and a readable storage medium, and relates to the technical field of communication. The method is applied to a tested device in communication connection with a test device, and comprises the following steps: obtaining a target frequency offset adjustment amount; according to the target frequency offset adjustment amount, the frequency offset condition of a first initial reference clock obtained based on a local first clock of the tested device is adjusted to obtain a first reference clock, and the minimum value of the frequency offset range of the first reference clock is not smaller than the maximum value of the second frequency offset range of the tested device; and based on the first reference clock, carrying out a line-speed streaming test. Therefore, the frequency offset range of the reference clock of the tested equipment is adjusted based on the target frequency offset adjustment amount, so that the minimum value of the frequency offset range of the tested equipment is not less than the maximum value of the frequency offset range of the tested equipment; therefore, the situation of line-speed streaming packet loss caused by the fact that the clock frequency offset of the tested equipment is smaller than that of the test equipment is avoided.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a line-speed flow testing method, device, electronic device and readable storage medium. Background Art

[0002] Currently, the network device under test is usually connected to the tester, and then the network device is tested for traffic. The network device has frequency deviation, which may cause the actual reference clock frequency of the network device to be lower than the reference clock frequency of the tester, that is, the data processing frequency of the network device is lower than the data processing frequency of the tester. In this case, the line speed traffic is continuously performed. As time accumulates, the data that cannot be processed in time will gradually increase, and eventually reach the upper limit of the network device data buffer, and then overflow, which will lead to packet loss, and then cause inaccurate traffic test results. Summary of the invention

[0003] The embodiments of the present application provide a line-speed traffic testing method, device, electronic device and readable storage medium, which adjust the frequency deviation range of the reference clock of the device under test based on the target frequency deviation adjustment amount so that the minimum value of the frequency deviation range of the device under test is not less than the maximum value of the frequency deviation range of the test device, thereby avoiding line-speed traffic packet loss caused by the clock frequency deviation of the device under test being less than the clock frequency deviation of the test device.

[0004] The embodiments of the present application can be implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a line speed flow testing method, which is applied to a device under test that is communicatively connected to a testing device, the method comprising:

[0006] Obtaining a target frequency deviation adjustment amount;

[0007] Adjusting the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain a first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device;

[0008] A line-speed traffic test is performed based on the first reference clock.

[0009] In a second aspect, an embodiment of the present application provides a line speed flow testing device, which is applied to a device under test that is communicatively connected to a testing device, and the device includes:

[0010] A processing module, used for obtaining a target frequency deviation adjustment amount;

[0011] The processing module is further used to adjust the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain the first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device;

[0012] A test module is used to perform a line speed flow test based on the first reference clock.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the line speed flow testing method described in the aforementioned embodiment.

[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the line-speed flow testing method as described in the aforementioned embodiment is implemented.

[0015] The line-speed streaming test method, device, electronic device and readable storage medium provided by the embodiments of the present application, the test device obtains a target frequency deviation adjustment amount, and adjusts the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain the first reference clock, and then performs a line-speed streaming test based on the first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device. In this way, by adjusting the frequency deviation range of the reference clock of the device under test based on the target frequency deviation adjustment amount, so that the minimum value of the frequency deviation range of the device under test is not less than the maximum value of the frequency deviation range of the test device, the line-speed streaming packet loss caused by the clock frequency deviation of the device under test being less than the clock frequency deviation of the test device is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A block diagram of an electronic device provided in an embodiment of the present application;

[0018] Figure 2 One of the flow charts of the line speed flow testing method provided in the embodiment of the present application;

[0019] Figure 3 The second flowchart of the line speed flow testing method provided in the embodiment of the present application;

[0020] Figure 4 A block diagram of a test system provided in an embodiment of the present application;

[0021] Figure 5 One of the block diagrams of the line speed flow testing device provided in the embodiment of the present application;

[0022] Figure 6 The second block diagram of the line-speed flow testing device provided in the embodiment of the present application.

[0023] Icon: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication unit; 200 - line speed flow test device; 210 - detection module; 220 - processing module; 230 - test module. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0027] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0028] Please refer to Figure 1 , Figure 1 A block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 may be, but is not limited to, a switch, etc. The electronic device 100 is a device that needs to perform a line-speed flow test, that is, a device under test. The electronic device 100 is communicatively connected to a test device to perform a line-speed flow test. The test device may be a tester. The electronic device 100 may include a memory 110, a processor 120, and a communication unit 130. The memory 110, the processor 120, and the communication unit 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0029] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0030] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions. For example, the memory 110 stores a line speed flow test device 200, and the line speed flow test device 200 includes at least one software function module that can be stored in the memory 110 in the form of software or firmware. The processor 120 executes various functional applications and data processing by running software programs and modules stored in the memory 110, such as the line speed flow test device 200 in the embodiment of the present application, that is, implementing the line speed flow test method in the embodiment of the present application.

[0031] The communication unit 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through a network, and to send and receive data through the network.

[0032] It should be understood that Figure 1 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 The components shown in can be implemented by hardware, software or a combination thereof. It is worth noting that Figure 1 The components shown can be implemented by hardware, software or a combination thereof. That is to say, the implementation of the processing flow of the flow table resource management method in the above embodiment is not limited to the processor reading and running pure computer-readable program code from the memory, but can also be implemented by hardware or logic devices.

[0033] It should be understood here that improvements to a technology can be divided into hardware improvements (for example, improvements to circuit structures such as diodes, transistors, switches, etc.) and software improvements (improvements to method flows). However, with the development of technology, many improvements to method flows today can be regarded as direct improvements to hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and make a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. Among them, VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and Verilog are currently the most commonly used. Those skilled in the art should also be aware that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0034] Please refer to Figure 2 , Figure 2One of the flow diagrams of the line speed flow test method provided in the embodiment of the present application. The method is applied to a device under test that is connected to the test device for communication. The method can be applied to Ethernet environments with high requirements for upstream and downstream clock synchronization, such as data center networks and industrial networks. The specific process of the line speed flow test method is described in detail below. In this embodiment, the method may include steps S120 to S140.

[0035] Step S120, obtaining a target frequency offset adjustment amount.

[0036] Step S130: adjusting the frequency deviation of a first initial reference clock of the device under test obtained based on a local first clock according to the target frequency deviation adjustment amount to obtain a first reference clock.

[0037] Step S140: performing a line-speed flow test based on the first reference clock.

[0038] In this embodiment, the local first clock of the device under test can be a crystal oscillator, and the first clock can be directly used as the first initial reference clock, or the first initial reference clock can be obtained by multiplication, division, etc. based on the first clock. The frequency deviation of the first initial reference clock is the frequency deviation of the first clock, so the frequency deviation of the first initial reference clock can be determined. If the target frequency deviation adjustment amount is greater than 0, a target frequency deviation adjustment amount can be determined in any way. For example, a value is set as the target frequency deviation adjustment amount based on experience.

[0039] In the case where a line-speed flow test is required, a target frequency deviation adjustment amount can be obtained, and then a quantitative frequency deviation is added to the first initial reference clock based on the target frequency deviation adjustment amount, thereby obtaining a first reference clock. Among them, when adding a quantitative frequency deviation, the specific amount of the increase in frequency deviation can be equal to the target frequency deviation adjustment amount, or it can be greater than the target frequency deviation adjustment amount, which can be determined according to actual needs. The minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device. After the adjustment, a line-speed flow test is performed based on the first reference clock.

[0040] In this way, the frequency deviation range of the reference clock of the device under test is adjusted based on the target frequency deviation adjustment amount so that the minimum value of the frequency deviation range of the device under test is not less than the maximum value of the frequency deviation range of the test device, thereby avoiding line-speed traffic packet loss caused by the clock frequency deviation of the device under test being less than the clock frequency deviation of the test device.

[0041] Devices that support synchronous Ethernet can recover the clock signal of the upstream device and use it as a reference clock for their own use, ultimately achieving the same frequency as the upstream device, thereby achieving frequency consistency for the entire networking device.

[0042] The solution for the device to implement synchronous Ethernet mainly depends on the system's clock circuit design. If this solution is to be implemented, first of all, the device's own reference clock has very high frequency accuracy requirements, and the accuracy needs to meet the + / -4.6ppm deviation range. Since the frequency accuracy of the reference clock is affected by the processing technology, it is impossible to guarantee that all deviations are completely consistent. On the basis of meeting the deviation range, the specific deviation value of the accuracy will be relatively random, and there may be positive deviations or negative deviations. Among them, ppm is the abbreviation of part per million, which means one part per million.

[0043] If the device supporting synchronous Ethernet is connected to the tester for flow testing, the tester, as a standard test device, has a very high frequency accuracy and can reach or nearly reach 0ppm without deviation. If the device under test has the synchronous Ethernet function enabled, it has no frequency deviation relative to the tester. When the frequencies on both sides are consistent, it can naturally meet the scenario of 100% line speed flow. However, if the synchronous Ethernet function is not enabled, the reference clock frequency of the device under test will inevitably deviate from the reference clock frequency of the tester. At this time, if the deviation is positive, that is, the data processing frequency of the device under test will be slightly higher than that of the tester, the data can be processed in time, and there will be no problem with line speed flow; but if the device under test has a negative deviation relative to the tester, and line speed flow is performed at the same time, the data processing frequency of the device under test will be lower than that of the tester. As time accumulates, the data that cannot be processed in time will gradually increase, and eventually reach the upper limit of the data buffer of the device under test, causing data overflow, resulting in packet loss.

[0044] Therefore, before executing step S120, the device under test may first determine whether the device supports the synchronous Ethernet function. If not, step S120 may be directly executed. Figure 3 As shown, before step S120, the method may further include step S110.

[0045] Step S110, determining whether the synchronous Ethernet function of the device under test is enabled.

[0046] In this embodiment, if the device under test is a device that supports synchronous Ethernet function, when it is necessary to perform a line-speed streaming test, it can be detected whether the synchronous Ethernet function of the local device is enabled (i.e., whether it is in the startup state). In the case that the synchronous Ethernet function of the device under test is not enabled, the clock chip of the device under test will choose to use the local clock as the reference source. If no processing is done at this time, the clock frequency deviation of the system of the device under test is completely determined by the frequency deviation of the local clock (i.e., the clock frequency deviation of the system is equal to the frequency deviation of the local clock), that is, it cannot be determined that the frequency deviation of the device under test is greater than or equal to the frequency of the test device. At this time, if line-speed streaming is performed, there may be probabilistic packet loss. To avoid the above situation, when it is determined that the synchronous Ethernet function of the device under test is not enabled, step S120 can be executed to adjust the frequency deviation to obtain a first reference clock, and then a line-speed streaming test is performed based on the first reference clock.

[0047] As a possible implementation method, the target frequency offset adjustment amount can be obtained according to the following method. The first frequency offset range of the device under test and the second frequency offset range of the test device can be obtained. The first frequency offset range of the device under test is the frequency offset range of the first initial reference clock of the device under test obtained based on the local first clock. Afterwards, the target frequency offset adjustment amount can be determined based on the first frequency offset range and the second frequency offset range. Next, the frequency offset of the second target frequency offset adjustment amount is increased for the first frequency offset range of the first initial reference clock, and the first initial clock after the frequency offset adjustment is used as the first reference clock. The frequency offset range obtained after the first frequency offset range is increased by the frequency offset of the target frequency offset adjustment amount is the frequency offset range of the first reference clock, and the minimum value of the frequency offset range of the first reference clock is greater than or equal to the maximum value of the second frequency offset range.

[0048] For example, if the frequency deviation range of the reference clock of the device under test (i.e., the local first clock) is +4.6 to -4.6ppm, then the first frequency deviation range can be determined to be +4.6 to -4.6ppm; if the frequency deviation of the test device is 0, then the second frequency deviation range is only 0; based on the first frequency deviation range of +4.6 to -4.6ppm and the second frequency deviation range of 0, the target frequency deviation adjustment amount can be determined to be 10ppm. In this way, after the first frequency deviation range of +4.6 to -4.6ppm is increased by 10ppm, the new frequency deviation range can be obtained as 10+4.6 to 10-4.6, that is, the minimum value of the frequency deviation range of the first reference clock of the device under test is greater than 0. Therefore, there will be no line rate packet loss caused by the clock frequency deviation of the device under test being smaller than the clock frequency deviation of the test device.

[0049] Alternatively, if Figure 4As shown, the device under test may include a first clock and a clock chip connected to the first clock. The first clock may be a high-precision clock, and the high-precision clock may be a crystal oscillator. The device under test may also include a CPU. When the target frequency deviation adjustment amount is obtained, the clock chip may be configured by the CPU, and the DCO (Digital Control Oscillator) function of the clock chip may be started, and then the frequency deviation increase processing is performed on the first initial reference clock through the DCO function, that is, a quantitative frequency deviation is increased to obtain the first reference clock, and the increased frequency deviation amount is the target frequency deviation adjustment amount.

[0050] For example, the frequency deviation range of the high-precision clock of the device under test is +4.6 to -4.6ppm, that is, the first frequency deviation range is +4.6 to -4.6ppm, and the frequency deviation of the test device is 0; assuming that the target frequency deviation is adjusted to 10ppm, the DCO function of the clock chip is started to increase the frequency deviation by 10ppm, which can ensure that the frequency deviation of the first reference clock provided by the clock chip to the switching chip is within the range of 10-4.6 to 10+4.6ppm, so that the frequency deviation of the device under test is greater than the frequency deviation of the test device, thereby achieving the purpose of line-speed streaming without packet loss.

[0051] In this embodiment, if it is determined that the synchronous Ethernet function of the device under test is enabled, the following steps may be performed: Figure 3 Steps S150 to S160 in .

[0052] Step S150: obtaining a second reference clock based on the signal of the test device through the synchronous Ethernet function.

[0053] Step S160: Perform a line-speed flow test based on the second reference clock.

[0054] In this embodiment, the frequency deviation adjustment based on the target frequency deviation adjustment amount is achieved by starting the DCO function of the clock chip in the device under test. If the device under test enables the synchronous Ethernet function, the software layer senses the need and can first determine whether the DCO function is in the enabled state. If the DCO function is in the enabled state, the CPU can be used to configure the clock chip, turn off the DCO function of the clock chip, and prohibit the output of the clock frequency deviation. Then, the switching chip can be controlled to recover the clock from the clock-carrying data sent by the test device, and send the clock to the input end of the clock chip; the clock chip locks the clock and uses it as a reference source, and then performs digital frequency multiplication and division on the signal, and outputs the reference clock (i.e., the second reference clock) to the switching chip. After that, the line speed flow test can be performed based on the second reference clock. At this time, it is equivalent to the reference clock of the entire device under test coming from the test device, that is, the two sides keep the frequency synchronized. In this case, there will be no packet loss problem when performing line speed flow.

[0055] Among them, optionally, the specific execution time of determining whether the synchronous Ethernet function of the device under test is enabled can be determined in combination with actual needs, and the action can be continuously executed. For example, when the device under test is started, it is detected whether the synchronous Ethernet function of the device under test is enabled. If it is not enabled, the target frequency offset adjustment amount is determined, and then the frequency offset adjustment is implemented based on the target frequency offset adjustment amount through the DCO function, and a line speed flow test is performed based on the first reference clock obtained after the frequency offset adjustment; if it is enabled, the DCO function is turned off, and the synchronous Ethernet function is provided to obtain a second reference clock, and then a line speed flow test is performed based on the second reference clock. If the device under test has started the synchronous Ethernet function for a period of time and then turns it off, that is, it does not obtain clock information from the upstream device, according to the protocol requirements of the synchronous Ethernet, after the clock loses lock, it still needs to maintain operation according to the previous state (that is, the frequency offset of the device under test is greater than or equal to the frequency offset of the test device). At this time, the software perceives that the function has been turned off, and will actively configure the clock chip, turn on the DCO function, and turn on the quantitative frequency offset, so as to ensure that the frequency offset of the device under test is higher than the frequency offset of the test device, so that there will be no packet loss when the device under test is streaming.

[0056] The above-mentioned line-speed streaming test method provided in this embodiment seamlessly integrates the synchronous Ethernet function of the device with the frequency deviation adjustment function of the clock chip. When the synchronous Ethernet function is enabled, the line-speed streaming test is performed based on the second reference clock obtained by the synchronous Ethernet function; when the synchronous Ethernet function is not enabled, the line-speed streaming test is performed based on the first reference clock obtained by the frequency deviation adjustment function of the clock chip. The above-mentioned method dynamically adjusts the reference clock output frequency deviation of the clock chip according to the real-time requirements of the synchronous Ethernet enable command, that is, adjusts the input reference clock frequency deviation of the switching chip to meet the clock frequency deviation of the device under test that is greater than or equal to the clock frequency deviation of the test device. In this way, the frequency deviation of the device under test system can be controlled. In the scenario of streaming test, the device under test can achieve the purpose of line-speed streaming without packet loss regardless of whether the synchronous Ethernet function is turned on, and it can adapt to more test scenarios.

[0057] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a line speed flow test device 200 is provided below. Optionally, the line speed flow test device 200 can adopt the above Figure 1 The device structure of the electronic device 100 is shown. Figure 5 , Figure 5This is one of the block diagrams of the line speed flow test device 200 provided in the embodiment of the present application. It should be noted that the basic principle and technical effects of the line speed flow test device 200 provided in this embodiment are the same as those of the above embodiments. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above embodiments. In this embodiment, the line speed flow test device 200 may include: a processing module 220 and a testing module 230.

[0058] The processing module 220 is used to obtain a target frequency offset adjustment amount.

[0059] The processing module 220 is further configured to adjust the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain the first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device.

[0060] The testing module 230 is used to perform a line-speed flow test based on the first reference clock.

[0061] In this embodiment, the device under test includes a first clock and a clock chip connected to the first clock, and the processing module 220 is specifically used to: start the digitally controlled oscillator DCO function of the clock chip, and perform frequency deviation increase processing on the first initial reference clock through the DCO function to obtain the first reference clock, wherein the increased frequency deviation amount is the target frequency deviation adjustment amount.

[0062] In this embodiment, the device under test supports synchronous Ethernet function. Figure 6 , Figure 6 The second block diagram of the line speed flow testing device 200 provided in the embodiment of the present application. In this embodiment, the line speed flow testing device 200 may further include a detection module 210. The detection module 210 is used to: determine whether the synchronous Ethernet function of the device under test is enabled; if it is determined that the synchronous Ethernet function of the device under test is not enabled, the processing module 220 obtains the target frequency offset adjustment amount.

[0063] In this embodiment, if it is determined that the synchronous Ethernet function of the device under test is enabled, the processing module 220 is also used to: obtain a second reference clock based on the signal of the test device through the synchronous Ethernet function, wherein the second reference clock is the reference clock of the test device; the test module 230 is also used to perform a line speed flow test based on the second reference clock.

[0064] In this embodiment, frequency deviation adjustment is achieved by starting the DCO function of the clock chip, and the processing module 220 is also specifically used to: when it is determined that the synchronous Ethernet function is enabled, determine whether the DCO function is in the started state, and if the DCO function is in the started state, turn off the DCO function; after turning off the DCO function, use the clock chip to obtain the second reference clock through the synchronous Ethernet function.

[0065] In this embodiment, the processing module 220 is specifically used to: obtain a first frequency offset range of the local device and a second frequency offset range of the test device; and determine the target frequency offset adjustment amount according to the first frequency offset range and the second frequency offset range.

[0066] Optionally, the above modules can be stored in the form of software or firmware. Figure 1 The memory 110 shown in the figure may be fixed in the operating system (OS) of the electronic device 100 and may be Figure 1 Meanwhile, the data and program codes required for executing the above modules may be stored in the memory 110.

[0067] The embodiment of the present application also provides a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the line-speed flow testing method is implemented.

[0068] In summary, the embodiments of the present application provide a line-speed streaming test method, device, electronic device and readable storage medium, wherein the test device obtains a target frequency deviation adjustment amount, and adjusts the frequency deviation of a first initial reference clock of a device under test obtained based on a local first clock according to the target frequency deviation adjustment amount to obtain a first reference clock, and then performs a line-speed streaming test based on the first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device. In this way, by adjusting the frequency deviation range of the reference clock of the device under test based on the target frequency deviation adjustment amount, so that the minimum value of the frequency deviation range of the device under test is not less than the maximum value of the frequency deviation range of the test device, the line-speed streaming packet loss caused by the clock frequency deviation of the device under test being less than the clock frequency deviation of the test device is avoided.

[0069] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0070] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0071] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0072] The above description is only an optional embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A line speed flow testing method, characterized in that: Applied to a device under test in communication connection with a test device, the method comprises: Obtaining a target frequency deviation adjustment amount; Adjusting the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain a first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device; A line-speed traffic test is performed based on the first reference clock.

2. The method according to claim 1, characterized in that The device under test includes a clock chip connected to the first clock, and the frequency deviation of a first initial reference clock of the device under test obtained based on a local first clock is adjusted according to the target frequency deviation adjustment amount to obtain a first reference clock, including: The digitally controlled oscillator DCO function of the clock chip is started, and the frequency deviation increasing process is performed on the first initial reference clock through the DCO function to obtain the first reference clock, wherein the increased frequency deviation amount is the target frequency deviation adjustment amount.

3. The method according to claim 1, characterized in that The device under test supports a synchronous Ethernet function. Before obtaining the target frequency offset adjustment amount, the method further includes: Determine whether the synchronous Ethernet function of the device under test is enabled; If it is determined that the synchronous Ethernet function of the device under test is not enabled, the step of obtaining the target frequency offset adjustment amount is performed.

4. The method according to claim 3, characterized in that The method further comprises: If it is determined that the synchronous Ethernet function of the device under test is enabled, obtaining a second reference clock based on the signal of the test device through the synchronous Ethernet function, wherein the second reference clock is a reference clock of the test device; A line-speed traffic test is performed based on the second reference clock.

5. The method according to claim 4, characterized in that The frequency deviation adjustment is realized by starting the DCO function of the clock chip in the device under test, and the second reference clock is obtained based on the signal of the test device through the synchronous Ethernet function, including: When it is determined that the synchronous Ethernet function is enabled, determining whether the DCO function is in an enabled state, and if the DCO function is in an enabled state, disabling the DCO function; After the DCO function is turned off, the second reference clock is obtained by using the clock chip through the synchronous Ethernet function.

6. The method according to any one of claims 1 to 5, characterized in that: The obtaining of the target frequency offset adjustment amount comprises: Obtaining a first frequency deviation range of the local device and a second frequency deviation range of the test device; The target frequency offset adjustment amount is determined according to the first frequency offset range and the second frequency offset range.

7. A line speed flow testing device, characterized in that: Applicable to a device under test that is communicatively connected to a test device, the device comprising: A processing module, used for obtaining a target frequency deviation adjustment amount; The processing module is further used to adjust the frequency deviation of the first initial reference clock of the device under test obtained based on the local first clock according to the target frequency deviation adjustment amount to obtain the first reference clock, wherein the minimum value of the frequency deviation range of the first reference clock is not less than the maximum value of the second frequency deviation range of the test device; A test module is used to perform a line speed flow test based on the first reference clock.

8. The device according to claim 7, characterized in that The device under test supports synchronous Ethernet function, and the device further includes a detection module. The detection module is used to determine whether the synchronous Ethernet function of the device under test is enabled; If it is determined that the synchronous Ethernet function of the device under test is enabled, the processing module obtains a second reference clock based on the signal of the test device through the synchronous Ethernet function, wherein the second reference clock is the reference clock of the test device, and the test module performs a line speed flow test based on the second reference clock.

9. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the line speed flow testing method described in any one of claims 1-6.

10. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the line-speed flow testing method as described in any one of claims 1 to 6 is implemented.

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