Display device

Abstract

The display device includes: a data line; a pixel circuit connected to the data line; a light emitting element connected to the pixel circuit; a first connection electrode under the data line; a sensing circuit connected to the first connection electrode; a light receiving element connected to the sensing circuit; and a receiving line under the first connection electrode and connected to the first connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0100352 filed in the Korean Intellectual Property Office on August 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure described herein relate to display devices. Background Art

[0004] Electronic devices that display images to users, such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs, include display devices to display images. The display device includes a display panel for generating images, an input device such as an input sensing unit, a camera for capturing external images, and various sensors.

[0005] The input sensing part may be located on the display panel to sense the user's touch. The sensor may include, for example, a fingerprint sensor, a proximity sensor, and an illumination sensor. The fingerprint sensor in the sensor may sense a fingerprint provided on the display panel. The fingerprint sensor is manufactured using a separate module and is located in the display device.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure include a display device capable of relatively improving the sensitivity of a sensor.

[0008] According to some embodiments of the present disclosure, a display device may include: a data line; a pixel circuit connected to the data line; a light emitting element connected to the pixel circuit; a first connecting electrode below the data line; a sensing circuit connected to the first connecting electrode; a light receiving element connected to the sensing circuit; and a receiving line below the first connecting electrode and connected to the first connecting line.

[0009] According to some embodiments of the present disclosure, a display device may include: a data line; a pixel circuit connected to the data line; a light emitting element connected to the pixel circuit; a lower metal layer below the pixel circuit; a receiving line in the same layer as the lower metal layer; a sensing circuit connected to the receiving line; and a light receiving element connected to the sensing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become apparent by describing in more detail aspects of some embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A cross-sectional view of a display device shown in FIG.

[0013] Figure 3 It is shown Figure 2 A cross-sectional view of a display panel shown in FIG.

[0014] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0015] Figure 5 It is shown Figure 4 A view of an equivalent circuit of any one of the pixels shown in and a sensor adjacent to the pixel.

[0016] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light emitting element, a first transistor, a fourth transistor and a sixth transistor of a pixel shown in FIG.

[0017] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0018] Figure 8 It is shown Figure 4 2 is a plan view of an arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in .

[0019] Fig. 9 It is shown by Figure 5 and Figure 7 2 is a view of a fingerprint sensing state performed by the sensor shown in .

[0020] FIG. 10A to FIG. 10I is a cross-sectional view showing the structure of a pixel circuit and a sensing circuit when viewed in a plan view.

[0021] Fig.11 is a diagram showing a display panel in which a FIG. 10A to FIG. 10I Schematic cross-sectional view of portions of the receiving line and the data line.

[0022] Fig.12 is a cross-sectional view showing a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0023] In the present specification, the statement that a first component (or region, layer, portion, part, etc.) is “on”, “connected to” or “coupled to” a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed between the first component and the second component.

[0024] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportion, and size of components may be exaggerated to effectively describe technical features.

[0025] The term "and / or" includes any and all combinations of one or more of the associated components.

[0026] Although the terms "first", "second", etc. may be used to describe various components, these components should not be understood to be limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope and spirit of the present invention. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0027] In addition, the terms "below", "at the lower portion", "above", "upper portion" are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0028] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0029] It will also be understood that the terms “comprises,” “comprising,” “including,” or “including,” or “having” specify the presence of stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0031] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0032] refer to Figure 1According to some embodiments of the present disclosure, the display device DD may have a rectangular shape having a longer side extending in a first direction DR1 and a shorter side extending in a second direction DR2 crossing the first direction DR1. However, the embodiments of the present disclosure are not limited thereto, and the display device DD may have various shapes such as a circle or a polygon.

[0033] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the meaning of "when viewed from above a plane" or "in a plan view" may mean "when viewed from the third direction DR3".

[0034] A top surface of the display device DD may be defined as a display surface DS and may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be displayed to a user through the display surface DS in a third direction DR3.

[0035] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA is used to display an image, and the non-display area NDA is not used to display an image. The non-display area NDA may be defined as an edge of the display device DD surrounding the display area DA and printed with a specific color.

[0036] The display device DD can be used for large electronic devices such as televisions, monitors or external billboards. In addition, the display device DD can be used for small and medium-sized display devices such as personal computers, laptop computers, personal digital terminals, car navigation systems, game consoles, smart phones, tablet computers or cameras. The above examples are provided as examples only, and as will be understood by those of ordinary skill in the art, the display device DD can be applied to any other electronic device without departing from the spirit and scope of the embodiments according to the present disclosure.

[0037] Figure 2 It is shown Figure 1 A cross-sectional view of a display device shown in FIG.

[0038] For example, Figure 2 A cross-sectional view of the display device DD when viewed in a first direction DR1 is shown.

[0039] refer to Figure 2 , the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0040] According to some embodiments of the present disclosure, the display panel DP may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. In the following, the display panel DP is an organic light-emitting display panel.

[0041] The input sensing unit ISP may be directly located on the display panel DP. The input sensing unit ISP may include a plurality of sensing units for sensing external input in a capacitive manner. When manufacturing the display device DD, the input sensing unit ISP may be directly formed on the display panel DP. However, the embodiments according to the present disclosure are not limited thereto. The input sensing unit ISP is manufactured separately from the display panel DP and may be attached to the display panel DP by an adhesive layer.

[0042] The anti-reflection layer RPL may be located on the input sensing unit ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be located on the input sensing unit ISP. However, the present disclosure is not limited thereto. The anti-reflection layer RPL may be manufactured using another panel and may be attached to the input sensing unit ISP through an adhesive layer.

[0043] The anti-reflection layer RPL may be defined as a film that prevents or reduces external light reflection. The anti-reflection layer RPL may relatively reduce the reflectance of external light incident from the top surface of the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be observed by the user.

[0044] When external light toward the display panel DP is reflected from the display panel DP and provided to an external user again, the user may visually observe the external light, which is similar to a mirror. In order to prevent or reduce the above phenomenon, the anti-reflection layer RPL may include a plurality of color filters to display the same color as the color of the pixels of the display panel DP.

[0045] The color filter may filter external light of the same color as the color of the pixel. In this case, the external light may not be observed by the user. However, the present disclosure is not limited thereto. For example, the anti-reflection layer RPL may include a phase retarder and / or a polarizer to relatively reduce the reflectivity of the external light.

[0046] The window WIN may be located on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0047] The panel protection film PPF may be located under the display panel DP. The panel protection film PPF may protect the bottom surface of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0048] The first adhesive layer AL1 may be interposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be combined with each other through the first adhesive layer AL1. The second adhesive layer AL2 may be interposed between the window WIN and the anti-reflection layer RPL to combine the window WIN with the anti-reflection layer RPL through the second adhesive layer AL2.

[0049] Figure 3 It is shown Figure 2 A cross-sectional view of a display panel shown in FIG.

[0050] For example, Figure 3 A cross-sectional view of the display panel DP when viewed in the first direction DR1 is shown.

[0051] refer to Figure 3 The display panel DP includes a substrate SUB, a circuit element layer DP-CL located on the substrate SUB, a display element layer DP-OLED located on the circuit element layer DP-CL, and a thin film encapsulation layer TFE located on the display element layer DP-OLED.

[0052] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include a flexible plastic material such as glass or polyimide (PI). The display element layer DP-OLED is located in the display area DA.

[0053] The plurality of pixels may include portions located in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor located in the circuit element layer DP-CL and a light emitting element located in the display element layer DP-OLED to be connected to the transistor.

[0054] The thin film encapsulation layer TFE may be located on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign matter.

[0055] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0056] refer to Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a plurality of data drivers DDV, a light emission driver EDV, and a plurality of pads PD.

[0057] Although the display panel DP may have a rectangular shape having longer sides extending in the first direction DR1 and shorter sides extending in the second direction DR2, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0058] The display panel DP may include a plurality of pixels PX, a plurality of sensors SN, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of light emission lines EL1 to ELm, a plurality of receiving lines RX1 to RXh, a first control line CSL1 and a second control line CSL2, a power line PL, a common line CNL, a first power line PL1 and a second power line PL2. In this case, "h", "m" and "n" are natural numbers greater than 0.

[0059] The pixel PX may be located in the display area DA. The scanning driver SDV and the light emission driver EDV may be located in the non-display area NDA adjacent to the longer sides of the display panel DP, respectively. The data driver DDV may be located in the non-display area NDA adjacent to one of the shorter sides of the display panel DP. When viewed in a plan view, the data driver DDV may be adjacent to the bottom end of the display panel DP.

[0060] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 to be connected to the pixels PX and the data driver DDV. The light emission lines EL1 to ELm may extend in the second direction DR2 to be connected to the pixels PX and the light emission driver EDV.

[0061] The display panel DP may include a sensing unit for sensing a fingerprint. The sensing unit may include a sensor SN. The sensing unit for sensing a fingerprint may be embedded in the display panel DP instead of being manufactured by an additional module. The configuration of the sensor SN will be described in detail.

[0062] The receiving lines RX1 to RXh may extend in the first direction DR1 and may be arranged in the second direction DR2. In this case, "h" is a natural number greater than 0. The receiving lines RX1 to RXh may be connected to the sensor SN and the data driver DDV. The signal sensed by the sensor SN may be output to the outside of the display panel DP through the receiving lines RX1 to RXh and the data driver DDV.

[0063] The power line PL may extend in the first direction DR1 and may be located in the non-display area NDA. The common line CNL may be located in the non-display area NDA adjacent to the lower portion of the display area DA and extend in the second direction DR2 when viewed in a plan view. The common line CNL may be connected to the power line PL.

[0064] The first power line PL1 may be located in the display area DA, may extend in the first direction DR1, and may be arranged in the second direction DR2. The first power line PL1 may be connected to the common line CNL and the pixel PX. A first voltage may be applied to the power line PL. The first voltage may be applied to the pixel PX through the power line PL, the common line CNL, and the first power line PL1.

[0065] The second power line PL2 may be located in the non-display area NDA and may extend along a longer side of the display panel DP and another shorter side of the display panel DP where the data driver DDV is not located. The second power line PL2 may be located outside the scan driver SDV and the light emission driver EDV.

[0066] According to some embodiments, the second power line PL2 may extend toward the display area DA to be connected to the pixel PX. A second voltage having a level lower than the first voltage may be applied to the pixel PX through the second power line PL2.

[0067] The first control line CSL1 may be connected to the scan driver SDV and may extend toward the lower end portion of the display panel DP. The second control line CSL2 may be connected to the light emission driver EDV and may extend toward the lower end portion of the display panel DP. The data driver DDV may be interposed between the first control line CSL1 and the second control line CSL2.

[0068] The pad PD may be located in the non-display area NDA adjacent to the lower end portion of the display panel DP and may be closer to the lower end portion of the display panel DP than the data driver DDV. The data driver DDV, the first and second power lines PL1 and PL2, and the first and second control lines CSL1 and CSL2 may be connected to the pad PD.

[0069] The data lines DL1 to DLn and the receiving lines RX1 to RXh may be connected to the data driver DDV. The data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn and the receiving lines RX1 to RXh.

[0070] According to some embodiments, the display device DD may further include a timing controller and a voltage generator, the timing controller is used to control the operation of the scan driver SDV, the data driver DDV and the light emission driver EDV, and the voltage generator is used to generate the first voltage and the second voltage. The timing controller and the voltage generator may be connected to the corresponding pads PD through a printed circuit board.

[0071] The scan driver SDV generates a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages. The data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emission driver EDV may generate a plurality of light emission signals, and the light emission signals may be applied to the pixels PX through the light emission lines EL1 to ELm.

[0072] The pixel PX may provide a data voltage in response to the scan signal, and as the pixel PX emits light having brightness corresponding to the data voltage in response to the light emission signal, the pixel PX may display an image.

[0073] Figure 5 It is shown Figure 4 A view of an equivalent circuit of any one of the pixels shown in and a sensor adjacent to the pixel.

[0074] For example, Figure 5 1 shows a pixel PXij connected to the i-th scan line SLi, the i-th light emission line ELi and the j-th data line DLj. Figure 5 The sensor SNij connected to the i-th reset scanning line GRi and the j-th receiving line RXj is shown. In this case, "i" and "j" are natural numbers greater than 0.

[0075] refer to Figure 5 , the pixel PXij may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may drive the light emitting element OLED.

[0076] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing through the light emitting element OLED. The light emitting element OLED may generate light with brightness (eg, set brightness or predetermined brightness) based on the amount of current provided.

[0077] The i-th scan line SLi may include an i-th write scan line GWi, an i-th compensation scan line GCi, an i-th initialization scan line GIi, an i-th bias scan line GBi, and an i-th reset scan line GRi.

[0078] The i-th write scan line GWi may receive the i-th write scan signal GWSi, and the i-th compensation scan line GCi may receive the i-th compensation scan signal GCSi. The i-th initialization scan line GIi may receive the i-th initialization scan signal GISi, and the i-th bias scan line GBi may receive the i-th bias scan signal GBSi. The i-th reset scan line GRi may receive the i-th reset scan signal GRSi. The i-th light emission line ELi may receive the i-th light emission signal ESi.

[0079] Pixel PXij can be connected to the jth data line DLj, the ith write scan line GWi, the ith compensation scan line GCi, the ith initialization scan line GIi, the ith bias scan line GBi, the ith light emission line ELi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0080] The pixel circuit PC may be connected to the jth data line DLj, the ith writing scan line GWi, the ith compensation scan line GCi, the ith initialization scan line GIi, the ith bias scan line GBi, the ith light emission line ELi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL and the first power line PL1. The light emitting element OLED may be connected to the second power line PL2.

[0081] The first initialization line VIL1 may receive a first initialization voltage VINT, and the second initialization line VIL2 may receive a second initialization voltage AINT. The bias line VBL may receive a bias voltage VBIAS. The first power line PL1 may receive a first voltage ELVDD, and the second power line PL2 may receive a second voltage ELVSS.

[0082] The first to eighth transistors T1 to T8 may each include a source electrode, a drain electrode, and a gate electrode. Figure 5 As shown in , any one of the source electrode and the drain electrode is defined as a first electrode, and the other of the source electrode and the drain electrode is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0083] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first and second transistors T1 to T2 and the fifth to eighth transistors T5 to T8 may be PMOS transistors. The third and fourth transistors T3 and T4 may be NMOS transistors.

[0084] The first transistor T1 may be defined as a driving transistor, and the second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 may be defined as light emission control transistors. The eighth transistor T8 may be defined as a bias transistor.

[0085] The light emitting element OLED may be defined as an organic light emitting device. The light emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first voltage ELVDD may be applied to the pixel circuit PC through a first power line PL1. The cathode CE may receive a second voltage ELVSS having a level lower than the first voltage ELVDD. The second voltage ELVSS may be applied to the pixel circuit PC through a second power line PL2.

[0086] The first transistor T1 may be inserted between the fifth transistor T5 and the sixth transistor T6 and may be connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5 and may be connected to the anode AE ​​through the sixth transistor T6.

[0087] The first transistor T1 may include a first electrode connected to the first power line PL1 through a fifth transistor T5 , a second electrode connected to the anode AE ​​through a sixth transistor T6 , and a control electrode connected to the first node N1 .

[0088] The first electrode of the first transistor T1 may be connected to the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED based on the voltage of the first node N1 applied to the control electrode of the first transistor T1.

[0089] The second transistor T2 may be interposed between the first transistor T1 and the jth data line DLj to be connected to the first transistor T1. The second transistor T2 may include a first electrode connected to the jth data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the ith write scan line GWi.

[0090] The second transistor T2 may be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi to electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 may perform a switching operation of providing the data voltage VD applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0091] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCi.

[0092] The third transistor T3 may be turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCi to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0093] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GIi. The fourth transistor T4 may be turned on by the i-th initialization scan signal GISi applied through the i-th initialization scan line GIi, and may apply the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0094] The fifth transistor T5 may include a first electrode connected to the first power line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a control electrode connected to the i th light emission line ELi.

[0095] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light emission line ELi.

[0096] The fifth transistor T5 and the sixth transistor T6 may be turned on by the i-th light emission signal ESi applied through the i-th light emission line ELi. The first voltage ELVDD is provided to the light emitting element OLED by the turned-on fifth transistor T5 and the sixth transistor T6, so that the driving current may flow through the light emitting element OLED. Therefore, the light emitting element OLED may emit light.

[0097] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBSi received through the i-th bias scan line GBi, so that the second initialization voltage AINT received through the second initialization line VIL2 is provided to the anode AE ​​of the light emitting element OLED.

[0098] According to some embodiments of the present disclosure, the seventh transistor T7 may be omitted. According to some embodiments of the present disclosure, the second initialization voltage AINT may have a level different from that of the first initialization voltage VINT, but the present disclosure is not limited thereto. For example, the second initialization voltage AINT may have the same level as the first initialization voltage VINT.

[0099] The seventh transistor T7 can relatively improve the black expression capability of the pixel PX (e.g., pixel PXij). When the seventh transistor T7 is turned on, the parasitic capacitance of the light emitting element OLED can be discharged. Therefore, when the brightness of black is achieved, the light emitting element OLED does not emit light due to the leakage current of the first transistor T1. Therefore, the black expression capability can be relatively improved.

[0100] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth and sixth transistors T5 and T6 are turned on, the amount of current flowing through the first transistor T1 may be determined based on a voltage stored in the capacitor CST.

[0101] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBi. According to some embodiments of the present disclosure, the eighth transistor T8 may be omitted.

[0102] The eighth transistor T8 may be turned on by the i-th bias scan signal GBSi and may provide the bias voltage VBIAS to the first electrode of the first transistor T1. When the bias voltage VBIAS is applied to the first transistor T1, a shift of the hysteresis curve of the first transistor T1 may be suppressed.

[0103] The sensor SNij may include a sensing circuit SNC and a light receiving element LRE connected to the sensing circuit SNC. The sensing circuit SNC may drive the light receiving element LRE.

[0104] The sensor SNij may be connected to an i-th reset scan line GRi, a reset line VRL, a second initialization line VIL2 , an i-th write scan line GWi, a j-th receiving line RXj, and a second power line PL2 .

[0105] The sensing circuit SNC may be connected to the i-th reset scan line GRi, the reset line VRL, the second initialization line VIL2, the i-th write scan line GWi, and the j-th receiving line RXj. The light receiving element LRE may be connected to the second power line PL2.

[0106] The sensing circuit SNC may include a first transistor T1 ′, a second transistor T2 ′, and a third transistor T3 ′. The first transistor T1 ′ and the third transistor T3 ′ may be PMOS transistors, and the second transistor T2 ′ may be an NMOS transistor.

[0107] The light receiving element LRE may be defined as a photodiode. The light receiving element LRE may convert light energy incident from the outside into electrical energy. The light receiving element LRE may include an anode AE' and a cathode CE'. The anode AE' may be connected to the second node N2, and the cathode CE' may be connected to the second power line PL2.

[0108] The first transistor T1' may be connected to the light receiving element LRE, the second transistor T2', and the third transistor T3'. The first transistor T1' may include a first electrode receiving a second initialization voltage AINT, a control electrode connected to a second node N2, and a second electrode connected to the third transistor T3'. The first electrode of the first transistor T1' may be connected to a second initialization line VIL2 to receive the second initialization voltage AINT.

[0109] The second transistor T2 ′ may include a first electrode connected to the second node N2 , a control electrode connected to the i th reset scan line GRi, and a second electrode connected to a reset line VRL receiving a reset voltage VRST.

[0110] The third transistor T3' may include a first electrode connected to the second electrode of the first transistor T1', a control electrode connected to the i-th write scan line GWi, and a second electrode connected to the j-th receiving line RXj. The third transistor T3' may be turned on by the i-th write scan signal GWSi received through the i-th write scan line GWi.

[0111] The second transistor T2' may be turned on by the i-th reset scan signal GRSi received through the i-th reset scan line GRi. The turned-on second transistor T2' may receive the reset voltage VRST and provide the reset voltage VRST to the second node N2. The second node N2 may be reset by the reset voltage VRST.

[0112] The i-th write scan signal GWSi may be applied to the control electrode of the third transistor T3' so that the third transistor T3' may be turned on. The first transistor T1' may be connected to the j-th receiving line RXj through the turned-on third transistor T3'.

[0113] The light receiving element LRE receives light and converts the light into an electrical signal. In this case, the voltage of the second node N2 may change. When the first transistor T1' is turned on, the second initialization voltage AINT provided to the first transistor T1' may be controlled according to the voltage change of the second node N2, and the second initialization voltage AINT may be provided to the jth receiving line RXj through the third transistor T3'. Therefore, the signal sensed by the light receiving element LRE may be output as a sensing signal RS through the jth receiving line RXj.

[0114] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light emitting element, a first transistor, a fourth transistor and a sixth transistor of a pixel shown in FIG.

[0115] refer to Figure 6The light emitting element OLED may include a first electrode AE ​​(or anode), a second electrode CE (or cathode), a hole control layer HCL, an electron control layer ECL and a light emitting layer EML. The first electrode AE ​​may be Figure 5 The anode AE ​​shown in FIG. 1 and the second electrode CE may be Figure 5 The second electrode CE may be located on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the light emitting layer EML may be interposed between the first electrode AE ​​and the second electrode CE.

[0116] The first transistor T1, the fourth transistor T4 and the sixth transistor T6 and the light emitting element OLED may be located on the substrate SUB. The display area DA may include a light emitting area LEA corresponding to the pixel PXij and a non-light emitting area NLEA adjacent to the light emitting area LEA. The light emitting element OLED may be located in the light emitting area LEA.

[0117] The lower metal layer BML may be located on the substrate SUB. For example, the lower metal layer BML located below the first transistor T1 and the sixth transistor T6 is shown. The lower metal layer BML may be located below the pixel circuit PC. For example, the lower metal layer BML may overlap with the first transistor T1 and may be located below the first transistor T1. In addition, the lower metal layer BML may overlap with the sixth transistor T6 and may be located below the sixth transistor T6.

[0118] According to some embodiments, the lower metal layer BML may receive a constant voltage. When the constant voltage is applied to the lower metal layer BML, the value of the threshold voltage Vth of the first transistor T1 located on the lower metal layer BML may be maintained unchanged.

[0119] The lower metal layer BML may block light incident to the first transistor T1 from a lower portion of the lower metal layer BML. For example, the lower metal layer BML may include a reflective metal. For example, the lower metal layer BML may be omitted.

[0120] The buffer layer BFL may be located on the substrate SUB. The buffer layer BFL may be an inorganic layer. The buffer layer BFL may cover the lower metal layer BML. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may be located on the buffer layer BFL. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include polycrystalline silicon. However, the semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include amorphous silicon.

[0121] The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layer of the first transistor T1 and the semiconductor layer of the sixth transistor T6 may include a heavily doped region and a lightly doped region. The heavily doped region has a conductivity greater than that of the lightly doped region and may be substantially used as a source electrode and a drain electrode of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to the active portion (or channel) of the first transistor T1 and the sixth transistor T6.

[0122] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be formed by the semiconductor layer of the first transistor T1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be formed by the semiconductor layer of the sixth transistor T6. The first channel region A1 may be interposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be interposed between the sixth source region S6 and the sixth drain region D6.

[0123] The lower metal layer BML may overlap with and be located below the semiconductor layer of the first transistor T1. In addition, the lower metal layer BML may overlap with and be located below the sixth channel region A6 of the sixth transistor T6.

[0124] The first insulating layer INS1 may be located on the buffer layer BFL to cover the semiconductor layers of the first transistor T1 and the sixth transistor T6. The first gate electrode G1 (or control electrode) of the first transistor T1 and the sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be located on the first insulating layer INS1.

[0125] According to some embodiments, the structure of the source region, channel region, drain region, and gate electrode of each of the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 may be substantially the same as the structure of the source region, channel region, drain region, and gate electrode of the first transistor T1 and the sixth transistor T6.

[0126] The second insulating layer INS2 may be located on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The dummy electrode DME may be located on the second insulating layer INS2. The dummy electrode DME may be located on the first gate electrode G1 and may overlap the first gate electrode G1 when viewed in a plan view. The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1.

[0127] The third insulating layer INS3 may be located on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layer of the fourth transistor T4 may be located on the third insulating layer INS3. The semiconductor layer of the fourth transistor T4 may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor.

[0128] The semiconductor layer of the fourth transistor T4 may include a plurality of regions classified according to whether the metal oxide is relatively reduced. The region in which the metal oxide is relatively reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region may be used as a source electrode or a drain electrode of the fourth transistor T4. The non-reduction region may substantially correspond to the active portion (or channel) of the fourth transistor T4.

[0129] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 may be formed of a semiconductor layer of the fourth transistor T4. The fourth channel region A4 may be interposed between the fourth source region S4 and the fourth drain region D4.

[0130] The fourth insulating layer INS4 may be located on the third insulating layer INS3 to cover the semiconductor layer of the fourth transistor T4. The fourth gate electrode G4 of the fourth transistor T4 may be located on the fourth insulating layer INS4.

[0131] The fifth insulating layer INS5 may be located on the fourth insulating layer INS4 to cover the fourth gate electrode G4. The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer. According to some embodiments, the structures of the source region, the channel region, the drain region, and the gate electrode of the third transistor T3 may be substantially the same as those of the fourth transistor T4.

[0132] The connection electrode CNE may be interposed between the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may electrically connect the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1, a second connection electrode CNE2 located on the first connection electrode CNE1, and a third connection electrode CNE3 located on the second connection electrode CNE2.

[0133] The first connection electrode CNE1 is located on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. The sixth insulating layer INS6 may be located on the fifth insulating layer INS5 to cover the first connection electrode CNE1.

[0134] The second connection electrode CNE2 may be located on the sixth insulating layer INS6. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6. The seventh insulating layer INS7 may be located on the sixth insulating layer INS6 to cover the second connection electrode CNE2.

[0135] The third connection electrode CNE3 may be located on the seventh insulating layer INS7. The third connection electrode CNE3 may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be located on the seventh insulating layer INS7 to cover the third connection electrode CNE3. The sixth to eighth insulating layers INS6 to INS8 may include an inorganic layer or an organic layer.

[0136] The first electrode AE ​​may be located on the eighth insulating layer INS8. The first electrode AE ​​may be electrically connected to the third connection electrode CNE3 through a fourth contact hole CH4 defined in the eighth insulating layer INS8.

[0137] A pixel defining layer PDL exposing a specific portion of the first electrode AE ​​may be positioned on the first electrode AE ​​and the eighth insulating layer INS8. An opening PX_OP for exposing the specific portion of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0138] The hole control layer HCL may be located on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be located in common in the light emitting area LEA and the non-light emitting area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0139] The light emitting layer EML may be located on the hole control layer HCL. The light emitting layer EML may be located in a region corresponding to the opening PX_OP. The light emitting layer EML may include an organic material and / or an inorganic material. The light emitting layer EML may generate any one of red light, green light, and blue light.

[0140] The electron control layer ECL may be located on the light emitting layer EML and the hole control layer HCL. The electron control layer ECL may be commonly located in the light emitting area LEA and the non-light emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0141] The second electrode CE may be located on the electron control layer ECL. The second electrode CE may be located in common in the pixels PX. In other words, the second electrode CE may be located in common on the light emitting layer EML of the pixels PX.

[0142] The layer including the buffer layer BFL to the eighth insulating layer INS8 may be defined as a circuit element layer DP-CL. The layer in which the light emitting element OLED is positioned may be defined as a display element layer DP-OLED.

[0143] The thin film encapsulation layer TFE may be located on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. The inorganic layer may include an inorganic material to protect the pixel PX from moisture / oxygen. The organic layer may include an organic material to protect the pixel PX from foreign matter such as dust particles.

[0144] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. Holes and electrons injected into the light emitting layer EML recombine to form excitons, and the light emitting element OLED may emit light as the excitons transition to a ground state. The light emitting element OLED may emit light and may display an image.

[0145] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0146] In the following, we will focus on Figure 6 The stacking structure shown in the figure is a simultaneous description of different structures. Figure 7 The parts shown in .

[0147] refer to Figure 7 , the display area DA may include a light receiving area LRA corresponding to the sensor SNij and a non-light emitting area NLEA adjacent to the light receiving area LRA. The non-light emitting area NLEA may be Figure 6 The non-luminous area NLEA shown in FIG.

[0148] The light receiving element LRE may include a first electrode AE', a second electrode CE', a hole control layer HCL', an electron control layer ECL', and a light receiving layer OPD. The first electrode AE' may be Figure 5 The anode AE' shown in FIG. 1 and the second electrode CE' may be Figure 5 The cathode CE' shown in FIG.

[0149] The light receiving element LRE may be defined as an organic photodiode. The first electrode AE', the second electrode CE', the hole control layer HCL' and the electron control layer ECL' may be Figure 6 The first electrode AE, the second electrode CE, the hole control layer HCL and the electron control layer ECL shown in FIG. 1 are substantially the same components.

[0150] Figure 7 The position of the light receiving layer OPD in Figure 6In other words, the second electrode CE' is located on the first electrode AE' and the hole control layer HCL' and the electron control layer ECL', and the light receiving layer OPD may be located between the first electrode AE' and the second electrode CE'. The second electrode CE' may be commonly located on the light receiving layer OPD of the light receiving element LRE. The second electrode CE' may be located on the light receiving layer OPD of the light receiving element LRE. Figure 6 The second electrode CE shown in FIG. 1 is integrally formed. An opening PX_OP′ for exposing a specific portion of the first electrode AE′ may be defined in the pixel defining layer PDL.

[0151] The receiving line RX may be located on the substrate SUB. The receiving line RX may be Figure 4 The receiving line RX1 to RXh shown in FIG. 1 may be any one of the receiving lines RX1 to RXh shown in FIG. 1 . The buffer layer BFL may be located on the substrate SUB to cover the receiving line RX. The first transistor T1' may be located on the buffer layer BFL. The receiving line RX may be located below the sensing circuit SNC. For example, the receiving line RX may be located below the first transistor T1' to overlap with the first transistor T1'.

[0152] The receive line RX can be connected with Figure 6 The lower metal layer BML shown in FIG. 1 is located on the same layer. The receiving line RX may be formed by simultaneously patterning the same material as the lower metal layer BML.

[0153] The first transistor T1' may include a first source region S1', a first drain region D1', a first channel region A1', and a first gate electrode G1'. The second transistor T2' may include a second source region S2', a second drain region D2', a second channel region A2', and a second gate electrode G2'. The receiving line RX may be located below the first source region S1' to overlap with the first source region S1'.

[0154] The stack structure of the first transistor T1' can be Figure 6 The stack structure of the first transistor T1 shown in FIG. 1 is substantially the same as that of the second transistor T2′. Figure 6 The stack structure of the fourth transistor T4 shown in FIG. 1 is substantially the same. According to some embodiments, the stack structure of the third transistor T3 ′ may be substantially the same as the stack structure of the first transistor T1 ′.

[0155] The connection electrode CNE' may include a first connection electrode CNE1', a second connection electrode CNE2', and a third connection electrode CNE3'. The first connection electrode CNE1' may be connected to Figure 6 The first connection electrode CNE1 shown in FIG. 1 is located in the same layer as the second connection electrode CNE2′. Figure 6 The second connection electrode CNE2 shown in FIG. 1 is located in the same layer, and the third connection electrode CNE3′ may be connected to the Figure 6The third connection electrode CNE3 shown in FIG. 1 is located in the same layer.

[0156] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' through a first contact hole CH1' defined in the second to fifth insulating layers INS2 to INS5. The second connection electrode CNE2' may be connected to the first connection electrode CNE1' through a second contact hole CH2' defined in the sixth insulating layer INS6.

[0157] The third link electrode CNE3' may be connected to the second link electrode CNE2' through a third contact hole CH3' defined in the seventh insulating layer INS7. The first electrode AE' may be connected to the third link electrode CNE3' through a fourth contact hole CH4' defined in the eighth insulating layer INS8.

[0158] Figure 8 It is shown that the Figure 4 2 is a plan view of an arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in .

[0159] refer to Figure 8 Each of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 can be connected with Figure 5 and Figure 6 Each of the light receiving elements LRE can correspond to the light emitting element OLED shown in FIG. Figure 5 and Figure 7 The light receiving element LRE shown in FIG. 1 corresponds to the first light emitting element OLED1 which can express (or display) red. The second light emitting element OLED2 can display green. The third light emitting element OLED3 can display blue.

[0160] The display panel DP may include a plurality of first pixel units PU1 and a plurality of second pixel units PU2. The first pixel units PU1 may be arranged in the second direction DR2. The second pixel units PU2 may be arranged in the second direction DR2 while being adjacent to the first pixel units PU1 in the first direction DR1.

[0161] Each of the first pixel units PU1 may include one first light emitting element OLED1, two second light emitting elements OLED2, one third light emitting element OLED3 and one light receiving element LRE. In each of the first pixel units PU1, the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may be arranged in the order of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 and the second light emitting element OLED2 in the second direction DR2.

[0162] In each of the first pixel units PU1, the light receiving element LRE may be adjacent to the third light emitting element OLED3 and the second arranged second light emitting element OLED2. In each of the first pixel units PU1, the light receiving element LRE may be adjacent to the second arranged second light emitting element OLED2 in the first direction DR1.

[0163] Each of the second pixel units PU2 may include one first light emitting element OLED1, two second light emitting elements OLED2, one third light emitting element OLED3 and one light receiving element LRE. In each of the second pixel units PU2, the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may be arranged in the second direction DR2 in the order of the third light emitting element OLED3, the second light emitting element OLED2 and the first light emitting element OLED1, the second light emitting element OLED2.

[0164] In each of the second pixel units PU2, the light receiving element LRE may be adjacent to the third light emitting element OLED3 and the first arranged second light emitting element OLED2. In each of the second pixel units PU2, the light receiving element LRE may be adjacent to the first arranged second light emitting element OLED2 in the first direction DR1.

[0165] When viewed in a plan view, in each of the first pixel unit PU1 and the second pixel unit PU2, the area of ​​the first light emitting element OLED1 may be larger than the area of ​​the second light emitting element OLED2, and the area of ​​the third light emitting element OLED3 may be larger than the area of ​​the first light emitting element OLED1. In addition, when viewed in a plan view, in each of the first pixel unit PU1 and the second pixel unit PU2, the area of ​​the second light emitting element OLED2 may be larger than the area of ​​the light receiving element LRE.

[0166] When viewed in a plan view, the first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3, and the light receiving element LRE may have a rectangular shape, but the present disclosure is not limited thereto. For example, the first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3, and the light receiving element LRE may have various shapes, such as a rhombus shape and a circular shape.

[0167] Fig. 9 It is shown by Figure 5 and Figure 7 2 is a view of a fingerprint sensing state performed by the sensor shown in .

[0168] refer to Fig. 9, the display device DD may include a sensing unit SNP embedded in the display panel DP, and the sensing unit SNP may include a plurality of sensors SN. Each of the sensors SN may have Figure 5 and Figure 7 The same configuration of the sensor SNij shown in FIG. Fig. 9 Two sensors SN are shown, but substantially more sensors SN may be located in the display panel DP to form the sensing unit SNP.

[0169] The sensor SN may sense a fingerprint FNT of a finger FN provided on the display panel DP. Light generated from the light emitting element OLED of the pixel PX is provided to the fingerprint FNT and may be reflected from the fingerprint FNT.

[0170] The light reflected from the fingerprint FNT may be provided to the light receiving element LRE of the sensor SN to be sensed. The sensor SN may sense the fingerprint FNT by the light reflected from the fingerprint FNT. The control module in the display device DD may receive information about the fingerprint FNT sensed by the sensor SN and perform a user authentication mode using the received fingerprint information.

[0171] FIG. 10A to FIG. 10I is a cross-sectional view showing the structure of a pixel circuit and a sensing circuit when viewed in a plan view.

[0172] exist FIG. 10A to FIG. 10I In the example, each pixel circuit PC can be connected to Figure 5 The pixel circuit PC shown in FIG. 1 corresponds to the pixel circuit PC shown in FIG. 1 , and each of the sensing circuits SNC can be connected to Figure 5 The sensing circuit SNC shown in FIG. FIG. 10A to FIG. 10I Can be shown connected to Figure 8 1 and 2 , and a circuit of the light emitting elements OLED1 , OLED2 , and OLED3 and the light receiving element LRE of two adjacent first and second pixel units PU1 and PU2 in the first direction DR1 .

[0173] When viewed in a plan view, the pixel circuit PC and the sensing circuit SNC may not be arranged to precisely overlap with the light emitting elements OLED1 , OLED2 , and OLED3 and the light receiving element LRE.

[0174] For example, in Fig. 10A In FIG. 1 , the boundary between one pixel circuit PC and one sensing circuit SNC is shown as a dotted line, and for ease of explanation, only Fig. 10A The reference numerals of the pixel circuit PC and the sensing circuit SNC are shown in FIG. FIG. 10A to FIG. 10I , a configuration of one pixel circuit PC and one sensing circuit SNC will be described.

[0175] FIG. 10A to FIG. 10IIt can be defined as a layout diagram of a pixel circuit PC and a sensing circuit SNC. FIG. 10A to FIG. 10I In the description to be made, the word "overlap" indicates a state in which components overlap each other when viewed in a plan view. In the drawings related to the following description, the words "i-th" and "j-th" indicating the order of the above-mentioned lines are omitted. In other words, the layout of the pixel circuit PC and the sensing circuit SNC will be described without limiting the lines in a specific order.

[0176] refer to Fig. 10A , two pixel circuits PC may be located on the left and right sides of each of the sensing circuits SNC. The lower conductive pattern BMP may be located Figure 6 and Figure 7 The lower metal layer BML may be formed of the lower conductive pattern BMP. The lower metal layer BML may overlap with the pixel circuit PC.

[0177] The lower conductive pattern BMP is not limited to Fig. 10A The shape shown in , and may have various shapes. Figure 6 The lower metal layer BML shown in FIG. 5 may be formed of the lower conductive pattern BMP.

[0178] Figure 7 The receiving line RX shown in FIG. 1 may be formed of the lower conductive pattern BMP. The receiving line RX is located in the same layer as the lower metal layer BML and may be electrically separated from the lower metal layer BML. The receiving line RX may extend in the first direction DR1 to overlap the sensing circuit SNC.

[0179] refer to Fig. 10A and Fig. 10B , the first semiconductor pattern SMP1 may be located on the lower conductive pattern BMP. The first semiconductor pattern SMP1 is not limited to Fig. 10B The shape shown in , and may have various shapes.

[0180] The first source region S1, the second source region S2, the fifth source region S5, the sixth source region S6, the seventh source region S7 and the eighth source region S8, the first drain region D1, the second drain region D2, the fifth drain region D5, the sixth drain region D6, the seventh drain region D7 and the eighth drain region D8, the first channel region A1, the second channel region A2, the fifth channel region A5, the sixth channel region A6, the seventh channel region A7 and the eighth channel region A8 and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be formed by the first semiconductor pattern SMP1.

[0181] Each of the first channel region A1, the second channel region A2, the fifth channel region A5, the sixth channel region A6, the seventh channel region A7 and the eighth channel region A8 can be inserted between a corresponding one of the first source region S1, the second source region S2, the fifth source region S5, the sixth source region S6, the seventh source region S7 and the eighth source region S8 and a corresponding one of the first drain region D1, the second drain region D2, the fifth drain region D5, the sixth drain region D6, the seventh drain region D7 and the eighth drain region D8.

[0182] The second drain region D2 of the second transistor T2 and the fifth drain region D5 of the fifth transistor T5 may be formed by extending from the first source region S1 of the first transistor T1. The sixth source region S6 of the sixth transistor T6 may be formed by extending from the first drain region D1 of the first transistor T1. The seventh source region S7 of the seventh transistor T7 may be formed by extending from the sixth drain region D6 of the sixth transistor T6.

[0183] According to the above structure, the first transistor T1 may be connected to the second transistor T2 , the fifth transistor T5 , and the sixth transistor T6 , and the sixth transistor T6 may be connected to the seventh transistor T7 .

[0184] The first semiconductor pattern SMP1 of the eighth transistor T8 may be interposed between the first semiconductor pattern SMP1 of the fifth transistor T5 and the first semiconductor pattern SMP1 of the seventh transistor T7. The first semiconductor pattern SMP1 of the eighth transistor T8 may be formed in an island shape.

[0185] The first source region S1', the first drain region D1', and the first channel region A1' of the first transistor T1' and the third source region S3', the third drain region D3', and the third channel region A3' of the third transistor T3' may be formed by the first semiconductor pattern SMP1. Each of the first channel region A1' and the third channel region A3' may be interposed between each of the first source region S1' and the third source region S3' and each of the first drain region D1' and the third drain region D3', respectively. Two third channel regions A3' may be formed in the third transistor T3'.

[0186] The third source region S3' of the third transistor T3' may be formed by extending from the first drain region D1' of the first transistor T1. According to the above structure, the first transistor T1' may be connected to the third transistor T3'.

[0187] The first semiconductor pattern SMP1 of the first transistor T1 ′ and the third transistor T3 ′ may be adjacent to the first semiconductor pattern SMP1 of the second transistor T2 in the second direction DR2 .

[0188] The lower conductive pattern BMP may overlap a portion of the first semiconductor pattern SMP1 of the first transistor T1, the fifth transistor T5, and the sixth transistor T6. The receiving line RX may overlap a portion of the first semiconductor pattern SMP1 of the first transistor T1' and the third transistor T3'. For example, the receiving line RX may overlap the first source region S1' and the third drain region D3'.

[0189] refer to FIG. 10A to FIG. 10C , the first gate pattern GPT1 may be located on the first semiconductor pattern SMP1. The first gate pattern GPT1 may include a write scan line GW, a light emission line EL, a bias scan line GB, a first gate electrode G1, and a first gate electrode G1'.

[0190] The write scan line GW, the light emission line EL, and the bias scan line GB may extend in the second direction DR2 and may be arranged in the first direction DR1. The light emission line EL may be located between the write scan line GW and the bias scan line GB. The first gate electrode G1 and the first gate electrode G1' may be located between the write scan line GW and the light emission line EL.

[0191] The first gate electrode G1 of the first transistor T1 may be formed of the first gate pattern GPT1. The first gate electrode G1 may overlap the first channel region A1.

[0192] The write scan line GW may extend to cross the first semiconductor pattern SMP1. The second gate electrode G2 of the second transistor T2 may be formed by the write scan line GW. When viewed in a plan view, a portion of the write scan line GW overlapping the first semiconductor pattern SMP1 may be defined as the second gate electrode G2. When viewed in a plan view, the second gate electrode G2 may overlap the second channel region A2.

[0193] The light emission line EL may extend to cross the first semiconductor pattern SMP1. A fifth gate electrode G5 of the fifth transistor T5 and a sixth gate electrode G6 of the sixth transistor T6 may be formed of the light emission line EL.

[0194] When viewed in plan view, a portion of the light emission line EL overlapping the first semiconductor pattern SMP1 may be defined as fifth and sixth gate electrodes G5 and G6. When viewed in plan view, the fifth gate electrode G5 may overlap the fifth channel region A5, and the sixth gate electrode G6 may overlap the sixth channel region A6.

[0195] The bias scan line GB may extend to cross the first semiconductor pattern SMP1. The seventh gate electrode G7 of the seventh transistor T7 and the eighth gate electrode G8 of the eighth transistor T8 may be formed by the bias scan line GB. A portion of the bias scan line GB overlapping the first semiconductor pattern SMP1 may be defined as the seventh gate electrode G7 and the eighth gate electrode G8. The seventh gate electrode G7 and the eighth gate electrode G8 may overlap the seventh channel region A7 and the eighth channel region A8, respectively.

[0196] The first gate electrode G1' of the first transistor T1' may be formed of the first gate pattern GPT1. The first gate electrode G1' may overlap the first channel region A1'.

[0197] The third gate electrode G3' of the third transistor T3' may be formed by the write scan line GW. When viewed in a plan view, a portion of the write scan line GW overlapping the first semiconductor pattern SMP1 may be defined as the third gate electrode G3'. When viewed in a plan view, the third gate electrode G3' may overlap the third channel region A3'. Two third gate electrodes G3' may be formed.

[0198] In the following reference FIG. 10D to FIG. 10I In the description, for the convenience of explanation and brief reference numerals, the reference numerals of the first source region S1, the second source region S2, the fifth source region S5 to the eighth source region S8, the first drain region D1, the second drain region D2, the fifth drain region D5 to the eighth drain region D8, the first channel region A1, the second channel region A2, the fifth channel region A5 to the eighth channel region A8, and the first gate electrode G1, the second gate electrode G2, and the fifth gate electrode G5 to the eighth gate electrode G8 are omitted. In addition, the reference numerals of the first source region S1' and the third source region S3', the first drain region D1' and the third drain region D3', the first channel region A1' and the third channel region A3', and the first gate electrode G1' and the third gate electrode G3' are omitted.

[0199] FIG. 10D to FIG. 10I Reference numerals for the first transistor T1 , the second transistor T2 , and the fifth to eighth transistors T5 to T8 , as well as the first transistor T1 ′ and the third transistor T3 ′ are shown.

[0200] refer to FIG. 10A to FIG. 10D , the second gate pattern GPT2 may be located on the first gate pattern GPT1. The second gate pattern GPT2 may include a dummy electrode DME and a plurality of sub-dummy electrodes SDE and SDE'.

[0201] When viewed in a plan view, the dummy electrode DME may overlap the above-mentioned first gate electrode G1. The dummy electrode DME may form a capacitor CST together with the first gate electrode G1. An opening OP may be defined in the dummy electrode DME.

[0202] The sub-dummy electrodes SDE and SDE′ may extend in the second direction DR2 and may be arranged in the first direction DR1. When viewed in a plan view, the sub-dummy electrodes SDE and SDE′ may extend in the second direction DR2 and may be arranged in the first direction DR1. Fig.10F The reset scan line GR, the compensation scan line GC, and the initialization scan line GI shown in FIG. 1 overlap.

[0203] refer to FIG. 10A to FIG. 10E The second semiconductor pattern SMP2 may be located on the second gate pattern GPT2. The third source region S3, the third drain region D3, and the third channel region A3 of the third transistor T3, and the fourth source region S4, the fourth drain region D4, and the fourth channel region A4 of the fourth transistor T4 may be formed by the second semiconductor pattern SMP2.

[0204] The third channel region A3 and the fourth channel region A4 may be interposed between the associated one of the third source region S3 and the fourth source region S4 and the associated one of the third drain region D3 and the fourth drain region D4, respectively. The fourth drain region D4 of the fourth transistor T4 may be formed to extend from the third source region S3 of the third transistor T3. According to the above structure, the fourth transistor T4 may be connected to the third transistor T3.

[0205] The second source region S2', the second drain region D2', and the second channel region A2' of the second transistor T2' may be formed by the second semiconductor pattern SMP2. The second channel region A2' may be interposed between the second source region S2' and the second drain region D2'.

[0206] In the following, omitted FIG. 10F to FIG. 10I The reference numerals of the sub-dummy electrodes SDE and SDE′ in FIG.

[0207] refer to FIG. 10A to FIG. 10F , the third gate pattern GPT3 may be located on the second semiconductor pattern SMP2. The third gate pattern GPT3 may include a compensation scan line GC, an initialization scan line GI, a reset scan line GR, and a second initialization line VIL2.

[0208] The compensation scan line GC, the initialization scan line GI, the reset scan line GR, and the second initialization scan line VIL2 may extend in the second direction DR2 and may be arranged in the first direction DR1. Fig. 10D Each of the sub-dummy electrodes SDE shown in overlaps.

[0209] The compensation scan line GC may extend to cross the second semiconductor pattern SMP2. The third gate electrode G3 of the third transistor T3 may be formed by the compensation scan line GC. When viewed in a plan view, a portion of the compensation scan line GC overlapping the second semiconductor pattern SMP2 may be defined as the third gate electrode G3.

[0210] The initialization scan line GI may extend to cross the second semiconductor pattern SMP2. A fourth gate electrode G4 of the fourth transistor T4 may be formed by the initialization scan line GI. When viewed in a plan view, a portion of the initialization scan line GI overlapping the second semiconductor pattern SMP2 may be defined as the fourth gate electrode G4.

[0211] The reset scan line GR may extend to cross the second semiconductor pattern SMP2. The second gate electrode G2' of the second transistor T2' may be formed by the reset scan line GR. When viewed in a plan view, a portion of the reset scan line GR overlapping the second semiconductor pattern SMP2 may be defined as the second gate electrode G2'.

[0212] The second initialization line VIL2 may be adjacent to the seventh and eighth transistors T7 and T8 and the first and second transistors T1 ′ and T2 ′.

[0213] In the following reference FIG. 10G to FIG. 10I In the description, for the convenience of explanation and brief reference numerals, the reference numerals of the third source region S3 and the fourth source region S4, the third drain region D3 and the fourth drain region D4, the third channel region A3 and the fourth channel region A4, and the third gate electrode G3 and the fourth gate electrode G4 are omitted. In addition, the reference numerals of the second source region S2', the second drain region D2', the second channel region A2', and the second gate electrode G2' are omitted.

[0214] In addition, FIG. 10G to FIG. 10I In FIG. 1 , reference numerals of the writing scanning line GW, the compensation scanning line GC, the initialization scanning line GI, the bias scanning line GB, and the reset scanning line GR are also omitted. FIG. 10G to FIG. 10I Reference numerals of the first to eighth transistors T1 to T8 and the first to third transistors T1 ′ to T3 ′ are shown.

[0215] refer to Figure 10G , the first connection pattern CNP1 may be located on the third gate pattern GPT3. The first connection pattern CNP1 may include first connection electrodes CNE1, CNE1', and CNE1-1 to CNE1-9, a first initialization line VIL1, a reset line VRL, and a bias line VBL. The first connection electrode CNE1 may be Figure 6 The first connection electrode CNE1 ′ may be Figure 7The first connection electrode CNE1 ′ is shown in FIG.

[0216] The first initialization line VIL1, the reset line VRL, and the bias line VBL may extend in the second direction DR2 and may be arranged in the first direction DR1. The first initialization line VIL1 may be adjacent to the fourth transistor T4. The reset line VRL may be adjacent to the second transistor T2'. The bias line VBL may be adjacent to the eighth transistor T8.

[0217] The first connection electrodes CNE1, CNE1' and CNE1-1 to CNE1-9, the first initialization line VIL1, the reset line VRL and the bias line VBL may be located in the same layer. The first connection electrodes CNE1, CNE1' and CNE1-1 to CNE1-9, the first initialization line VIL1, the reset line VRL and the bias line VBL may be formed by patterning the same material at the same time.

[0218] A plurality of first contact holes CH1, CH1', and CH1-1 to CH1-12 may be defined. The first contact hole CH1 may be Figure 6 The first contact hole CH1' overlapped with the first gate electrode G1' may be Figure 7 The first contact holes CH1-1 to CH1-12 may be formed to be Figure 6 and Figure 7 The first contact hole CH1 or the first contact hole CH1 ′ shown in FIG.

[0219] The first connection electrode CNE1 may be connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CH1 .

[0220] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' and the second source region S2' of the second transistor T2' through the first contact hole CH1'. The first transistor T1' and the second transistor T2' may be connected to each other through the first connection electrode CNE1'.

[0221] The first connection electrode CNE1-1 may be connected to the third transistor T3 and the first and sixth transistors T1 and T6 through the first contact hole CH1-1. The first connection electrode CNE1-1 may be connected to the first drain region D1 of the first transistor T1, the sixth source region S6 of the sixth transistor T6, and the third drain region D3 of the third transistor T3. The third transistor T3 may be connected to the first transistor T1 and the sixth transistor T6 through the first connection electrode CNE1-1.

[0222] The first connection electrode CNE1-2 may be connected to the fifth transistor T5 and the dummy electrode DME of the capacitor CST through the first contact hole CH1-2. The first connection electrode CNE1-2 may be connected to the fifth source region S5 of the fifth transistor T5.

[0223] The first connection electrode CNE1-3 may be connected to the first gate electrode G1 of the first transistor T1 and the third and fourth transistors T3 and T4 through the first contact hole CH1-3. The first connection electrode CNE1-3 may be connected to the third source region S3 of the third transistor T3 and the fourth drain region D4 of the fourth transistor T4. The third and fourth transistors T3 and T4 may be connected to the first transistor T1 through the first connection electrode CNE1-3.

[0224] An opening OP may be formed in the dummy electrode DME so that a portion of the first gate electrode G1 may be exposed by the opening OP. Since the first contact hole CH1-3 is formed to overlap the opening OP, the first connection electrode CNE1-3 may be easily connected to the first gate electrode G1.

[0225] The first connection electrode CNE1-4 may be connected to the second transistor T2 through the first contact hole CH1-4. The first connection electrode CNE1-4 may be connected to the second source region S2 of the second transistor T2.

[0226] The first connection electrode CNE1-5 may be connected to any one of the second initialization lines VIL2 and the seventh transistor T7 through the first contact hole CH1-5. The first connection electrode CNE1-5 may be connected to the seventh drain region D7 of the seventh transistor T7 through the first contact hole CH1-5. The seventh transistor T7 may be connected to the second initialization line VIL2 through the first connection electrode CNE1-5.

[0227] The first connection electrode CNE1-6 may be connected to the fifth transistor T5 and the eighth transistor T8 through the first contact hole CH1-6. The first connection electrode CNE1-6 may be connected to the fifth drain region D5 of the fifth transistor T5 and the eighth drain region D8 of the eighth transistor T8 through the first contact hole CH1-6. The fifth transistor T5 may be connected to the eighth transistor T8 through the first connection electrode CNE1-6.

[0228] The first connection electrode CNE1-7 may be connected to any one of the second initialization lines VIL2 and the first transistor T1' through the first contact hole CH1-7. The first connection electrode CNE1-7 may be connected to the first source region S1' of the first transistor T1' through the first contact hole CH1-7. The first transistor T1' may be connected to the second initialization line VIL2 through the first connection electrode CNE1-7.

[0229] The first connection electrode CNE1-8 may be connected to the third transistor T3' and the receiving line RX through the first contact hole CH1-8. The first connection electrode CNE1-8 may be connected to the third drain region D3' of the third transistor T3'. The sensing circuit SNC may be connected to the receiving line RX through the first connection electrode CNE1-8.

[0230] The 1-9th connection electrode CNE1-9 may be connected to the Fig. 10D The sub-dummy electrode SDE' shown in .

[0231] The first initialization line VIL1 may be connected to the fourth transistor T4. The first initialization line VIL1 may be connected to the fourth source region S4 of the fourth transistor T4 through the first contact hole CH1-10.

[0232] The bias line VBL may be connected to the eighth transistor T8. The bias line VBL may be connected to the eighth source region S8 of the eighth transistor T8 through the first contact hole CH1-11.

[0233] The reset line VRL may be connected to the second transistor T2 ′. The reset line VRL may be connected to the second drain region D2 ′ of the second transistor T2 ′ through the first contact hole CH1 - 12 .

[0234] In the following reference FIG. 10H to FIG. 10I In the description made, reference numerals of the first connection electrodes CNE1, CNE1' and CNE1-1 to CNE1-9, the first contact holes CH1, CH1' and CH1-1 to CH1-12, and the dummy electrodes DME are omitted for convenience of explanation and brief reference numerals.

[0235] refer to FIG. 10A to FIG. 10H , the second connection pattern CNP2 may be located on the first connection pattern CNP1. The second connection pattern CNP2 may include second connection electrodes CNE2, CNE2', and CNE2-1 to CNE2-2, a first power line PL1, and a reset line VRL'.

[0236] The second connection electrode CNE2 may be Figure 6 The second connection electrode CNE2′ may be Figure 7 The second connection electrode CNE2 ′ is shown in FIG.

[0237] The first power line PL1 may extend in the first direction DR1 and may overlap the pixel circuit PC. The reset line VRL′ may extend in the first direction DR1 and may overlap the sensing circuit SNC.

[0238] An opening POP may be defined in the first power line PL1, and the second link electrodes CNE2 and CNE2-2 may be located in the opening POP. An opening ROP may be defined in the reset line VRL', and the second link electrode CNE2' may be located in the opening ROP. The second link electrode CNE2-1 may be interposed between the first power line PL1 and the reset line VRL'.

[0239] The second connection electrodes CNE2, CNE2' and CNE2-1 to CNE2-2, the first power line PL1 and the reset line VRL' may be located in the same layer. The second connection electrodes CNE2, CNE2' and CNE2-1 to CNE2-2, the first power line PL1 and the reset line VRL' may be formed by patterning the same material at the same time.

[0240] A plurality of second contact holes CH2, CH2', and CH2-1 to CH2-4 may be defined. The second contact hole CH2 may be Figure 6 The second contact hole CH2' may be Figure 7 The second contact holes CH2-1 to CH2-4 may be formed to be Figure 6 and Figure 7 The second contact holes CH2 and CH2' shown in FIG. 5 are similar.

[0241] The second link electrode CNE2 may be connected to the first link electrode CNE1 through the second contact hole CH2. Therefore, the second link electrode CNE2 may be connected to the sixth transistor T6 through the first link electrode CNE1.

[0242] The second link electrode CNE2' may be connected to the first link electrode CNE1' through the second contact hole CH2'. Therefore, the second link electrode CNE2' may be connected to the second transistor T2' through the first link electrode CNE1'.

[0243] The second link electrode CNE2-1 may be connected to the first link electrode CNE1-4 through the second contact hole CH2-1. Therefore, the second link electrode CNE2-1 may be connected to the second transistor T2 through the first link electrode CNE1-4.

[0244] The second link electrode CNE2-2 may be connected to the first link electrode CNE1-5 through the second contact hole CH2-2. Therefore, the second link electrode CNE2-2 may be connected to the second initialization line VIL2 through the first link electrode CNE1-5.

[0245] exist Fig. 10H, the second connection electrode CNE2-2 may be located at the left and right sides. The second connection electrode CNE2-2 at the left side may be connected to one first connection electrode CNE1-5 through one second contact hole CH2-2. The second connection electrode CNE2-2 at the right side may be connected to two second connection electrodes CNE1-5 through two second contact holes CH2-2.

[0246] The first power line PL1 may be connected to the first link electrode CNE1-2 through the second contact hole CH2-3. Therefore, the first power line PL1 may be connected to the fifth transistor T5 and the dummy electrode DME through the first link electrode CNE1-2.

[0247] The reset line VRL' may be connected to the reset line VRL through the second contact hole CH2-4. The reset line VRL' may be connected to the second transistor T2' through the reset line VRL. The reset line VRL and the reset line VRL' may be connected to each other to receive the reset voltage VRST as a constant voltage. The reset line VRL' may overlap a portion of the receiving line RX. The reset line VRL' may be defined as a first shielding electrode SHE1.

[0248] In the following Fig.10I , for simplicity of reference numerals, reference numerals of the second connection electrodes CNE2, CNE2', and CNE2-1 to CNE2-2 and the second contact holes CH2, CH2', and CH2-1 to CH2-4 are omitted.

[0249] refer to FIG. 10A to FIG. 10I , the third connection pattern CNP3 may be located on the second connection pattern CNP2. The third connection pattern CNP3 may include a plurality of third connection electrodes CNE3 and CNE3', a data line DL, a reset line VRL', and a second initialization line VIL2'.

[0250] The third connection electrode CNE3 may be Figure 6 The third connection electrode CNE3′ may be Figure 7 The third connection electrode CNE3 ′ shown in FIG.

[0251] The data line DL, the reset line VRL″, and the second initialization line VIL2′ may extend in the first direction DR1 and may be arranged in the second direction DR2. The data line DL and the second initialization line VIL2′ may overlap the pixel circuit PC, and the reset line VRL″ may overlap the sensing circuit SNC.

[0252] The third link electrode CNE3 may be located between the second initialization line VIL2' and the data line DL. The data line DL may be located between the second initialization line VIL2' and the reset line VRL".

[0253] The third link electrodes CNE3 and CNE3', the data line DL, the reset line VRL", and the second initialization line VIL2' may be located in the same layer. The third link electrodes CNE3 and CNE3', the data line DL, the reset line VRL", and the second initialization line VIL2' may be formed by patterning the same material at the same time.

[0254] A plurality of third contact holes CH3, CH3', and CH3-1 to CH3-3 may be defined. The third contact hole CH3 may be Figure 6 The third contact hole CH3 'may be Figure 7 The third contact holes CH3-1 to CH3-3 may be formed to be Figure 6 and Figure 7 The third contact holes CH3 and CH3' shown in FIG.

[0255] The third link electrode CNE3 may be connected to the second link electrode CNE2 through the third contact hole CH3. Figure 6 The fourth contact hole CH4 shown in FIG. 1 is connected to the first electrode AE. Therefore, the first electrode AE ​​may be connected to the sixth transistor T6 through the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3.

[0256] The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through the third contact hole CH3'. According to some embodiments, the third connection electrode CNE3' may be connected to the second connection electrode CNE2' through the third contact hole CH3'. Figure 7 The fourth contact hole CH4' shown in FIG. Figure 7 Therefore, the first electrode AE' may be connected to the second transistor T2' through the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3'.

[0257] The data line DL may be connected to the second link electrode CNE2-1 through the third contact hole CH3-1. Therefore, the data line DL may be connected to the second transistor T2 through the first link electrode CNE1-4 and the second link electrode CNE2-1.

[0258] The second initialization line VIL2' may be connected to the second connection electrode CNE2-2 through the third contact hole CH3-2. Therefore, the second initialization line VIL2' may be connected to the second initialization line VIL2 through the second connection electrode CNE2-2 and the first connection electrode CNE1-5. The second initialization voltage AINT may be provided to the seventh transistor T7 through the second initialization line VIL2' and the second initialization line VIL2.

[0259] The reset line VRL" may be connected to the reset line VRL' through the third contact hole CH3-3. The reset line VRL" may be connected to the reset line VRL through the reset line VRL'. The reset voltage VRST may be provided to the second transistor T2' through the reset line VRL, the reset line VRL' and the reset line VRL". The reset line VRL" may overlap with a portion of the receiving line RX. The reset line VRL" may be defined as a second shielding electrode SHE2.

[0260] The data lines DL may be located at the left and right sides of the reset lines VRL′ and VRL″ when viewed in a plan view. In other words, the reset lines VRL′ and VRL″ may be located between the data lines DL.

[0261] The data voltage VD applied to the data line DL may be a pulse-type signal. The pulse-type signal may affect the sensing signal RS output through the receiving line RX.

[0262] When viewed in a plan view, the reset lines VRL' and VRL" are placed between the data lines DL and overlap the receiving line RX to block the influence of the pulse-type data voltage VD on the sensing signal RS. In other words, the reset lines VRL' and VRL" may be used as shielding electrodes. The reset lines VRL' and VRL" may receive a reset voltage VRST as a constant voltage of the shielding electrode.

[0263] Fig.11 is a diagram showing a display panel in which a FIG. 10A to FIG. 10I Schematic cross-sectional view of portions of the receiving line and the data line.

[0264] For example, Fig.11 A reception line RX, a first connection electrode CNE1-8 connected to the reception line RX, a first shielding electrode SHE1 and a second shielding electrode SHE2 defined by reset lines VRL′ and VRL″, a data line DL, and connection electrodes CNE1-4 and CNE2-1 connected to the data line DL and the second transistor T2 and the third transistor T3 are shown. In addition, some electrode patterns of the first connection pattern CNP1, the second connection pattern CNP2, and the third connection pattern CNP3 around the second transistor T2 and the third transistor T3 are shown as examples.

[0265] exist Fig.11 For the sake of convenience, the FIG. 10A to FIG. 10I The contact holes shown in FIG.

[0266] If necessary, Figure 6 Describe together Fig.11 .

[0267] refer to Figure 6 and Fig.11, when viewed in a plan view, the first connection electrode CNE1-8 may be located under the data line DL without overlapping the data line DL. The receiving line RX may be located under the first connection electrode CNE1-8 and connected to the first connection electrode CNE1-8.

[0268] The receiving line RX may not be located in the same layer as the second connection pattern CNP2. In addition, the receiving line RX may not be located in the same layer as the third connection pattern CNP3. According to some embodiments of the present disclosure, the receiving line RX may be located in the same layer as the lower metal layer BML under the first connection electrode CNE1-8, so that the receiving line RX is spaced far apart from the data line DL.

[0269] The capacitance of the capacitor may be inversely proportional to the distance between the conductors. The receiving line RX may be located in the same layer as the second connection pattern CNP2 or the third connection pattern CNP3, and may be located adjacent to the data line DL. In this case, the capacitance of the parasitic capacitor formed between the receiving line RX and the data line DL may be increased.

[0270] As the capacitance of the parasitic capacitor increases, the noise of the sensing signal RS output through the receiving line RX may increase according to the influence of the pulse-shaped data voltage VD applied to the data line DL. This phenomenon may be defined as a coupling phenomenon. When the capacitance of the parasitic capacitor increases, the coupling phenomenon may also increase.

[0271] However, according to some embodiments of the present disclosure, the receiving line RX may be located in the same layer as the lower metal layer BML to be away from the data line DL. In this case, the capacitance of the parasitic capacitor formed between the receiving line RX and the data line DL may be relatively reduced, and the coupling phenomenon may be relatively reduced. Therefore, the influence of the data voltage VD on the sensing signal RS output through the receiving line RX may be relatively reduced, thereby relatively reducing the noise of the sensing signal RS. Therefore, the sensing sensitivity of the sensor SN may be relatively improved.

[0272] For example, when the receiving line RX overlaps with the sensing circuit SNC and is placed on the same layer as the second connection pattern CNP2, the capacitance of the parasitic capacitor formed by the receiving line RX and the data line DL is measured to be 257.1 [fF]. However, according to some embodiments of the present disclosure, when the receiving line RX overlaps with the sensing circuit SNC and is placed in the same layer as the lower metal layer BML, the capacitance of the parasitic capacitor formed by the receiving line RX and the data line DL is measured to be 45 [fF].

[0273] Hereinafter, the first connection electrode CNE1 - 4 is defined as a 1-1th connection electrode CN1 - 1 , and the second connection electrode CNE2 - 1 is defined as a 2-1th connection electrode CN2 - 1 .

[0274] The 1-1th connection electrode CN1-1 may be located on the pixel circuit PC and connected to the second transistor T2. The 2-1th connection electrode CN2-1 may be located on the 1-1th connection electrode CN1-1 and connected to the 1-1th connection electrode CN1-1. The data line DL may be located on the 2-1th connection electrode CN2-1 and connected to the 2-1th connection electrode CN2-1.

[0275] The first connection electrode CNE1-8 may be located in the same layer as the 1-1th connection electrode CN1-1. The 2-1th connection electrode CN2-1 may be located above the first connection electrode CNE1-8.

[0276] The first shielding electrode SHE1 and the second shielding electrode SHE2 may be located on the receiving line RX. As described above, the first shielding electrode SHE1 may be located on the first connection electrode CNE1-8, and when viewed in a plan view, the first shielding electrode SHE1 may overlap a portion of the receiving line RX. The first shielding electrode SHE1 may be located in the same layer as the 2-1st connection electrode CN2-1. The first shielding electrode SHE1 may be located under the data line DL.

[0277] The second shielding electrode SHE2 may be located on and connected to the first shielding electrode SHE1. As described above, the second shielding electrode SHE2 may overlap a portion of the receiving line RX when viewed in a plan view. The second shielding electrode SHE2 may be located in the same layer as the data line DL and adjacent to the data line DL.

[0278] The first and second shielding electrodes SHE1 and SHE2 may receive a reset voltage VRST as a constant voltage to serve as shielding electrodes. The influence of the data voltage VD on the sensing signal RS may be blocked by the first and second shielding electrodes SHE1 and SHE2.

[0279] like Fig. 10H and Fig.10I As shown in FIG. 1 , the reset lines VRL′ and VRL″ defining the first shielding electrode SHE1 and the second shielding electrode SHE2 may be connected to the reset line VRL. Therefore, the first shielding electrode SHE1 and the second shielding electrode SHE2 may be connected to the reset line VRL. Figure 10G As shown in FIG. 1 , the reset line VRL may be located in the same layer as the first link electrode CNE1 - 8 .

[0280] Fig.12 is a view showing a cross-sectional structure of a display panel according to some embodiments of the present disclosure.

[0281] Fig.12 With Fig.11 The corresponding cross-sectional view is shown in the following, and the Fig.12The configuration shown in Fig.11 The configuration shown in the figure is different from the configuration.

[0282] refer to Fig.12 , the display panel DP may further include a dummy electrode DET. The dummy electrode DET may be located on the sixth insulating layer INS6. The dummy electrode DET may be located in the same layer as the second connection pattern CNP2. The dummy electrode DET may be connected to the first connection electrode CNE1-8 through a contact hole CH" defined in the sixth insulating layer INS6. In addition, since the dummy electrode DET is connected to the first connection electrode CNE1-8, the wiring resistance of the receiving line RX may be relatively reduced.

[0283] According to some embodiments of the present disclosure, the receiving line of the sensor is arranged in the same layer as the lower metal layer, so that the receiving line is spaced far apart from the data line. Therefore, as the influence of the data voltage on the sensing signal output through the receiving line is relatively reduced, the noise of the sensing signal output through the receiving line can be relatively reduced. Therefore, the sensitivity of the sensor can be relatively improved.

[0284] Although aspects of some embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications and substitutions may be made without departing from the scope and spirit of the present invention as disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0285] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims and their equivalents.

Claims

1. Display equipment, including: Data cable; A pixel circuit connected to the data line; A light emitting element connected to the pixel circuit; A first connecting electrode, below the data line; A sensing circuit connected to the first connecting electrode; a light receiving element connected to the sensing circuit; as well as A receiving line is below the first connection electrode and connected to the first connection electrode.

2. The display device according to claim 1, wherein: The receive line is below the sensing circuit.

3. The display device according to claim 1, further comprising: The lower metal layer, below the pixel circuit, The receiving line and the lower metal layer are in the same layer.

4. The display device according to claim 3, wherein: The receiving line is separated from the lower metal layer.

5. The display device according to claim 3, wherein: The pixel circuit comprises: a first transistor including a first electrode connected to a first power line, a second electrode connected to an anode of the light emitting element, and a control electrode connected to a first node; a second transistor including a first electrode connected to the data line, a second electrode connected to the first electrode of the first transistor, and a control electrode connected to a write scan line; and a capacitor connected to the first power line and the first node, and Wherein, the lower metal layer is below the first transistor.

6. The display device according to claim 1, further comprising: A 1-1 connecting electrode, on the pixel circuit; as well as a 2-1st connecting electrode on the 1-1st connecting electrode and connected to the 1-1st connecting electrode, Wherein, the data line is on the 2-1th connecting electrode and connected to the 2-1th connecting electrode.

7. The display device according to claim 6, wherein: The first connecting electrode and the 1-1th connecting electrode are in the same layer.

8. The display device according to claim 6, further comprising: A first shielding electrode is on the first connecting electrode and overlaps a portion of the receiving line in a plan view.

9. The display device according to claim 8, wherein: The first shielding electrode and the 2-1st connecting electrode are in the same layer.

10. The display device according to claim 8, further comprising: A second shielding electrode is on the first shielding electrode and overlaps a portion of the receiving line in the plan view.

11. The display device according to claim 10, wherein: The second shielding electrode is in the same layer as the data line and is adjacent to the data line.

12. The display device according to claim 10, wherein: The second shielding electrode is connected to the first shielding electrode.

13. The display device according to claim 10, wherein: The first shielding electrode and the second shielding electrode receive a constant voltage.

14. The display device according to claim 10, further comprising: A reset line is connected to the sensing circuit and is configured to receive a reset voltage.

15. The display device according to claim 14, wherein: The first shielding electrode and the second shielding electrode are connected to the reset line.

16. The display device according to claim 14, wherein: The reset line is in the same layer as the first connection electrode.

17. The display device according to claim 1, further comprising: A dummy electrode is on the first connection electrode and connected to the first connection electrode.

18. Display equipment, including: Data cable; A pixel circuit connected to the data line; A light emitting element connected to the pixel circuit; A lower metal layer, below the pixel circuit; a receiving line in the same layer as the lower metal layer; a sensing circuit connected to the receiving line; as well as A light receiving element is connected to the sensing circuit.

19. The display device according to claim 18, further comprising: a first shielding electrode, on the receiving line and overlapping a portion of the receiving line in a plan view; as well as A second shielding electrode is on the first shielding electrode and overlaps a portion of the receiving line in the plan view.

20. The display device according to claim 19, wherein The second shielding electrode and the data line are in the same layer, Wherein, the first shielding electrode is below the data line, and Wherein, the first shielding electrode and the second shielding electrode are configured to receive a constant voltage.

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