Display device

Abstract

There is provided a display device including: a display element including a light emitter emitting light; a first refractive layer disposed over the display element; and a second refractive layer covering the first refractive layer, in which an edge of the light emitter includes a first light emitting edge extending in a first direction, and an edge of the first refractive layer includes a first refractive edge corresponding to the first light emitting edge, and the first refractive edge includes a first portion forming a first angle with the first light emitting edge on a plane and a second portion forming a second angle larger than the first angle with the first light emitting edge on the plane.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0105631 filed on August 11, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device having excellent light emitting efficiency. Background Art

[0004] As the demand for display devices expands, the demand for display devices that can be used for various purposes is also increasing. With this trend, display devices tend to gradually become larger or thinner, and the demand for display devices that provide larger and thinner displays while having accurate and vivid colors is also increasing. Summary of the invention

[0005] One or more embodiments include a display device in which the efficiency of light extracted from the display device is improved. However, the one or more embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device is provided, including: a display element including a light emitter that emits light; a first refractive layer disposed on the display element; and a second refractive layer covering the first refractive layer. An edge of the light emitter includes a first light-emitting edge extending in a first direction. An edge of the first refractive layer includes a first refractive edge corresponding to the first light-emitting edge. The first refractive edge includes a first portion that forms a first angle with the first light-emitting edge on a plane and a second portion that forms a second angle with the first light-emitting edge on a plane that is larger than the first angle.

[0008] According to one or more embodiments, an edge of the first refractive layer surrounds the light emitter in a plane.

[0009] According to one or more embodiments, the first light emitting edge and the first portion may be parallel on a plane.

[0010] According to one or more embodiments, the second angle is at least about 20° but not more than about 70° in the plane.

[0011] According to one or more embodiments, the second portion may be shaped to protrude in a second direction intersecting the first direction on a plane.

[0012] According to one or more embodiments, the first refractive edge may have a form in which the first portion and the second portion are alternately connected.

[0013] According to one or more embodiments, a length of the second portion in the first direction may be at least about 0.2 times but not more than about 4 times a length of the first portion in the first direction.

[0014] According to one or more embodiments, the first refraction layer may at least partially overlap with the light emitter.

[0015] According to one or more embodiments, a refractive index of the first refractive layer may be greater than a refractive index of the second refractive layer.

[0016] According to one or more embodiments, a portion of an edge of the first refraction layer may overlap a portion of an edge of the light emitter on a plane.

[0017] According to one or more embodiments, the second portion may be arc-shaped in a plane.

[0018] According to one or more embodiments, the first refraction layer may have a thickness of at least about 1.5 μm but not more than about 5 μm.

[0019] According to one or more embodiments, an edge of the first refraction layer may be provided with a slope forming an angle of at least about 30° but not more than about 85° with a layer disposed therebelow.

[0020] According to one or more embodiments, the device may further include an encapsulation layer between the display element and the first refraction layer.

[0021] According to one or more embodiments, the device may further include an input detection layer disposed on the encapsulation layer and including a conductive layer and a touch insulating layer covering the conductive layer. The touch insulating layer and the first refractive layer may be arranged in the same layer.

[0022] According to another aspect of the present disclosure, a display device is provided, comprising: a display element including a light emitter that emits light; an encapsulation layer covering the display element; a first refractive layer disposed on the encapsulation layer, the first refractive layer having an edge surrounding the light emitter on a plane; and a second refractive layer covering the first refractive layer. The edge of the first refractive layer includes a first portion parallel to the edge of the light emitter on a plane and a second portion protruding in a direction perpendicular to the edge of the light emitter on a plane.

[0023] According to one or more embodiments, a refractive index of the first refractive layer may be at least 0.04 greater than a refractive index of the second refractive layer.

[0024] According to one or more embodiments, the edge of the first refraction layer may have a form in which the first portions and the second portions are alternately connected.

[0025] According to one or more embodiments, the second portion may be arc-shaped in a plane.

[0026] According to one or more embodiments, an edge of the first refraction layer may be provided with a slope forming an angle of at least about 30° but not more than about 85° with a layer disposed therebelow.

[0027] Other aspects and features besides those described above will become apparent from the detailed description, claims and drawings for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a perspective view schematically showing a display device according to an embodiment.

[0030] Figure 2 is as along Figure 1 FIG. 1 is a cross-sectional view taken along line II′ of FIG. 1 , schematically showing a cross-sectional view of a display device according to an embodiment.

[0031] Figure 3 is a top view schematically showing a display device according to an embodiment.

[0032] Figure 4A and Figure 4B is a schematic diagram of an equivalent circuit of a pixel that may be included in the display device according to the embodiment.

[0033] Figure 5 is a partial top view schematically showing the arrangement of pixels according to the embodiment.

[0034] Figure 6 is as along Figure 5 FIG. 1 is a cross-sectional view taken along line II-II′ of FIG. 1 , schematically showing a cross-sectional view of a display device according to an embodiment.

[0035] Figure 7 is a top view schematically showing an arrangement of light emitters in a display area according to an embodiment.

[0036] Figure 8 is as along Figure 7 FIG. 1 is a cross-sectional view taken along line III-III′ of FIG. 1 , schematically showing a cross-sectional view of a display device according to an embodiment.

[0037] Fig. 9is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment.

[0038] Fig.10 is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment.

[0039] Fig.11A and Fig. 11B is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment.

[0040] Fig.12 is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment.

[0041] Fig.13A and Fig. 13B is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment.

[0042] Fig.14 is a top view schematically illustrating a placement relationship of a light emitter and a first refraction layer according to an embodiment. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to the embodiments of which examples are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the current embodiment may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, the following only describes the embodiments to explain the aspects of the current description by reference to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] Since the present disclosure can be modified in various ways and can have many embodiments, specific embodiments will be shown in the drawings and will be described in detail in the detailed description. With reference to the embodiments described in detail below together with the drawings, the effects and features of the present disclosure and the methods for realizing them will become clear. However, the present disclosure is not limited to the embodiments described herein and can be implemented in various forms.

[0045] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and when describing with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and their repeated description will be omitted.

[0046] In the following embodiments, the terms “first”, “second”, etc. are not intended to be limiting but are used to distinguish one component from another.

[0047] In the following embodiments, a singular expression includes a plural number unless the context clearly indicates otherwise.

[0048] In the following embodiments, the terms “comprising”, “having” and the like are intended to imply the presence of the stated features or components, and do not exclude the possibility of adding one or more other features or components.

[0049] In the following embodiments, when a film, region, component, etc. is referred to as being on or above another film, region, component, etc., this includes not only when it is directly on the other film, region, component, etc., but also when there are other films, regions, components, etc. arranged between them.

[0050] In the drawings, the size of components may be exaggerated or reduced for ease of illustration. For example, for ease of description, the size and thickness of each configuration shown in the drawings are arbitrary, and the present disclosure is not necessarily limited to the shown sizes and thicknesses.

[0051] In some embodiments, a particular process sequence may be performed in an order different from the order in which it is described. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order in which it is described.

[0052] As used herein, "A and / or B" means A, B, or both A and B. In addition, "at least one of A and B" means the case of A, B, or both A and B.

[0053] In the following embodiments, references to connections of films, regions, components, etc. include direct connections between films, regions, and components and / or indirect connections between films, regions, and components (wherein other films, regions, and components are arranged between these films, regions, and components). For example, as used herein, when films, regions, components, etc. are mentioned to be electrically connected herein, this refers to direct electrical connections of films, regions, components, etc. and / or indirect electrical connections of films, regions, components, etc. (wherein other films, regions, components, etc. are arranged between these films, regions, components, etc.).

[0054] The terms "x direction", "y direction" and "z direction" are not limited to directions corresponding to the three axes in a rectangular coordinate system, but can be broadly interpreted as including directions corresponding to the three axes in a Cartesian coordinate system. For example, the x direction, the y direction and the z direction may be orthogonal to each other, however, the x direction, the y direction and the z direction may also refer to different directions that are not orthogonal to each other.

[0055] Figure 1is a perspective view schematically showing a display device 1 according to the embodiment.

[0056] refer to Figure 1 , the display device 1 according to the embodiment may include a display area DA and a peripheral area PA. The peripheral area PA may be arranged to surround the display area DA at the periphery of the display area DA. The peripheral area PA may include various wirings and driving circuit parts for transmitting electrical signals to be applied to the display area DA. The display device 1 may provide a specific image using light emitted by a plurality of pixels arranged in the display area DA. Although not shown, the display device 1 may be bent by including a bending area in a portion of the peripheral area PA.

[0057] The display device 1 may be a display device such as an organic light-emitting display device, an inorganic light-emitting display device (e.g., an inorganic electroluminescent (EL) display device), or a quantum dot light-emitting display device. Hereinafter, an organic light-emitting display device will be described as an example. The display device 1 may be implemented in various types of electronic devices such as a mobile phone, a laptop computer, or a smart watch.

[0058] Figure 2 is a cross-sectional view schematically showing a display device 1 according to an embodiment. More specifically, Figure 2 Along with Figure 1 It corresponds to the cross-sectional view taken along line II'.

[0059] refer to Figure 2 The display device 1 may include a substrate 100, a pixel layer PXL on the substrate 100, an encapsulation layer 300 sealing the pixel layer PXL, an input detection layer 400 on the encapsulation layer 300, a refraction layer 500, a polarization layer 600 on the refraction layer 500, an adhesive layer 700 and a window 800 sequentially stacked in a thickness direction (z direction).

[0060] The substrate 100 may include a glass material, or may include a polymer resin. For example, the substrate 100 may include a substrate including silicon oxide (SiO 2 ) or may include various materials having flexible or bendable properties (eg, resin such as reinforced plastic). Although not shown, the substrate 100 may be bent by including a bending region in a portion of the peripheral area PA.

[0061] The pixel layer PXL may be disposed on the substrate 100. The pixel layer PXL may include a display element layer DPL including a display element disposed in each pixel and a pixel circuit layer PCL including a pixel circuit disposed in each pixel and an insulating layer. The display element layer DPL may be disposed on an upper layer of the pixel circuit layer PCL, and a plurality of insulating layers may be disposed between the pixel circuit and the display element. Some wiring and insulating layers of the pixel circuit layer PCL may extend to the peripheral area PA.

[0062] The encapsulation layer 300 may be a thin film encapsulation layer. The thin film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display device 1 is provided with the substrate 100 including a polymer resin and the encapsulation layer 300 including a thin film encapsulation layer of an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display device 1 may be improved.

[0063] The input detection layer 400 may acquire coordinate information according to an external input (eg, a touch event of an object such as a finger or a stylus pen).

[0064] The refractive layer 500 can adjust the path of light emitted by the display element of the display element layer DPL and can improve the light emitting efficiency of the display device 1. As will be described below, the refractive layer 500 can improve the light extraction efficiency of the display device 1 by changing the path of light emitted from the display element of the display element layer DPL.

[0065] The polarizing layer 600 can transmit the light emitted from the display element of the display element layer DPL only as light oscillating in the same direction as the direction of the polarization axis, and can absorb or reflect light oscillating in other directions. The polarizing layer 600 may include a retarder and / or a polarizer. In addition, the polarizing layer 600 may include a black matrix and / or a color filter. Although not shown, the refractive layer 500 and the polarizing layer 600 may be bonded by an adhesive such as an optically clear adhesive (OCA).

[0066] The window 800 is disposed on the polarizing layer 600 , and an adhesive layer 700 , such as an optically clear adhesive (OCA) layer, may be disposed between the polarizing layer 600 and the window 800 .

[0067] Figure 3 is a top view schematically showing a display device 1 according to the embodiment.

[0068] refer to Figure 3 , the substrate 100 may include a display area DA and a peripheral area PA. The peripheral area PA may be located at the periphery of the display area DA and may surround the display area DA.

[0069] The display area DA on the upper portion of the substrate 100 may be provided with a plurality of pixels PX arranged in an x-direction (row direction) and a y-direction (column direction) in a certain pattern.

[0070] In the peripheral area PA on the upper portion of the substrate 100, a scan driver 1100 for supplying a scan signal to each pixel PX through a scan line SL, a data driver 1200 for supplying a data signal to each pixel PX through a data line DL, and a first power supply voltage (or driving voltage) ELVDD (see Figure 4A and Figure 4B ) and the second power supply voltage (or common voltage) ELVSS (see Figure 4A and Figure 4B ), a main power wiring (not shown), etc. The pad portion 140 on which a plurality of signal pads SP connected to the data lines DL are arranged may be located in the peripheral area PA on the upper portion of the substrate 100.

[0071] The scan driver 1100 may include an oxide semiconductor TFT gate driver circuit (OSG) or an amorphous silicon TFT gate driver circuit (ASG). Figure 3 An example in which the scan driver 1100 is disposed adjacent to one side of the substrate 100 is depicted, but according to an embodiment, the scan driver 1100 may be disposed adjacent to each of two opposite sides of the substrate 100 .

[0072] Figure 3 A chip on film (COF) method is shown in which the data driver 1200 is disposed on a film 1300 electrically connected to a group of signal pads SP disposed over the substrate 100. According to some embodiments, the data driver 1200 may be directly disposed on the substrate 100 using a chip on glass (COG) method or a chip on plastic (COP) method. The data driver 1200 may be electrically connected to a flexible printed circuit board (FPCB).

[0073] Figure 4A and Figure 4B is a schematic diagram of an equivalent circuit of a pixel that may be included in the display device according to the embodiment.

[0074] refer to Figure 4A The pixel PX includes a pixel circuit PC connected to a scan line SL and a data line DL and a display element connected to the pixel circuit PC. The pixel circuit PC may include thin film transistors T1, T2 and a storage capacitor Cst, and the display element may be an organic light emitting diode OLED.

[0075] The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. Each pixel PX may emit light (eg, red light, green light, blue light, or white light) through an organic light emitting diode OLED.

[0076] The switching thin film transistor T2 may be connected to the scan line SL and the data line DL. The switching thin film transistor T2 may transmit a data signal input from the data line DL to the driving thin film transistor T1 according to a scan signal input from the scan line SL. The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage corresponding to the data signal received from the switching thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0077] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst. The driving thin film transistor T1 may control a driving current I flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a value of a voltage stored in the storage capacitor Cst. OLED .

[0078] The organic light emitting diode OLED can be driven by a current I OLED To emit light with a specific brightness. The organic light emitting diode OLED may include a pixel electrode, a counter electrode (or a common electrode), and an intermediate layer including an emission layer between the pixel electrode and the counter electrode. The counter electrode of the organic light emitting diode OLED may be supplied with a second power supply voltage ELVSS.

[0079] Figure 4A The pixel circuit PC including two thin film transistors T1, T2 and one storage capacitor Cst is shown, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously changed according to the design of the pixel circuit PC.

[0080] As another example, refer to Figure 4B , one pixel PX may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC.

[0081] like Figure 4B As shown in , the pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The thin film transistors T1 to T7 and the storage capacitor Cst may be connected to the signal lines SL, SL-1, SL+1, EL, DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the driving voltage line PL.

[0082] The signal lines SL, SL-1, SL+1, EL, DL may include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 configured to transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4, a next scan line SL+1 configured to transmit the scan signal Sn to the second initialization thin film transistor T7, a light emitting control line EL transmitting a light emitting control signal En to each of the operation control thin film transistor T5 and the light emitting control thin film transistor T6, and a data line DL intersecting the scan line SL and transmitting a data signal Dm. The driving voltage line PL may be configured to transmit the driving voltage ELVDD to the driving thin film transistor T1, the first initialization voltage line VL1 may be configured to transmit the initialization voltage Vint to the first initialization thin film transistor T4, and the second initialization voltage line VL2 may be configured to transmit the initialization voltage Vint to the second initialization thin film transistor T7.

[0083] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the light emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2, and can drive the driving current I OLED Supply to the organic light emitting diode OLED.

[0084] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is also connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the scan signal Sn received through the scan line SL, and can perform a switching operation for transmitting the data signal Dm transmitted by the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0085] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and is also connected to the pixel electrode of the organic light emitting diode OLED through the light emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to each of the lower electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby diode-connecting the driving thin film transistor T1.

[0086] A first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1, and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to each of the lower electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and may perform an initialization operation for initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0087] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emitting control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to each of the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0088] The light emitting control gate electrode G6 of the light emitting control thin film transistor T6 is connected to the light emitting control line EL, the light emitting control source electrode S6 of the light emitting control thin film transistor T6 is connected to each of the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the light emitting control drain electrode D6 of the light emitting control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and each of the pixel electrodes of the organic light emitting diode OLED.

[0089] The operation control thin film transistor T5 and the light emission control thin film transistor T6 may be simultaneously turned on according to the light emission control signal En received through the light emission control line EL, so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current I OLED Flow to the organic light emitting diode OLED.

[0090] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the subsequent scan line SL+1, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the light emitting control drain electrode D6 of the light emitting control thin film transistor T6 and each of the pixel electrodes of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the second initialization voltage line VL2.

[0091] At the same time, the scan line SL and the subsequent scan line SL+1 are electrically connected to each other, so that the same scan signal Sn can be applied to the scan line SL and the subsequent scan line SL+1. Therefore, the second initialization thin film transistor T7 can be turned on according to the scan signal Sn received through the subsequent scan line SL+1, and can perform an operation for initializing the pixel electrode of the organic light emitting diode OLED.

[0092] The upper electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the common electrode of the organic light emitting diode OLED is connected to a line for transmitting a common voltage ELVSS. Accordingly, the organic light emitting diode OLED receives a driving current I from the driving thin film transistor T1. OLED , and can emit light to display images.

[0093] exist Figure 4B In FIG. 1 , the compensation thin film transistor T3 and the first initialization thin film transistor T4 are shown to have a double gate electrode, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have a single gate electrode.

[0094] In addition, although Figure 4B The structure of one pixel circuit PC is shown, but a plurality of pixels PX having the same pixel circuit PC may be arranged to form a plurality of rows, wherein a first initialization voltage line VL1, a previous scan line SL-1, a second initialization voltage line VL2, and a subsequent scan line SL+1 may be shared by adjacent pixels PX.

[0095] For example, the first initialization voltage line VL1 and the previous scan line SL-1 may be electrically connected to the second initialization thin film transistor T7 of another pixel circuit PC arranged along the y direction. Therefore, the previous scan signal applied to the previous scan line SL-1 may be transmitted to the second initialization thin film transistor T7 of the other pixel circuit PC as the next scan signal. Similarly, the second initialization voltage line VL2 and the next scan line SL+1 may be electrically connected to the first initialization thin film transistor T4 of another pixel circuit PC arranged adjacently along the y direction to transmit the previous scan signal and the initialization voltage.

[0096] Figure 5 is a partial top view schematically showing the arrangement of pixels according to the embodiment. Figure 6 is as along Figure 5 FIG. 1 is a cross-sectional view taken along line II-II′ of FIG. 1 , schematically showing a cross-sectional view of a display device according to an embodiment.

[0097] The plurality of pixels arranged in the display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged in a column direction and a row direction according to a specific pattern. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel circuit and an organic light emitting diode 200 electrically connected to the pixel circuit (which may be connected to the pixel circuit). Figure 4A and Figure 4B The organic light emitting diode 200 of each pixel may be directly arranged on the upper portion overlapping with the pixel circuit, or may be deviated from the upper portion overlapping with the pixel circuit to overlap with the pixel circuit of the pixel in the adjacent row or column. The arrangement of pixels may be the arrangement of the organic light emitting diode 200 in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, or may be the arrangement of the pixel electrode 211 constituting the organic light emitting diode 200.

[0098] In each row R1, R2, ..., the pixel electrode 211 of the first pixel PX1, the pixel electrode 211 of the second pixel PX2, the pixel electrode 211 of the third pixel PX3, and the pixel electrode 211 of the second pixel PX2 may be spaced apart from each other and may be alternately arranged in a zigzag shape. The pixel electrode 211 of the first pixel PX1 and the pixel electrode 211 of the third pixel PX3 may be spaced apart from each other and may be alternately arranged on an imaginary first straight line IL1 in the x direction. The pixel electrode 211 of the second pixel PX2 deviates from the pixel electrode 211 of the first pixel PX1 and the pixel electrode 211 of the third pixel PX3 in a direction between the x direction and the y direction, and may be repeatedly arranged on an imaginary second straight line IL2 in the x direction.

[0099] In the first column C1, the pixel electrode 211 of the first pixel PX1 and the pixel electrode 211 of the third pixel PX3 are spaced apart from each other and may be alternately disposed on an imaginary third straight line IL3 in the y direction. In the second column C2 adjacent to the first column C1, the pixel electrodes 211 of the second pixel PX2 are spaced apart from each other and may be repeatedly disposed on an imaginary fourth straight line IL4 in the y direction. In the third column C3 adjacent to the second column C2, opposite to the first column C1, the pixel electrode 211 of the third pixel PX3 and the pixel electrode 211 of the first pixel PX1 are spaced apart from each other and may be alternately disposed on an imaginary fifth straight line IL5 in the y direction.

[0100] The pixel electrode 211 of the first pixel PX1, the pixel electrode 211 of the second pixel PX2, and the pixel electrode 211 of the third pixel PX3 may have different areas. In an embodiment, the pixel electrode 211 of the third pixel PX3 may have a larger area than the pixel electrode 211 of the adjacent first pixel PX1. In addition, the pixel electrode 211 of the third pixel PX3 may have a larger area than the pixel electrode 211 of the adjacent second pixel PX2. The pixel electrode 211 of the second pixel PX2 may have a smaller area than the pixel electrode 211 of the adjacent first pixel PX1. In some embodiments, the pixel electrode 211 of the third pixel PX3 may have the same area as the pixel electrode 211 of the first pixel PX1. The pixel electrode 211 may have a polygonal shape (e.g., a quadrilateral shape, an octagonal shape, etc.), a circular shape, an elliptical shape, etc., and the polygonal shape may also include a shape with rounded vertices. As used herein, a rounded apex refers not only to a shape in which an apex is arc-shaped and rounded, but also to a shape in which a sharp apex is slightly cut off.

[0101] The pixel defining film 117 covers at least a portion of the pixel electrode 211 and may define a light emitter EA of the organic light emitting diode 200. The light emitter EA corresponds to a region disposed in the intermediate layer 231 that may be defined by the opening 117OP of the pixel defining film 117. The light emitter EA may include a first light emitter EA1, a second light emitter EA2, and a third light emitter EA3. The first pixel PX1 may include the first light emitter EA1, the second pixel PX2 may include the second light emitter EA2, and the third pixel PX3 may include the third light emitter EA3. The light emitter EA may have a polygonal shape (e.g., a quadrilateral shape, an octagonal shape, etc.), and the polygonal shape may also include a shape having rounded vertices.

[0102] In an embodiment, the first pixel PX1 may be a red pixel that emits red light, the second pixel PX2 may be a blue pixel that emits blue light, and the third pixel PX3 may be a green pixel that emits green light. In some embodiments, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel.

[0103] refer to Figure 6 A buffer layer 111 formed to prevent impurities from penetrating into the semiconductor layer 132 of the thin film transistor TFT may be disposed on the substrate 100 .

[0104] The substrate 100 may be formed of various materials such as glass, metal, or plastic, etc. According to an embodiment, the substrate 100 may be a flexible substrate, and may include a polymer resin such as, for example, polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0105] The buffer layer 111 may include an inorganic insulating material such as silicon nitride or silicon oxide, and may be a single layer or a multi-layer.

[0106] The thin film transistor TFT, the storage capacitor Cst, and the organic light emitting diode 200 electrically connected to the thin film transistor TFT may be disposed on the substrate 100. When the organic light emitting diode 200 is electrically connected to the thin film transistor TFT, it can be understood that the pixel electrode 211 is electrically connected to the thin film transistor TFT. The thin film transistor TFT may be Figure 4A and Figure 4B The driving thin film transistor T1.

[0107] The thin film transistor TFT may include a semiconductor layer 132, a gate electrode 134, a source electrode 136S and a drain electrode 136D. The semiconductor layer 132 may include an oxide semiconductor material. The semiconductor layer 132 may include amorphous silicon, polycrystalline silicon or an organic semiconductor material. Considering the adhesion to the adjacent layers, the surface flatness of the stacked layers and the processability, the gate electrode 134 may be formed as a single layer or multilayer of one or more materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu).

[0108] A gate insulating layer 112 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be provided between the semiconductor layer 132 and the gate electrode 134. A first interlayer insulating layer 113 and a second interlayer insulating layer 114 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be disposed between the gate electrode 134 and the source electrode 136S and the drain electrode 136D. The source electrode 136S and the drain electrode 136D may each be electrically connected to the semiconductor layer 132 through a contact hole formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0109] The source electrode 136S and the drain electrode 136D may be formed as a single layer or multiple layers of one or more of the following materials: aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0110] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 overlapping the first interlayer insulating layer 113. The storage capacitor Cst may overlap the thin film transistor TFT. Figure 6 , the gate electrode 134 of the thin film transistor TFT is shown to be the lower electrode CE1 of the storage capacitor Cst. According to some embodiments, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 114.

[0111] The pixel circuit including the thin film transistor TFT and the storage capacitor Cst may be covered with the first insulating layer 115 and the second insulating layer 116. The first insulating layer 115 and the second insulating layer 116 are planarized insulating layers that may be organic insulating layers. The first insulating layer 115 and the second insulating layer 116 may include an organic insulating material (e.g., a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof). In an embodiment, the first insulating layer 115 and the second insulating layer 116 may include polyimide.

[0112] A display element (eg, an organic light emitting diode 200) may be disposed on the second insulating layer 116. The organic light emitting diode 200 may include a pixel electrode 211, an intermediate layer 231, and an opposing electrode 251.

[0113] The pixel electrode 211 is disposed on the second insulating layer 116 and may be connected to the thin film transistor TFT through the connection electrode 181 on the first insulating layer 115. Wiring 183 such as a data line DL and a driving voltage line PL may be disposed on the first insulating layer 115.

[0114] The pixel electrode 211 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 211 may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In some embodiments, the pixel electrode 211 may further include a conductive oxide of ITO, IZO, ZnO or In above / below the above reflective film. 2 O 3 The film formed.

[0115] The pixel defining film 117 may be disposed on the second insulating layer 116. The pixel defining film 117 covers the edge of the pixel electrode 211 and may define a pixel by having an opening 117OP through which a portion of the pixel electrode 211 is exposed. The pixel defining film 117 may be used to prevent arc discharge, etc., from occurring at the edge of the pixel electrode 211 by increasing the distance between the edge of the pixel electrode 211 and the counter electrode 251. The pixel defining film 117 may be formed of an organic material such as, for example, polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0116] The intermediate layer 231 includes an emission layer. The emission layer may include a polymer organic material or a low molecular weight organic material that emits light of a specific color. The emission layer may be arranged in the opening 117OP of the pixel defining film 117 to form a light emitter EA. In an embodiment, the intermediate layer 231 may include a first functional layer disposed below the emission layer and / or a second functional layer disposed above the emission layer. The first functional layer and / or the second functional layer may include a single layer throughout the plurality of pixel electrodes 211, or may include a layer patterned to correspond to each of the plurality of pixel electrodes 211.

[0117] The first functional layer may be a single layer or a multilayer. For example, when the first functional layer is formed of a polymer material, the first functional layer may be a hole transport layer (HTL) having a single layer structure formed of poly-(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer is formed of a low molecular weight material, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0118] The second functional layer is not always provided. For example, when the first functional layer and the emission layer are formed of a polymer material, it is desirable to form a second functional layer to improve the performance of the organic light emitting diode 200. The second functional layer may be a single layer or a multilayer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0119] The counter electrode 251 is arranged to face the pixel electrode 211, wherein the intermediate layer 231 is between the pixel electrode 211 and the counter electrode 251. The counter electrode 251 can be formed of a low work function conductive material. For example, the counter electrode 251 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or their alloys. Alternatively, the counter electrode 251 may further include a (semi) transparent layer including the above-mentioned materials such as ITO, IZO, ZnO or In 2 O 3 The formed layer.

[0120] The opposing electrode 251 may be disposed on the intermediate layer 231 and the pixel defining film 117. The opposing electrode 251 may be integrally formed in the plurality of organic light emitting diodes 200 to be opposite to the plurality of pixel electrodes 211 in the display area DA.

[0121] Figure 7 is a top view schematically showing an arrangement of light emitters in a display area according to an embodiment. Figure 8 is as along Figure 7 A cross-sectional view taken along line III-III' of FIG. 1 schematically shows a cross-sectional view of a display device according to an embodiment. Figure 5 and Figure 6 The description will be omitted.

[0122] In an embodiment, the encapsulation layer 300 may be disposed on top of the counter electrode 251. The encapsulation layer 300 may be used to protect the organic light emitting diode 200 from external moisture, oxygen, and the like. The encapsulation layer 300 may have a multilayer structure. The encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330. By forming the encapsulation layer 300 into a multilayer structure, even if cracks occur in the encapsulation layer 300, the cracks may not be connected between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330, thereby preventing or minimizing the formation of a path for moisture or oxygen, etc., to penetrate from the outside into the display area DA. According to some embodiments, the number of organic encapsulation layers and the number of inorganic encapsulation layers and the stacking order of the organic encapsulation layers and the inorganic encapsulation layers may be changed.

[0123] The first inorganic encapsulating layer 310 covers the counter electrode 251 and may include an inorganic insulating material including one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulating layer 310 is formed along the structure below it and thus may not have a flat upper surface.

[0124] The organic encapsulation layer 320 covers the first inorganic encapsulation layer 310 and may have a sufficient thickness. The upper surface of the organic encapsulation layer 320 may be substantially flat throughout the display area DA. The organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0125] The second inorganic encapsulation layer 330 covers the organic encapsulation layer 320 and may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride. The second inorganic encapsulation layer 330 may extend to the outside of the organic encapsulation layer 320 and contact the first inorganic encapsulation layer 310 in the peripheral area PA, thereby preventing the organic encapsulation layer 320 from being exposed to the outside.

[0126] On the other hand, the process of forming the encapsulation layer 300 may damage the structure below it. For example, in the process of forming the first inorganic encapsulation layer 310, the layer directly below the first inorganic encapsulation layer 310 may be damaged. Therefore, at least one capping layer and / or protective layer may be provided between the electrode 251 and the encapsulation layer 300 to prevent damage to the underlying structure during the process of forming the encapsulation layer 300. The capping layer and / or protective layer may include an inorganic material.

[0127] The input detection layer 400 may be disposed on the organic light emitting diode 200, for example, on the encapsulation layer 300. The input detection layer 400 may acquire coordinate information according to an external input (for example, a touch event of an object such as a finger or a stylus). The input detection layer 400 may include sensing electrodes and / or traces, etc. The input detection layer 400 may detect external input in a mutual capacitance manner or a self-capacitance manner.

[0128] The input detection layer 400 may include a first conductive layer MTL1 and a second conductive layer MTL2, which may include sensing electrodes and / or traces, etc. A first touch insulating layer 410 may be disposed between the encapsulation layer 300 and the first conductive layer MTL1, and a second touch insulating layer 420 may be disposed between the first conductive layer MTL1 and the second conductive layer MTL2. A third touch insulating layer 430 may be disposed on the second conductive layer MTL2 and the second touch insulating layer 420.

[0129] The first conductive layer MTL1 and the second conductive layer MTL2 may include a conductive material. The conductive material may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer including any of the above materials. In some embodiments, the first conductive layer MTL1 and the second conductive layer MTL2 may have a structure (Ti / Al / Ti) in which a titanium layer, an aluminum layer, and a titanium layer are sequentially stacked.

[0130] The first touch insulating layer 410, the second touch insulating layer 420 and the third touch insulating layer 430 may include inorganic insulating materials and / or organic insulating materials. The inorganic insulating materials may include silicon oxide, silicon oxynitride, silicon nitride, etc. The organic insulating materials may include acrylic organic materials, imide organic materials, etc.

[0131] The refractive layer 500 may be disposed on the organic light emitting diode 200, for example, on the encapsulation layer 300. The refractive layer 500 may adjust the path of the light L emitted from the emission layer of the organic light emitting diode 200, and may function as a focusing lens. The refractive layer 500 may change the path of the light L emitted from the emission layer of the organic light emitting diode 200 traveling in a lateral direction (for example, a direction other than the z direction), and may allow the light L to travel in a substantially forward z direction.

[0132] The refractive layer 500 may include a first refractive layer 510 and a second refractive layer 520. The edge RE of the first refractive layer 510 may be patterned to have a uniform surface in a plane (eg, an xy plane (see Figure 1)) surrounds the light emitter EA. In other words, the first refractive layer 510 may be formed in a pattern surrounding the light emitter EA on a plane. The first refractive layer 510 may be arranged to overlap the light emitter EA in the z direction. The first refractive layer 510 may be arranged to cover the light emitter EA. The first refractive layer 510 may be arranged in the same layer as the third touch insulating layer 430 and may include the same material. The thickness TH of the first refractive layer 510 in a direction perpendicular to the substrate 100 (e.g., the z direction) may be at least about 1.5 μm but not more than about 5 μm.

[0133] The edge RE of the first refractive layer 510 may be formed to be inclined. In other words, the edge RE of the first refractive layer 510 may be provided as a slope. An angle θ510 formed by the edge RE of the first refractive layer 510 and a layer disposed below, for example, in an xy plane, may be at least about 30° but not more than about 85°. Since the second touch insulating layer 420 may be disposed below the first refractive layer 510, the angle θ510 formed by the edge RE of the first refractive layer 510 and the second touch insulating layer 420 disposed below may be at least about 30° but not more than about 85°.

[0134] The second refractive layer 520 may be disposed on the first refractive layer 510 and the third touch insulating layer 430. The second refractive layer 520 may cover the first refractive layer 510 and fill between the patterns of the first refractive layer 510 and the third touch insulating layer 430. In an embodiment, the second refractive layer 520 may be an adhesive layer disposed under the polarizing layer 600. The adhesive layer may include at least one of an acrylic resin, a silicone resin, a urethane resin, an epoxy resin, a rubber resin, and a polyester resin, and may include one or more types of the same series of resins. The second refractive layer 520 disposed on the first refractive layer 510 and the third touch insulating layer 430 may utilize an adhesive layer disposed under the polarizing layer 600 instead of a separate high-refractive flat layer, thereby reducing material costs or process costs.

[0135] The refractive index of the first refractive layer 510 may be greater than the refractive index of the second refractive layer 520. The difference between the refractive index of the first refractive layer 510 and the refractive index of the second refractive layer 520 may be at least about 0.04 but not more than about 1. In an embodiment, the refractive index of the first refractive layer 510 may be approximately about 1.45 to about 1.65. The refractive index of the second refractive layer 520 may be approximately about 1.4 to about 1.5.

[0136] In an embodiment, by including the first refraction layer 510 and the second refraction layer 520 disposed on the light emitter EA, among the light L emitted from the organic light emitting diode 200, the light L incident on the first refraction layer 510 is refracted at the interface between the first refraction layer 510 and the second refraction layer 520 and can be extracted in the z direction.

[0137] In an embodiment, the polarizing layer 600 may be disposed on the second refraction layer 520. The polarizing layer 600 may be configured to Figure 2 ) is transmitted only as light oscillating in the same direction as the direction of the polarization axis, and light oscillating in other directions may be absorbed or reflected. The polarizing layer 600 may include a retarder and / or a polarizer. In addition, the polarizing layer 600 may include a black matrix and / or a color filter. Although not shown, the refractive layer 500 and the polarizing layer 600 may be bonded by an adhesive such as an optically clear adhesive (OCA).

[0138] The window 800 is disposed on the polarizing layer 600 , and an adhesive layer 700 , such as an optically clear adhesive (OCA) layer, may be disposed between the polarizing layer 600 and the window 800 .

[0139] Fig. 9 5 is a top view schematically showing a placement relationship of a light emitter EA and a first refraction layer 510 according to an embodiment.

[0140] In an embodiment, the light emitter EA may have a polygonal shape (e.g., a quadrilateral shape, an octagonal shape, etc.), and the polygonal shape may also include a shape having a rounded vertex. As described above, as used herein, the rounded vertex refers not only to a shape in which the vertex is arc-shaped and rounded, but also to a shape in which a sharp vertex is slightly cut off. Fig. 9 , for convenience of explanation, the light emitter EA is described as having an octagonal shape (basically, a shape in which vertices of a square are cut into straight lines), but the embodiment is not limited thereto.

[0141] The light emitter EA corresponds to a region in which an emission layer disposed within the opening 117OP of the pixel defining film 117 is formed, and an edge EE of the light emitter EA may refer to an edge of the emission layer.

[0142] refer to Fig. 9, the edge EE of the light emitter EA may include a first light emitting edge EE1 and a third light emitting edge EE3 extending in a first direction (D1 direction) and a second light emitting edge EE2 and a fourth light emitting edge EE4 extending in a second direction (D2 direction). The first to fourth light emitting edges EE1, EE2, EE3, and EE4 may be connected to each other by rounded vertex portions, so that the light emitter EA may have a substantially quadrilateral shape.

[0143] The first refraction layer 510 may be arranged to overlap with the light emitter EA. The first refraction layer 510 may be arranged to completely overlap with the light emitter EA. The edge RE of the first refraction layer 510 may be arranged to surround the edge EE of the light emitter EA on a plane. The edge RE of the first refraction layer 510 may include a first refraction edge RE1 corresponding to the first light emitting edge EE1, a second refraction edge RE2 corresponding to the second light emitting edge EE2, a third refraction edge RE3 corresponding to the third light emitting edge EE3, and a fourth refraction edge RE4 corresponding to the fourth light emitting edge EE4.

[0144] In the following, the description will be based on the first light emitting edge EE1 and the corresponding first refraction edge RE1, however, the same description can be applied to the second light emitting edge EE2 and the corresponding second refraction edge RE2, the third light emitting edge EE3 and the corresponding third refraction edge RE3, and the fourth light emitting edge EE4 and the corresponding fourth refraction edge RE4.

[0145] In an embodiment, the first refraction edge RE1 corresponding to the first light emitting edge EE1 may include a first portion EP1 and a second portion EP2. The first portion EP1 may be a portion of the first refraction edge RE1 when in a direction perpendicular to the substrate 100 (eg, in the z direction (see Figure 2 ) (hereinafter, in a plane (eg, xy plane (see Figure 1 )) on the plane) forms a first angle with the first light emitting edge EE1, and the second portion EP2 may be a portion of the first refraction edge RE1 that forms a second angle larger than the first angle with the first light emitting edge EE1 on the plane.

[0146] As used herein, the angle formed by each of the first and second portions EP1 and EP2 of the first refraction edge RE1 and the first light emitting edge EE1 refers to an acute angle formed by each of the first and second portions EP1 and EP2 on a plane with the first light emitting edge EE1 .

[0147] refer to Fig. 9In an embodiment, the first portion EP1 is parallel to the first light emitting edge EE1, and the second portion EP2 may not be parallel to the first light emitting edge EE1. In other words, the first angle between the first portion EP1 and the first light emitting edge EE1 is 0°, and the second angle θ formed by the second portion EP2 and the first light emitting edge EE1 may be greater than 0°. In an embodiment, the second angle θ formed by the second portion EP2 and the first light emitting edge EE1 may be at least about 20° but not more than about 70°. The second angle θ formed by the second portion EP2 and the first light emitting edge EE1 may be about 45°.

[0148] In an embodiment, on a plane, the first portion EP1 is parallel to the first light emitting edge EE1, and the second portion EP2 may protrude in a direction perpendicular to the first light emitting edge EE1. Fig. 9 , the first portion EP1 may be shaped to extend in the first direction (the D1 direction), and the second portion EP2 may be shaped to protrude in the second direction (the D2 direction).

[0149] In an embodiment, the first refractive edge RE1 may be formed by connecting the first portion EP1, the second portion EP2, and the first portion EP1 in this order. When the first refractive edge RE1 includes a plurality of first portions EP1 spaced apart from each other, the length of the first portion EP1 refers to the total length LP1+LP3 of the first portion EP1, and the same is true for the length LP2 of the second portion EP2. In an embodiment, the length LP2 of the second portion EP2 may be at least about 0.2 times but not more than about 4 times the length LP1+LP3 of the first portion EP1. The length LP2 of the second portion EP2 in the first direction (D1 direction) may be at least about 0.2 times but not more than about 4 times the length LP1+LP3 of the first portion EP1 in the first direction (D1 direction).

[0150] When the organic light emitting diode emits white light, the white characteristic observed from the front is different from the white characteristic observed from the side. White angle difference (WAD) is an item for evaluating the change of white characteristics according to the observation angle, and its level is evaluated by measuring the amount of change in brightness and the amount of change in color coordinates according to the observation angle compared with the front side perpendicular to the screen. By including the first part EP1 and the second part EP2 that form different angles with the edge EE of the light emitter EA on the plane, the edge RE of the first refraction layer 510 according to the embodiment can reduce the difference between the white characteristic observed from the front and the white characteristic observed from the side by changing the path of the light passing through the first refraction layer 510.

[0151] refer to Fig. 9To explain in detail, the first light L1, which is a portion of the light emitted from the light emitter EA in the second direction (D2 direction), may be vertically incident to the edge RE of the first refraction layer 510, and the second light L2, which is another portion of the light emitted from the light emitter EA in the second direction (D2 direction), may be obliquely incident to the edge RE of the first refraction layer 510. The third light L3, which is a portion of the light emitted from the light emitter EA in the third direction (D3 direction), may be vertically incident to the edge RE of the first refraction layer 510, and the fourth light L4, which is another portion of the light emitted from the light emitter EA in the third direction (D3 direction), may be obliquely incident to the edge RE of the first refraction layer 510.

[0152] If the edge RE of the first refraction layer 510 is formed with only the first portion EP1 , both the first light L1 and the second light L2 are vertically incident to the edge RE of the first refraction layer 510 , and both the third light L3 and the fourth light L4 are obliquely incident to the edge RE of the first refraction layer 510 .

[0153] On the other hand, according to an embodiment, the edge RE of the first refraction layer 510 includes a first portion EP1 and a second portion EP2 having different angles from the edge EE of the light emitter EA, so that light emitted from the light emitter EA in a specific direction can be dispersed at various angles and can be incident on the edge RE of the first refraction layer 510, thereby improving the WAD characteristics.

[0154] Figures 10 to 14 5 is a top view schematically showing the placement relationship of the light emitter EA and the first refraction layer 510 according to the embodiment. Figure 8 and Fig. 9 The description will be omitted.

[0155] refer to Fig.10 , the first refraction edge RE1 corresponding to the first light emitting edge EE1 may include a first portion EP1 parallel to the first light emitting edge EE1 and a second portion EP2 at an angle of about 45° to the first light emitting edge EE1. Fig. 9 The embodiments are different. Fig.10The first refraction edge RE1 may be provided in the order of the second portion EP2, the first portion EP1, and the second portion EP2. That is, the first portion EP1 parallel to the first light emitting edge EE1 may be located at the center of the first refraction edge RE1, and the second portion EP2 protruding in a direction perpendicular to the first light emitting edge EE1 may be located on both sides of the first portion EP1. Therefore, the edge RE of the first refraction layer 510 according to the embodiment includes the first portion EP1 and the second portion EP2 forming different angles with the edge EE of the light emitter EA, and the positions, arrangement order, and arrangement ratio of the first portion EP1 and the second portion EP2 may be changed as needed, thereby allowing freedom of design.

[0156] refer to Fig.11A and Fig. 11B , a portion of the edge RE of the first refractive layer 510 may overlap a portion of the edge EE of the light emitter EA on a plane. In an embodiment, a rounded vertex portion of the edge EE of the light emitter EA may coincide with the edge RE of the first refractive layer 510. In an embodiment, a portion of the edge RE of the first refractive layer 510 may overlap each of a portion of a first light emitting edge EE1, a portion of a second light emitting edge EE2, a portion of a third light emitting edge EE3, and a portion of a fourth light emitting edge EE4 of the edge EE of the light emitter EA. Since a portion of the edge RE of the first refractive layer 510 is arranged to overlap a portion of the edge EE of the light emitter EA, a margin for arranging the first refractive layer 510 may be reduced and a spacing between pixels may be reduced.

[0157] refer to Fig.12 , the edge RE of the first refraction layer 510 may be provided with alternately connected first portions EP1 and second portions EP2. The first refraction edge RE1 corresponding to the first light emitting edge EE1 may be provided with a plurality of alternately connected second portions EP2 and a plurality of first portions EP1. Since the second portion EP2 may have a shape protruding in a direction perpendicular to the first light emitting edge EE1 of the light emitter EA, the first refraction edge RE1 may include a plurality of protruding second portions EP2. For example, Fig.12 As shown in FIG. 5 , the first refractive edge RE1 may include four second portions EP2 and three first portions EP1 connected alternately. The embodiment is not limited thereto, and the edge RE of the first refractive layer 510 may be provided with the first and second portions EP1 and EP2 connected repeatedly as needed.

[0158] refer to Fig.13A and Fig. 13B, the second portion EP2 may be provided in the form of a curve on a plane. The second angle formed by the second portion EP2 and the edge EE of the light emitter EA may not be a specific value, but may refer to a range of angles greater than the first angle formed by the first portion EP1 and the edge EE of the light emitter EA. In an embodiment, the second angle formed by the second portion EP2 and the edge EE of the light emitter EA may be understood as an angle formed by a tangent line at the second portion EP2 and the edge EE of the light emitter EA. When the second portion EP2 is provided in an arc shape, the space for arranging the first refractive layer 510 may be reduced, and a high-resolution display device may be easily implemented.

[0159] refer to Fig.14 , the light emitter EA may have a hexagonal shape on a plane. In the above drawings, for simplicity, the light emitter EA is described based on having a substantially quadrilateral shape, but the embodiment is not limited thereto. When the light emitter EA is provided in an n-gonal shape, the edge EE of the light emitter EA may include first to n-th light emitting edges EE1, EE2, ... The edge RE of the first refractive layer 510 may have first to n-th refraction edges RE1, RE2, ... corresponding to the first to n-th light emitting edges EE1, EE2, ..., respectively, and each refraction edge may include a first portion EP1 and a second portion EP2.

[0160] The display device according to the embodiment includes a light emitter EA, a first refraction layer 510 on the light emitter EA, and a second refraction layer 520 covering the first refraction layer 510, and an edge RE of the first refraction layer 510 has a first portion EP1 and a second portion EP2, thereby providing a display device with improved light emitting efficiency and WAD characteristics.

[0161] Therefore, the present disclosure has been described with reference to the embodiments shown in the accompanying drawings which are only for example, and those skilled in the art will understand that various modifications and variations of the embodiments are possible according to the embodiments. Therefore, the true technical protection scope of the present disclosure should be determined by the technical ideas of the claims.

[0162] According to the embodiment, a display device having improved efficiency of light extracted from the display device and emitting light with uniform brightness distribution even when the viewing angle of the user changes can be provided. However, such effects are for example, and the effects according to the embodiment are not limited thereto.

[0163] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: A display element including a light emitter that emits light; A first refractive layer, disposed on the display element; as well as a second refractive layer, covering the first refractive layer, The edge of the light emitter includes a first light emitting edge extending in a first direction, wherein the edge of the first refraction layer includes a first refraction edge corresponding to the first light emitting edge, and The first refractive edge includes a first portion forming a first angle with the first luminous edge on a plane and a second portion forming a second angle with the first luminous edge on the plane that is larger than the first angle.

2. The display device according to claim 1, in, The edge of the first refractive layer surrounds the light emitter on the plane.

3. The display device according to claim 1, in, The first light emitting edge and the first portion are parallel on the plane.

4. The display device according to claim 3, in, The second angle is at least 20° but not more than 70° on the plane.

5. The display device according to claim 1, in, The first refractive edge has a form in which the first portions and the second portions are alternately connected.

6. The display device according to claim 1, in, A length of the second portion in the first direction is at least 0.2 times but not more than 4 times a length of the first portion in the first direction.

7. The display device according to claim 1, in, The first refractive layer has a refractive index greater than that of the second refractive layer.

8. The display device according to claim 1, in, A portion of the edge of the first refractive layer overlaps a portion of the edge of the light emitter on the plane.

9. The display device according to any one of claims 1 to 8, in, The first refractive layer has a thickness of at least 1.5 μm but not more than 5 μm.

10. The display device according to any one of claims 1 to 8, in, The edge of the first refractive layer is provided with a slope forming an angle of at least 30° but not more than 85° with a layer disposed therebelow.

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