Common mode current removal scheme for digital-to-analog converter

Abstract

Methods and apparatus for common mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current steering units, a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, and an adjustable resistance circuit coupled between an intermediate node of the plurality of shunt branches and a reference potential node of the DAC circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 811,706, filed on July 11, 2022, which is hereby incorporated by reference into this application. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to techniques and apparatus for common-mode current removal in digital-to-analog converters (DACs). Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services, such as telephony, video, data, messaging, broadcast, etc. Such wireless communication devices may send and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RATs (e.g., WiFi), etc.

[0005] A wireless communication network may include multiple base stations that can support communications for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, while an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may send data and control information to a mobile station on a downlink, and / or may receive data and control information from a mobile station on an uplink. A base station and / or a mobile station may include a transmit digital-to-analog converter (TX DAC), which may be used, for example, to convert a digital signal into an analog signal for signal processing (e.g., filtering, up-conversion, and amplification) before being transmitted by one or more antennas. Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desired characteristics. Without limiting the scope of the present disclosure as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide advantages, including increased voltage margin, smaller area, reduced common-mode current variation with process, voltage, and / or temperature (PVT), and improved differential and common-mode noise performance in current-steering digital-to-analog converters (DACs).

[0007] Certain aspects of the present disclosure provide a DAC, which generally includes a plurality of current steering units, a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, and an adjustable resistance circuit coupled between intermediate nodes of the plurality of shunt branches and a reference potential node of the DAC circuit.

[0008] Certain aspects of the present disclosure provide a DAC, which generally includes a plurality of current steering units, a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, and a plurality of switches, each switch being coupled between an intermediate node of a shunt branch in the plurality of shunt branches and a reference potential node of the DAC circuit.

[0009] Certain aspects of the present disclosure provide a method for operating a DAC. The DAC generally includes a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches. The method generally involves controlling an adjustable resistor circuit coupled between an intermediate node of the plurality of shunt branches and a reference potential node of a DAC circuit to absorb at least a portion of a common mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

[0010] Certain aspects of the present disclosure provide a method for operating a DAC. The DAC generally includes a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches. The method generally involves controlling a plurality of switches, each switch coupled between an intermediate node of a shunt branch in the plurality of shunt branches and a reference potential node of the DAC circuit to selectively absorb portions of the common mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

[0011] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0013] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0014] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0015] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0016] Figure 4 is a circuit diagram of an example digital-to-analog converter (DAC) in which aspects of the present disclosure may be practiced.

[0017] Figure 5A is a circuit diagram of an example resistor ladder circuit coupled to a current source circuit for sinking common mode current.

[0018] Figure 5B is a circuit diagram of an example resistor ladder circuit coupled to an adjustable resistance circuit for sinking common-mode current in accordance with certain aspects of the present disclosure.

[0019] Figure 5C , Figure 5D and Figure 5E Illustrate some aspects of the present disclosure for implementing Figure 5B An example of an adjustable resistor circuit of a switched resistor element network.

[0020] Fig. 5F is a circuit diagram of an example resistor ladder circuit with multiple switches for sinking common-mode current, according to certain aspects of the present disclosure.

[0021] Figure 5G is a circuit diagram of an example resistor ladder circuit with a hybrid common-mode removal circuit according to certain aspects of the present disclosure.

[0022] Figure 6 and Figure 7 is a flow chart of example operations for digital-to-analog conversion with common-mode current removal in accordance with certain aspects of the present disclosure.

[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0024] Certain aspects of the present disclosure relate to techniques and devices for common-mode current removal in a digital-to-analog converter (DAC), such as a current steering DAC having multiple current steering units and a resistor ladder circuit having multiple shunt branches. For certain aspects, common-mode current removal can be achieved using an adjustable resistor circuit coupled between an intermediate node of multiple shunt branches and a reference potential node of the DAC. The adjustable resistor circuit can be designed to remove (or at least substantially reduce) common-mode current from the DAC. For other aspects, common-mode current removal can be achieved by multiple switches, each of which is coupled between an intermediate node of a shunt branch in the multiple shunt branches and a reference potential node of the DAC. Other aspects can use a hybrid approach in combination with the common-mode current removal scheme described herein.

[0025] The various aspects of the disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the protection scope of the disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0026] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0028] Example Wireless System

[0029] Figure 1 An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0030] like Figure 1 As shown in , the wireless communication network 100 may include several base stations (BSs) 110a to 110z (each also individually referred to as BS 110 or collectively referred to as BS 110 herein) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB) or some other terminology.

[0031] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or mobile depending on the location of a mobile BS. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1 In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0032] The BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also individually or collectively referred to herein as UE 120) in the wireless communication network 100. A UE may be fixed or mobile, and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

[0033] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, and the subscript "up" indicates an uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to N dn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and the UE 120.

[0034] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.) that receives transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0035] BS 110 may communicate on the downlink and uplink with one or more UEs 120 at any given moment. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0036] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from BS 110. Typically, each UE 120 may be equipped with one or more antennas. u The UEs 120 may have the same or different numbers of antennas.

[0037] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported).

[0038] The network controller 130 (sometimes also referred to as a "system controller") may communicate with a set of BSs 110 and provide coordination and control (e.g., via backhaul) for these BSs 110. In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network open functions, network repository functions, network slice selection functions, etc.

[0039] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a digital-to-analog converter (DAC) circuit that implements a common-mode current removal scheme, as described in more detail herein.

[0040] Figure 2 1 and 120a (eg, from a BS 110a) in which various aspects of the present disclosure may be implemented. Figure 1 Example components of a wireless communication network 100).

[0041] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0042] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0043] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0044] At UE 120a, antennas 252a-252r may receive downlink signals from BS110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (where applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0045] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for single carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to controller / processor 240.

[0046] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0047] The antennas 252, processors 258, 264, 266 and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238 and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0048] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include digital-to-analog converter (DAC) circuitry that implements a common-mode current removal scheme, as described in greater detail herein.

[0049] NR can use orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR can use time division duplex (TDD) to support half-duplex operation. OFDM and single carrier frequency division multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into multiple subbands. For example, one subband can cover multiple resource blocks (RBs).

[0050] Example RF Transceiver

[0051] Figure 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via interface 308, which can include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0052] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0053] For certain aspects, DAC 310 can be implemented by any of a variety of suitable high-speed DAC topologies, such as a current-steering DAC. For certain aspects, DAC 310 can be implemented with a common-mode current removal scheme for removing common-mode current from the DAC, as described in more detail below.

[0054] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0055] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0056] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0057] Controller 336 (eg, Figure 2 Controller / processor 280 in the RF transceiver circuit 300A may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. Controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the controller 336 may store data and / or program codes for operating the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0058] Although Figures 1 to 3 Wireless communications are provided as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, but certain aspects described herein may be used for digital-to-analog conversion in any of a variety of other suitable systems (e.g., audio systems or other electronic systems).

[0059] Introduction to Digital-to-Analog Conversion Using Current Steering

[0060] A current-steering digital-to-analog converter (DAC) is an example architecture used for high-performance digital-to-analog conversion in many wireless transmitters. A current-steering DAC provides design versatility, high-speed operation, and high performance (such as relatively high linearity). Although a current-steering DAC is described as an example type of DAC that can implement aspects of the present disclosure, it should be understood that aspects of the present disclosure may also be applied to other suitable types of DACs.

[0061] Figure 4An example current steering DAC 400 (eg, which may implement Figure 3 DAC 310). As shown, the current steering DAC 400 includes a current steering unit 401 and a resistor ladder circuit 402. The resistor ladder circuit 402 can be implemented as an R-2R type ladder circuit, as explained below. For example, the resistor ladder circuit 402 may include a plurality of segments (e.g., segments 490, 492), each of which includes a positive ladder node R2Rp <0> to R2Rp <k>and negative step node R2Rn <0> To R2Rn <k>. Between the positive ladder node and the negative ladder node of each segment may be a resistance element (e.g., resistance elements 440, 442 or resistance elements 450, 452). In addition, a resistance element (e.g., resistance element 444 or 454) may be coupled between the positive nodes of adjacent segments of the resistor ladder circuit 402, and a resistance element (e.g., resistance element 446 or 456) may be coupled between the negative nodes of adjacent segments of the resistor ladder circuit 402. In an R-2R ladder circuit, the series resistance element (e.g., resistance elements 444, 454) has a resistance value R, and the shunt resistance element (e.g., resistance elements 450, 452 in the shunt branch 441 of the ladder circuit) has twice the resistance (2R) in each half of the R-2R ladder circuit. For certain aspects, the least significant bit (LSB) may follow the R-2R ladder structure, while the most significant bit (MSB) may have a different resistance value in the resistor ladder circuit (e.g., according to a thermometer code).

[0062] Each current steering unit in the current steering unit 401 (e.g., current steering unit n, n is a positive integer) includes a current source coupled to the voltage rail Vdd, a positive switch coupled to the current source and configured to selectively provide a positive current (e.g., Ipos n) to the positive ladder node, and a negative switch coupled to the current source and configured to selectively provide a negative current (e.g., Ineg n) to the negative ladder node. For example, the supply current Isupply 0 (e.g., Isupply n, where n is 0) through the current source 430 can be guided via the positive switch 403 of the current steering unit 410 to the positive ladder node R2Rp <0> Similarly, Isupply 0 through current source 430 can be additionally directed via negative switch 404 to the negative ladder node R2Rn. <0> In a similar manner, the currents from the current sources of the other current steering units can be directed to the corresponding positive and negative ladder nodes (R2Rp) via the positive or negative switches in each current steering unit. <1> to R2Rp <k>, and R2Rm <1> To R2Rm <k>).

[0063] The control inputs to the positive switch 403 and the negative switch 404 can be complementary. In some aspects, the switches 403 and 404 can be implemented as p-type metal oxide semiconductor (PMOS) transistors, as illustrated. Thus, a logic high signal can be used to open the switch 403 or 404, and a logic low signal can be used to close the switch 403 or 404.

[0064] The output signal from the DAC 400 is in the form of a differential current at the positive and negative output nodes (labeled "outp" and "outm") of the resistor ladder circuit 402. To achieve high linearity, it is desirable to remove common-mode current from the DAC 400 (and / or other locations along the transmit path (e.g., TX path 302)). It may be desirable to minimize (or at least reduce) variations in the output common-mode current over process, voltage, and / or temperature (PVT) variations while keeping noise and offset contributions from the common-mode current removal scheme to a minimum (or at least substantially low).

[0065] In some cases, an amplifier-based common-mode feedback circuit can be used to remove some of the common-mode current. However, such a feedback circuit may be implemented with an external voltage reference (increasing area) and / or may degrade the differential noise performance and DC offset of the DAC.

[0066] Alternatively, a current source (such as a current mirror circuit) can be used as a current sink to sink the common-mode current through the middle of the resistor ladder circuit (e.g., to a reference potential node of the DAC, such as electrical ground). This approach does not require the use of a buffer and an external voltage reference as in an amplifier-based common-mode feedback circuit.

[0067] As an example, Figure 5A is a schematic diagram of a resistor ladder circuit 500A having a current source 502 for sinking common-mode current to electrical ground. As shown, the resistor ladder circuit 500A can have a plurality of shunt branches 506a, ..., 506h (collectively referred to as "shunt branches 506"). The resistor ladder circuit 500A can be similar to the resistor ladder circuit 402, but the middle node 504 (labeled "Vmid") is shorted together and coupled to the current source 502, and the shunt branches 506 are associated with each bit from the MSB on the left (here, bit 7, labeled "b7") to the LSB on the right (bit 0, labeled "b0"), with Figure 4 The directions of the bits in resistor ladder circuit 402 are opposite. Although not shown, resistor ladder circuit 500A can be coupled to multiple current steering cells (such as current steering cell 401), and the output of resistor ladder circuit 500A (labeled "Vop" and "Vom" for the positive and negative output voltage nodes) can be coupled to a filter (e.g., a baseband filter such as BBF 312).

[0068] According to some techniques, current source 502 can absorb current Isink to remove the common mode current of the intermediate node 504 through resistor ladder circuit 500A.Current source 502 can be programmed to change current Isink to effectively adjust the common mode voltage (e.g., to the input of baseband filter) output by resistor ladder circuit 500A. However, current source 502 may have a limited margin, which may be further limited when the equivalent resistance of resistor ladder circuit 500A is increased. In addition, current source 502 may occupy a relatively large area and may contribute common mode noise. In some cases, the lower the margin, the more common mode noise contributed by current source 502.

[0069] Therefore, certain aspects of the present disclosure provide common-mode current removal schemes that do not add margin constraints to resistor ladder circuits, occupy less area than current mirror circuits, have less thermal noise, and improve differential and common-mode noise performance. The programmability of these schemes allows the process variations of the DAC to be eliminated or at least reduced. In addition, the common-mode current removal schemes of the present disclosure allow the total equivalent resistance of the resistor ladder circuit to be increased, which provides lower differential noise and less DC offset and noise gain from the baseband filter.

[0070] Example common-mode current removal scheme for a digital-to-analog converter

[0071] Figure 5B is a schematic diagram of an example resistor ladder circuit 500B. Resistor ladder circuit 500B may be similar to resistor ladder circuit 500A, but has an adjustable resistance circuit 508 (in contrast to current source 502) coupled between intermediate node 504 and a reference potential node (e.g., electrical ground) of resistor ladder circuit 500B (which may also be a reference potential node of a DAC circuit of which resistor ladder circuit 500B is a part). Adjustable resistance circuit 508 may not be subject to the same margin constraints as current source 502, and may generate less thermal noise (i.e., less common-mode noise) than current source 502. In addition, adjustable resistance circuit 508 may occupy a smaller total surface area (e.g., footprint) than current source 502.

[0072] As shown, resistor ladder circuit 500B may have a plurality of resistor elements, each resistor element having a resistance that is a multiple of a base unit resistance R. For certain aspects, the base unit used to determine the size of the resistors in adjustable resistor circuit 508 may be the same as the base unit used to determine the size of the resistors in resistor ladder circuit 500B. When intermediate node 504 is shorted to ground (e.g., when adjustable resistor circuit 508 is adjusted to have a resistance of 0), the maximum common mode current will be absorbed.

[0073] According to some aspects, adjustable resistance circuit 508 can be implemented as a network of switched resistance elements (such as Figure 5C , Figure 5D ,and Figure 5E , discussed in more detail below). In some aspects, the switched resistor element network can be a binary weighted resistor element network. The switches in the switched resistor element network can be used to change the resistance of the adjustable resistor circuit 508, so that the common mode current removed from the DAC circuit can be adjusted (e.g., during calibration).

[0074] Figure 5C An example switched resistor element network 508A for implementing the adjustable resistor circuit 508 is illustrated.

[0075] As shown, the switched resistor element network 508A may include a plurality of network branches 510a, ..., 510h (sometimes individually referred to as "network branches 510" and collectively referred to as "network branches 510") coupled in parallel. Although eight network branches 510 are shown, the switched resistor element network 508A may have more or less than eight network branches. One or more of the network branches 510 may each include a switch 512a, ..., 512h (sometimes individually referred to as "switch 512" and collectively referred to as "switch 512") coupled in series with a resistor element (e.g., one of resistor elements 514a, ..., 514g, collectively referred to as "resistance element 514"). Switch 512 may be connected via a switch labeled "Sel_rsink" <0> "To"Sel_rsink <7> ” control signal is individually controlled. As illustrated, in some aspects, the resistive element 514 can be binary weighted, ranging from a resistance of R / 4 in the network branch 510b to 16R in the network branch 510h.

[0076] For certain aspects, one of the plurality of network branches 510 (e.g., network branch 510a) can be configured to selectively short the switched resistor element network 508A (e.g., short the intermediate node 504 to the reference potential node). Additionally or alternatively, in certain aspects, another network branch in the plurality of network branches 510 can be configured to present a fixed resistance to the switched resistor element network 508A when other switches 512 in the switched resistor element network 508A are open.

[0077] Figure 5D Another example switched resistor element network 508B with segments for implementing the adjustable resistor circuit 508 is illustrated. The switched resistor element network 508B may include a plurality of network branches 528a, ..., 528e (collectively referred to as "network branches 528") coupled in parallel. Figure 5D 5, but it should be understood that there may be more or less than five network branches 528. As shown, one or more of the network branches 528 may each include switches 532a, ..., 532e (collectively referred to as "switches 532") coupled in series with resistor elements 536a, ..., 536e (collectively referred to as "resistance elements 536").

[0078] One or more other network branches 530 each include a plurality of resistive elements 538a, ..., 538c (collectively "resistive elements 538") selectively coupled in series via switches 534a, ..., 534c (collectively "switches 534"). In this manner, the resistance of network branch 530 can be effectively segmented in switched resistive element network 508B. Figure 5D Although three resistor elements 538 are illustrated in the network branch 530 of the example switched resistor element network 508B, it should be understood that the segmented network branch may include two or more than three resistor elements coupled in series. Figure 5D A single segmented network branch 530 is shown in FIG. 5 , but it should be understood that the switched resistor element network may include more than one segmented network branch.

[0079] Figure 5E Yet another example switched resistor element network 508C is illustrated for implementing adjustable resistor circuit 508. Switched resistor element network 508C may be similar to switched resistor element network 508B, but with fewer network branches having resistor elements coupled in parallel and a greater number of resistor elements in segmented network branches (e.g., network branches having multiple resistor elements selectively coupled in series).

[0080] The switched resistor network 508C may include a plurality of network branches 540a, ..., 540d coupled in parallel (collectively referred to as a "first set of network branches 540"). Figure 5D , but it should be understood that there may be more or less than four network branches 540. As shown, one or more of the first set of network branches 540 may each include switches 544a, ..., 544d (collectively referred to as "switches 544") coupled in series with resistor elements 546a, ..., 546c (collectively referred to as "resistance elements 546"). For certain aspects, one of the first set of network branches 540 (e.g., network branch 540a) may be configured to selectively short the switched resistor element network 508C (e.g., short the intermediate node 504 to the reference potential node).

[0081] One or more other network branches 542 each include a plurality of resistive elements 548a, ..., 548d (collectively referred to as "resistive elements 548") selectively coupled in series via switches 550a, ..., 550d (collectively referred to as "switches 550"). Figure 5E In the example of the switched resistor network 508C, four resistor elements 548 are shown in the network branch 542, but it should be understood that the segmented network branch may include two, three, or more than four resistor elements coupled in series. Figure 5E A single segmented network branch 542 is shown in FIG. 5 , but it should be understood that the switched resistor element network may include more than one segmented network branch.

[0082] Fig. 5F is a circuit diagram of an example resistor ladder circuit 500C having multiple switches for absorbing common-mode current according to certain aspects of the present disclosure. The resistor ladder circuit 500C may have multiple shunt branches 552a, ..., 552h (collectively referred to as "shunt branches 552"). As shown, each of the multiple switches 554a, ..., 554h (collectively referred to as "switch 554") may be coupled between an intermediate node (e.g., one of the nodes labeled "Vmid0, ..., Vmid7") of one of the multiple shunt branches 552 and a reference potential node of the DAC circuit. This specific implementation allows the resistor ladder circuit 500C to be used as an adjustable common-mode current removal circuit itself (e.g., similar to the adjustable resistor circuit 508) to obtain a more compact solution.

[0083] According to certain aspects, the plurality of switches 554 are configured to be independently controlled. The independent control may be implemented by a separate control signal labeled "Rsink_ctrl<7:0>", such as Fig. 5F For other aspects, at least some of the switches 554 can be controlled by a shared control signal.

[0084] For Fig. 5F For some aspects shown in , the number of the plurality of switches 554 can be equal to the number of the plurality of shunt branches 552 (i.e., each shunt branch has a switch 554 associated therewith). For other aspects, only some of the shunt branches 552 can have switches 554 associated therewith. For some aspects, the number of the plurality of current steering units (e.g., Figure 4 The current steering unit 401 shown in the figure may be equal to the number of the plurality of shunt branches 552 .

[0085] Figure 5G is a circuit diagram of an example resistor ladder circuit 500D having a hybrid common-mode current removal circuit according to certain aspects of the present disclosure. The hybrid common-mode current removal circuit utilizes two different common-mode current removal schemes in the resistor ladder circuit, wherein the first scheme is used for a first set of intermediate nodes of the shunt branches, and the second scheme is used for a second set of intermediate nodes. The resistor ladder circuit 500D may be similar to Figure 5B The resistor ladder circuit 500B of the embodiment of the present invention is different in that the adjustable resistance circuit 508 is coupled to a first set of intermediate nodes of the plurality of shunt branches (e.g., intermediate nodes in shunt branches 506a to 506f), rather than being coupled to all intermediate nodes of the plurality of shunt branches. In this example, the resistor ladder circuit 500D may also include one or more switches 558a and 558b, each switch coupled between an intermediate node in a second set of intermediate nodes in the plurality of shunt branches (e.g., intermediate nodes in shunt branches 556a and 556b) and a reference potential node of the DAC circuit. The first set of intermediate nodes and the second set of intermediate nodes may be disjoint sets. Although only two switches 558a and 558b are shown, it will be appreciated by those skilled in the art that a greater or lesser number of shunt branches may have intermediate nodes coupled to switches. In addition, the switch coupled between the intermediate node and the reference potential node may be coupled to the intermediate node of any one of the shunt branches, and need not be coupled to the intermediate node of an adjacent shunt branch.

[0086] Example Transformation Operation

[0087] Figure 6 6 is a flow chart of example operations 600 for performing digital-to-analog conversion with common-mode current removal in a DAC circuit (e.g., DAC 400) according to certain aspects of the present disclosure. The DAC circuit generally includes a plurality of current steering units (e.g., current steering unit 401) and a resistor ladder circuit (e.g., resistor ladder circuit 500B or 500D) coupled to the plurality of current steering units and having a plurality of shunt branches (e.g., shunt branch 506). Operations 600 generally may involve, at block 602, controlling an adjustable resistance circuit (e.g., adjustable resistance circuit 508) coupled between an intermediate node (e.g., intermediate node 504) of the plurality of shunt branches and a reference potential node (e.g., electrical ground) of the DAC circuit to absorb at least a portion of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

[0088] According to certain aspects, the adjustable resistance circuit may include a switched resistance element network (e.g., switched resistance element network 508A, 508B, or 508C). In some aspects, the switched resistance element network may include a binary weighted resistance element network. According to certain aspects, operation 600 may also involve controlling switches (e.g., switches 512a or 544a) in network branches of the binary weighted resistance element network to selectively short the intermediate nodes of the plurality of shunt branches to a reference potential node.

[0089] According to certain aspects, the switched resistance element network may include a plurality of network branches (e.g., network branches 510, 528, or 540) coupled in parallel. One or more of the network branches may each include a switch (e.g., one of switches 512, 532, or 544) coupled in series with a resistance element (e.g., one of resistance elements 514, 536, or 546). In this case, controlling the adjustable resistance circuit may include selectively closing a switch in each of the one or more of the network branches. For certain aspects, operation 600 may also involve controlling another switch (e.g., switch 512a or 544a) in another of the plurality of network branches (e.g., network branch 510a or 540a) to selectively short the switched resistance element network. According to certain aspects, one or more other network branches (e.g., network branch 530 or 542) may each include a plurality of resistive elements (e.g., resistive elements 538 or 548) selectively coupled in series (e.g., via switch 534 or 550). In this case, controlling the adjustable resistance circuit at block 602 may also involve controlling (e.g., by closing or opening a particular switch 534 or 550) an effective number of the plurality of resistive elements coupled in series in each of the one or more other network branches.

[0090] In some aspects, the intermediate nodes of multiple shunt branches may be shorted together (e.g., Figure 5B ).

[0091] For some aspects (e.g. Figure 5G ), the adjustable resistance circuit may be coupled to a first set of intermediate nodes of the plurality of shunt branches (e.g., the intermediate node of shunt branch 506). According to certain aspects, operation 600 may also involve controlling one or more switches (e.g., switches 558a and / or 558b), each switch coupled between an intermediate node of a second set of intermediate nodes of the plurality of shunt branches (e.g., the intermediate node of shunt branch 556) and a reference potential node of the DAC circuit. The first set and the second set may be disjoint sets.

[0092] Figure 7 7 is a flow chart of an example operation 700 for performing digital-to-analog conversion with common-mode current removal in a DAC circuit (e.g., DAC 400) according to certain aspects of the present disclosure. The DAC circuit generally includes a plurality of current steering units (e.g., current steering unit 401) and a resistor ladder circuit (e.g., resistor ladder circuit 500C) coupled to the plurality of current steering units and having a plurality of shunt branches (e.g., shunt branch 552). Operation 700 generally may involve controlling a plurality of switches (e.g., switch 554) at block 702, each switch coupled between a middle node (e.g., one of the middle nodes Vmid0, ..., Vmid7) of a shunt branch in the plurality of shunt branches and a reference potential node (e.g., electrical ground) of the DAC circuit to selectively absorb portions of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

[0093] According to certain aspects, controlling at block 702 may involve independently controlling at least a portion of the plurality of switches.

[0094] For some aspects, the number of the plurality of switches may be equal to the number of the plurality of shunt branches. In addition, the number of the plurality of current steering units may be equal to the number of the plurality of shunt branches in the resistor ladder circuit.

[0095] Example aspects

[0096] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0097] Aspect 1: A digital-to-analog converter (DAC) circuit, comprising: a plurality of current steering units; a resistor ladder circuit, the resistor ladder circuit being coupled to the plurality of current steering units and having a plurality of shunt branches; and an adjustable resistance circuit, the adjustable resistance circuit being coupled between the intermediate nodes of the plurality of shunt branches and a reference potential node of the DAC circuit.

[0098] Aspect 2: The DAC circuit according to aspect 1, wherein the adjustable resistance circuit comprises a switched resistance element network.

[0099] Aspect 3: The DAC circuit according to aspect 2, wherein the switched resistor element network comprises a binary weighted resistor element network.

[0100] Aspect 4: The DAC circuit according to Aspect 3, wherein the binary weighted resistor element network includes a network branch configured to selectively short-connect the intermediate nodes of the plurality of shunt branches to the reference potential node.

[0101] Aspect 5: A DAC circuit according to aspect 2 or 3, wherein the switched resistor element network comprises a plurality of network branches coupled in parallel, and wherein one or more of the network branches each comprises a switch coupled in series with a resistor element.

[0102] Aspect 6: The DAC circuit according to aspect 5, wherein another network branch of the plurality of network branches is configured to selectively short the switched resistor element network.

[0103] Aspect 7: The DAC circuit according to aspect 5 or 6, wherein another network branch of the plurality of network branches is configured to present a fixed resistance to the switched resistor element network when other switches in the switched resistor element network are open.

[0104] Aspect 8: The DAC circuit according to any one of aspects 5 to 7, wherein the one or more other network branches each include a plurality of resistive elements selectively coupled in series.

[0105] Aspect 9: The DAC circuit according to any one of the preceding aspects, wherein the intermediate nodes of the plurality of shunt branches are short-circuited together.

[0106] Aspect 10: The DAC circuit of any one of aspects 1 to 8, wherein the adjustable resistance circuit is coupled to a first set of the intermediate nodes of the plurality of shunt branches.

[0107] Aspect 11: The DAC circuit according to Aspect 10 further includes one or more switches, each switch coupled between an intermediate node in a second set of the intermediate nodes of the plurality of shunt branches and the reference potential node of the DAC circuit, wherein the first set and the second set are non-overlapping sets.

[0108] Aspect 12: A DAC circuit, comprising: a plurality of current steering units; a resistor ladder circuit, the resistor ladder circuit being coupled to the plurality of current steering units and having a plurality of shunt branches; and a plurality of switches, each switch being coupled between an intermediate node of a shunt branch among the plurality of shunt branches and a reference potential node of the DAC circuit.

[0109] Aspect 13: The DAC circuit of aspect 12, wherein at least a portion of the plurality of switches are configured to be independently controlled.

[0110] Aspect 14: The DAC circuit according to aspect 12 or 13, wherein the number of the plurality of switches is equal to the number of the plurality of shunt branches, and wherein the number of the plurality of current steering units is equal to the number of the plurality of shunt branches.

[0111] Aspect 15: A method for operating a DAC circuit, the DAC circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, the method comprising controlling an adjustable resistor circuit coupled between intermediate nodes of the plurality of shunt branches and a reference potential node of the DAC circuit to absorb at least a portion of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

[0112] Aspect 16: The method according to aspect 15, wherein the adjustable resistance circuit includes a network of switched resistance elements.

[0113] Aspect 17: The method of aspect 16, wherein the switched resistor element network comprises a binary weighted resistor element network.

[0114] Aspect 18: The method according to aspect 17, further comprising controlling switches in network branches of the binary weighted resistor element network to selectively short-circuit the intermediate nodes of the plurality of shunt branches to the reference potential node.

[0115] Aspect 19: A method according to Aspect 16 or 17, wherein the switched resistor element network includes a plurality of network branches coupled in parallel, wherein one or more of the network branches each includes a switch coupled in series with a resistor element, and wherein controlling the adjustable resistor circuit includes selectively closing the switch in each of the one or more of the network branches.

[0116] Aspect 20: The method according to aspect 19, further comprising controlling another switch in another network branch of the plurality of network branches to selectively short-circuit the switched resistor element network.

[0117] Aspect 21: A method according to Aspect 19 or 20, wherein one or more other network branches each include a plurality of resistance elements selectively coupled in series, and wherein controlling the adjustable resistance circuit also includes controlling the effective number of the plurality of resistance elements coupled in series in each network branch in the one or more other network branches.

[0118] Aspect 22: The method according to aspects 15 to 21, wherein the intermediate nodes of the plurality of shunt branches are short-circuited together.

[0119] Aspect 23: The method according to any one of aspects 15 to 21, wherein the adjustable resistance circuit is coupled to a first set of the intermediate nodes of the plurality of shunt branches.

[0120] Aspect 24: The method according to Aspect 23 further includes controlling one or more switches, each switch coupled between an intermediate node in a second set of intermediate nodes of the plurality of shunt branches and the reference potential node of the DAC circuit, wherein the first set and the second set are non-overlapping sets.

[0121] Aspect 25: A method for operating a DAC circuit, the DAC circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, the method comprising controlling a plurality of switches to selectively absorb portions of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit, each switch being coupled between an intermediate node of a shunt branch among the plurality of shunt branches and a reference potential node of the DAC circuit.

[0122] Aspect 26: The method according to aspect 25, wherein the controlling comprises independently controlling at least a portion of the plurality of switches.

[0123] Aspect 27: The method according to aspect 25 or 26, wherein the number of the plurality of switches is equal to the number of the plurality of shunt branches, and wherein the number of the plurality of current steering units is equal to the number of the plurality of shunt branches in the resistor ladder circuit.

[0124] Additional considerations

[0125] The above description provides examples, but does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Various processes or components may be omitted, replaced or added to each example as appropriate. For example, the method described may be performed in a different order than described, and various steps may be added, omitted or combined. In addition, the features described in some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functional functions or structures and functionality other than or different from the various aspects of the present disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims. The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or having advantages over other aspects.

[0126] The various operations of the above method can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, in the case of the operations illustrated in the accompanying drawings, these operations may have corresponding corresponding components plus functional components.

[0127] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0128] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0129] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.< / k> < / k> < / k> < / k>

Claims

1. A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: multiple current steering units; a resistor ladder circuit, the resistor ladder circuit being coupled to the plurality of current steering units and having a plurality of shunt branches; and An adjustable resistance circuit is coupled between the middle nodes of the plurality of shunt branches and a reference potential node of the DAC circuit.

2. The DAC circuit of claim 1, wherein the adjustable resistance circuit comprises a network of switched resistance elements.

3. The DAC circuit of claim 2, wherein the switched resistor element network comprises a binary weighted resistor element network.

4. The DAC circuit of claim 3, wherein the binary-weighted resistor element network comprises a network branch configured to selectively short the intermediate nodes of the plurality of shunt branches to the reference potential node.

5. The DAC circuit of claim 2, wherein the switched resistor element network comprises a plurality of network branches coupled in parallel, and wherein one or more of the network branches each comprises a switch coupled in series with a resistor element. 6 . The DAC circuit of claim 5 , wherein another network branch of the plurality of network branches is configured to selectively short the switched resistor element network. 7 . The DAC circuit of claim 5 , wherein another network branch of the plurality of network branches is configured to present a fixed resistance to the switched resistor network when other switches in the switched resistor network are open.

8. The DAC circuit of claim 5, wherein the one or more other network branches each include a plurality of resistive elements selectively coupled in series.

9. The DAC circuit of claim 1, wherein the intermediate nodes of the plurality of shunt branches are shorted together.

10. The DAC circuit of claim 1, wherein the adjustable resistance circuit is coupled to a first set of the intermediate nodes of the plurality of shunt branches.

11. The DAC circuit according to claim 10 further includes one or more switches, each switch being coupled between an intermediate node in a second set of the intermediate nodes of the plurality of shunt branches and the reference potential node of the DAC circuit, wherein the first set and the second set are disjoint sets.

12. A digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising: multiple current steering units; a resistor ladder circuit, the resistor ladder circuit being coupled to the plurality of current steering units and having a plurality of shunt branches; and A plurality of switches, each switch is coupled between a middle node of a shunt branch among the plurality of shunt branches and a reference potential node of the DAC circuit.

13. The DAC circuit of claim 12, wherein at least a portion of the plurality of switches are configured to be independently controlled. 14 . The DAC circuit according to claim 12 , wherein the number of the plurality of switches is equal to the number of the plurality of shunt branches, and wherein the number of the plurality of current steering units is equal to the number of the plurality of shunt branches.

15. A method for operating a digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, the method comprising controlling an adjustable resistor circuit coupled between intermediate nodes of the plurality of shunt branches and a reference potential node of the DAC circuit to absorb at least a portion of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.

16. The method of claim 15, wherein the adjustable resistance circuit comprises a network of switched resistance elements.

17. The method of claim 16, wherein the switched resistor network comprises a binary weighted resistor network.

18. The method of claim 17, further comprising controlling switches in network branches of the binary weighted network of resistor elements to selectively short the intermediate nodes of the plurality of shunt branches to the reference potential node.

19. A method according to claim 16, wherein the switched resistor element network includes a plurality of network branches coupled in parallel, wherein one or more of the network branches each includes a switch coupled in series with a resistor element, and wherein controlling the adjustable resistor circuit includes selectively closing the switch in each of the one or more of the network branches.

20. The method of claim 19, further comprising controlling another switch in another network branch of the plurality of network branches to selectively short the switched resistor element network.

21. A method according to claim 19, wherein one or more other network branches each include a plurality of resistive elements selectively coupled in series, and wherein controlling the adjustable resistance circuit also includes controlling the effective number of the plurality of resistive elements coupled in series in each of the one or more other network branches.

22. The method of claim 15, wherein the intermediate nodes of the plurality of shunt branches are shorted together.

23. The method of claim 15, wherein the adjustable resistance circuit is coupled to a first set of the intermediate nodes of the plurality of shunt branches.

24. The method according to claim 23 further includes controlling one or more switches, each switch being coupled between an intermediate node in a second set of the intermediate nodes of the plurality of shunt branches and the reference potential node of the DAC circuit, wherein the first set and the second set are disjoint sets.

25. A method for operating a digital-to-analog converter (DAC) circuit, the digital-to-analog converter (DAC) circuit comprising a plurality of current steering units and a resistor ladder circuit coupled to the plurality of current steering units and having a plurality of shunt branches, the method comprising controlling a plurality of switches to selectively absorb portions of the common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit, each switch being coupled between an intermediate node of a shunt branch among the plurality of shunt branches and a reference potential node of the DAC circuit.

26. The method of claim 25, wherein the controlling comprises independently controlling at least a portion of the plurality of switches. 27 . The method of claim 25 , wherein the number of the plurality of switches is equal to the number of the plurality of shunt branches, and wherein the number of the plurality of current steering units is equal to the number of the plurality of shunt branches in the resistor ladder circuit.

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