An all-round hardware-in-the-loop test system for static synchronous machines

Abstract

The present invention discloses a universal static synchronous machine hardware-in-the-loop test system. The system comprises: a first host computer, a second host computer, a first slave computer, a second slave computer, and an oscilloscope. The first host computer is used to construct a power system simulation model and transmit it to the first slave computer. The second host computer is used to construct a modular multilevel converter control strategy model and a battery energy storage control strategy model and transmit them to the second slave computer. The second slave computer is used to obtain a switch control signal and transmit the switch control signal to the first slave computer. The first slave computer is used to generate electrical data and transmit the electrical data to the second slave computer and the oscilloscope. The oscilloscope is used to obtain electrical data within a preset time period and compare it with preset theoretical electrical data. The performance of the synchronous machine to be tested is obtained based on the comparison results. By implementing the present invention, the testing efficiency of the universal static synchronous machine and the accuracy of the test results can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic converters, and in particular to an all-round static synchronous machine hardware-in-the-loop testing system. Background Art

[0002] Renewable energy generation technology is a key factor in achieving my country's carbon neutrality goals. As the existing power system evolves towards a new one dominated by renewable energy, there is an urgent need to construct a large number of renewable energy power sources with the performance of synchronous generators. Scholars have proposed the concept of a versatile static synchronous generator and a synchronous generator-like control strategy. By combining the active frequency support capabilities of battery energy storage systems with the fast response speed of flexible DC converters, the versatile static synchronous generator can mimic the operating characteristics of synchronous generators, in principle approaching or even exceeding the performance of traditional synchronous generators, making it one of the most promising supporting technologies for building new power systems.

[0003] Because the all-purpose static synchronous machine combines a modular multilevel converter and a lithium-ion battery energy storage system, the complexity of the modular multilevel converter structure makes the overall circuit structure more complex when combined with the lithium-ion battery energy storage system. Typically, the modular multilevel converter and the lithium-ion battery energy storage system are placed in different lower-level computers and tested using physical controllers and virtual simulation controls, respectively. This makes it difficult to simulate the actual system for test verification throughout the entire test process. Summary of the Invention

[0004] The present invention provides a universal static synchronous machine hardware-in-the-loop test system, which can improve the test efficiency of the universal static synchronous machine and the accuracy of the test results.

[0005] An embodiment of the present invention provides an all-round static synchronous machine hardware-in-the-loop test system, comprising: a first host computer, a second host computer, a first slave computer, a second slave computer, and an oscilloscope;

[0006] The first host computer is connected to a first end of the first slave computer, the second end of the first slave computer is connected to the oscilloscope, and the second host computer is connected to the second slave computer;

[0007] The first upper computer is configured to obtain an initial capacitor voltage, an initial capacitor current, and an initial switch control signal of the synchronous machine to be tested, construct a power system simulation model based on the initial capacitor voltage, the initial capacitor current, and the initial switch control signal, and transmit the power system simulation model to the first lower computer;

[0008] The second upper computer is configured to construct a modular multilevel converter control strategy model and a battery energy storage control strategy model based on the initial electrical data of the synchronous machine to be tested, and to translate and encode the data before transmitting the model to the second lower computer. The electrical data includes: three-phase grid voltage, three-phase grid current, bridge arm current, battery voltage, capacitor voltage, battery current, and battery capacity.

[0009] The second lower computer is configured to calculate a current switch control signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current switch control signal to the first lower computer;

[0010] The first slave computer is configured to generate electrical data at a next moment based on the power system simulation model and the current switch control signal, transmit the electrical data at the next moment to the second slave computer to update the current electrical data of the second slave computer, and transmit the electrical data at the next moment to the oscilloscope;

[0011] The above-mentioned oscilloscope is used to obtain electrical data at each moment in real time until all electrical data within a preset time period are obtained, and all electrical data within the preset time period are compared with preset theoretical electrical data. Based on the comparison results, the performance of the above-mentioned synchronous machine to be tested is obtained.

[0012] Furthermore, the construction of the above power system simulation model includes:

[0013] A switching function model is constructed based on the initial capacitor voltage, initial capacitor current and initial switch control signal;

[0014] According to the above switch function model, a power system simulation model is obtained;

[0015] Among them, the above switching function model is:

[0016]

[0017] i dc_ua_i =T ua_S1_i i ua +T ua_S3_i i B_ua_i

[0018] v L_ua_i =T ua_S3_i v C_ua_i

[0019] Where, v ua Indicates the equivalent output voltage of the upper bridge arm of phase a, v C_ua_i represents the capacitor voltage of the ith submodule of the upper bridge arm of phase a, T ua_S1_iIndicates the switching signal of the ith submodule switch T1 of the upper bridge arm of phase a, i dc_ua_i Represents the capacitive current flowing into the capacitor of the i-th submodule of the upper bridge arm of phase a, i ua Indicates the bridge arm current of phase a, T ua_S3_i Indicates the switching signal of the ith submodule switch T3 of the upper bridge arm of phase a, i B_ua_i represents the battery current output by the battery cell of the ith submodule of the upper bridge arm of phase a, v L_ua_i It represents the low-voltage side voltage of the energy storage half-bridge of the i-th submodule in the upper arm of phase a, and N represents the number of submodules.

[0020] Furthermore, the construction of the above modular multi-level converter control strategy model and the battery energy storage control strategy model includes:

[0021] According to the above three-phase grid current, three-phase grid voltage, capacitor voltage and bridge arm current, a modular multilevel converter control strategy model is constructed;

[0022] According to the above battery voltage, battery current and battery capacity, a battery energy storage control strategy model is constructed.

[0023] Furthermore, the modular multilevel converter control strategy model is constructed based on the three-phase grid current, three-phase grid voltage, capacitor voltage, and bridge arm current, including:

[0024] According to the above three-phase grid current and three-phase grid voltage, the AC side synchronous machine control strategy is constructed;

[0025] Based on the above capacitor voltage, a capacitor voltage balance control strategy is constructed;

[0026] According to the above bridge arm current, a circulating current suppression control strategy is constructed;

[0027] According to the above-mentioned AC-side synchronous machine control strategy, capacitor voltage balance control strategy and circulating current suppression control strategy, the above-mentioned modular multilevel converter control strategy model is obtained;

[0028] The above-mentioned AC side synchronous machine control strategy is:

[0029]

[0030]

[0031] Δω=ω pcc -ω N

[0032]

[0033] θ set-θ pcc =δ

[0034] E′ qset =E′ q0 +T v (s)·(U ref -U s )

[0035]

[0036] Where, T represents the moment of inertia of the synchronous machine, P m Indicates mechanical power, P s Indicates the actual electromagnetic power of the system, K D represents the damping coefficient, δ represents the generator power angle, ω N Indicates rated power, ω pcc Indicates the actual frequency, Δω indicates the difference between the actual frequency and the rated frequency, u a Indicates the voltage of phase a, u b Indicates the b-phase voltage, u c Indicates the phase c voltage, V d Represents the d-axis component of the voltage vector, V q represents the q-axis component of the voltage vector, i a Indicates the a-phase current, i b represents the b-phase current, i c Indicates the c-phase current, I d represents the d-axis component of the current vector, I q represents the q-axis component of the current vector, represents the mechanical power setting reference value, G(s) represents the transfer function of the frequency regulator equation in the s domain, R d Indicates the adjustment coefficient, T G Represents the time constant of the speed control system, θ set It indicates that the active power reference value generated by the frequency regulation link passes through the rotor motion balance equation and outputs the phase angle of the transient potential of the synchronous generator, θ ref Indicates the rated value of the phase angle, E′ qset represents the transient potential, E′ q0 Indicates the transient potential reference value, T v (s) represents the s-domain transfer function corresponding to the simulated synchronous generator excitation circuit, U ref Indicates the reference value of the voltage amplitude at the grid connection point, U s Indicates the actual voltage amplitude at the grid connection point, K v Represents the gain coefficient, P ref Indicates the active power reference value output by the pseudo-synchronous control loop, x d represents the internal reactance of the simulated synchronous generator operation, Q refIndicates the reactive power reference value output by the pseudo-synchronous control loop;

[0037] The above capacitor voltage balance control strategy is:

[0038]

[0039] K c (v C_kj_i -v kj_ave )+sign(i kj )=Δv C_kj_i

[0040]

[0041] Where, v kj_ave represents the average value of the capacitor voltage of the j-phase k-bridge arm, v C_kj_i represents the capacitor voltage of the i-th submodule of the j-phase k-bridge arm, K c represents the gain coefficient, i kj Indicates the output current of the j-phase k-bridge arm, Δv C_kj_i represents the correction value of the modulation signal of the i-th submodule;

[0042] The above circulation suppression control strategy is:

[0043] (i pj +i nj ) / 2=i zj

[0044]

[0045] (0-i zj_ac )*PIR(s)=Δv cir_j

[0046]

[0047] Where i pj represents the bridge arm current of the upper bridge arm of phase j, i nj represents the bridge arm current of the lower bridge arm of phase j, i zj represents the circulation of phase j, T L represents the low-pass filter time constant, i zj_ac represents the AC component in the circulating current, PIR(s) represents the transfer function of the PIR controller in the circulating current suppression link in the s domain, Δv cir_j Indicates the voltage correction component output by the circulating current suppression link, k p_PIR Indicates the proportional coefficient of the PIR controller, k i_PIR Indicates the integral coefficient, k r_PIR represents the resonance coefficient, ω c represents the cutoff frequency, ω rIndicates the resonant frequency.

[0048] Furthermore, the battery energy storage control strategy model is constructed based on the battery voltage, battery current and battery capacity, including:

[0049] Based on the above battery voltage and battery current, an energy storage system control strategy is constructed;

[0050] According to the above battery capacity, a SoC balancing control strategy is constructed;

[0051] Generate the battery energy storage control strategy model based on the energy storage system control strategy and the SoC balancing control strategy;

[0052] Among them, the control strategy of the above energy storage system is:

[0053] P Bat =V Bat ×I Bat

[0054]

[0055] Where, P Bat Indicates the actual battery power, V Bat Indicates the battery voltage, I Bat Represents the battery current, K p Represents the proportional coefficient of the proportional integral link, K i Indicates the integral coefficient of the proportional integral link, P Batref Battery outer ring power reference value, d represents the duty cycle, I Batref Indicates the current reference value output by the power outer loop;

[0056] The above SoC balance control strategy is:

[0057]

[0058]

[0059] Where, SoC avg_kj Indicates the average state of charge on the j-phase k-bridge arm, SoC kji Indicates the charge state of the i-th submodule on the j-th phase k bridge arm, SoC avg_j Indicates the average state of charge of the upper and lower bridge arms of phase j, SoC avg_uj Represents the average state of charge on the j-th phase u bridge arm, SoC avg_lj Represents the average state of charge on the j-th phase l bridge arm, SoC avg_ph Indicates the three-phase average state of charge, SoC avg_a Indicates the average state of charge of the upper and lower bridge arms of phase a, SoC avg_bIndicates the average state of charge of the upper and lower bridge arms of phase b, SoC avg_c Indicates the average charge state of the upper and lower bridge arms of phase c, P j * Indicates the total power of the j-phase battery, P bat_ref Indicates the total battery power, K ph represents the inter-phase SoC balance coefficient, Indicates the total power of the battery in the j-phase k-bridge arm, K arm Indicates the SoC balance coefficient between bridge arms, Indicates the total battery power of each battery unit, K sm Indicates the SoC balance coefficient between sub-modules.

[0060] Furthermore, the current switch control signal is obtained by calculating based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and the current electrical data, including:

[0061] According to the modular multilevel converter control strategy model and the current electrical data, the current voltage modulation signal of each switch group on the bridge arm side is obtained;

[0062] After processing the above voltage modulation signal through pulse width modulation technology, the current switch control signal of the bridge arm side switch is obtained;

[0063] Based on the above battery energy storage control strategy model and current electrical data, the current duty cycle signal of each submodule switch on the energy storage side is obtained;

[0064] The duty cycle signal is processed by pulse width modulation technology to obtain the current switch control signal of the energy storage side switch.

[0065] Furthermore, the first lower computer includes: a first communication unit, a first input and output unit, and a real-time simulation unit; the second lower computer includes: a second communication unit, a second input and output unit, and a real-time digital control unit;

[0066] The first end of the first communication unit is connected to the first host computer, the second end of the first communication unit is connected to the first end of the real-time simulation unit, the second end of the real-time simulation unit is connected to the first end of the first input / output unit, the second end of the first input / output unit is connected to the first end of the second input / output unit, the second end of the second input / output unit is connected to the first end of the real-time digital control unit, the second end of the real-time digital control unit is connected to the first end of the second communication unit, the second end of the second communication unit is connected to the second host computer, and the third end of the first input / output unit is connected to the oscilloscope;

[0067] The second communication unit is configured to transmit the translated and encoded modular multi-level converter control strategy model and battery energy storage control strategy model to the real-time digital control unit;

[0068] The real-time digital control unit is configured to calculate a current switch control signal based on the modular multilevel converter control strategy model, the battery energy storage control strategy model, the electrical data, and the current electrical data, and transmit the current switch control signal to the first input / output unit via the second input / output unit;

[0069] The first communication unit is used to transmit the power system simulation model to the real-time simulation unit;

[0070] The real-time simulation unit is configured to generate electrical data at a next moment based on the power system simulation model and the current switch control signal, and transmit the electrical data at the next moment to the second input / output unit via the first input / output unit;

[0071] The first input-output unit is used to transmit the electrical data at the next moment to the second input-output unit and the oscilloscope;

[0072] The second input-output unit is used to transmit the electrical data at the next moment to the real-time digital control unit, and to transmit the current switch control signal to the first input-output unit.

[0073] Furthermore, the above-mentioned real-time digital control unit includes: a DSP processor, a signal port and an FPGA processor;

[0074] The first end of the DSP processor is connected to the second communication unit, the second end of the DSP processor is connected to the first end of the signal port, the second end of the signal port is connected to the first end of the FPGA processor, and the second end of the FPGA processor is connected to the second input / output unit;

[0075] The DSP processor is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multilevel converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the FPGA processor via the signal port.

[0076] the FPGA processor is configured to generate an electrical digital signal at a next moment based on the electrical data at a next moment, and transmit the electrical digital signal at the next moment to the signal port, and to generate a current switch control signal based on the current voltage modulation signal and duty cycle signal, and transmit the current switch control signal to the first input / output unit via the second input / output unit;

[0077] The above-mentioned signal port is used to transmit the current voltage modulation signal and duty cycle signal to the above-mentioned FPGA processor, and transmit the electrical digital signal at the next moment to the above-mentioned DSP processor, so as to update the current electrical data of the DSP processor.

[0078] Furthermore, the DSP processor includes: a core control unit and a first ADC converter;

[0079] The first ADC converter is used to convert the current electrical digital signal into current electrical data;

[0080] The core control unit is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the signal port;

[0081] The FPGA processor includes: a PWM signal generating unit and a second ADC converter;

[0082] The PWM signal generating unit is used to generate the current switch control signal according to the current voltage modulation signal and the duty cycle signal;

[0083] The second ADC converter is used to convert the electrical data at the next moment into the electrical digital signal at the next moment, and transmit the electrical digital signal at the next moment to the signal port.

[0084] Furthermore, it also includes: a first power supply unit and a second power supply unit;

[0085] The first end of the first power supply unit is connected to the first host computer, the second end of the first power supply unit is connected to the first slave computer, the third end of the first power supply unit is connected to the oscilloscope, the first end of the second power supply unit is connected to the second host computer, and the second end of the second power supply unit is connected to the second slave computer;

[0086] The first power supply unit is used to supply power to the first host computer, the first slave computer and the oscilloscope;

[0087] The second power supply unit is used to supply power to the second host computer and the second slave computer.

[0088] The embodiments of the present invention have the following beneficial effects:

[0089] The present invention provides an all-round static synchronous machine hardware-in-the-loop test system, which includes: a first host computer, a second host computer, a first slave computer, a second slave computer and an oscilloscope; the first host computer is connected to the first end of the first slave computer, the second end of the first slave computer is connected to the oscilloscope, and the second host computer is connected to the second slave computer; the first host computer is used to obtain the initial capacitor voltage, initial capacitor current and initial switch control signal of the synchronous machine to be tested, and construct a power system simulation model according to the initial capacitor voltage, initial capacitor current and initial switch control signal, and transmit the power system simulation model to the first slave computer; the second host computer is used to construct a modular multi-level converter control strategy model and a battery energy storage control strategy model according to the electrical data of the synchronous machine to be tested at the initial time, and transmit the model to the second slave computer after translating and encoding; wherein the electrical data includes: three Phase grid voltage, three-phase grid current, bridge arm current, battery voltage, capacitor voltage, battery current and battery capacity; the above-mentioned second lower computer is used to calculate the current switch control signal according to the above-mentioned modular multi-level converter control strategy model, the battery energy storage control strategy model and the current electrical data, and transmit the current switch control signal to the above-mentioned first lower computer; the above-mentioned first lower computer is used to generate the electrical data at the next moment according to the above-mentioned power system simulation model and the current switch control signal, and transmit the electrical data at the next moment to the above-mentioned second lower computer to update the current electrical data of the second lower computer, and at the same time transmit the electrical data at the next moment to the above-mentioned oscilloscope; the above-mentioned oscilloscope is used to obtain the electrical data at each moment in real time until all the electrical data within the preset time period are obtained, and compare all the electrical data within the preset time period with the preset theoretical electrical data, and obtain the performance of the above-mentioned synchronous machine to be tested according to the comparison result. Therefore, the present invention, based on the control logic of the modular multilevel converter and the lithium battery energy storage system in the overall structure of the all-round static synchronous machine, does not affect each other. Therefore, the modular multilevel converter and the lithium battery energy storage system are controlled and tested simultaneously using a physical real-time data controller. This is more consistent with the control logic of the entire all-round static synchronous machine hardware test system in reality, improving test efficiency and the accuracy of test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0090] Figure 1 The figure is a schematic structural diagram of a universal static synchronous machine hardware-in-the-loop test system provided by one embodiment of the present invention.

[0091] Figure 2The figure is a schematic diagram of the circuit topology structure of an all-round static synchronous machine provided by one embodiment of the present invention.

[0092] Figure 3 3 is a circuit simulation diagram of a half-bridge circuit switching function model provided by an embodiment of the present invention.

[0093] Figure 4 This is a circuit simulation diagram of a switching function model of a single submodule provided by an embodiment of the present invention.

[0094] Figure 5 3 is a circuit simulation diagram of a simplified switching function model provided by an embodiment of the present invention.

[0095] Figure 6 This is a schematic diagram of the topology of the power system model provided by one embodiment of the present invention.

[0096] Figure 7 This is a schematic diagram of the control system structure corresponding to the modular multi-level converter control strategy model provided by one embodiment of the present invention.

[0097] Figure 8 It is a schematic diagram of the control system structure corresponding to the battery energy storage control strategy model provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0098] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0099] like Figure 1 As shown, an embodiment of the present invention provides an all-round static synchronous machine hardware-in-the-loop test system, comprising:

[0100] A first host computer, a second host computer, a first slave computer, a second slave computer, and an oscilloscope;

[0101] Specifically, the first slave computer is a real-time digital simulation machine, and the second slave computer is a real-time digital controller.

[0102] The first host computer is connected to a first end of the first slave computer, the second end of the first slave computer is connected to the oscilloscope, and the second host computer is connected to the second slave computer;

[0103] Specifically, the first host computer and the first slave computer are connected via network communication, the second host computer and the second slave computer are also connected via network communication, and the first slave computer and the second slave computer are electrically connected.

[0104] The first upper computer is configured to obtain an initial capacitor voltage, an initial capacitor current, and an initial switch control signal of the synchronous machine to be tested, construct a power system simulation model based on the initial capacitor voltage, the initial capacitor current, and the initial switch control signal, and transmit the power system simulation model to the first lower computer;

[0105] In a preferred embodiment, the construction of the above-mentioned power system simulation model includes:

[0106] A switching function model is constructed based on the initial capacitor voltage, initial capacitor current and initial switch control signal;

[0107] According to the above switch function model, a power system simulation model is obtained;

[0108] Among them, the above switching function model is:

[0109]

[0110] i dc_ua_i =T ua_S1_i i ua +T ua_S3_i i B_ua_i

[0111] v L_ua_i =T ua_S3_i v C_ua_i

[0112] Where, v ua Indicates the equivalent output voltage of the upper bridge arm of phase a, v C_ua_i represents the capacitor voltage of the ith submodule of the upper bridge arm of phase a, T ua_S1_i Indicates the switching signal of the ith submodule switch T1 of the upper bridge arm of phase a, i dc_ua_i Represents the capacitive current flowing into the capacitor of the i-th submodule of the upper bridge arm of phase a, i ua Indicates the bridge arm current of phase a, T ua_S3_i Indicates the switching signal of the ith submodule switch T3 of the upper bridge arm of phase a, i B_ua_i represents the battery current output by the battery cell of the ith submodule of the upper bridge arm of phase a, v L_ua_i It represents the low-voltage side voltage of the energy storage half-bridge of the i-th submodule in the upper arm of phase a, and N represents the number of submodules.

[0113] Specifically, the above formula is the switching function model corresponding to a single bridge arm, and the switching function models of the other five bridge arms can be obtained similarly.

[0114] Specifically, the initial switch control signal is a switch closing signal.

[0115] Schematically, the all-purpose static synchronous machine is based on a modular multi-level converter structure, so the circuit topology diagram of the all-purpose static synchronous machine is as follows: Figure 2 As shown, a single bridge arm contains multiple submodules, each consisting of two half-bridge circuits. One half-bridge circuit is used to generate multi-level voltages in the bridge arm, while the other acts as a DC / DC converter to control the power, voltage, or current of the energy storage unit.

[0116] Specifically, considering that the submodule capacitor voltage is generally positive, the output voltage of the half-bridge circuit will show a waveform related to the switch state when the switch is switched. For example, when the upper switch is turned on, the output voltage is equal to the capacitor voltage, and the current flowing into the DC capacitor is equal to the half-bridge input current; when the lower switch is turned on, the output voltage is 0, and the current flowing into the DC capacitor is equal to 0. Therefore, we can get the following Figure 3 The circuit simulation diagram of the half-bridge circuit switching function model shown in FIG. Figure 3 V in sm Indicates the output voltage of the submodule, i sm Represents the current flowing into the submodule, T1 and T2 are the switches of the half-bridge submodule on the MMC side, v c is the capacitor voltage, i c is the current flowing into the capacitor of the half-bridge on the MMC side, Figure 3 Part (a) shows the circuit simulation diagram of the switching function model of the half-bridge circuit before equivalent operation, and part (b) shows the circuit simulation diagram of the switching function model of the half-bridge circuit after equivalent operation. The AC side of the half-bridge circuit is equivalent to a controlled voltage source, and the DC side is equivalent to a controlled current source. The two controlled sources are coupled via the switching function.

[0117] Schematically, according to the above principle, the submodule of the all-purpose static synchronous machine can be extended to obtain the circuit simulation diagram of the switching function model of a single submodule of the all-purpose static synchronous machine. Figure 4 As shown, Figure 4 T1, T2, T3 and T4 are all bridge switches, v DC Represents the low-voltage side voltage of the energy storage half-bridge, i c1 Represents the current flowing into the capacitor on the energy storage half-bridge side, i DC Represents the output current of the low-voltage side of the energy storage half-bridge, Figure 4 Part (c) is a circuit simulation diagram of the switching function model of a single submodule before equivalence. Figure 4 Part (d) is a circuit simulation diagram of the equivalent switching function model of a single sub-module.

[0118] Schematically, after superimposing each submodule, a simplified switching function model of the entire all-purpose static synchronous machine can be obtained. The circuit simulation diagram of the simplified switching function model of the all-purpose static synchronous machine is shown in FIG. Figure 5 shown.

[0119] Schematically, the topology diagram of the power system model is as follows Figure 6 As shown, in the present invention, Figure 6 The all-round static synchronous machine in the embodiment is replaced with a simplified model of the switching function of the all-round static synchronous machine to obtain the above-mentioned power system simulation model. The power system simulation model is built in the first upper computer, and the built power system simulation model is loaded into the first lower computer through the first communication.

[0120] Preferably, a switching function model is used to ensure the simulation accuracy under normal operation and typical AC / DC port fault scenarios. Since the impedance and admittance matrix of the sub-module is a constant, the simulation efficiency is greatly improved and the calculation time of a single simulation step is reduced.

[0121] In this preferred embodiment, a switching function model is constructed through the initial capacitor voltage, the initial capacitor current and the initial switch control signal, and then a power system simulation model is obtained based on the switching function model.

[0122] The second upper computer is configured to construct a modular multilevel converter control strategy model and a battery energy storage control strategy model based on the initial electrical data of the synchronous machine to be tested, and to translate and encode the data before transmitting the model to the second lower computer. The electrical data includes: three-phase grid voltage, three-phase grid current, bridge arm current, battery voltage, capacitor voltage, battery current, and battery capacity.

[0123] In a preferred embodiment, the construction of the modular multi-level converter control strategy model and the battery energy storage control strategy model includes:

[0124] According to the above three-phase grid current, three-phase grid voltage, capacitor voltage and bridge arm current, a modular multilevel converter control strategy model is constructed;

[0125] According to the above battery voltage, battery current and battery capacity, a battery energy storage control strategy model is constructed.

[0126] In this preferred embodiment, a modular multi-level converter control strategy model is constructed using the three-phase grid current, three-phase grid voltage, capacitor voltage, and bridge arm current; and a battery energy storage control strategy model is constructed based on the battery voltage, battery current, and battery capacity.

[0127] In another preferred embodiment, the modular multilevel converter control strategy model is constructed based on the three-phase grid current, three-phase grid voltage, capacitor voltage, and bridge arm current, including:

[0128] According to the above three-phase grid current and three-phase grid voltage, the AC side synchronous machine control strategy is constructed;

[0129] Based on the above capacitor voltage, a capacitor voltage balance control strategy is constructed;

[0130] According to the above bridge arm current, a circulating current suppression control strategy is constructed;

[0131] According to the above-mentioned AC-side synchronous machine control strategy, capacitor voltage balance control strategy and circulating current suppression control strategy, the above-mentioned modular multilevel converter control strategy model is obtained;

[0132] Specifically, in order for the all-purpose static synchronous machine to realize the function of a synchronous generator, the all-purpose static synchronous machine grid-connected converter adopts a synchronous machine simulation control strategy, that is, the typical second-order motion equation of the synchronous generator is used to simulate the operating state of the synchronous generator.

[0133] Specifically, in order for the all-purpose static synchronous machine to realize the function of primary frequency regulation of the synchronous generator, the rated frequency is subtracted from the actual frequency obtained by actual monitoring of the AC bus, and the rated active power output value of the all-purpose static synchronous machine is output after the frequency regulator acts.

[0134] Specifically, the active power reference value generated by the frequency regulation link is output through the rotor motion balance equation to simulate the phase angle of the transient potential of the synchronous generator.

[0135] Specifically, the all-purpose static synchronous machine also needs to realize the function of synchronous generator voltage support. The output of the voltage support loop is used to obtain the transient potential of the synchronous generator.

[0136] The above-mentioned AC side synchronous machine control strategy is:

[0137]

[0138] Δω=ω pcc -ω N

[0139]

[0140]

[0141] θ set -θ pcc =δ

[0142] E′ qset =E′ q0 +T v (s)·(U ref -U s )

[0143]

[0144] Where, T represents the moment of inertia of the synchronous machine, P m Indicates mechanical power, P s Indicates the actual electromagnetic power of the system, K D represents the damping coefficient, δ represents the generator power angle, ω N Indicates rated power, ω pcc Indicates the actual frequency, Δω indicates the difference between the actual frequency and the rated frequency, u a Indicates the voltage of phase a, u b Indicates the b-phase voltage, u c Indicates the phase c voltage, V d Represents the d-axis component of the voltage vector, V q represents the q-axis component of the voltage vector, i a Indicates the a-phase current, i b represents the b-phase current, i c Indicates the c-phase current, I d represents the d-axis component of the current vector, I q represents the q-axis component of the current vector, represents the mechanical power setting reference value, G(s) represents the transfer function of the frequency regulator equation in the s domain, R d Indicates the adjustment coefficient, T G Represents the time constant of the speed control system, θ set It indicates that the active power reference value generated by the frequency regulation link passes through the rotor motion balance equation and outputs the phase angle of the transient potential of the synchronous generator, θ ref Indicates the rated value of the phase angle, E′ qset represents the transient potential, E′ q0 Indicates the transient potential reference value, T v (s) represents the s-domain transfer function corresponding to the simulated synchronous generator excitation circuit, U ref Indicates the reference value of the voltage amplitude at the grid connection point, U s Indicates the actual voltage amplitude at the grid connection point, K v Represents the gain coefficient, P ref Indicates the active power reference value output by the pseudo-synchronous control loop, x d represents the internal reactance of the simulated synchronous generator operation, Q ref Indicates the reactive power reference value output by the pseudo-synchronous control loop;

[0145] Specifically, the active power reference and reactive power reference values ​​output by the AC-side synchronous generator simulation control strategy serve as inputs to the all-purpose static synchronous generator grid-connected control strategy, which includes an outer power loop controller and an inner current loop controller. This grid-connected control strategy is identical to the control strategy for conventional grid-connected converters.

[0146] Specifically, due to the large number of sub-modules in the modular multi-level converter topology, and in actual scenarios, the differences in switching times and component parameters of each sub-module will lead to inconsistent charging and discharging of capacitor voltages. If not controlled, it will affect the safe and stable operation of the equipment.

[0147] The above capacitor voltage balance control strategy is:

[0148]

[0149] K c (v C_kj_i -v kj_ave )+sign(i kj )=Δv C_kj_i

[0150]

[0151] Where, v kj_ave represents the average value of the capacitor voltage of the j-phase k-bridge arm, v C_kj_i represents the capacitor voltage of the i-th submodule of the j-phase k-bridge arm, K c represents the gain coefficient, i kj Indicates the output current of the j-phase k-bridge arm, Δv C_kj_i represents the correction value of the modulation signal of the i-th submodule;

[0152] Specifically, because the three phase units of a modular multilevel converter are connected in parallel to the DC bus, voltage imbalances occur between the submodules during operation, generating interphase circulating currents between the three-phase bridge arms. This interphase circulating current can cause current distortion in the bridge arms, affecting the output voltage waveform quality and reducing converter efficiency. Therefore, for safe and stable system operation, it is necessary to implement an effective circulating current suppression control strategy.

[0153] The above circulation suppression control strategy is:

[0154] (i pj +i nj ) / 2=i zj

[0155]

[0156] (0-i zj_ac )*PIR(s)=Δv cir_j

[0157]

[0158] Where i pj represents the bridge arm current of the upper bridge arm of phase j, i nj represents the bridge arm current of the lower bridge arm of phase j, izj represents the circulation of phase j, T L represents the low-pass filter time constant, i zj_ac represents the AC component in the circulating current, PIR(s) represents the transfer function of the PIR controller in the circulating current suppression link in the s domain, Δv cir_j Indicates the voltage correction component output by the circulating current suppression link, k p_PIR Indicates the proportional coefficient of the PIR controller, k i_PIR Indicates the integral coefficient, k r_PIR represents the resonance coefficient, ω c represents the cutoff frequency, ω r Indicates the resonant frequency.

[0159] Specifically, the upper and lower bridge arm currents of each phase are added and divided by 2 to obtain the circulating current of each phase. Then, the AC component in the circulating current is separated by a low-pass filter and its reference value is set to 0. After the quasi-PIR circulating current suppression link, the reference value of the internal unbalanced voltage Δv can be obtained. cir_j It is superimposed on the voltage modulation signal of each phase to achieve circulating current suppression.

[0160] Schematically, the control system structure diagram corresponding to the constructed modular multi-level converter control strategy model is as follows: Figure 7 shown.

[0161] In this preferred embodiment, an AC side simulated synchronous machine control strategy is constructed based on the three-phase grid current and the three-phase grid voltage, a capacitor voltage balance control strategy is constructed based on the capacitor voltage, and a circulating current suppression control strategy is constructed based on the bridge arm current. Based on the AC side simulated synchronous machine control strategy, the capacitor voltage balance control strategy and the circulating current suppression control strategy, a modular multi-level converter control strategy model is obtained.

[0162] In another preferred embodiment, the battery energy storage control strategy model constructed based on the battery voltage, battery current and battery capacity includes:

[0163] Based on the above battery voltage and battery current, an energy storage system control strategy is constructed;

[0164] According to the above battery capacity, a SoC balancing control strategy is constructed;

[0165] Generate the battery energy storage control strategy model based on the energy storage system control strategy and the SoC balancing control strategy;

[0166] Among them, the control strategy of the above energy storage system is:

[0167] P Bat =V Bat ×I Bat

[0168]

[0169] Where, P Bat Indicates the actual battery power, V Bat Indicates the battery voltage, I Bat Represents the battery current, K p Represents the proportional coefficient of the proportional integral link, K i Indicates the integral coefficient of the proportional integral link, P Batref Battery outer ring power reference value, d represents the duty cycle, I Batref Indicates the current reference value output by the power outer loop;

[0170] Specifically, the control strategy of the lithium battery energy storage system adopts a dual closed-loop control structure of a power outer loop and a current inner loop. The outer loop power reference value is subtracted from the actual battery power, and then the current inner loop reference value is generated through the proportional integral (PI) control link. This reference value is subtracted from the actual battery current value, and the PI link finally generates the duty cycle of the DC / DC converter of the lithium battery energy storage system. The current direction when the energy storage battery releases power is set to the positive direction of current. When the power setting value of the lithium battery energy storage system is positive, the energy storage system discharges and releases power to the outside world. When the setting value is negative, the energy storage system charges and absorbs power.

[0171] The above SoC balance control strategy is:

[0172]

[0173] Assume that the total battery power in the energy storage system is P bat_ref According to the power ratio control scheme, when the battery SoC in each submodule is inconsistent, the power distribution value of each phase, each bridge arm and each submodule is as follows:

[0174]

[0175] Where, SoC avg_kj Indicates the average state of charge on the j-phase k-bridge arm, SoC kji Indicates the charge state of the i-th submodule on the j-th phase k bridge arm, SoC avg_j Indicates the average state of charge of the upper and lower bridge arms of phase j, SoC avg_uj Represents the average state of charge on the j-th phase u bridge arm, SoC avg_lj Represents the average state of charge on the j-th phase l bridge arm, SoC avg_ph Indicates the three-phase average state of charge, SoC avg_a Indicates the average state of charge of the upper and lower bridge arms of phase a, SoC avg_b Indicates the average state of charge of the upper and lower bridge arms of phase b, SoC avg_cIndicates the average charge state of the upper and lower bridge arms of phase c, P j * Indicates the total power of the j-phase battery, P bat_ref Indicates the total battery power, K ph represents the inter-phase SoC balance coefficient, Indicates the total power of the battery in the j-phase k-bridge arm, K arm Indicates the SoC balance coefficient between bridge arms, Indicates the total battery power of each battery unit, K sm Indicates the SoC balance coefficient between sub-modules.

[0176] Specifically, after power proportional distribution, That is, the P of each energy storage battery unit in the energy storage system control strategy bat_ref .

[0177] Schematically, the control system structure diagram corresponding to the battery energy storage control strategy model is as follows Figure 8 shown.

[0178] Preferably, in actual engineering, the number of converter submodules is large, so the number of energy storage batteries assembled in each submodule is also large. When the state of charge (SoC) of these energy storage batteries is inconsistent, it will affect the energy utilization and service life of the battery. For example, when the energy storage battery is charging, the battery with a high SoC is fully charged first. At this time, the battery protection circuit starts and no longer charges the battery, but the remaining batteries are not fully charged; when discharging, the inconsistent SoC will cause some batteries with high SoC to not be fully discharged. In addition, if the protection circuit cannot respond in time, it may cause some battery modules to be overcharged or over-discharged, affecting the service life of the battery. Therefore, when the energy storage system is working, if the energy utilization and service life of the battery are to be improved, balanced control should be adopted for each battery module to ensure that the state of each battery module is the same. In the present invention, a power proportional control strategy is adopted to achieve SoC balance.

[0179] In this preferred embodiment, an energy storage system control strategy is constructed based on the battery voltage and battery current, and a SoC balance control strategy is constructed based on the battery capacity. A battery energy storage control strategy model is generated based on the energy storage system control strategy and the SoC balance control strategy.

[0180] The second lower computer is configured to calculate a current switch control signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current switch control signal to the first lower computer;

[0181] In a preferred embodiment, the current switch control signal is calculated based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and the current electrical data, including:

[0182] According to the modular multilevel converter control strategy model and the current electrical data, the current voltage modulation signal of each switch group on the bridge arm side is obtained;

[0183] After processing the above voltage modulation signal through pulse width modulation technology, the current switch control signal of the bridge arm side switch is obtained;

[0184] Based on the above battery energy storage control strategy model and current electrical data, the current duty cycle signal of each submodule switch on the energy storage side is obtained;

[0185] The duty cycle signal is processed by pulse width modulation technology to obtain the current switch control signal of the energy storage side switch.

[0186] In this preferred embodiment, the voltage modulation signal obtained by the modular multilevel converter control strategy model and the duty cycle signal obtained by the battery energy storage control strategy model are processed respectively by pulse width modulation technology to obtain the switching control signals of the bridge arm side switch and the energy storage side switch.

[0187] The first slave computer is configured to generate electrical data at a next moment based on the power system simulation model and the current switch control signal, transmit the electrical data at the next moment to the second slave computer to update the current electrical data of the second slave computer, and transmit the electrical data at the next moment to the oscilloscope;

[0188] In another preferred embodiment, the first slave computer comprises: a first communication unit, a first input / output unit, and a real-time simulation unit; the second slave computer comprises: a second communication unit, a second input / output unit, and a real-time digital control unit;

[0189] The first end of the first communication unit is connected to the first host computer, the second end of the first communication unit is connected to the first end of the real-time simulation unit, the second end of the real-time simulation unit is connected to the first end of the first input / output unit, the second end of the first input / output unit is connected to the first end of the second input / output unit, the second end of the second input / output unit is connected to the first end of the real-time digital control unit, the second end of the real-time digital control unit is connected to the first end of the second communication unit, the second end of the second communication unit is connected to the second host computer, and the third end of the first input / output unit is connected to the oscilloscope;

[0190] The second communication unit is configured to transmit the translated and encoded modular multi-level converter control strategy model and battery energy storage control strategy model to the real-time digital control unit;

[0191] The real-time digital control unit is configured to calculate a current switch control signal based on the modular multilevel converter control strategy model, the battery energy storage control strategy model, the electrical data, and the current electrical data, and transmit the current switch control signal to the first input / output unit via the second input / output unit;

[0192] The first communication unit is used to transmit the power system simulation model to the real-time simulation unit;

[0193] The real-time simulation unit is configured to generate electrical data at a next moment based on the power system simulation model and the current switch control signal, and transmit the electrical data at the next moment to the second input / output unit via the first input / output unit;

[0194] The first input-output unit is used to transmit the electrical data at the next moment to the second input-output unit and the oscilloscope;

[0195] The second input-output unit is used to transmit the electrical data at the next moment to the real-time digital control unit, and to transmit the current switch control signal to the first input-output unit.

[0196] Schematically, the first input and output unit and the second input and output unit can be an I / O board, which includes a digital input / digital output interface (Digital Input / Digital Output, DI / DO) and an analog input / analog output interface (Analog Input / Analog Output, AI / AO), where the DI / DO and AI / AO interfaces can determine the required model and connection method according to actual test requirements.

[0197] Specifically, based on the electrical quantities required to construct the power system simulation model, the modular multilevel converter control strategy model, and the battery energy storage control strategy model, the minimum hardware scale parameters for the first and second slave computers can be obtained as shown in Tables 1 and 2:

[0198] Table 1:

[0199]

[0200] Table 2:

[0201]

[0202] Based on the two tables above, we can determine the minimum number of input and output ports for the two groups of slave computers: the minimum number of output ports for the first slave computer and the minimum number of input ports for the second slave computer is 24N+12; the minimum number of input ports for the first slave computer and the minimum number of output ports for the second slave computer is 12N. Based on this minimum standard, we can select appropriate slave computers to build a comprehensive hardware-in-the-loop test platform for static synchronous machines.

[0203] In a preferred embodiment, the real-time digital control unit comprises: a DSP processor, a signal port and an FPGA processor;

[0204] The first end of the DSP processor is connected to the second communication unit, the second end of the DSP processor is connected to the first end of the signal port, the second end of the signal port is connected to the first end of the FPGA processor, and the second end of the FPGA processor is connected to the second input / output unit;

[0205] The DSP processor is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multilevel converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the FPGA processor via the signal port.

[0206] the FPGA processor is configured to generate an electrical digital signal at a next moment based on the electrical data at a next moment, and transmit the electrical digital signal at the next moment to the signal port, and to generate a current switch control signal based on the current voltage modulation signal and duty cycle signal, and transmit the current switch control signal to the first input / output unit via the second input / output unit;

[0207] The above-mentioned signal port is used to transmit the current voltage modulation signal and duty cycle signal to the above-mentioned FPGA processor, and transmit the electrical digital signal at the next moment to the above-mentioned DSP processor, so as to update the current electrical data of the DSP processor.

[0208] Preferably, considering that in order to achieve the above control, the real-time digital controller (second slave) needs to collect a large amount of electrical data and output a large number of switch control signals, a conventional real-time digital controller using a DSP processor as the controller cannot meet the above requirements. Therefore, the present invention adopts a real-time digital controller using a DSP chip as the core processor and an FPGA chip as the peripheral signal processor. The sampling channel of the FPGA processor collects electrical data and transmits it to the DSP processor via a data interface. The DSP processor outputs relevant control signals after calculation, which are also transmitted to the FPGA processor via the data interface. The control signals are output to the real-time digital simulator (first slave) through the output interface of the FPGA processor.

[0209] In this preferred embodiment, in the DSP processor, a voltage modulation signal and a duty cycle signal are generated based on the modular multilevel converter control strategy model, the battery energy storage control strategy model and the electrical digital signal, and the voltage modulation signal and the duty cycle signal are then transmitted to the FPGA processor via the signal port, a switch control signal is generated in the FPGA processor, and the generated switch control signal is transmitted to the second input and output unit; wherein, the obtained electrical data is converted into an electrical digital signal in the FPGA processor and transmitted to the DSP processor via the signal port.

[0210] In another preferred embodiment, the DSP processor includes: a core control unit and a first ADC converter;

[0211] The first ADC converter is used to convert the current electrical digital signal into current electrical data;

[0212] The core control unit is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the signal port;

[0213] The FPGA processor includes: a PWM signal generating unit and a second ADC converter;

[0214] The PWM signal generating unit is used to generate the current switch control signal according to the current voltage modulation signal and the duty cycle signal;

[0215] The second ADC converter is used to convert the electrical data at the next moment into the electrical digital signal at the next moment, and transmit the electrical digital signal at the next moment to the signal port.

[0216] Specifically, the PWM signal generation unit generates a square wave switching control signal for switching control based on the voltage modulation signal and the duty cycle signal. The core control unit includes RAM and corresponding core control level. The RAM is used to write the control programs corresponding to the modular multilevel converter control strategy model and the battery energy storage control strategy model, and the memory parameters can be modified in real time.

[0217] In this preferred embodiment, the core control unit generates a voltage modulation signal and a duty cycle signal based on the modular multilevel converter control strategy model, the battery energy storage control strategy model, and the electrical data. The voltage modulation signal and the duty cycle signal are then transmitted to the aforementioned signal port, and then transmitted to the PWM signal generation unit via the signal port to generate a switch control signal. The second ADC converter converts the electrical data transmitted from the second input / output unit into an electrical digital signal, which is then transmitted to the first ADC converter via the signal port, where the first ADC converter converts the electrical digital signal into electrical data.

[0218] In another preferred embodiment, the present invention further comprises: a first power supply unit and a second power supply unit;

[0219] The first end of the first power supply unit is connected to the first host computer, the second end of the first power supply unit is connected to the first slave computer, the third end of the first power supply unit is connected to the oscilloscope, the first end of the second power supply unit is connected to the second host computer, and the second end of the second power supply unit is connected to the second slave computer;

[0220] The first power supply unit is used to supply power to the first host computer, the first slave computer and the oscilloscope;

[0221] The second power supply unit is used to supply power to the second host computer and the second slave computer.

[0222] In this preferred embodiment, the first power supply unit is used to supply power to the first host computer, the first slave computer and the oscilloscope, and the second power supply unit is used to supply power to the second host computer and the second slave computer.

[0223] The above-mentioned oscilloscope is used to obtain electrical data at each moment in real time until all electrical data within a preset time period are obtained, and all electrical data within the preset time period are compared with preset theoretical electrical data. Based on the comparison results, the performance of the above-mentioned synchronous machine to be tested is obtained.

[0224] Specifically, the oscilloscope is used to record the electrical data and waveforms corresponding to the electrical data that need to be saved during the entire system test operation, and compare them with the preset theoretical electrical data obtained by offline simulation to prove that the results obtained by this hardware-in-the-loop test solution are consistent with the theory, and then obtain the performance test results of the synchronous motor to be tested.

[0225] Compared with the prior art, by implementing the above-mentioned embodiments of the present invention, the test efficiency of the all-round static synchronous machine and the accuracy of the test results can be improved.

[0226] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A versatile static synchronous machine hardware-in-the-loop test system, characterized in that: include: A first host computer, a second host computer, a first slave computer, a second slave computer, and an oscilloscope; The first host computer is connected to a first end of the first slave computer, the second end of the first slave computer is connected to the oscilloscope, and the second host computer is connected to the second slave computer; The first host computer is configured to obtain an initial capacitor voltage, an initial capacitor current, and an initial switch control signal of the synchronous machine to be tested, construct a power system simulation model based on the initial capacitor voltage, the initial capacitor current, and the initial switch control signal, and transmit the power system simulation model to the first slave computer; The second upper computer is configured to construct a modular multilevel converter control strategy model and a battery energy storage control strategy model based on the initial electrical data of the synchronous machine to be tested, and to translate and encode the model before transmitting the model to the second lower computer; wherein the electrical data includes: three-phase grid voltage, three-phase grid current, bridge arm current, battery voltage, capacitor voltage, battery current, and battery capacity; The second lower computer is configured to calculate a current switch control signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current switch control signal to the first lower computer; The first slave computer is configured to generate electrical data at a next moment according to the power system simulation model and the current switch control signal, and transmit the electrical data at the next moment to the second slave computer to update the current electrical data of the second slave computer, and transmit the electrical data at the next moment to the oscilloscope; The oscilloscope is used to obtain electrical data at each moment in real time until all electrical data within a preset period is obtained, and all electrical data within the preset period is compared with preset theoretical electrical data. Based on the comparison result, the performance of the synchronous machine to be tested is obtained.

2. The all-round static synchronous machine hardware-in-the-loop test system according to claim 1, characterized in that: The construction of the power system simulation model includes: constructing a switching function model according to the initial capacitor voltage, the initial capacitor current, and the initial switch control signal; According to the switching function model, a power system simulation model is obtained; Wherein, the switching function model is: i dc_ua_i =T ua_S1_i i ua +T ua_S3_i i B_ua_i v L_ua_i =T ua_S3_i v C_ua_i Where, v ua Indicates the equivalent output voltage of the upper bridge arm of phase a, v C_ua_i represents the capacitor voltage of the ith submodule of the upper bridge arm of phase a, T ua_S1_i Indicates the switching signal of the ith submodule switch T1 of the upper bridge arm of phase a, i dc_ua_i Represents the capacitive current flowing into the capacitor of the i-th submodule of the upper bridge arm of phase a, i ua Indicates the bridge arm current of phase a, T ua_S3_i Indicates the switching signal of the ith submodule switch T3 of the upper bridge arm of phase a, i B_ua_i represents the battery current output by the battery cell of the ith submodule of the upper bridge arm of phase a, v L_ua_i It represents the low-voltage side voltage of the energy storage half-bridge of the i-th submodule in the upper arm of phase a, and N represents the number of submodules.

3. The all-round static synchronous machine hardware-in-the-loop test system according to claim 2, characterized in that: The construction of the modular multi-level converter control strategy model and the battery energy storage control strategy model includes: A modular multilevel converter control strategy model is constructed based on the three-phase grid current, the three-phase grid voltage, the capacitor voltage, and the bridge arm current; A battery energy storage control strategy model is constructed based on the battery voltage, battery current and battery capacity.

4. The all-round static synchronous machine hardware-in-the-loop test system according to claim 3, characterized in that: The modular multi-level converter control strategy model is constructed based on the three-phase grid current, the three-phase grid voltage, the capacitor voltage, and the bridge arm current, including: According to the three-phase grid current and the three-phase grid voltage, an AC side synchronous machine control strategy is constructed; According to the capacitor voltage, a capacitor voltage balance control strategy is constructed; According to the bridge arm current, a circulating current suppression control strategy is constructed; According to the AC side synchronous machine control strategy, capacitor voltage balance control strategy and circulating current suppression control strategy, the modular multilevel converter control strategy model is obtained; The AC side synchronous machine control strategy is as follows: Give = oh pcc -oh N i set -θ pcc =d E q ′ set =E q ′0+T v (s)·(U ref -U s ) Where, T represents the moment of inertia of the synchronous machine, P m Indicates mechanical power, P s Indicates the actual electromagnetic power of the system, K D represents the damping coefficient, δ represents the generator power angle, ω N Indicates rated power, ω pcc Indicates the actual frequency, Δω indicates the difference between the actual frequency and the rated frequency, u a Indicates the voltage of phase a, u b Indicates the b-phase voltage, u c Indicates the phase c voltage, V d Represents the d-axis component of the voltage vector, V q represents the q-axis component of the voltage vector, i a Indicates the a-phase current, i b represents the b-phase current, i c Indicates the c-phase current, I d represents the d-axis component of the current vector, I q represents the q-axis component of the current vector, represents the mechanical power setting reference value, G(s) represents the transfer function of the frequency regulator equation in the s domain, R d Indicates the adjustment coefficient, T G Represents the time constant of the speed control system, θ set It indicates that the active power reference value generated by the frequency regulation link passes through the rotor motion balance equation and outputs the phase angle of the transient potential of the synchronous generator, θ ref Indicates the rated value of the phase angle, E′ qset represents the transient potential, E′ q0 Indicates the transient potential reference value, T v (s) represents the s-domain transfer function corresponding to the simulated synchronous generator excitation circuit, U ref Indicates the reference value of the voltage amplitude at the grid connection point, U s Indicates the actual voltage amplitude at the grid connection point, K v Represents the gain coefficient, P ref Indicates the active power reference value output by the pseudo-synchronous control loop, x d represents the internal reactance of the simulated synchronous generator operation, Q ref Indicates the reactive power reference value output by the pseudo-synchronous control loop; The capacitor voltage balance control strategy is: K c (v C_kj_i -v kj_ave )+sign(i kj )=Δv C_kj_i Where, v kj_ave represents the average value of the capacitor voltage of the j-phase k-bridge arm, v C_kj_i represents the capacitor voltage of the i-th submodule of the j-phase k-bridge arm, K c represents the gain coefficient, i kj Indicates the output current of the j-phase k-bridge arm, Δv C_kj_i Indicates the correction value of the modulation signal of the i-th submodule of the j-phase k-bridge arm; The circulation suppression control strategy is: (i pj +i nj ) / 2=i zj (0-i zj_ac )*PIR(s)=Δv cir_j Where i pj represents the bridge arm current of the upper bridge arm of phase j, i nj represents the bridge arm current of the lower bridge arm of phase j, i zj represents the circulation of phase j, T L represents the low-pass filter time constant, i zj_ac represents the AC component in the circulating current, PIR(s) represents the transfer function of the PIR controller in the circulating current suppression link in the s domain, Δv cir_j Indicates the voltage correction component output by the circulating current suppression link, k p_PIR Indicates the proportional coefficient of the PIR controller, k i_PIR Indicates the integral coefficient, k r_PIR represents the resonance coefficient, ω c represents the cutoff frequency, ω r Indicates the resonant frequency.

5. The all-round static synchronous machine hardware-in-the-loop test system according to claim 4, characterized in that: The battery energy storage control strategy model is constructed based on the battery voltage, battery current and battery capacity, including: Constructing an energy storage system control strategy based on the battery voltage and battery current; According to the battery capacity, a SoC balancing control strategy is constructed; Generate the battery energy storage control strategy model according to the energy storage system control strategy and the SoC balancing control strategy; The energy storage system control strategy is: P Bat =V Bat ×I Bat Where, P Bat Indicates the actual battery power, V Bat Indicates the battery voltage, I Bat Represents the battery current, K p Represents the proportional coefficient of the proportional integral link, K i Indicates the integral coefficient of the proportional integral link, P Batref Battery outer ring power reference value, d represents the duty cycle, I Batref Indicates the current reference value output by the power outer loop; The SoC balance control strategy is: Where, SoC avg_kj Indicates the average state of charge on the j-phase k-bridge arm, SoC kji Indicates the charge state of the i-th submodule on the j-th phase k bridge arm, SoC avg_j Indicates the average state of charge of the upper and lower bridge arms of phase j, SoC avg_uj Represents the average state of charge on the j-th phase u bridge arm, SoC avg_lj Represents the average state of charge on the j-th phase l bridge arm, SoC avg_ph Indicates the three-phase average state of charge, SoC avg_a Indicates the average state of charge of the upper and lower bridge arms of phase a, SoC avg_b Indicates the average state of charge of the upper and lower bridge arms of phase b, SoC avg_c Indicates the average charge state of the upper and lower bridge arms of phase C, Indicates the total power of the j-phase battery, P bat_ref Indicates the total battery power, K ph represents the inter-phase SoC balance coefficient, Indicates the total power of the battery in the j-phase k-bridge arm, K arm Indicates the SoC balance coefficient between bridge arms, Indicates the total battery power of each battery unit, K sm Indicates the SoC balance coefficient between sub-modules.

6. The all-round static synchronous machine hardware-in-the-loop test system according to claim 5, characterized in that: The calculating and obtaining the current switch control signal according to the modular multi-level converter control strategy model, the battery energy storage control strategy model and the current electrical data includes: Obtaining a current voltage modulation signal for each switch group on the bridge arm side according to the modular multilevel converter control strategy model and current electrical data; After processing the voltage modulation signal through pulse width modulation technology, a current switch control signal of the bridge arm side switch is obtained; Obtaining a current duty cycle signal of each submodule switch on the energy storage side according to the battery energy storage control strategy model and current electrical data; The duty cycle signal is processed by pulse width modulation technology to obtain the current switch control signal of the energy storage side switch.

7. The all-round static synchronous machine hardware-in-the-loop test system according to claim 6, characterized in that: The first lower computer includes: a first communication unit, a first input and output unit, and a real-time simulation unit; the second lower computer includes: a second communication unit, a second input and output unit, and a real-time digital control unit; A first end of the first communication unit is connected to the first host computer, a second end of the first communication unit is connected to the first end of the real-time simulation unit, a second end of the real-time simulation unit is connected to the first end of the first input / output unit, a second end of the first input / output unit is connected to the first end of the second input / output unit, a second end of the second input / output unit is connected to the first end of the real-time digital control unit, a second end of the real-time digital control unit is connected to the first end of the second communication unit, a second end of the second communication unit is connected to the second host computer, and a third end of the first input / output unit is connected to the oscilloscope; The second communication unit is configured to transmit the translated and encoded modular multilevel converter control strategy model and battery energy storage control strategy model to the real-time digital control unit; The real-time digital control unit is configured to calculate a current switch control signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, the electrical data, and the current electrical data, and transmit the current switch control signal to the first input-output unit via the second input-output unit; The first communication unit is configured to transmit the power system simulation model to the real-time simulation unit; The real-time simulation unit is configured to generate electrical data at a next moment based on the power system simulation model and the current switch control signal, and transmit the electrical data at the next moment to the second input-output unit via the first input-output unit; The first input-output unit is configured to transmit the electrical data at the next moment to the second input-output unit and the oscilloscope; The second input-output unit is used to transmit the electrical data at the next moment to the real-time digital control unit, and to transmit the current switch control signal to the first input-output unit.

8. The all-round static synchronous machine hardware-in-the-loop test system according to claim 7, characterized in that: The real-time digital control unit includes: a DSP processor, a signal port and an FPGA processor; The first end of the DSP processor is connected to the second communication unit, the second end of the DSP processor is connected to the first end of the signal port, the second end of the signal port is connected to the first end of the FPGA processor, and the second end of the FPGA processor is connected to the second input and output unit; The DSP processor is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the FPGA processor through the signal port; the FPGA processor is configured to generate an electrical digital signal at a next moment based on the electrical data at a next moment, and transmit the electrical digital signal at the next moment to the signal port, and to generate a current switch control signal based on the current voltage modulation signal and the duty cycle signal, and transmit the current switch control signal to the first input / output unit via the second input / output unit; The signal port is used to transmit the current voltage modulation signal and duty cycle signal to the FPGA processor, and transmit the electrical digital signal at the next moment to the DSP processor, so as to update the current electrical data of the DSP processor.

9. The all-round static synchronous machine hardware-in-the-loop test system according to claim 8, characterized in that: The DSP processor includes: a core control unit and a first ADC converter; The first ADC converter is used to convert the current electrical digital signal into current electrical data; The core control unit is configured to calculate a current voltage modulation signal and a duty cycle signal based on the modular multi-level converter control strategy model, the battery energy storage control strategy model, and current electrical data, and transmit the current voltage modulation signal and the duty cycle signal to the signal port; The FPGA processor includes: a PWM signal generating unit and a second ADC converter; The PWM signal generating unit is used to generate a current switch control signal according to a current voltage modulation signal and a duty cycle signal; The second ADC converter is used to convert the electrical data at the next moment into the electrical digital signal at the next moment, and transmit the electrical digital signal at the next moment to the signal port.

10. The all-round static synchronous machine hardware-in-the-loop test system according to claim 9, characterized in that: Also includes: a first power supply unit and a second power supply unit; The first end of the first power supply unit is connected to the first host computer, the second end of the first power supply unit is connected to the first slave computer, the third end of the first power supply unit is connected to the oscilloscope, the first end of the second power supply unit is connected to the second host computer, and the second end of the second power supply unit is connected to the second slave computer; The first power supply unit is used to supply power to the first host computer, the first slave computer and the oscilloscope; The second power supply unit is used to supply power to the second upper computer and the second lower computer.

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